JP2009021278A - Manufacturing method of thin film transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To form a thin film transistor which has small variation in gate electrode width and high driving capability when a gate electrode structure is formed by using electroless plating. <P>SOLUTION: A manufacturing method includes the steps of: injecting impurities into a semiconductor layer 4 to high density using a patterned metal diffusion preventive layer 21 and metal seed layer 22 as a mask; forming an opening portion 33 in resist 32 to expose a portion of a top surface of the metal seed layer 22; forming a metal (Cu) plating layer 23 by electroless plating on the metal seed layer 22 exposed to the bottom surface of the opening portion 33 of the resist 32; patterning the metal diffusion preventive layer 21 and metal seed layer 22 using the metal plating layer 23 as a mask after removing the resist 32; and forming a gate electrode 6 constituted of three layers which are the metal diffusion preventive layer 21, metal seed layer 22, and metal plating layer 23; and injecting impurities into the semiconductor layer 4 to low density using the gate electrode as a mask. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a thin film transistor in which a gate electrode is formed by electroless plating.

  In recent years, there has been a demand for a reduction in the frame portion of a liquid crystal display device, particularly a liquid crystal display device for mobile products. In order to reduce the frame portion of the liquid crystal display device, it is effective to make finer wiring of peripheral circuits formed in the frame portion. Therefore, the conventional process technology shifts from wet etching to dry etching and reduces the etching conversion difference. Miniaturization is realized. However, since the wiring resistance increases as the wiring becomes finer, it is desired to use a wiring material having a resistance lower than that of general Al as a wiring material. In addition, since the wiring film thickness increases while the wiring width becomes finer, the etching conversion difference gradually increases even in dry etching as the film thickness increases, and the narrowing of the frame is stopped. Therefore, it has been proposed to employ a plating method that does not cause a conversion difference and Cu wiring and a gate electrode, which are low-resistance materials.

  By the way, since fine processing by etching of Cu is difficult, in the field of semiconductors represented by LSI and ULSI, Cu is processed by a so-called damascene method. In the damascene method, first, a wiring groove is formed in an insulating layer on a single crystal silicon substrate, and a Cu layer is formed over the entire surface in the groove and on the insulating layer so as to bury the wiring groove by sputtering or the like. Thereafter, the Cu wiring embedded in the insulating layer is formed by removing the Cu layer up to the upper end surface of the groove portion embedded by a polishing method such as CMP (Chemical Mechanical Polishing).

  However, unlike a single crystal silicon substrate, a glass substrate used as a substrate for a TFT for a display device such as a liquid crystal display device has thickness unevenness and waviness, and thus is not suitable for polishing such as a CMP method. In recent years, the size of glass substrates for liquid crystal panels has been remarkably increased, but along with this, the waviness of the substrate surface tends to increase. Therefore, it is difficult to apply a damascene method using CMP for Cu processing in the field of display devices.

  Therefore, a wiring processing technique not based on the damascene method has been proposed (see, for example, Patent Document 1). Hereinafter, a method of manufacturing a TFT having an LDD (lightly doped drain) structure by forming a gate electrode without using the damascene method will be described with reference to FIG.

  First, as shown in FIG. 7A, a semiconductor layer 102 made of polycrystalline silicon and a gate insulating layer 103 that covers the semiconductor layer 102 are formed on an insulating substrate 101 such as a glass substrate, and Cu is formed on the gate insulating layer 103. A diffusion prevention layer 104 and a Cu seed layer 105 are selectively formed. Next, by performing electroless plating, Cu is deposited from the Cu seed layer 105 to form a Cu plating layer 106 having a structure protruding from the end of the Cu diffusion preventing layer 104. The gate electrode 107 includes three layers, a Cu diffusion preventing layer 104, a Cu seed layer 105, and a Cu plating layer 106 (FIG. 7B). Next, impurities are implanted into the semiconductor layer 104 by ion doping using the gate electrode 107 as a mask. Impurities are implanted at a high concentration in a portion of the semiconductor layer 104 located outside the end portion of the Cu plating layer 106 to form a source region 108 and a drain region 109. On the other hand, impurities are implanted at a low concentration in the portion of the semiconductor layer 104 where the end portion of the Cu plating layer 106 is located immediately below the end portion of the Cu diffusion preventing layer 104, and the channel region 110 and the source region 108 are implanted. The LDD region 111 is formed between the drain region 109 and the drain region 109 (FIG. 7C).

Moreover, the method shown below is also possible as a method of utilizing plating. That is, first, a semiconductor layer 102 made of polycrystalline silicon, a gate insulating layer 103 covering the semiconductor layer 102, and a Cu diffusion preventing layer 104 covering the gate insulating layer 103 are formed on the insulating substrate 101, and on the Cu diffusion preventing layer 104. A Cu seed layer 105 is selectively formed. Next, using the Cu seed layer 105 as a mask, impurities are implanted at a low concentration into the semiconductor layer 102 by ion doping (FIG. 8A). Next, the Cu diffusion prevention layer 104 was patterned so that the Cu diffusion prevention layer 104 was exposed outside the end portion of the Cu seed layer 105, and a resist 112 having an opening 113 having a shape corresponding to the gate electrode 107 was formed. Thereafter, electroless plating is performed. As a result, Cu is deposited so as to fill the opening 113 of the resist 112, and a Cu plating layer 106 is formed on the Cu seed layer 105 exposed on the bottom surface of the opening 113 of the resist 112 (FIG. 8B). ). After the resist 112 is removed, impurities are implanted into the semiconductor layer 102 at a high concentration by ion doping. As a result, a source region 108 and a drain region 109 are formed outside the Cu plating layer 106, and an LDD region 111 is formed between the source region 108, the drain region 109, and the channel region 110 (FIG. 8C). .
JP 2004-134771 A

  However, in the method of isotropically growing the Cu plating layer 106 from the patterned Cu seed layer 105 as described with reference to FIG. 7, the width (gate) of the Cu plating layer 106 due to fluctuations in the chemical concentration distribution or the like. The width of the electrode 107 is likely to fluctuate, and as a result, there is a problem that variation in TFT characteristics becomes large. Further, according to the method described with reference to FIG. 8, the Cu plating layer 106 is formed inside the opening 113 of the resist 112, so that the width of the Cu plating layer 106 ( Variation in the width of the gate electrode 107 is suppressed. However, since the LDD region 111 is located immediately below the end portion of the gate electrode 107, when an AC signal is input, this overlapping portion becomes a capacitive component, and the driving capability is reduced.

  The present invention has been proposed in view of such a conventional situation, and in the case of forming a gate electrode structure using electroless plating, a thin film transistor having a small variation in the gate electrode width and a high driving capability. It is an object of the present invention to provide a method for manufacturing a thin film transistor capable of forming a thin film transistor.

  In order to achieve the above object, a method of manufacturing a thin film transistor according to the present invention includes a step of forming a metal diffusion prevention layer on a gate insulating layer covering a semiconductor layer, and a formation of a metal seed layer on the metal diffusion prevention layer. A step of patterning the metal diffusion prevention layer and the metal seed layer; a step of implanting impurities into the semiconductor layer at a high concentration using the patterned metal diffusion prevention layer and the metal seed layer as a mask; An opening that exposes a portion of the upper surface of the metal seed layer by exposing the resist after depositing a resist over the gate insulating layer, the metal diffusion prevention layer, and the metal seed layer; And forming a metal plating layer by electroless plating on the metal seed layer exposed on the bottom surface of the opening of the resist. And after removing the resist, the metal seed layer is removed by wet etching using the metal plating layer as a mask, the metal diffusion prevention layer is then removed by dry etching, and the metal diffusion prevention layer, the metal The method includes a step of forming a gate electrode including three layers of a seed layer and the metal plating layer, and a step of injecting impurities into the semiconductor layer at a low concentration using the gate electrode as a mask.

  According to the manufacturing method as described above, since the metal plating layer is formed inside the opening of the resist, the lateral growth of the end of the metal plating layer is limited by the side wall of the opening. As a result, it is possible to obtain a thin film transistor in which fluctuations in the width of the gate electrode are suppressed and characteristics are less varied. Further, according to the above manufacturing method, since the LDD region is formed at a position that does not overlap with the gate electrode, there is no reduction in driving capability due to the LDD structure. Furthermore, since the LDD region is formed using the difference between the opening width of the resist opening and the width of the metal seed layer, the length of the LDD region can be arbitrarily controlled.

  The method of manufacturing a thin film transistor according to the present invention includes a step of forming a metal diffusion prevention layer on a gate insulating layer covering a semiconductor layer, a step of forming a metal seed layer on the metal diffusion prevention layer, and the metal seed layer After forming a resist on the resist, exposing the resist to form an opening in the resist such that a part of the upper surface of the metal seed layer is exposed, and exposing to the bottom of the opening of the resist Forming a metal plating layer on the metal seed layer by electroless plating, removing the resist, and then implanting impurities into the semiconductor layer using the metal plating layer as a mask, and wet etching Removing the metal seed layer using the metal plating layer as a mask and removing a portion of the surface of the metal plating layer; Using the etched metal plating layer and the metal seed layer as a mask, the metal diffusion prevention layer is removed by dry etching, and the gate electrode is formed of the metal diffusion prevention layer, the metal seed layer, and the metal plating layer. And a step of injecting impurities into the semiconductor layer at a low concentration using the gate electrode as a mask.

  According to the manufacturing method as described above, since the metal plating layer is formed inside the opening of the resist, the lateral growth of the end of the metal plating layer is limited by the sidewall of the opening. As a result, it is possible to obtain a thin film transistor in which fluctuations in the width of the gate electrode are suppressed and characteristics are less varied. Further, according to the above manufacturing method, since the LDD region is formed at a position that does not overlap with the gate electrode, there is no reduction in driving capability due to the LDD structure. Furthermore, the LDD structure can be formed in a self-aligned manner in one photolithography process.

  A method of manufacturing a thin film transistor according to the present invention includes a step of forming a metal diffusion prevention layer on a gate insulating layer covering a semiconductor layer, a step of forming a metal seed layer on the metal diffusion prevention layer, and the metal diffusion prevention layer And patterning the metal seed layer, and forming a resist over the gate insulating layer, the metal diffusion prevention layer and the metal seed layer, and then exposing the resist using a halftone mask, Forming a part of the top surface of the metal seed layer exposed and having an opening width narrower on the bottom side than the surface side in the resist; and the metal exposed on the bottom surface of the resist opening. A metal plating layer is formed on the seed layer by electroless plating, and a gate electrode including the metal diffusion prevention layer, the metal seed layer, and the metal plating layer is formed. And that step, after removing the resist, the gate electrode as a mask, characterized by a step of implanting an impurity into the semiconductor layer.

  According to the manufacturing method as described above, since the metal plating layer is formed inside the opening of the resist, the lateral growth of the end of the metal plating layer is limited by the side wall of the opening. As a result, it is possible to obtain a thin film transistor in which fluctuations in the width of the gate electrode are suppressed and characteristics are less varied. In addition, since the LDD region is formed at a position where the influence of the electric field of the gate electrode is weak, a decrease in driving capability due to the LDD structure is small. Further, when impurities are implanted using a metal plating layer formed by using a halftone mask and having an end on the upper surface side protruding outward from the end of the metal seed layer, the metal plating layer of the semiconductor layer The impurity concentration in the portion located immediately below the overhanging portion becomes low, and an LDD region is formed. That is, the LDD structure is formed by one impurity implantation process.

  According to the thin film transistor manufacturing method of the present invention, the width of the gate electrode composed of the metal diffusion prevention layer, the metal seed layer, and the metal plating layer can be formed with good control, and variations in characteristics of the thin film transistor can be suppressed. Can do. In addition, since the LDD region is formed at a position that does not overlap with the gate electrode or is weakly affected by the electric field of the gate electrode, a thin film transistor with high current driving capability can be manufactured.

  Hereinafter, a method of manufacturing a thin film transistor to which the present invention is applied will be described with reference to the drawings.

<First Embodiment>
FIG. 1 shows a thin film transistor substrate 1 having a thin film transistor (TFT) formed by the manufacturing method of the first embodiment. The thin film transistor substrate 1 is used for a display device such as a liquid crystal display device, and a plurality of TFTs 3 are formed on one main surface of the insulating substrate 2.

  The TFT 3 includes an island-shaped semiconductor layer 4 made of polycrystalline silicon and a gate insulating layer 5 that covers the semiconductor layer 4. A gate electrode 6 is formed at a position overlapping the semiconductor layer 4 on the gate insulating layer 5. Both sides of the gate electrode 6 of the semiconductor layer 4 are a source region 7 and a drain region 8 as high concentration impurity regions which are n + regions. Between the channel region 9 located immediately below the gate electrode 6 of the semiconductor layer 4, the source region 7 and the drain region 8, an LDD region 10 as a low concentration impurity region which is an n− region is formed. An interlayer insulating layer 11 is overlaid on the gate insulating layer 5 and the gate electrode 6, and the source region 7 of the semiconductor layer 4 and the source electrode 13 are electrically connected through a contact hole 12 provided in the interlayer insulating layer 11. Is done. Further, a drain electrode 14 that is electrically connected to the drain region 8 of the semiconductor layer 4 is formed through a contact hole 12 provided in the interlayer insulating layer 11.

  The gate electrode 6 has a three-layer structure including a Cu diffusion prevention layer 21, a Cu seed layer 22 provided on the Cu diffusion prevention layer 21, and a Cu plating layer 23 provided on the Cu seed layer 22. ing.

  Hereinafter, an example of a method for manufacturing the thin film transistor having the above-described structure will be described with reference to FIG.

First, an island-shaped semiconductor layer 4 made of polycrystalline silicon is formed on an insulating substrate 2 such as a transparent glass substrate. The semiconductor layer 4 is formed by annealing amorphous silicon (a-Si) formed by, for example, a plasma CVD method and then polycrystallizing it by laser irradiation or the like. Next, a SiO ₂ layer as the gate insulating layer 5 is formed by PE-CVD so as to cover the semiconductor layer 4. A TaN layer is formed as a Cu diffusion preventing layer 21 on the gate insulating layer 5 by sputtering. As the Cu diffusion preventing layer 21, a Ta layer, a TiN layer, a TaSiN layer, a WSiN layer, or the like can be used in addition to the TaN layer. A Cu seed layer 22 is formed on the Cu diffusion preventing layer 21 by, for example, electroless plating. In the present embodiment, the Cu diffusion prevention layer 21 is formed with a thickness of about 50 nm, and the Cu seed layer 22 is formed with a thickness of about 50 nm. After the formation of the Cu seed layer 22, a resist 31 for patterning the Cu diffusion preventing layer 21 and the Cu seed layer 22 is formed by photolithography (FIG. 2A).

Next, the Cu diffusion prevention layer 21 and the Cu seed layer 22 are patterned using the resist 31 as a mask. Specifically, the Cu seed layer 22 is first removed by wet etching using the resist 31 as a mask, and then the Cu diffusion preventing layer 21 is removed by dry etching using the resist 31 and the Cu seed layer 22 as a mask. Impurities are implanted into the semiconductor layer 4 at a high concentration using the patterned Cu diffusion prevention layer 21 and the Cu seed layer 22 as a mask. In this embodiment, phosphorus is implanted into the semiconductor layer 4 by ion doping using PH ₃ as a doping gas (dose amount 1.5E15 / cm ² , acceleration voltage 50 KeV). The region into which the impurity of the semiconductor layer 4 is implanted becomes a source region 7 and a drain region 8 as a high concentration impurity region (FIG. 2B).

  After the source region 7 and the drain region 8 are formed, the resist 31 for patterning the Cu diffusion preventing layer 21 and the Cu seed layer 22 is removed, and then a negative resist is used as the resist 32 for forming the Cu plating layer 23. Is deposited over the entire surface covering the gate insulating layer 5, the Cu diffusion preventing layer 21, and the Cu seed layer 22. The formed resist 32 is exposed from the surface opposite to the resist 32 forming surface of the insulating substrate 2 using the Cu diffusion preventing layer 21 and the Cu seed layer 22 as a mask, and the resist 32 in the unexposed portion is removed. The exposure is overexposure. As a result of this back exposure, an opening 33 is formed in a self-aligning manner so that the top surface of the Cu seed layer 22 is exposed on the bottom surface. Thereafter, Cu is deposited on the Cu seed layer 22 by electroless plating. As a result, a Cu plating layer 23 is formed on the Cu seed layer 22 so as to fill the opening 33 of the resist 32 (FIG. 2C).

  As described above, when a negative resist is used as the resist 32 and the opening 33 is formed in a self-aligning manner by backside exposure, the exposure light wraps around the surface side of the Cu seed layer 22 caused by overexposure is used. Then, the end portion of the opening portion 33 of the resist 32 is made to enter inside from the end portion of the Cu seed layer 22. The distance A from the end of the Cu seed layer 22 to the opening 33 of the resist 32, that is, the length of the LDD region 10 can be controlled by overexposure setting. Note that the opening 33 of the resist 32 is not limited to the case where the negative resist and the backside exposure are combined to form the opening 33 in a self-aligned manner, and a positive resist is used as the resist 32 and a region corresponding to the opening 33 is formed. It is also possible to perform the exposure using a mask having an opening and remove the resist 32 in the exposed portion. However, when the opening 33 is formed in a self-aligning manner by combining negative resist and backside exposure, the length of the LDD region 10 is determined by using the wraparound of exposure light, so that the LDD region is determined by mask alignment. The length of the LDD region 10 can be further shortened compared to the case where the length of the LDD region 10 is adjusted.

  After the opening 33 of the resist 32 is filled with the Cu plating layer 23, the resist 32 is removed (FIG. 2D). Next, the Cu diffusion prevention layer 21 and the Cu seed layer 22 are patterned using the Cu plating layer 23 as a mask. Thereby, the gate electrode 6 composed of three layers of the Cu diffusion preventing layer 21, the Cu seed layer 22, and the Cu plating layer 23 is obtained. Specifically, first, the Cu seed layer 22 is removed by wet etching using the Cu plating layer 23 as a mask, and the Cu diffusion preventing layer 21 is further formed by dry etching using the Cu plating layer 23 and the Cu seed layer 22 as a mask. Remove.

After patterning the Cu diffusion preventing layer 21 and the Cu seed layer 22, impurities are implanted into the semiconductor layer 4 at a low concentration using the gate electrode 6 as a mask. In the present embodiment, phosphorus is implanted into the semiconductor layer 4 by ion doping using PH ₃ as a doping gas (dose amount 3E13 / cm ² , acceleration voltage 50 KeV). An LDD region 10 as a low-concentration impurity region is formed between the channel region 9 which is a region where the impurity just under the gate electrode 6 is not implanted, and the source region 7 and the drain region 8 (FIG. 2E).

  Thereafter, the interlayer insulating layer 11, the contact hole 12, the source electrode 13 and the drain electrode 14 are formed by a normal method, thereby forming the TFT 3 having the structure shown in FIG.

  According to the manufacturing method of the first embodiment described above, the Cu plating layer 23 is formed so as to embed the inside of the opening 33 of the resist 32, so that the lateral growth of the Cu plating layer 23 is performed in the opening 33. Since it is limited by the side wall, the controllability of the width of the gate electrode 6 including the Cu plating layer 23 is improved, and variations in characteristics of the TFT 3 can be suppressed. In addition, since the LDD region 10 is formed at a position that does not overlap with the gate electrode 6, it is possible to suppress a decrease in driving capability. Furthermore, the length of the LDD region 10 can be controlled with high accuracy by utilizing the difference between the size of the opening 33 of the resist 32 and the size of the Cu seed layer 22.

<Second Embodiment>
Hereinafter, a second embodiment will be described with reference to FIGS. 3 and 4. Hereinafter, members having the same functions as those described in the first embodiment are denoted by the same reference numerals, and detailed description thereof is omitted.

  FIG. 3 shows a thin film transistor substrate 1 having a thin film transistor (TFT) 3 formed by the manufacturing method of the second embodiment. The TFT 3 includes an island-shaped semiconductor layer 4 made of polycrystalline silicon and a gate insulating layer 5 that covers the semiconductor layer 4. A gate electrode 6 is formed at a position overlapping the semiconductor layer 4 on the gate insulating layer 5. Both sides of the gate electrode 6 of the semiconductor layer 4 are a source region 7 and a drain region 8 as high concentration impurity regions which are n + regions. Between the channel region 9 located immediately below the gate electrode 6 of the semiconductor layer 4, the source region 7 and the drain region 8, an LDD region 10 as a low concentration impurity region which is an n− region is formed. An interlayer insulating layer 11 is overlaid on the gate insulating layer 5 and the gate electrode 6, and the source region 7 of the semiconductor layer 4 and the source electrode 13 are electrically connected through a contact hole 12 provided in the interlayer insulating layer 11. Is done. Further, a drain electrode 14 that is electrically connected to the drain region 8 of the semiconductor layer 4 is formed through a contact hole 12 provided in the interlayer insulating layer 11.

  The gate electrode 6 has a three-layer structure including a Cu diffusion prevention layer 21, a Cu seed layer 22 provided on the Cu diffusion prevention layer 21, and a Cu plating layer 23 provided on the Cu seed layer 22. ing.

  In the present embodiment, the Cu diffusion prevention layer 21 and the Cu seed layer 22 constituting the gate electrode 6 are formed thin. For example, the film thickness of the Cu diffusion prevention layer 21 is 20 nm, and the film thickness of the Cu seed layer 22 is 15 nm.

  Hereinafter, an example of a method for manufacturing the thin film transistor having the above-described structure will be described with reference to FIG.

First, a semiconductor layer 4, a SiO ₂ layer as a gate insulating layer 5, a Cu diffusion preventing layer 21, and a Cu seed layer 22 are formed on an insulating substrate 2 such as a transparent glass substrate. The method so far is almost the same as that of the first embodiment, but in this embodiment, the Cu diffusion prevention layer 21 and the Cu seed layer 22 are formed thin in consideration of the next impurity implantation step (for example, 20 nm / 15 nm). The film thickness of the Cu diffusion preventing layer 21 is preferably set to 10 nm to 25 nm, and the film thickness of the Cu seed layer 22 is preferably set to 5 nm to 20 nm. After the formation of the Cu seed layer 22, a resist 32 is formed on the entire surface of the Cu seed layer 22 and exposed using a mask to form an opening 33 in the resist 32. Thereafter, Cu is deposited on the Cu seed layer 22 by electroless plating. As a result, a Cu plating layer 23 is formed on the Cu seed layer 22 so as to fill the opening 33 of the resist 32 (FIG. 4A).

Next, the resist 32 for forming the Cu plating layer 23 is removed, and impurities are implanted into the semiconductor layer 4 at a high concentration using the Cu plating layer 23 as a mask (FIG. 4B). At this time, in order to achieve impurity implantation into the semiconductor layer 4 through the Cu diffusion preventing layer 21 and the Cu seed layer 22 in addition to the gate insulating layer 5, the acceleration voltage for ion implantation is set to a high condition. In this embodiment, when phosphorus is injected into the semiconductor layer 4 by ion doping using PH ₃ as a doping gas, the acceleration voltage is set to 80 keV to 150 keV.

  After the impurity implantation, wet etching is performed. By wet etching, a portion of the Cu seed layer 22 that is not covered with the Cu plating layer 23 is removed. Here, since the Cu seed layer 22 and the Cu plating layer 23 are made of Cu, which is the same metal material, the etching of the Cu plating layer 23 also proceeds simultaneously by the wet etching, as shown in FIG. 2C. A part of 23 is removed. By controlling the etching amount B at the end of the Cu plating layer 23, the length of the LDD region 10 can be controlled.

After the wet etching, the Cu diffusion prevention layer 21 is removed by dry etching using the Cu seed layer 22 and the Cu plating layer 23 as a mask. Thereby, the gate electrode 6 composed of three layers of the Cu diffusion preventing layer 21, the Cu seed layer 22, and the Cu plating layer 23 is obtained. Next, impurities are implanted into the semiconductor layer 4 at a low concentration using the gate electrode 6 as a mask. In the present embodiment, phosphorus is implanted into the semiconductor layer 4 by ion doping using PH ₃ as a doping gas (dose amount 3E13 / cm ² , acceleration voltage 50 KeV). An LDD region 10 as a low-concentration impurity region is formed between the channel region 9 which is a region where the impurity just under the gate electrode 6 is not implanted, and the source region 7 and the drain region 8 (FIG. 4D).

  Thereafter, the interlayer insulating layer 11, the contact hole 12, the source electrode 13 and the drain electrode 14 are formed by a normal method, thereby forming the TFT 3 having the structure shown in FIG.

  According to the manufacturing method of the second embodiment described above, the Cu plating layer 23 is formed so as to embed the inside of the opening 33 of the resist 32, whereby the lateral growth of the Cu plating layer 23 is caused by the opening 33. Since it is limited by the side wall, the controllability of the width of the gate electrode 6 including the Cu plating layer 23 is improved, and variations in characteristics of the TFT 3 can be suppressed. In addition, since the LDD region 10 is formed at a position that does not overlap with the gate electrode 6, it is possible to suppress a decrease in driving capability. Furthermore, the length of the LDD region 10 can be arbitrarily controlled by the wet etching conditions of the Cu plating layer 23.

<Third Embodiment>
Hereinafter, a third embodiment will be described with reference to FIGS. 5 and 6.
FIG. 5 shows a thin film transistor substrate 1 having a thin film transistor (TFT) 3 formed by the manufacturing method of the third embodiment. The TFT 3 includes an island-shaped semiconductor layer 4 made of polycrystalline silicon and a gate insulating layer 5 that covers the semiconductor layer 4. A gate electrode 6 is formed at a position overlapping the semiconductor layer 4 on the gate insulating layer 5. Both sides of the gate electrode 6 of the semiconductor layer 4 are a source region 7 and a drain region 8 as high concentration impurity regions which are n + regions. Between the channel region 9 located immediately below the gate electrode 6 of the semiconductor layer 4, the source region 7 and the drain region 8, an LDD region 10 as a low concentration impurity region which is an n− region is formed. An interlayer insulating layer 11 is overlaid on the gate insulating layer 5 and the gate electrode 6, and the source region 7 of the semiconductor layer 4 and the source electrode 13 are electrically connected through a contact hole 12 provided in the interlayer insulating layer 11. Is done. Further, a drain electrode 14 that is electrically connected to the drain region 8 of the semiconductor layer 4 is formed through a contact hole 12 provided in the interlayer insulating layer 11.

  The gate electrode 6 has a three-layer structure including a Cu diffusion prevention layer 21, a Cu seed layer 22 provided on the Cu diffusion prevention layer 21, and a Cu plating layer 23 provided on the Cu seed layer 22. ing. In this embodiment, the width of the Cu plating layer 23 constituting the gate electrode 6 differs in the thickness direction, and the width on the upper surface side is made wider than the width on the insulating substrate 2 side. That is, the Cu plating layer 23 has an overhang shape in which the end on the upper surface side protrudes outward from the end on the insulating substrate 2 side.

  Hereinafter, an example of a method for manufacturing the thin film transistor having the above-described structure will be described with reference to FIGS.

First, a semiconductor layer 4, a SiO ₂ layer as a gate insulating layer 5, a Cu diffusion preventing layer 21, and a Cu seed layer 22 are formed on an insulating substrate 2 such as a transparent glass substrate. After the formation of the Cu seed layer 22, a resist 31 for patterning the Cu diffusion preventing layer 21 and the Cu seed layer 22 is formed by photolithography (FIG. 6A).

  Next, the Cu diffusion prevention layer 21 and the Cu seed layer 22 are patterned using the resist 31 as a mask. Specifically, the Cu seed layer 22 is first removed by wet etching using the resist 31 as a mask, and then the Cu diffusion prevention layer 21 is removed by dry etching using the resist 31 and the Cu seed layer 22 as a mask ( FIG. 6 (b)). This process is the same as in the first embodiment.

  After patterning the Cu diffusion preventing layer 21 and the Cu seed layer 22, the resist 31 for patterning the Cu diffusion preventing layer 21 and the Cu seed layer 22 is removed, and then as a resist 32 for forming the Cu plating layer 23, A positive resist is formed over the entire surface covering the gate insulating layer 5, the Cu diffusion preventing layer 21 and the Cu seed layer 22. The formed resist 32 is exposed using a halftone mask 34 to remove the unexposed portion of the resist 32 and the low-exposed portion of the resist 32. As a result, the opening 33 is formed so that a part of the upper surface of the Cu seed layer 22 is exposed. The opening width of the obtained opening 33 is different in the depth direction, specifically, it is narrow on the bottom side and wide on the opening end side. In other words, the film thickness of the resist 32 is made thinner at the portion that overlaps the end portion of the gate electrode 6 that is the low-exposed portion than at the outer unexposed portion.

  After the opening 33 is formed in the resist 32, Cu is deposited on the Cu seed layer 22 by electroless plating. As a result, a Cu plating layer 23 having an overhang shape is formed on the Cu seed layer 22 (FIG. 6C).

  After the opening 33 of the resist 32 is filled with the Cu plating layer 23, the resist 32 for forming the Cu plating layer 23 is removed. Thereby, the gate electrode 6 composed of three layers of the Cu diffusion preventing layer 21, the Cu seed layer 22, and the Cu plating layer 23 is obtained (FIG. 6D).

Next, using the gate electrode 6 as a mask, impurities are implanted into the semiconductor layer 4 at a high concentration (dose amount 1.5E15 / cm ² , acceleration voltage 50 KeV). At this time, since the Cu plating layer 23 has an overhang shape, impurities are implanted at a lower concentration in the portion of the semiconductor layer 4 that is located directly below the portion where the Cu plating layer 23 projects. The As a result, the source region 7 and the drain region 8 as the high concentration impurity region and the LDD region 10 as the low concentration impurity region are simultaneously formed (FIG. 6E).

  Thereafter, the interlayer insulating layer 11, the contact hole 12, the source electrode 13 and the drain electrode 14 are formed by a normal method, thereby forming the TFT 3 having the structure shown in FIG.

  According to the manufacturing method of the third embodiment described above, the Cu plating layer 23 is formed so as to embed the inside of the opening 33 of the resist 32, so that the lateral growth of the Cu plating layer 23 is caused by the opening 33. Since it is limited by the side wall, the controllability of the width of the gate electrode 6 including the Cu plating layer 23 is improved, and variations in characteristics of the TFT 3 can be suppressed. Further, since the LDD region 10 is formed at a position where the influence of the electric field of the gate electrode 6 is weak, it is possible to suppress a decrease in driving capability. Furthermore, according to this embodiment, an LDD structure can be formed by a single impurity implantation process.

  In the first to third embodiments, the case where Cu is used as the material of the metal seed layer and the metal plating layer has been described as an example. However, the present invention is limited to this. For example, other metals such as a Cu alloy may be used.

It is a schematic sectional drawing of TFT manufactured by applying 1st Embodiment. (A)-(e) is sectional drawing for demonstrating an example of the manufacturing method of 1st Embodiment. It is a schematic sectional drawing of TFT manufactured by applying 2nd Embodiment. (A)-(d) is sectional drawing for demonstrating an example of the manufacturing method of 2nd Embodiment. It is a schematic sectional drawing of TFT manufactured by applying 3rd Embodiment. (A)-(e) is sectional drawing for demonstrating an example of the manufacturing method of 3rd Embodiment. (A)-(c) is sectional drawing for demonstrating an example of the conventional manufacturing method. (A)-(c) is sectional drawing for demonstrating the other example of the conventional manufacturing method.

Explanation of symbols

1 TFT substrate, 2 insulating substrate, 3 TFT, 4 semiconductor layer, 5 gate insulating layer, 6 gate electrode, 7 source region, 8 drain region, 9 channel region, 10 LDD region, 11 interlayer insulating layer, 12 contact hole, 13 Source electrode, 14 Drain electrode 21 Cu diffusion prevention layer, 22 Cu seed layer, 23 Cu plating layer, 31 Cu diffusion prevention layer and Cu seed layer patterning resist, 32 Cu plating layer formation resist, 33 opening, 34 halftone mask

Claims (4)

Forming a metal diffusion prevention layer on the gate insulating layer covering the semiconductor layer;
Forming a metal seed layer on the metal diffusion barrier layer;
Patterning the metal diffusion prevention layer and the metal seed layer;
Using the patterned metal diffusion prevention layer and the metal seed layer as a mask, implanting impurities into the semiconductor layer at a high concentration;
After forming a resist film covering the gate insulating layer, the metal diffusion prevention layer, and the metal seed layer, the resist is exposed to form an opening that exposes a part of the upper surface of the metal seed layer. Forming the resist;
Forming a metal plating layer by electroless plating on the metal seed layer exposed at the bottom of the opening of the resist;
After removing the resist, the metal diffusion prevention layer and the metal seed layer are patterned using the metal plating layer as a mask, and a gate electrode comprising three layers of the metal diffusion prevention layer, the metal seed layer, and the metal plating layer Forming a step;
And a step of implanting impurities into the semiconductor layer at a low concentration using the gate electrode as a mask.   In the step of forming an opening in the resist such that a part of the upper surface of the metal seed layer is exposed, a negative resist is used as the resist, and the back surface is formed using the metal diffusion prevention layer and the metal seed layer as a mask. 2. The method of manufacturing a thin film transistor according to claim 1, wherein exposure is performed from the side. Forming a metal diffusion prevention layer on the gate insulating layer covering the semiconductor layer;
Forming a metal seed layer on the metal diffusion barrier layer;
Forming a resist opening on the resist so that a part of the upper surface of the metal seed layer is exposed by exposing the resist after depositing a resist on the metal seed layer;
Forming a metal plating layer by electroless plating on the metal seed layer exposed at the bottom of the opening of the resist;
After removing the resist, a step of implanting impurities in the semiconductor layer at a high concentration using the metal plating layer as a mask;
Removing a portion of the metal seed layer not covered with the metal plating layer by wet etching, and removing a part of the metal plating layer;
Using the metal plating layer and the metal seed layer that have been wet etched as a mask, the metal diffusion prevention layer is removed by dry etching, and the gate comprises three layers, the metal diffusion prevention layer, the metal seed layer, and the metal plating layer. Forming an electrode;
And a step of implanting impurities into the semiconductor layer at a low concentration using the gate electrode as a mask. Forming a metal diffusion prevention layer on the gate insulating layer covering the semiconductor layer;
Forming a metal seed layer on the metal diffusion barrier layer;
Patterning the metal diffusion prevention layer and the metal seed layer;
A resist is formed to cover the gate insulating layer, the metal diffusion prevention layer, and the metal seed layer, and then the resist is exposed using a halftone mask to expose a part of the upper surface of the metal seed layer. And forming an opening in the resist in which the opening width on the bottom side is narrower than the opening end side;
A metal plating layer is formed by electroless plating on the metal seed layer exposed on the bottom surface of the opening of the resist, and a gate electrode including three layers of the metal diffusion prevention layer, the metal seed layer, and the metal plating layer is formed. Forming, and
And a step of injecting impurities into the semiconductor layer using the gate electrode as a mask after removing the resist.

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