JP2008130884A - Soq基板およびsoq基板の製造方法 - Google Patents
Soq基板およびsoq基板の製造方法 Download PDFInfo
- Publication number
- JP2008130884A JP2008130884A JP2006315363A JP2006315363A JP2008130884A JP 2008130884 A JP2008130884 A JP 2008130884A JP 2006315363 A JP2006315363 A JP 2006315363A JP 2006315363 A JP2006315363 A JP 2006315363A JP 2008130884 A JP2008130884 A JP 2008130884A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- soq
- film
- silicon
- hydrogen
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6758—Thin-film transistors [TFT] characterised by the insulating substrates
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
【解決手段】単結晶Si基板10の表面に酸化膜11を介して水素イオンを注入して単結晶Si基板10の表面近傍の所定の深さ(平均イオン注入深さL)に均一なイオン注入層12を形成し、これらの基板の接合面にプラズマ処理やオゾン処理を施す。単結晶Si基板10と石英基板20を貼り合わせた状態で外部衝撃を付与して単結晶シリコンのバルク14からシリコン膜13を機械的に剥離して石英基板20上に酸化膜11を介して設けられたSOQ膜13が得られる。このSOQ膜表面の更なる平滑化のために、石英のガラス転移温度以下の1000℃以下の温度で水素熱処理が施される。剥離直後の表面粗さがRMS平均値約5nmのサンプルに水素熱処理を施した後のSOQ膜の表面粗さはRMS平均値で0.3nm以下と良好である。
【選択図】図1
Description
11 酸化膜
12 イオン注入層
13 シリコン膜
14 単結晶シリコンのバルク
20 石英基板
Claims (8)
- シリコン基板の主面に水素イオン注入層を形成するイオン注入工程と、石英基板と前記シリコン基板の少なくとも一方の主面に活性化処理を施す表面処理工程と、前記石英基板と前記シリコン基板の主面同士を貼り合わせる工程と、前記貼り合せ基板の前記シリコン基板からシリコン薄膜を加熱なしに機械的剥離して前記石英基板の主面上にシリコン膜を形成する剥離工程と、前記シリコン膜に1000℃以下の温度で水素熱処理を施す工程とを備えていることを特徴とするSOQ基板の製造方法。
- 前記水素熱処理時の温度範囲が800℃以上である請求項1に記載のSOQ基板の製造方法。
- 前記水素熱処理の雰囲気中の水素濃度が0.5%以上である請求項1又は2に記載のSOQ基板の製造方法。
- 前記活性化処理がプラズマ処理又はオゾン処理の少なくとも一方で実行される
請求項1乃至3の何れか1項に記載のSOQ基板の製造方法。 - 前記貼り合わせる工程の後で前記剥離工程の前に、前記石英基板と前記シリコン基板を貼り合わせた状態で350℃以下の温度で熱処理する工程を備えている請求項1乃至4の何れか1項に記載のSOQ基板の製造方法。
- 前記シリコン基板は主面にシリコン酸化膜を有するものである請求項1乃至5の何れか1項に記載のSOQ基板の製造方法。
- 前記シリコン酸化膜の厚みが0.2μm以上である請求項6に記載のSOQ基板の製造方法。
- 請求項1乃至7の何れか1項に記載の方法で得られたSOQ基板であって、前記シリコン膜の表面の粗さがRMSで0.3nm以下であることを特徴とするSOQ基板。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006315363A JP5249511B2 (ja) | 2006-11-22 | 2006-11-22 | Soq基板およびsoq基板の製造方法 |
EP07022103.1A EP1926139B1 (en) | 2006-11-22 | 2007-11-14 | SOQ substrate and method of manufacturing SOQ substrate |
US11/984,184 US7790571B2 (en) | 2006-11-22 | 2007-11-14 | SOQ substrate and method of manufacturing SOQ substrate |
CN2007101864843A CN101188190B (zh) | 2006-11-22 | 2007-11-22 | Soq基板以及soq基板的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2006315363A JP5249511B2 (ja) | 2006-11-22 | 2006-11-22 | Soq基板およびsoq基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008130884A true JP2008130884A (ja) | 2008-06-05 |
JP5249511B2 JP5249511B2 (ja) | 2013-07-31 |
Family
ID=39155509
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2006315363A Active JP5249511B2 (ja) | 2006-11-22 | 2006-11-22 | Soq基板およびsoq基板の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7790571B2 (ja) |
EP (1) | EP1926139B1 (ja) |
JP (1) | JP5249511B2 (ja) |
CN (1) | CN101188190B (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012146902A (ja) * | 2011-01-14 | 2012-08-02 | Mitsubishi Electric Corp | 平面導波路型レーザ装置およびその製造方法 |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5143477B2 (ja) | 2007-05-31 | 2013-02-13 | 信越化学工業株式会社 | Soiウエーハの製造方法 |
JP4967842B2 (ja) * | 2007-06-18 | 2012-07-04 | セイコーエプソン株式会社 | シリコン基材の接合方法、液滴吐出ヘッド、液滴吐出装置および電子デバイス |
JP5248838B2 (ja) * | 2007-10-25 | 2013-07-31 | 信越化学工業株式会社 | 半導体基板の製造方法 |
US7820527B2 (en) * | 2008-02-20 | 2010-10-26 | Varian Semiconductor Equipment Associates, Inc. | Cleave initiation using varying ion implant dose |
CN102259829A (zh) * | 2011-07-04 | 2011-11-30 | 上海先进半导体制造股份有限公司 | 隔离腔体及其制造方法 |
WO2016006663A1 (ja) * | 2014-07-10 | 2016-01-14 | 株式会社豊田自動織機 | 半導体基板および半導体基板の製造方法 |
US12007695B2 (en) * | 2020-01-15 | 2024-06-11 | Board Of Regents, The University Of Texas System | Rapid large-scale fabrication of metasurfaces with complex unit cells |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10326883A (ja) * | 1997-03-26 | 1998-12-08 | Canon Inc | 基板及びその作製方法 |
JPH1145840A (ja) * | 1997-03-27 | 1999-02-16 | Canon Inc | 複合部材の分離方法、分離された部材、分離装置、半導体基体の作製方法および半導体基体 |
JPH11274018A (ja) * | 1998-10-09 | 1999-10-08 | Canon Inc | 複合部材の分離方法および半導体基体の作製方法 |
JP2001291851A (ja) * | 1996-11-15 | 2001-10-19 | Canon Inc | 半導体部材の製造方法 |
JP2004247610A (ja) * | 2003-02-14 | 2004-09-02 | Canon Inc | 基板の製造方法 |
JP2005101630A (ja) * | 1996-12-18 | 2005-04-14 | Canon Inc | 半導体部材の製造方法 |
JP2006210900A (ja) * | 2004-12-28 | 2006-08-10 | Shin Etsu Chem Co Ltd | Soiウエーハの製造方法及びsoiウェーハ |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57149301A (en) | 1981-03-11 | 1982-09-14 | Daiichi Togyo Kk | Novel polysaccharide having coagulating property |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
CA2194653A1 (en) * | 1997-01-08 | 1998-07-08 | Junichi Matsushita | Hydrogen heat treatment method of silicon wafers using a high-purity inert substitution gas |
US6413874B1 (en) * | 1997-12-26 | 2002-07-02 | Canon Kabushiki Kaisha | Method and apparatus for etching a semiconductor article and method of preparing a semiconductor article by using the same |
JP3697106B2 (ja) * | 1998-05-15 | 2005-09-21 | キヤノン株式会社 | 半導体基板の作製方法及び半導体薄膜の作製方法 |
JP3395661B2 (ja) * | 1998-07-07 | 2003-04-14 | 信越半導体株式会社 | Soiウエーハの製造方法 |
EP1212787B1 (en) * | 1999-08-10 | 2014-10-08 | Silicon Genesis Corporation | A cleaving process to fabricate multilayered substrates using low implantation doses |
JP4103391B2 (ja) * | 1999-10-14 | 2008-06-18 | 信越半導体株式会社 | Soiウエーハの製造方法及びsoiウエーハ |
US7094667B1 (en) * | 2000-12-28 | 2006-08-22 | Bower Robert W | Smooth thin film layers produced by low temperature hydrogen ion cut |
JP2004063730A (ja) * | 2002-07-29 | 2004-02-26 | Shin Etsu Handotai Co Ltd | Soiウェーハの製造方法 |
EP2293326A3 (en) * | 2004-06-10 | 2012-01-25 | S.O.I.TEC Silicon on Insulator Technologies S.A. | Method for manufacturing a SOI wafer |
FR2881573B1 (fr) * | 2005-01-31 | 2008-07-11 | Soitec Silicon On Insulator | Procede de transfert d'une couche mince formee dans un substrat presentant des amas de lacunes |
-
2006
- 2006-11-22 JP JP2006315363A patent/JP5249511B2/ja active Active
-
2007
- 2007-11-14 US US11/984,184 patent/US7790571B2/en active Active
- 2007-11-14 EP EP07022103.1A patent/EP1926139B1/en active Active
- 2007-11-22 CN CN2007101864843A patent/CN101188190B/zh not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001291851A (ja) * | 1996-11-15 | 2001-10-19 | Canon Inc | 半導体部材の製造方法 |
JP2005101630A (ja) * | 1996-12-18 | 2005-04-14 | Canon Inc | 半導体部材の製造方法 |
JPH10326883A (ja) * | 1997-03-26 | 1998-12-08 | Canon Inc | 基板及びその作製方法 |
JPH1145840A (ja) * | 1997-03-27 | 1999-02-16 | Canon Inc | 複合部材の分離方法、分離された部材、分離装置、半導体基体の作製方法および半導体基体 |
JPH11274018A (ja) * | 1998-10-09 | 1999-10-08 | Canon Inc | 複合部材の分離方法および半導体基体の作製方法 |
JP2004247610A (ja) * | 2003-02-14 | 2004-09-02 | Canon Inc | 基板の製造方法 |
JP2006210900A (ja) * | 2004-12-28 | 2006-08-10 | Shin Etsu Chem Co Ltd | Soiウエーハの製造方法及びsoiウェーハ |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012146902A (ja) * | 2011-01-14 | 2012-08-02 | Mitsubishi Electric Corp | 平面導波路型レーザ装置およびその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
JP5249511B2 (ja) | 2013-07-31 |
US20080119028A1 (en) | 2008-05-22 |
EP1926139A3 (en) | 2011-05-04 |
EP1926139B1 (en) | 2013-10-23 |
EP1926139A2 (en) | 2008-05-28 |
US7790571B2 (en) | 2010-09-07 |
CN101188190A (zh) | 2008-05-28 |
CN101188190B (zh) | 2012-08-08 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP2008153411A (ja) | Soi基板の製造方法 | |
JP2007220782A (ja) | Soi基板およびsoi基板の製造方法 | |
US7977209B2 (en) | Method for manufacturing SOI substrate | |
JP5249511B2 (ja) | Soq基板およびsoq基板の製造方法 | |
TWI545614B (zh) | 低溫下分離半導體層之方法 | |
JP5284576B2 (ja) | 半導体基板の製造方法 | |
JP2013534056A (ja) | 補剛層を有するガラス上半導体基板及びその作製プロセス | |
WO2007072632A1 (ja) | Soi基板およびsoi基板の製造方法 | |
TW200931507A (en) | Semiconductor wafer re-use in an exfoliation process using heat treatment | |
CN102484093B (zh) | 使用三重植入通过裂开分离硅薄膜的方法 | |
JP4720163B2 (ja) | Soiウェーハの製造方法 | |
JP2009105315A (ja) | 半導体基板の製造方法 | |
WO2003079447A1 (fr) | Procede de production de plaquettes par collage | |
JP5064693B2 (ja) | Soi基板の製造方法 | |
JP4720164B2 (ja) | Soiウェーハの製造方法 | |
JP5019852B2 (ja) | 歪シリコン基板の製造方法 | |
CN101179054B (zh) | Soq基板及其制造方法 | |
Moriceau et al. | Cleaning and polishing as key steps for Smart-cut (R) SOI process | |
JP2008263010A (ja) | Soi基板の製造方法 | |
WO2010137683A1 (ja) | Soi基板の製造方法 | |
JP2009295667A (ja) | 貼り合わせウェーハの製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20081224 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120627 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120703 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20120829 |
|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 20121113 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130131 |
|
A911 | Transfer to examiner for re-examination before appeal (zenchi) |
Free format text: JAPANESE INTERMEDIATE CODE: A911 Effective date: 20130207 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130326 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130412 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5249511 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20160419 Year of fee payment: 3 |