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JP2008060419A - Thin film transistor manufacturing method - Google Patents

Thin film transistor manufacturing method Download PDF

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JP2008060419A
JP2008060419A JP2006236828A JP2006236828A JP2008060419A JP 2008060419 A JP2008060419 A JP 2008060419A JP 2006236828 A JP2006236828 A JP 2006236828A JP 2006236828 A JP2006236828 A JP 2006236828A JP 2008060419 A JP2008060419 A JP 2008060419A
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insulating film
thin film
oxide semiconductor
semiconductor thin
film layer
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JP5128792B2 (en
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Takashi Hirao
孝 平尾
Mamoru Furuta
守 古田
Hiroshi Furuta
寛 古田
Tokiyoshi Matsuda
時宜 松田
Takahiro Hiramatsu
孝浩 平松
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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Casio Computer Co Ltd
Kochi Prefecture Sangyo Shinko Center
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/674—Thin-film transistors [TFT] characterised by the active materials
    • H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6706—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device for preventing leakage current 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6729—Thin-film transistors [TFT] characterised by the electrodes
    • H10D30/6737—Thin-film transistors [TFT] characterised by the electrodes characterised by the electrode materials
    • H10D30/6739—Conductor-insulator-semiconductor electrodes

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Abstract

【課題】 酸化物半導体薄膜層上に絶縁膜を形成した積層構造において、該酸化物半導体薄膜表面の構成元素の脱離や還元による欠陥の増大を抑制する。それにより、リーク電流の増大等の弊害を抑制することができる薄膜トランジスタの製法を提供することを解決課題とする。加えて、酸化物半導体薄膜層とゲート絶縁膜の界面特性を良好にする。それにより、リーク電流がさらに抑制された、信頼性に優れた薄膜トランジスタの製法を提供することも解決課題とする。
【解決手段】 基板上に酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層上に第一絶縁膜を形成する工程と、該第一絶縁膜上に第二絶縁膜を形成する工程を有する薄膜トランジスタの製法において、前記第二絶縁膜を成膜する前に、第一絶縁膜を酸化することを特徴とする薄膜トランジスタの製法である。
【選択図】 図３
PROBLEM TO BE SOLVED: To suppress an increase in defects due to desorption or reduction of constituent elements on the surface of an oxide semiconductor thin film in a stacked structure in which an insulating film is formed on the oxide semiconductor thin film layer. Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film transistor that can suppress adverse effects such as an increase in leakage current. In addition, the interface characteristics between the oxide semiconductor thin film layer and the gate insulating film are improved. Accordingly, another object of the present invention is to provide a method for manufacturing a thin film transistor with excellent leakage and further reduced leakage current.
A step of forming an oxide semiconductor thin film layer containing zinc oxide as a main component on a substrate, a step of forming a first insulating film on the oxide semiconductor thin film layer, and a step of forming an oxide semiconductor thin film layer on the first insulating film. In the method of manufacturing a thin film transistor including a step of forming a second insulating film, the first insulating film is oxidized before forming the second insulating film.
[Selection] Figure 3

Description

本発明は、薄膜トランジスタ（以下、TFTと略）の製法に係り、より詳しくは、酸化亜鉛を主成分とする酸化物半導体薄膜層を有する薄膜トランジスタの製法に関する。   The present invention relates to a method of manufacturing a thin film transistor (hereinafter abbreviated as TFT), and more particularly to a method of manufacturing a thin film transistor having an oxide semiconductor thin film layer containing zinc oxide as a main component.

酸化亜鉛あるいは酸化マグネシウム亜鉛等の酸化物が優れた半導体(活性層)の性質を示すことは古くから知られており、近年薄膜トランジスタ、発光デバイス、透明導電膜等の電子デバイス応用を目指し、これらの化合物を用いた半導体薄膜層の研究開発が活発化している。
酸化亜鉛や酸化マグネシウム亜鉛を半導体薄膜層として用いたTFTは、従来液晶ディスプレイに主に用いられているアモルファスシリコン(a−Si：H)を半導体薄膜層として用いたアモルファスシリコンTFTに比較して電子移動度が大きく、優れたTFT特性を有し、また、室温付近の低温でも多結晶薄膜が得られることで高い移動度が期待できる等の利点もあり、積極的な開発が進められている。 It has been known for a long time that oxides such as zinc oxide or magnesium zinc oxide exhibit excellent semiconductor (active layer) properties.In recent years, with the aim of application to electronic devices such as thin film transistors, light-emitting devices, transparent conductive films, etc. Research and development of semiconductor thin film layers using compounds has been activated.
TFTs using zinc oxide or magnesium zinc oxide as semiconductor thin film layers are electrons compared to amorphous silicon TFTs using amorphous silicon (a-Si: H), which is mainly used in conventional liquid crystal displays, as semiconductor thin film layers. Active development is underway, with advantages such as high mobility, excellent TFT characteristics, and the expectation of high mobility by obtaining a polycrystalline thin film even at low temperatures near room temperature.

酸化亜鉛を酸化物半導体薄膜層として用いたTFT(酸化亜鉛TFT)としては、トップゲート型（下記特許文献１参照）及びボトムゲート型の構造が報告されている。   As a TFT (zinc oxide TFT) using zinc oxide as an oxide semiconductor thin film layer, a top gate type (see Patent Document 1 below) and bottom gate type structure have been reported.

トップゲート型構造の一例としては、基板上より順にソース・ドレイン電極、酸化物半導体薄膜層、ゲート絶縁膜、ゲート電極を積層して形成される構造を例示することができる。
ボトムゲート型構造の一例としては、基板上より順にゲート電極、ゲート絶縁膜、酸化物半導体薄膜層、保護絶縁膜、ソース・ドレイン電極を積層して形成される構造を例示することができる。 As an example of the top gate structure, a structure in which a source / drain electrode, an oxide semiconductor thin film layer, a gate insulating film, and a gate electrode are stacked in this order from the substrate can be exemplified.
As an example of the bottom gate structure, a structure in which a gate electrode, a gate insulating film, an oxide semiconductor thin film layer, a protective insulating film, and a source / drain electrode are stacked in this order from the substrate can be exemplified.

しかしながら、トップゲート型の薄膜トランジスタの場合、酸化物半導体薄膜層の上部をチャネル部として用いるため、酸化物半導体薄膜層上へのゲート絶縁膜の成膜時に発生する熱やプラズマ雰囲気に、チャネル部が曝されるという問題が生じる。
特に、酸化物半導体薄膜層の主成分である酸化亜鉛は耐熱性が充分でないため、ゲート絶縁膜の成膜に伴う熱履歴により、酸化物半導体薄膜層表面（チャネル部）近傍からの構成元素である亜鉛や酸素の脱離が生じる。酸化物半導体薄膜から、その構成元素である亜鉛や酸素が脱離することで、欠陥が生じ、膜質を低下させる。
また、ゲート絶縁膜成膜時には、熱工程を経ると同時に、酸化物半導体表面がプラズマ雰囲気に曝される。該プラズマは高エネルギー粒子を含むため、酸化物半導体表面にダメージを誘起する。さらに、該プラズマが水素や水酸基といった還元性雰囲気の場合には、酸化物半導体表面を還元し、酸素欠損を引き起こし、欠陥となり、さらに膜質を低下させる。
これらの欠陥は電気的には浅い不純物準位を形成し、酸化物半導体薄膜層の低抵抗化を引き起こす。そのため、酸化亜鉛をトップゲート型の薄膜トランジスタの活性層に用いた場合、ゲート電圧を印加しなくてもドレイン電流が流れるノーマリーオン型すなわちデプレッション型の動作となり、欠陥準位の増大とともに、しきい電圧が小さくなり、リーク電流が増大する。
また、欠陥は活性層となる酸化亜鉛中のキャリアのトラップとなり、薄膜トランジスタの電子移動度の低下を引き起こす。
さらに、ゲート絶縁膜を有機金属等を原料ガスとするプラズマ化学気相成長法にて、例えば２００℃以下といった低温域で成膜した場合等、膜中に炭素が取り込まれることとなるが、当該炭素はゲート絶縁膜の膜質を低下させる要因となり、リーク電流の増大や信頼性の悪化といった課題を生じる。 However, in the case of a top-gate thin film transistor, since the upper portion of the oxide semiconductor thin film layer is used as a channel portion, the channel portion is exposed to heat or plasma atmosphere generated when the gate insulating film is formed on the oxide semiconductor thin film layer. The problem of being exposed arises.
In particular, since zinc oxide, which is the main component of the oxide semiconductor thin film layer, does not have sufficient heat resistance, it is a constituent element from the vicinity of the surface of the oxide semiconductor thin film layer (channel portion) due to the thermal history associated with the formation of the gate insulating film. Some desorption of zinc and oxygen occurs. The constituent elements zinc and oxygen are desorbed from the oxide semiconductor thin film, so that defects are generated and the film quality is deteriorated.
Further, when the gate insulating film is formed, the surface of the oxide semiconductor is exposed to a plasma atmosphere at the same time as a thermal process. Since the plasma contains high-energy particles, damage is induced on the surface of the oxide semiconductor. Further, in the case where the plasma is a reducing atmosphere such as hydrogen or a hydroxyl group, the surface of the oxide semiconductor is reduced, causing oxygen vacancies, resulting in defects, and further reducing the film quality.
These defects form an electrically shallow impurity level and cause a reduction in resistance of the oxide semiconductor thin film layer. Therefore, when zinc oxide is used for the active layer of a top gate type thin film transistor, it becomes a normally-on type, that is, a depletion type operation in which a drain current flows without applying a gate voltage. The voltage decreases and the leakage current increases.
Further, the defect becomes a trap of carriers in zinc oxide serving as an active layer, and causes a decrease in electron mobility of the thin film transistor.
Furthermore, when the gate insulating film is formed in a low temperature region such as 200 ° C. or less by a plasma chemical vapor deposition method using an organic metal or the like as a source gas, carbon is taken into the film. Carbon becomes a factor that degrades the quality of the gate insulating film, and causes problems such as an increase in leakage current and deterioration in reliability.

一方、ボトムゲート型の薄膜トランジスタにおいても、酸化物半導体薄膜層上に保護絶縁膜を成膜する際、トップゲート型の薄膜トランジスタと同様の理由で、酸化物半導体薄膜層及び保護絶縁膜自体に欠陥が生じ、膜質が低下する。また、保護絶縁膜に炭素が含まれることによっても、保護絶縁膜の膜質が低下する。それにより、酸化物半導体薄膜層と第一保護絶縁膜の界面特性が悪化する。該界面はチャネルと反対面で、バックチャネルにあたる部分であるが、バックチャネルの界面特性の悪化によってもリーク電流の増大といった問題が生じる。   On the other hand, in the case of a bottom gate type thin film transistor, when a protective insulating film is formed on the oxide semiconductor thin film layer, the oxide semiconductor thin film layer and the protective insulating film itself have defects for the same reason as the top gate type thin film transistor. Occurs and the film quality decreases. Further, the film quality of the protective insulating film also deteriorates when carbon is contained in the protective insulating film. This deteriorates the interface characteristics between the oxide semiconductor thin film layer and the first protective insulating film. The interface is the opposite surface of the channel and corresponds to the back channel. However, the deterioration of the interface characteristics of the back channel also causes a problem of increased leakage current.

特開２００３−２９８０６２号公報JP 2003-298062 A

本発明は上記問題に鑑みてなされたものであり、酸化物半導体薄膜層上に絶縁膜を形成した積層構造において、該酸化物半導体薄膜表面の構成元素の脱離や還元による欠陥の増大を抑制する。それにより、リーク電流の増大等の弊害を抑制することができる薄膜トランジスタの製法を提供することを解決課題とする。
加えて、酸化物半導体薄膜層とゲート絶縁膜の界面特性を良好にする。それにより、リーク電流がさらに抑制された、信頼性に優れた薄膜トランジスタの製法を提供することも解決課題とする。 The present invention has been made in view of the above problems, and suppresses an increase in defects due to desorption and reduction of constituent elements on the surface of the oxide semiconductor thin film in a stacked structure in which an insulating film is formed on the oxide semiconductor thin film layer. To do. Accordingly, it is an object of the present invention to provide a method for manufacturing a thin film transistor that can suppress adverse effects such as an increase in leakage current.
In addition, the interface characteristics between the oxide semiconductor thin film layer and the gate insulating film are improved. Accordingly, another object of the present invention is to provide a method for manufacturing a thin film transistor with excellent leakage and further reduced leakage current.

請求項１に係る発明は、基板上に酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層上に第一絶縁膜を形成する工程と、該第一絶縁膜上に第二絶縁膜を形成する工程を有する薄膜トランジスタの製法において、前記第二絶縁膜を成膜する前に、第一絶縁膜を酸化することを特徴とする薄膜トランジスタの製法に関する。   The invention according to claim 1 includes a step of forming an oxide semiconductor thin film layer containing zinc oxide as a main component on a substrate, a step of forming a first insulating film on the oxide semiconductor thin film layer, and the first The present invention relates to a method of manufacturing a thin film transistor, characterized in that a first insulating film is oxidized before forming the second insulating film in the method of manufacturing a thin film transistor including a step of forming a second insulating film on the insulating film.

請求項２に係る発明は、前記第一絶縁膜を前記酸化物半導体薄膜層の上側表面のみを被覆するようにパターン形成し、その後、該第一絶縁膜及び該酸化物半導体薄膜層を酸化することを特徴とする請求項１記載の薄膜トランジスタの製法に関する。   According to a second aspect of the present invention, the first insulating film is patterned so as to cover only the upper surface of the oxide semiconductor thin film layer, and then the first insulating film and the oxide semiconductor thin film layer are oxidized. The method for producing a thin film transistor according to claim 1.

請求項３に係る発明は、前記第一絶縁膜が炭素を含むことを特徴する請求項１又は２記載の薄膜トランジスタの製法に関する。   The invention according to claim 3 relates to the method of manufacturing a thin film transistor according to claim 1 or 2, wherein the first insulating film contains carbon.

請求項４に係る発明は、前記第一絶縁膜が酸素を構成元素に含む化合物からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタの製法に関する。   The invention according to claim 4 relates to the method of manufacturing a thin film transistor according to any one of claims 1 to 3, wherein the first insulating film is made of a compound containing oxygen as a constituent element.

請求項５に係る発明は、前記第一絶縁膜が酸素を構成元素に含まない化合物からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタの製法に関する。   The invention according to claim 5 relates to the method of manufacturing a thin film transistor according to any one of claims 1 to 3, wherein the first insulating film is made of a compound not containing oxygen as a constituent element.

請求項６に係る発明は、前記第一絶縁膜の酸化を、少なくとも酸素を構成元素として含むプラズマに第一絶縁膜を暴露させることにより行うことを特徴とする請求項１乃至５いずれか記載の薄膜トランジスタの製法に関する。   The invention according to claim 6 is characterized in that the oxidation of the first insulating film is performed by exposing the first insulating film to plasma containing at least oxygen as a constituent element. The present invention relates to a method for manufacturing a thin film transistor.

請求項７に係る発明は、前記酸化物半導体薄膜層の形成と前記第一絶縁膜の形成を、真空中で連続して行うことを特徴とする請求項１乃至６いずれか記載の薄膜トランジスタの製法に関する。   The invention according to claim 7 is characterized in that the formation of the oxide semiconductor thin film layer and the formation of the first insulating film are carried out continuously in a vacuum. About.

請求項１に係る発明によれば、第二絶縁膜を成膜する前に、第一絶縁膜を酸化することにより、第一絶縁膜とともに第一絶縁膜に被覆された酸化物半導体薄膜層も酸化することができる。そのため、トップゲート型の薄膜トランジスタにおいて、第一絶縁膜の成膜に伴う熱処理により生じた酸化物半導体薄膜層中の欠陥が減少し、酸化物半導体薄膜層の低抵抗化、導電率の減少を抑制することができる。そのため、低しきい電圧で、リーク電流の抑制された電子移動度の高い薄膜トランジスタとなる。
また、酸化物半導体薄膜層中の欠陥が減少することにより、酸化物半導体薄膜層の膜質も向上する。加えて、第一絶縁膜を酸化することで、第一絶縁膜中の欠陥準位も減少するので、第一絶縁膜の膜質も向上する。そのため、酸化物半導体薄膜層との界面特性が向上し、リーク電流がさらに抑制された薄膜トランジスタとなる。
また、ボトムゲート型の薄膜トランジスタでも、酸化物半導体薄膜層のバックチャネル側において、欠陥の減少に伴う第一絶縁膜との界面特性の向上が起こり、リーク電流の抑制といった効果を十分に奏することができる。 According to the first aspect of the invention, the oxide semiconductor thin film layer covered with the first insulating film together with the first insulating film is obtained by oxidizing the first insulating film before forming the second insulating film. Can be oxidized. Therefore, in the top gate type thin film transistor, defects in the oxide semiconductor thin film layer caused by the heat treatment accompanying the formation of the first insulating film are reduced, and the resistance of the oxide semiconductor thin film layer is reduced and the decrease in conductivity is suppressed. can do. Therefore, a thin film transistor having a high electron mobility with a low threshold voltage and suppressed leakage current is obtained.
In addition, since the defects in the oxide semiconductor thin film layer are reduced, the film quality of the oxide semiconductor thin film layer is also improved. In addition, since the defect level in the first insulating film is reduced by oxidizing the first insulating film, the film quality of the first insulating film is also improved. Therefore, the interface characteristics with the oxide semiconductor thin film layer are improved, and a thin film transistor in which leakage current is further suppressed is obtained.
In addition, even in a bottom-gate thin film transistor, the interface characteristics with the first insulating film accompanying the reduction in defects occur on the back channel side of the oxide semiconductor thin film layer, and the effect of suppressing leakage current can be sufficiently achieved. it can.

請求項２に係る発明によれば、第一絶縁膜を酸化物半導体薄膜層の上側表面のみを被覆するようにパターン形成し、その後、該第一絶縁膜を酸化することにより、酸化物半導体薄膜層側面を酸化することができる。そのため、酸化物半導体薄膜層中の欠陥をより減少させることができ、リーク電流をさらに抑制することができる。   According to the invention of claim 2, the oxide semiconductor thin film is formed by patterning the first insulating film so as to cover only the upper surface of the oxide semiconductor thin film layer, and then oxidizing the first insulating film. The layer sides can be oxidized. Therefore, defects in the oxide semiconductor thin film layer can be further reduced, and leakage current can be further suppressed.

請求項３に係る発明によれば、第一絶縁膜が炭素を含む場合、第一絶縁膜を酸化することで、炭素と酸素が結合する。それにより、炭素が酸素と共に第一絶縁膜から脱離し、炭素の含有量の少ない良好な第一絶縁膜を形成することができる。そのため、第一絶縁膜の膜質を向上させることができ、第一絶縁膜と酸化物半導体薄膜層の界面が良好なものとなる。   According to the invention of claim 3, when the first insulating film contains carbon, carbon and oxygen are bonded by oxidizing the first insulating film. Accordingly, carbon is desorbed from the first insulating film together with oxygen, and a good first insulating film with a low carbon content can be formed. Therefore, the film quality of the first insulating film can be improved, and the interface between the first insulating film and the oxide semiconductor thin film layer becomes good.

請求項４に係る発明によれば、第一絶縁膜が酸素を構成元素に含む化合物からなる場合、第一絶縁膜に存在する酸素欠損等の欠陥を酸化処理により補い、それにより欠陥準位が減少する。そのため、第一絶縁膜の膜質が向上すると同時に、酸化物半導体薄膜層との界面が良好なものとなる。   According to the invention of claim 4, when the first insulating film is made of a compound containing oxygen as a constituent element, defects such as oxygen vacancies existing in the first insulating film are compensated for by oxidation treatment, whereby the defect level is reduced. Decrease. Therefore, the film quality of the first insulating film is improved and the interface with the oxide semiconductor thin film layer is improved.

請求項５に係る発明によれば、第一絶縁膜が酸素を構成元素に含まない化合物からなる場合、第一絶縁膜に存在する未結合手等の欠陥を酸化処理により酸素で補償し、欠陥準位が減少する。そのため、第一絶縁膜の膜質が向上すると同時に、酸化物半導体薄膜層との界面が良好なものとなる。   According to the fifth aspect of the invention, when the first insulating film is made of a compound that does not contain oxygen as a constituent element, defects such as dangling bonds existing in the first insulating film are compensated with oxygen by oxidation treatment, and the defect The level decreases. Therefore, the film quality of the first insulating film is improved and the interface with the oxide semiconductor thin film layer is improved.

請求項６に係る発明によれば、第一ゲート絶縁膜の酸化を構成元素として少なくとも酸素を含むプラズマに暴露することで行うことにより、広範囲に亘り、第一ゲート絶縁膜及び第一ゲート絶縁膜に被膜された酸化物半導体薄膜層を酸化することができる。   According to the invention of claim 6, the first gate insulating film and the first gate insulating film are extensively exposed by exposing the first gate insulating film to plasma containing at least oxygen as a constituent element. The oxide semiconductor thin film layer coated on the surface can be oxidized.

請求項７に係る発明によれば、酸化物半導体薄膜層の形成と第一絶縁膜の形成を、真空中で連続して行うことにより酸化物半導体薄膜層と第一絶縁膜の界面特性がさらに良好となり、よりリーク電流を抑制することができる。   According to the seventh aspect of the present invention, the formation of the oxide semiconductor thin film layer and the formation of the first insulating film are continuously performed in a vacuum, whereby the interface characteristics between the oxide semiconductor thin film layer and the first insulating film are further increased. The leakage current can be further suppressed.

本発明の第一実施例に係る薄膜トランジスタについて、図１に基づいて以下に説明する。
なお、本発明に係る薄膜トランジスタは該実施例の構造によって、何ら限定されるものではない。 A thin film transistor according to a first embodiment of the present invention will be described below with reference to FIG.
The thin film transistor according to the present invention is not limited by the structure of the embodiment.

本発明の第一実施例に係る薄膜トランジスタ１００は、基板１、一対のソース・ドレイン電極２、酸化物半導体薄膜層３、第一ゲート絶縁膜４、コンタクト部５ａ、第二ゲート絶縁膜６、一対のソース・ドレイン外部電極２ａ、ゲート電極７、表示電極８を有しており、図１に示すように、これら各構成を積層して形成されている。   A thin film transistor 100 according to a first embodiment of the present invention includes a substrate 1, a pair of source / drain electrodes 2, an oxide semiconductor thin film layer 3, a first gate insulating film 4, a contact portion 5a, a second gate insulating film 6, and a pair. Source / drain external electrode 2a, gate electrode 7, and display electrode 8, each of which is laminated as shown in FIG.

薄膜トランジスタ１００は、図１に示す通り、ガラス（SiO2とAl2O3を主成分とする無アルカリガラス）からなる基板１上に形成されている。
基板１の材料は、ガラスに限定されず、プラスチックや金属箔に絶縁体をコーティングしたもの等、絶縁体であれば使用可能である。 As shown in FIG. 1, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass mainly composed of SiO 2 and Al 2 O 3 ).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulator such as a plastic or metal foil coated with an insulator.

基板１上には、一対のソース・ドレイン電極２が積層されている。この一対のソース・ドレイン電極２は、基板１上面に間隙を有して配置されている。
ソース・ドレイン電極２は、例えば、インジウムスズ酸化物(ITO)、n＋ZnO等の導電性酸化物、金属、もしくは前記導電性酸化物により少なくとも一部を被覆された金属により形成される。 A pair of source / drain electrodes 2 are stacked on the substrate 1. The pair of source / drain electrodes 2 are disposed on the upper surface of the substrate 1 with a gap.
The source / drain electrode 2 is formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n + ZnO, a metal, or a metal at least partially covered with the conductive oxide.

酸化物半導体薄膜層３は、基板１とソース・ドレイン電極２上に積層されている。
酸化物半導体薄膜層３は、一対のソース・ドレイン電極２の電極間にチャネルを形成するように配置されており、酸化亜鉛を主成分とする酸化物半導体から形成されている。ここで、酸化亜鉛を主成分とする酸化物半導体とは、真性の酸化亜鉛の他、Li、Na、N、C等のp型ドーパント及びB、Al、Ga、In等のn型ドーパントがドーピングされた酸化亜鉛およびMg、Be、In、Sn等がドーピングされた酸化亜鉛を含む。
なお、酸化物半導体薄膜層３は、各ソース・ドレイン電極２上に形成されている部分の厚さが、一対のソース・ドレイン電極２間に形成された部分よりも薄く図示されているが、これは単なる図示の都合であって、実際には、両者の厚さはほぼ同一である。 The oxide semiconductor thin film layer 3 is stacked on the substrate 1 and the source / drain electrodes 2.
The oxide semiconductor thin film layer 3 is disposed so as to form a channel between the pair of source / drain electrodes 2, and is formed of an oxide semiconductor containing zinc oxide as a main component. Here, the oxide semiconductor containing zinc oxide as a main component is doped with intrinsic zinc oxide, p-type dopants such as Li, Na, N, and C and n-type dopants such as B, Al, Ga, and In. Zinc oxide and zinc oxide doped with Mg, Be, In, Sn or the like.
In the oxide semiconductor thin film layer 3, the thickness of the portion formed on each source / drain electrode 2 is shown to be thinner than the portion formed between the pair of source / drain electrodes 2. This is merely for the convenience of illustration, and in reality, the thicknesses of both are substantially the same.

第一ゲート絶縁膜４は、酸化物半導体薄膜層３の上側表面のみを被覆するように形成されている。この第一ゲート絶縁膜４は、ゲート絶縁膜の一部として設けられ、酸化物半導体薄膜層３を製造工程でのレジスト剥離液から保護する保護膜としての役割をも果たすものである。   The first gate insulating film 4 is formed so as to cover only the upper surface of the oxide semiconductor thin film layer 3. The first gate insulating film 4 is provided as a part of the gate insulating film, and also serves as a protective film for protecting the oxide semiconductor thin film layer 3 from a resist stripping solution in the manufacturing process.

また第一ゲート絶縁膜４は、第二ゲート絶縁膜６の成膜前に酸化される。これにより、第一ゲート絶縁膜４だけでなく酸化物半導体薄膜層３も酸化することができる。酸化物半導体薄膜層３を酸化することにより、酸化物半導体薄膜層中の欠陥が減少し、酸化物半導体薄膜層の低抵抗化を抑制することができる。そのため、リーク電流の抑制された薄膜トランジスタとなる。また、欠陥が減少することにより、キャリア濃度が増加し、高移動度の薄膜トランジスタとなる。   The first gate insulating film 4 is oxidized before the second gate insulating film 6 is formed. Thereby, not only the first gate insulating film 4 but also the oxide semiconductor thin film layer 3 can be oxidized. By oxidizing the oxide semiconductor thin film layer 3, defects in the oxide semiconductor thin film layer can be reduced, and a reduction in resistance of the oxide semiconductor thin film layer can be suppressed. Therefore, a thin film transistor in which leakage current is suppressed is obtained. In addition, when the number of defects is reduced, the carrier concentration is increased and a thin film transistor with high mobility is obtained.

また、第一ゲート絶縁膜４が酸素を含む化合物で構成されている場合、第一ゲート絶縁膜４には酸素欠損等の欠陥が存在する。この時、第一ゲート絶縁膜４を酸化することで、第一ゲート絶縁膜中の欠陥が酸素により補償され、欠陥準位が減少する。それにより、膜質が向上する。酸素を含む化合物としては、酸化珪素、酸窒化珪素、酸化アルミニウム、酸化マグネシウム、酸化イットリウム、酸化ハフニウム等が挙げられる。
また、第一ゲート絶縁膜４が酸素を含まない化合物で構成されている場合、第一ゲート絶縁膜４には未結合手等の欠陥が存在する。当該欠陥は酸素欠損ではないが、第一ゲート絶縁膜４を酸化することで、欠陥を酸素で補償し、欠陥準位が減少する。それにより、膜質が向上する。酸素を含まない化合物としては窒化珪素等が挙げられる。 Further, when the first gate insulating film 4 is made of a compound containing oxygen, the first gate insulating film 4 has defects such as oxygen vacancies. At this time, by oxidizing the first gate insulating film 4, defects in the first gate insulating film are compensated by oxygen, and the defect level is reduced. Thereby, the film quality is improved. Examples of the compound containing oxygen include silicon oxide, silicon oxynitride, aluminum oxide, magnesium oxide, yttrium oxide, and hafnium oxide.
Further, when the first gate insulating film 4 is composed of a compound not containing oxygen, the first gate insulating film 4 has defects such as dangling bonds. Although the defect is not an oxygen vacancy, by oxidizing the first gate insulating film 4, the defect is compensated with oxygen, and the defect level is reduced. Thereby, the film quality is improved. Examples of the compound not containing oxygen include silicon nitride.

また、例えば、有機材料を用いてプラズマ化学気相成長法にて、２００℃以下といった低温域で第一ゲート絶縁膜を成膜した場合、有機材料の乖離が十分に行われない。そのため、第一ゲート絶縁膜４に不純物である炭素が取り込まれ、第一ゲート絶縁膜の膜質が悪化する。しかしながら、第一ゲート絶縁膜４を酸化することによって、炭素と酸素が結合し、ゲート絶縁膜から脱離する。それにより、不純物である炭素の少ない絶縁膜となり、良質なゲート絶縁膜となる。   Further, for example, when the first gate insulating film is formed at a low temperature range of 200 ° C. or lower by plasma chemical vapor deposition using an organic material, the organic material is not sufficiently separated. Therefore, carbon as an impurity is taken into the first gate insulating film 4 and the film quality of the first gate insulating film is deteriorated. However, when the first gate insulating film 4 is oxidized, carbon and oxygen are combined and desorbed from the gate insulating film. As a result, an insulating film with a small amount of carbon as an impurity is formed, and a high-quality gate insulating film is obtained.

上記したように、ゲート絶縁膜４の膜質が向上し、加えて、酸化物半導体薄膜層３も欠陥の減少により膜質が向上する。そのため、酸化物半導体薄膜層３と第一ゲート絶縁膜４との界面特性が向上し、リーク電流の抑制された信頼性の高い薄膜トランジスタとなる。
第一ゲート絶縁膜４の厚みは、酸化処理によって酸化物半導体薄膜層３の上表面まで酸化できる程度の薄い膜厚である必要がある。酸化物半導体薄膜層表面まで酸化されなければ、酸化物半導体薄膜層表面の欠陥が減少せず、本発明の効果が半減するからである。具体的な膜厚は、酸化処理の方法にもよるが、酸素を構成元素として含むプラズマで暴露することによって酸化処理を行う場合、100Å程度が好ましい。 As described above, the film quality of the gate insulating film 4 is improved, and in addition, the film quality of the oxide semiconductor thin film layer 3 is also improved by reducing defects. Therefore, the interface characteristics between the oxide semiconductor thin film layer 3 and the first gate insulating film 4 are improved, and a highly reliable thin film transistor in which leakage current is suppressed is obtained.
The thickness of the first gate insulating film 4 needs to be thin enough to oxidize to the upper surface of the oxide semiconductor thin film layer 3 by oxidation treatment. This is because if the oxide semiconductor thin film layer surface is not oxidized, defects on the oxide semiconductor thin film layer surface are not reduced, and the effect of the present invention is halved. Although the specific film thickness depends on the oxidation treatment method, it is preferably about 100 mm when the oxidation treatment is performed by exposure with plasma containing oxygen as a constituent element.

第二ゲート絶縁膜６は、一対のソース・ドレイン電極２、酸化物半導体薄膜層３側面及び第一ゲート絶縁膜４の表面全面を被覆するように積層されている。このように、第二ゲート絶縁膜６が積層されることにより、酸化物半導体薄膜層３表面を第一ゲート絶縁膜４にて、側面を第二ゲート絶縁膜６にて完全に被覆することができる。
第二ゲート絶縁膜６の厚みは、例えば、200〜400nmに形成され、好ましくは、約300nmに形成される。 The second gate insulating film 6 is laminated so as to cover the pair of source / drain electrodes 2, the side surfaces of the oxide semiconductor thin film layer 3, and the entire surface of the first gate insulating film 4. Thus, by laminating the second gate insulating film 6, the surface of the oxide semiconductor thin film layer 3 can be completely covered with the first gate insulating film 4 and the side surface can be completely covered with the second gate insulating film 6. it can.
The thickness of the second gate insulating film 6 is formed, for example, to 200 to 400 nm, and preferably about 300 nm.

第二ゲート絶縁膜６は、酸化珪素（SiOx）膜、酸窒化珪素（SiON）膜、窒化珪素（SiNx）膜あるいは窒化珪素（SiNx）に酸素もしくは酸素を構成元素に含む化合物を用いて酸素をドーピングした膜により形成される。この第二ゲート絶縁膜６としては、酸化珪素化合物（SiOx）や酸窒化珪素（SiON）に比較して誘電率の大きい、SiNxに酸素あるいは酸素を構成元素として含む化合物、例えばN2O、を用いて酸素をドーピングした膜が好ましく用いられる。これにより、誘電率が高く、酸化物半導体薄膜層の保護の観点からも優れた薄膜トランジスタとなるからである。
第一ゲート絶縁膜４及び第二ゲート絶縁膜６は、例えばプラズマ化学気相成長（PCVD)法により形成される。 The second gate insulating film 6 is formed using a silicon oxide (SiOx) film, a silicon oxynitride (SiON) film, a silicon nitride (SiNx) film, or silicon nitride (SiNx) using oxygen or a compound containing oxygen as a constituent element. It is formed by a doped film. As the second gate insulating film 6, a compound having a dielectric constant larger than that of a silicon oxide compound (SiOx) or silicon oxynitride (SiON) and containing oxygen or oxygen as a constituent element in SiNx, such as N 2 O, is used. A film doped with oxygen is preferably used. This is because the thin film transistor has a high dielectric constant and is excellent from the viewpoint of protecting the oxide semiconductor thin film layer.
The first gate insulating film 4 and the second gate insulating film 6 are formed by plasma chemical vapor deposition (PCVD), for example.

一対のソース・ドレイン外部電極２ａはそれぞれ対応したソース・ドレイン電極２とコンタクト部５ａを介して接続される。   The pair of source / drain external electrodes 2a are connected to the corresponding source / drain electrodes 2 via the contact portions 5a.

ゲート電極７は、第二ゲート絶縁膜６上に形成されている。このゲート電極７は、薄膜トランジスタに印加するゲート電圧により酸化物半導体薄膜層３中の電子密度を制御する役割を果たすものである。
ゲート電極７はCr、Tiに例示される金属膜からなる。 The gate electrode 7 is formed on the second gate insulating film 6. The gate electrode 7 serves to control the electron density in the oxide semiconductor thin film layer 3 by a gate voltage applied to the thin film transistor.
The gate electrode 7 is made of a metal film exemplified by Cr and Ti.

表示電極８は、液晶ディスプレイに用いる液晶に薄膜トランジスタを介して電圧を印加するために形成される。この電極は可視光に対する高い透過率が要求されるため、インジウムスズ酸化物(ITO)などを用いた酸化物導電性薄膜が形成される。なお、図１では、省略されているが、表示電極８は第二ゲート絶縁膜６上をゲート電極７と逆方向に延出されている。   The display electrode 8 is formed in order to apply a voltage to the liquid crystal used for the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, an oxide conductive thin film using indium tin oxide (ITO) or the like is formed. Although omitted in FIG. 1, the display electrode 8 extends on the second gate insulating film 6 in the direction opposite to the gate electrode 7.

本発明の第一実施例に係る薄膜トランジスタ（TFT）の製造方法について、図２及び図３に基づいて以下に説明する。但し、図２及び３は、スペースの関係で二つの図面に分かれているが、連続した工程を示している。   A method of manufacturing a thin film transistor (TFT) according to the first embodiment of the present invention will be described below with reference to FIGS. However, FIGS. 2 and 3 are divided into two drawings due to space, but show a continuous process.

まず、図２（１）に示される如く、基板１上全面にマグネトロンスパッタリング法等により、Ti、Cr等の金属薄膜を例えば100nmの厚みで形成した後、この薄膜に、フォトリソグラフィー法を用いて一対のソース・ドレイン電極２を形成する。   First, as shown in FIG. 2A, after a metal thin film such as Ti or Cr is formed to a thickness of, for example, 100 nm on the entire surface of the substrate 1 by a magnetron sputtering method or the like, the photolithography method is applied to the thin film. A pair of source / drain electrodes 2 is formed.

図２（２）に示す如く、基板１および一対のソース・ドレイン電極２上の全面に酸化物半導体薄膜層３として、酸化亜鉛を主成分とする半導体薄膜、好適には真性酸化亜鉛を例えば50〜100nm程度の膜厚で形成する。   As shown in FIG. 2B, a semiconductor thin film containing zinc oxide as a main component, preferably intrinsic zinc oxide, is used as the oxide semiconductor thin film layer 3 on the entire surface of the substrate 1 and the pair of source / drain electrodes 2, for example, 50 It is formed with a film thickness of about 100 nm.

図２（３）に示される如く、酸化物半導体薄膜層３上に第一ゲート絶縁膜４を形成する。このとき、酸化物半導体薄膜層３及び第一ゲート絶縁膜４の形成を真空中で連続して行うことが好ましい。これにより、酸化物半導体薄膜層３と第一ゲート絶縁膜４の界面特性を良好に維持することができるからである。   As shown in FIG. 2 (3), the first gate insulating film 4 is formed on the oxide semiconductor thin film layer 3. At this time, it is preferable to continuously form the oxide semiconductor thin film layer 3 and the first gate insulating film 4 in a vacuum. This is because the interface characteristics between the oxide semiconductor thin film layer 3 and the first gate insulating film 4 can be maintained well.

図２（４）に示される如く、前記第一ゲート絶縁膜４上にフォトレジストをコーティングし、パターニングされたフォトレジスト４ａを形成し、このフォトレジスト４aをマスクとして、前記第一ゲート絶縁膜４をSF6等のガスを用いてドライエッチングし、次いで0．2％HNO3溶液にて酸化物半導体薄膜層３に対しウェットエッチングを行う。 As shown in FIG. 2 (4), a photoresist is coated on the first gate insulating film 4 to form a patterned photoresist 4a. Using the photoresist 4a as a mask, the first gate insulating film 4 is formed. Is dry-etched using a gas such as SF 6 and then wet etching is performed on the oxide semiconductor thin film layer 3 with a 0.2% HNO 3 solution.

続きの工程を図３を用いて説明する。
図３（１）は酸化物半導体薄膜層３のウェットエッチング後にフォトレジスト４ａを除去した断面図を示しており、酸化物半導体薄膜層３と同一形状の第一ゲート絶縁膜４を有するTFT活性層領域が形成されている。第一ゲート絶縁膜４は、酸化物半導体薄膜層３との界面形成に加えて、活性領域をパターン形成する時の酸化物半導体薄膜層を保護する役目も同時に果たしている。すなわち、活性層パターニング後のフォトレジスト４ａを剥離する場合に使用するレジスト剥離液が酸化物半導体薄膜層３表面に接すると、薄膜表面や結晶粒界をエッチングで荒らしてしまうが、第一ゲート絶縁膜４が酸化物半導体薄膜層３表面に存在することで、フォトリソグラフィー工程におけるレジスト剥離液といった各種薬液に対する保護絶縁膜としての機能を果たし、酸化物半導体薄膜層３の表面あれを防ぐことができる。 The subsequent steps will be described with reference to FIG.
FIG. 3A is a cross-sectional view in which the photoresist 4a is removed after wet etching of the oxide semiconductor thin film layer 3, and the TFT active layer having the first gate insulating film 4 having the same shape as the oxide semiconductor thin film layer 3 is shown. A region is formed. In addition to forming an interface with the oxide semiconductor thin film layer 3, the first gate insulating film 4 also plays a role of protecting the oxide semiconductor thin film layer when patterning the active region. That is, if the resist stripping solution used for stripping the photoresist 4a after patterning the active layer contacts the surface of the oxide semiconductor thin film layer 3, the surface of the thin film and the crystal grain boundary are roughened by etching, but the first gate insulation The presence of the film 4 on the surface of the oxide semiconductor thin film layer 3 serves as a protective insulating film against various chemicals such as a resist stripping solution in a photolithography process, and can prevent surface roughness of the oxide semiconductor thin film layer 3. .

酸化物半導体薄膜層３及び第一ゲート絶縁膜４のパターン形成後、第一ゲート絶縁膜４を酸化する。当該酸化は、構成元素に酸素を含むプラズマに第一ゲート絶縁膜４を暴露させることで行うことが好ましい。それにより、広範囲に亘り、第一ゲート絶縁膜４及び第一ゲート絶縁膜４に被膜された酸化物半導体薄膜層３を酸化することができるからである。当該プラズマは、酸素（O２）或いは亜酸化窒素（N２O）といった酸化性ガスを用いて発生させることができる。
第一ゲート絶縁膜４の成膜時には熱工程を伴う。酸化物半導体薄膜層の主成分である酸化亜鉛は耐熱性が充分でないため、当該熱処理により、酸化物半導体薄膜層表面（チャネル部）近傍からの構成元素である亜鉛や酸素の脱離が生じる。そのため、酸化物半導体薄膜層３に欠陥が生じ、膜質が低下する。
また、第一ゲート絶縁膜４の成膜時には、熱工程を経ると同時に、酸化物半導体表面がプラズマ雰囲気に曝される。該プラズマが水素や水酸基といった還元性雰囲気の場合には、酸化物半導体表面を還元するので、酸素欠損を引き起こし、欠陥となり、膜質が低下する。当該酸化処理は上記ゲート絶縁膜４の成膜による欠陥の影響を緩和するために行われる。以下、当該酸化処理の効果について詳しく述べる。
上記したように、ゲート絶縁膜４の成膜に伴い、酸化物半導体薄膜層中の亜鉛や酸素が脱離し、欠陥が形成される。当該欠陥は電気的に浅い不純物準位を形成するため、酸化物半導体薄膜層の低抵抗化を引き起こす。そのため、薄膜トランジスタはノーマリーオン型すなわちデプレッション型の動作となり、欠陥の増大とともに、しきい電圧が小さくなり、リーク電流が増大することとなる。
また、当該欠陥は活性層となる酸化亜鉛中のキャリアのトラップとなり、薄膜トランジスタの電子移動度の低下を引き起こす。
そこで、第一ゲート絶縁膜４を成膜後、第一ゲート絶縁膜とともに酸化物半導体薄膜層３も酸化することで、酸素が欠陥を補償し、欠陥が減少するので、欠陥による上記影響を抑えることができる。それにより、リーク電流の抑制された高移動度の薄膜トランジスタとなる。
また、酸化物半導体薄膜層中の欠陥が減少することにより、酸化物半導体薄膜層の膜質も向上する。 After the oxide semiconductor thin film layer 3 and the first gate insulating film 4 are formed, the first gate insulating film 4 is oxidized. The oxidation is preferably performed by exposing the first gate insulating film 4 to plasma containing oxygen as a constituent element. This is because the first gate insulating film 4 and the oxide semiconductor thin film layer 3 coated on the first gate insulating film 4 can be oxidized over a wide range. The plasma can be generated using an oxidizing gas such as oxygen (O 2 ) or nitrous oxide (N 2 O).
When the first gate insulating film 4 is formed, a thermal process is involved. Since zinc oxide, which is a main component of the oxide semiconductor thin film layer, does not have sufficient heat resistance, the heat treatment causes desorption of zinc and oxygen as constituent elements from the vicinity of the oxide semiconductor thin film layer surface (channel portion). Therefore, defects occur in the oxide semiconductor thin film layer 3 and the film quality is deteriorated.
Further, when the first gate insulating film 4 is formed, the surface of the oxide semiconductor is exposed to a plasma atmosphere at the same time as a thermal process. In the case where the plasma is a reducing atmosphere such as hydrogen or a hydroxyl group, the oxide semiconductor surface is reduced, which causes oxygen deficiency, resulting in defects, and film quality is degraded. The oxidation treatment is performed in order to reduce the influence of defects due to the formation of the gate insulating film 4. Hereinafter, the effect of the oxidation treatment will be described in detail.
As described above, with the formation of the gate insulating film 4, zinc and oxygen in the oxide semiconductor thin film layer are desorbed and defects are formed. The defect forms an electrically shallow impurity level, which causes a reduction in resistance of the oxide semiconductor thin film layer. Therefore, the thin film transistor is normally on, that is, a depletion type operation. As the defect increases, the threshold voltage decreases and the leakage current increases.
In addition, the defect becomes a trap of carriers in zinc oxide serving as an active layer, which causes a decrease in electron mobility of the thin film transistor.
Therefore, after the first gate insulating film 4 is formed, the oxide semiconductor thin film layer 3 is oxidized together with the first gate insulating film, so that oxygen compensates for defects and reduces the defects. be able to. Accordingly, a thin film transistor with high mobility in which leakage current is suppressed is obtained.
In addition, since the defects in the oxide semiconductor thin film layer are reduced, the film quality of the oxide semiconductor thin film layer is also improved.

加えて、第一ゲート絶縁膜４自体にも酸素欠損や未結合手といった欠陥が存在するが、酸化処理を行うことで、第一ゲート絶縁膜中の欠陥準位も減少する。それにより、第一ゲート絶縁膜の膜質も向上し、第一ゲート絶縁膜４と酸化物半導体薄膜層３の界面特性が良好となる。以下、欠陥準位が減少する過程を、ゲート絶縁膜を構成する化合物が酸素を含む場合と、含まない場合に分けて、説明する。
第一ゲート絶縁膜４が酸素を含む化合物で構成されている場合、第一ゲート絶縁膜４中には酸素欠損等の欠陥が存在する。この時、第一ゲート絶縁膜４を酸化することにより、酸素が補充され、欠陥準位が減少する。
また、第一ゲート絶縁膜４が酸素を含まない化合物で構成されている場合、未結合手等の欠陥が存在する。当該欠陥は酸素欠損ではないが、第一ゲート絶縁膜４を酸化することで、酸素が当該欠陥を補償し、欠陥準位が減少する。 In addition, defects such as oxygen vacancies and dangling bonds also exist in the first gate insulating film 4 itself, but the defect level in the first gate insulating film is reduced by performing the oxidation treatment. Thereby, the film quality of the first gate insulating film is also improved, and the interface characteristics between the first gate insulating film 4 and the oxide semiconductor thin film layer 3 are improved. Hereinafter, the process of decreasing the defect level will be described separately for the case where the compound constituting the gate insulating film contains oxygen and the case where it does not contain oxygen.
When the first gate insulating film 4 is composed of a compound containing oxygen, the first gate insulating film 4 has defects such as oxygen vacancies. At this time, by oxidizing the first gate insulating film 4, oxygen is replenished and the defect level is reduced.
Further, when the first gate insulating film 4 is composed of a compound not containing oxygen, defects such as dangling bonds exist. Although the defect is not an oxygen deficiency, by oxidizing the first gate insulating film 4, oxygen compensates the defect and the defect level decreases.

また、第一ゲート絶縁膜４に炭素が含まれる場合、炭素が不純物となり、第一ゲート絶縁膜の膜質が悪化する。しかしながら、第一ゲート絶縁膜４を酸化することによって、炭素と酸素が結合し、ゲート絶縁膜から脱離する。それにより、不純物である炭素が減少し、良質なゲート絶縁膜となる。これにより、さらにリーク電流が抑制された信頼性に優れた薄膜トランジスタとなる。
第一ゲート絶縁膜４に炭素が含まれる場合として、例えば、有機シリコンや有機アルミニウム等の有機金属を原料として、プラズマ化学気相成長法にて、２００℃以下といった低温域でゲート絶縁膜４を成膜する場合が考えられる。有機金属は低温域では乖離が十分に行われず、膜中に炭素を含むこととなる。有機シリコンとしては、テトラエトキシシラン(TEOS)、テトラメチルシラン(TMS)、ジメチルジメトキシシラン(DMDMOS)、テトラメトキシシラン(TMOS)、テトラエチルシラン(TES)、オクトメチルサイクロテトラシロキサン(OMCTS)、テトラプロポキシシラン(TPOS)、テトラメチルサイクロテトラシロキサン(TMCTS)、ヘキサメチルジシラザン(HMDS)等が挙げられ、有機アルミニウムとしては、テトラメチルアルミニウム(TMA)、テトラエチルアルミ二ウム(TEA)等が挙げられる。
なお、当該酸化処理は酸化物半導体薄膜層と第一ゲート絶縁膜のパターン形成前に行ってもよいが、パターン形成後に行うことによって、酸化物半導体薄膜層側面も酸化することができる。それにより、酸化物半導体薄膜層の側面付近の欠陥をより抑えることができ、リーク電流をさらに抑制することができる。 Further, when the first gate insulating film 4 contains carbon, carbon becomes an impurity, and the film quality of the first gate insulating film is deteriorated. However, when the first gate insulating film 4 is oxidized, carbon and oxygen are combined and desorbed from the gate insulating film. Thereby, carbon as an impurity is reduced, and a high-quality gate insulating film is obtained. As a result, a thin film transistor having excellent reliability in which leakage current is further suppressed is obtained.
In the case where carbon is contained in the first gate insulating film 4, for example, the gate insulating film 4 is formed in a low temperature region of 200 ° C. or less by plasma chemical vapor deposition using an organic metal such as organic silicon or organic aluminum as a raw material. The case where it forms into a film is considered. Organic metals are not sufficiently dissociated at low temperatures and contain carbon in the film. Examples of organic silicon include tetraethoxysilane (TEOS), tetramethylsilane (TMS), dimethyldimethoxysilane (DMDMOS), tetramethoxysilane (TMOS), tetraethylsilane (TES), octomethylcyclotetrasiloxane (OMCTS), tetrapropoxy Examples include silane (TPOS), tetramethylcyclotetrasiloxane (TMCTS), and hexamethyldisilazane (HMDS). Examples of the organic aluminum include tetramethylaluminum (TMA) and tetraethylaluminum (TEA).
Note that the oxidation treatment may be performed before the pattern formation of the oxide semiconductor thin film layer and the first gate insulating film, but the side surface of the oxide semiconductor thin film layer can also be oxidized by performing the oxidation treatment after the pattern formation. Accordingly, defects near the side surface of the oxide semiconductor thin film layer can be further suppressed, and leakage current can be further suppressed.

第一ゲート絶縁膜４の酸化処理後、図３（２）に示す如く、基板１、ソース・ドレイン電極２、酸化物半導体薄膜層３、および第一ゲート絶縁膜４上全面に第二ゲート絶縁膜６を形成し、その後フォトリソグラフィー法を用いて一対のソース・ドレイン電極２上にコンタクトホール５を開口する。この場合、第二ゲート絶縁膜６は第一ゲート絶縁膜４（界面制御型絶縁膜）と同様の条件で、プラズマ化学気相成長（PCVD）法を用いて形成することが望ましい。   After the oxidation treatment of the first gate insulating film 4, as shown in FIG. 3B, the second gate insulation is formed on the entire surface of the substrate 1, the source / drain electrodes 2, the oxide semiconductor thin film layer 3, and the first gate insulating film 4. A film 6 is formed, and then a contact hole 5 is opened on the pair of source / drain electrodes 2 by photolithography. In this case, it is desirable to form the second gate insulating film 6 by using a plasma enhanced chemical vapor deposition (PCVD) method under the same conditions as the first gate insulating film 4 (interface control type insulating film).

最後に図３（３）に示す如く、第二ゲート絶縁膜６上にCr、Tiといった金属膜からなるゲート電極７を形成し、ゲート電極７と同一材料にて一対のソース・ドレイン外部電極２ａをコンタクト部５aを介してそれぞれに対応したソース・ドレイン電極２と接続するよう形成する。その後、インジウムスズ酸化物(ITO)等からなる表示電極８を形成することでTFTアレイが完成する。   Finally, as shown in FIG. 3 (3), a gate electrode 7 made of a metal film such as Cr or Ti is formed on the second gate insulating film 6, and a pair of source / drain external electrodes 2 a made of the same material as the gate electrode 7. Are connected to the corresponding source / drain electrodes 2 via the contact portions 5a. Thereafter, a display electrode 8 made of indium tin oxide (ITO) or the like is formed to complete the TFT array.

次いで、本発明の第二実施例に係る薄膜トランジスタの構造について図４を用いて以下説明する。第二実施例の構造は、液晶ディスプレイの駆動素子として現在事業化されているボトムゲート型アモルファスシリコンTFTの構造と類似しており、該アモルファスシリコンTFTの製造のプロセスを応用できるので、新たな設備投資を削減して酸化亜鉛TFTの事業化を図れる点で有効である。   Next, the structure of the thin film transistor according to the second embodiment of the present invention will be described with reference to FIG. The structure of the second embodiment is similar to the structure of a bottom gate type amorphous silicon TFT currently commercialized as a driving element for a liquid crystal display, and the process for manufacturing the amorphous silicon TFT can be applied. This is effective in reducing investment and commercializing zinc oxide TFTs.

図４は本発明の第二実施例に係る薄膜トランジスタ１０１の構造を示す断面図である。薄膜トランジスタ１０１は、基板９、ゲート電極１０、ゲート絶縁膜１１、酸化物半導体薄膜層１２、第一保護絶縁膜１３、第二保護絶縁膜１４、一対のソース・ドレイン電極１５、オーバーコート絶縁膜１６を有してなり、図４に示すように、上記の各構成を積層して形成されている。   FIG. 4 is a sectional view showing the structure of the thin film transistor 101 according to the second embodiment of the present invention. The thin film transistor 101 includes a substrate 9, a gate electrode 10, a gate insulating film 11, an oxide semiconductor thin film layer 12, a first protective insulating film 13, a second protective insulating film 14, a pair of source / drain electrodes 15, and an overcoat insulating film 16. As shown in FIG. 4, each of the above components is stacked.

薄膜トランジスタ１０１は、図４に示す通り、基板９上に形成される。
基板９上には、ゲート電極１０が形成されている。 The thin film transistor 101 is formed on the substrate 9 as shown in FIG.
A gate electrode 10 is formed on the substrate 9.

ゲート絶縁膜１１は、ゲート電極１０を被覆するように基板９上の全面に積層されている。
酸化物半導体薄膜層１２は、ゲート電極１０を横断してゲート絶縁膜１１の一部を被覆するように形成されている。酸化物半導体薄膜層１２は酸化亜鉛を主成分とする酸化物半導体から形成されている。 The gate insulating film 11 is laminated on the entire surface of the substrate 9 so as to cover the gate electrode 10.
The oxide semiconductor thin film layer 12 is formed so as to cover a part of the gate insulating film 11 across the gate electrode 10. The oxide semiconductor thin film layer 12 is formed of an oxide semiconductor containing zinc oxide as a main component.

第一保護絶縁膜１３は、酸化物半導体薄膜層１２の上面を被覆するように積層されている。第一保護絶縁膜１３は、酸化亜鉛からなる酸化物半導体薄膜層１２を損傷及び還元脱離から保護するために設けられるが、製造工程において酸化物半導体薄膜層１２をレジスト剥離液から保護する保護絶縁膜としての役割も果たしている。   The first protective insulating film 13 is laminated so as to cover the upper surface of the oxide semiconductor thin film layer 12. The first protective insulating film 13 is provided to protect the oxide semiconductor thin film layer 12 made of zinc oxide from damage and reductive desorption, but protects the oxide semiconductor thin film layer 12 from the resist stripping solution in the manufacturing process. It also plays a role as an insulating film.

また第一保護絶縁膜１３は、第二保護絶縁膜１４の成膜前に酸化される。これにより、第一保護絶縁膜１３だけでなく酸化物半導体薄膜層１２も酸化することができる。酸化物半導体薄膜層１２及び第一保護絶縁膜１３が酸化されることにより、欠陥が減少し、膜質が向上する。それにより、酸化物半導体薄膜層１２と第一保護絶縁膜１３との界面（バックチャネルにあたる部分）の特性が向上し、リーク電流の抑制された薄膜トランジスタとなる。また、例えば、有機材料を用いてプラズマ化学気相成長法にて、２００℃以下といった低温域で第一保護絶縁膜１３を成膜した場合等、第一保護絶縁膜１３に炭素が含有されることとなるが、第一保護絶縁膜１３が酸化されることにより、炭素が酸素と結合し、脱離する。それにより、第一保護絶縁膜の膜厚がより向上し、リーク電流がさらに抑制される。
第一保護絶縁膜１３の厚みは、酸化処理によって酸化物半導体薄膜層１２の上表面まで酸化できる程度の薄い膜厚である必要がある。酸化物半導体薄膜層表面まで酸化されなければ、酸化物半導体薄膜層表面の欠陥が減少せず、本発明の効果が半減するからである。具体的な膜厚としては、酸化処理の方法にもよるが、酸素を構成元素として含むプラズマで暴露することによって酸化処理を行う場合、100Å程度が好ましい。 The first protective insulating film 13 is oxidized before the second protective insulating film 14 is formed. Thereby, not only the first protective insulating film 13 but also the oxide semiconductor thin film layer 12 can be oxidized. Oxidation of the oxide semiconductor thin film layer 12 and the first protective insulating film 13 reduces defects and improves film quality. Thereby, the characteristics of the interface (portion corresponding to the back channel) between the oxide semiconductor thin film layer 12 and the first protective insulating film 13 are improved, and a thin film transistor in which leakage current is suppressed is obtained. Further, for example, when the first protective insulating film 13 is formed in a low temperature range of 200 ° C. or less by plasma chemical vapor deposition using an organic material, the first protective insulating film 13 contains carbon. However, when the first protective insulating film 13 is oxidized, carbon is combined with oxygen and desorbed. Thereby, the film thickness of the first protective insulating film is further improved, and the leakage current is further suppressed.
The thickness of the first protective insulating film 13 needs to be thin enough to oxidize to the upper surface of the oxide semiconductor thin film layer 12 by oxidation treatment. This is because if the oxide semiconductor thin film layer surface is not oxidized, defects on the oxide semiconductor thin film layer surface are not reduced, and the effect of the present invention is halved. Although the specific film thickness depends on the method of oxidation treatment, it is preferably about 100 mm when the oxidation treatment is performed by exposure with plasma containing oxygen as a constituent element.

第二保護絶縁膜１４は、第一保護絶縁膜１３の全面及び酸化物半導体薄膜層１２の側面を被覆するように積層されている。
第二保護絶縁膜１４を設けることで、第一保護絶縁膜１３が被覆していない酸化物半導体薄膜層１２の側表面を確実に被覆することができる。 The second protective insulating film 14 is laminated so as to cover the entire surface of the first protective insulating film 13 and the side surfaces of the oxide semiconductor thin film layer 12.
By providing the second protective insulating film 14, the side surface of the oxide semiconductor thin film layer 12 that is not covered by the first protective insulating film 13 can be reliably covered.

一対のソース・ドレイン電極１５は第一保護絶縁膜１３、第二保護絶縁膜１４に開口したコンタクトホールを介して、酸化物半導体薄膜層１２に接するように互いに間隔を有して形成される。   The pair of source / drain electrodes 15 are formed at a distance from each other so as to be in contact with the oxide semiconductor thin film layer 12 through contact holes opened in the first protective insulating film 13 and the second protective insulating film 14.

オーバーコート絶縁膜１６は、薄膜トランジスタ１０１のデバイス保護の目的で設けられ、薄膜トランジスタの全面を被覆するように積層されている。
オーバーコート絶縁膜１６を設けることにより、薄膜トランジスタ１０１のデバイス全体をより確実に保護することができる。 The overcoat insulating film 16 is provided for the purpose of protecting the device of the thin film transistor 101, and is laminated so as to cover the entire surface of the thin film transistor.
By providing the overcoat insulating film 16, the entire device of the thin film transistor 101 can be more reliably protected.

次に、本発明の第二実施例に係るボトムゲート型TFTの製法について、図５に基づいて以下に説明する。   Next, the manufacturing method of the bottom gate type TFT according to the second embodiment of the present invention will be described below with reference to FIG.

図５（１）に示される如く、基板９上全面に、マグネトロンスパッタリング法等により形成し、フォトリソグラフィーによりゲート電極１０を形成する。   As shown in FIG. 5A, a gate electrode 10 is formed on the entire surface of the substrate 9 by a magnetron sputtering method or the like, and by photolithography.

図４（２）に示される如く、ゲート電極１０を被覆するように基板９上の全面にゲート絶縁膜１１を形成する。
このゲート絶縁膜１１の形成方法は、特に限定されないが、大面積基板への成膜が可能なプラズマ化学気相成長（PCVD）法を用いることが好ましい。
ゲート絶縁膜１１の成膜後に、酸素（O2）あるいは亜酸化窒素（N2O）といった酸化性ガスを用いたプラズマにより、基板表面を清浄化することが好ましい。特に、酸化性ガスとして酸素を用いた場合は、ArやXe、He、Krといった希ガスを酸素に添加したプラズマを用いることで、酸素ラジカルの発生量が増大し、酸化物半導体薄膜層表面に吸着された有機成分や水分に対するクリーニング効率が増大すると同時に、添加ガスによるスパッタ効果により酸化物半導体薄膜層表面の金属不純物が除去可能となるため、より好ましい。 As shown in FIG. 4B, a gate insulating film 11 is formed on the entire surface of the substrate 9 so as to cover the gate electrode 10.
The method for forming the gate insulating film 11 is not particularly limited, but it is preferable to use a plasma enhanced chemical vapor deposition (PCVD) method capable of forming a film over a large area substrate.
After the gate insulating film 11 is formed, the substrate surface is preferably cleaned with plasma using an oxidizing gas such as oxygen (O 2 ) or nitrous oxide (N 2 O). In particular, when oxygen is used as the oxidizing gas, the amount of oxygen radicals generated is increased by using a plasma in which a rare gas such as Ar, Xe, He, or Kr is added to oxygen, and the surface of the oxide semiconductor thin film layer is increased. The cleaning efficiency for the adsorbed organic component and moisture is increased, and at the same time, metal impurities on the surface of the oxide semiconductor thin film layer can be removed by the sputtering effect of the additive gas, which is more preferable.

ゲート絶縁膜１１の形成後、図５（３）に示される如く、ゲート絶縁膜１１の全面に酸化物半導体薄膜層１２を例えば50〜100nm程度の膜厚で形成する。酸化物半導体薄膜層１２としては、酸化亜鉛を主成分とする半導体薄膜、好適には真性酸化亜鉛が用いられる。   After the formation of the gate insulating film 11, as shown in FIG. 5C, the oxide semiconductor thin film layer 12 is formed on the entire surface of the gate insulating film 11 with a film thickness of, for example, about 50 to 100 nm. As the oxide semiconductor thin film layer 12, a semiconductor thin film containing zinc oxide as a main component, preferably intrinsic zinc oxide is used.

酸化物半導体薄膜層１２の形成後、図５（４）に示される如く、酸化物半導体薄膜層１２の全面を被覆する第一保護絶縁膜１３を形成する。このとき、ゲート絶縁膜１１、酸化物半導体薄膜層１２、第一保護絶縁膜１３を真空中にて連続して形成することが好ましい。これにより、各層の界面が良好に維持できるからである。   After the oxide semiconductor thin film layer 12 is formed, a first protective insulating film 13 that covers the entire surface of the oxide semiconductor thin film layer 12 is formed as shown in FIG. At this time, it is preferable to continuously form the gate insulating film 11, the oxide semiconductor thin film layer 12, and the first protective insulating film 13 in a vacuum. This is because the interface of each layer can be maintained well.

第一保護絶縁膜１３の形成後、酸化物半導体薄膜層１２及び第一保護絶縁膜１３をチャネルの形状に加工する。形状加工は、酸化物半導体薄膜層１２及び第一保護絶縁膜１３がゲート電極１０の上部を含むゲート絶縁膜の一部を被覆するように施される。この形状加工により、チャネル層としての酸化物半導体薄膜層１２の機能を保ちつつ、第二保護絶縁膜１４によって酸化物半導体薄膜層１２を完全に被覆する構造が実現できる。   After the formation of the first protective insulating film 13, the oxide semiconductor thin film layer 12 and the first protective insulating film 13 are processed into a channel shape. The shape processing is performed so that the oxide semiconductor thin film layer 12 and the first protective insulating film 13 cover a part of the gate insulating film including the upper portion of the gate electrode 10. By this shape processing, a structure in which the oxide semiconductor thin film layer 12 is completely covered with the second protective insulating film 14 can be realized while maintaining the function of the oxide semiconductor thin film layer 12 as the channel layer.

具体的には、第一保護絶縁膜１３の上表面にフォトレジストをコーティングし、パターニングされたフォトレジストをマスクとして、第一保護絶縁膜１３をエッチングし、次いでパターニングされた第一保護絶縁膜１３をマスクとして酸化物半導体薄膜層１２に対しウェットエッチングを行う。   Specifically, a photoresist is coated on the upper surface of the first protective insulating film 13, the first protective insulating film 13 is etched using the patterned photoresist as a mask, and then the patterned first protective insulating film 13 is used. The oxide semiconductor thin film layer 12 is wet-etched using as a mask.

酸化物半導体薄膜層１２及び第一保護絶縁膜１３のパターン形成後、第一保護絶縁膜１３を酸化する。当該酸化は、構成元素として酸素を含むプラズマに第一保護絶縁膜１３を暴露させることで行うことが好ましい。それにより、広範囲に亘り、第一保護絶縁膜１３及び第一保護絶縁膜１３に被膜された酸化物半導体薄膜層１２を酸化することができるからである。
第一保護絶縁膜１３を酸化することで、酸化物半導体薄膜層１２も酸化される。それにより、酸化物半導体薄膜層１２及び第一保護絶縁膜１３中の欠陥が減少し、膜質が向上する。そのため、酸化物半導体薄膜層との界面特性が向上する。当該界面はバックチャネルにあたる部分であるが、バックチャネルの特性が向上するので、リーク電流が抑制された薄膜トランジスタとなる。
加えて、例えば、有機材料を用いてプラズマ化学気相成長法にて、２００℃以下といった低温域で第一保護絶縁膜を成膜した場合、第一保護絶縁膜１３中に炭素が含まれ、膜質が悪化するが、酸化処理を行うことにより、炭素が酸素と結合して脱離する。それにより、第一保護絶縁膜１３の膜質が向上し、酸化物半導体薄膜層１２との界面特性の向上により、さらに、リーク電流が抑制される。第一保護絶縁膜中に炭素が含まれる場合としては、有機金属を原料ガスとして成膜した場合が挙げられる。
なお、当該酸化処理は酸化物半導体薄膜層１２と第一保護絶縁膜１３のパターン形成前に行ってもよいが、パターン形成後に行うことによって、酸化物半導体薄膜層１２側面も酸化することができる。それにより、酸化物半導体薄膜層１２の側面付近の欠陥をより抑えることができ、リーク電流をさらに抑制することができる。 After the oxide semiconductor thin film layer 12 and the first protective insulating film 13 are formed, the first protective insulating film 13 is oxidized. The oxidation is preferably performed by exposing the first protective insulating film 13 to plasma containing oxygen as a constituent element. This is because the first protective insulating film 13 and the oxide semiconductor thin film layer 12 coated on the first protective insulating film 13 can be oxidized over a wide range.
By oxidizing the first protective insulating film 13, the oxide semiconductor thin film layer 12 is also oxidized. Thereby, defects in the oxide semiconductor thin film layer 12 and the first protective insulating film 13 are reduced, and the film quality is improved. Therefore, interface characteristics with the oxide semiconductor thin film layer are improved. Although the interface corresponds to a back channel, the back channel characteristics are improved, so that a thin film transistor in which leakage current is suppressed is obtained.
In addition, for example, when the first protective insulating film is formed at a low temperature range of 200 ° C. or less by plasma chemical vapor deposition using an organic material, carbon is contained in the first protective insulating film 13, Although the film quality is deteriorated, carbon is bonded to oxygen and desorbed by the oxidation treatment. Thereby, the film quality of the first protective insulating film 13 is improved, and the leakage current is further suppressed by improving the interface characteristics with the oxide semiconductor thin film layer 12. As a case where carbon is contained in the first protective insulating film, a case where an organic metal is used as a raw material gas is cited.
The oxidation treatment may be performed before the pattern formation of the oxide semiconductor thin film layer 12 and the first protective insulating film 13, but the side surface of the oxide semiconductor thin film layer 12 can also be oxidized by performing the oxidation treatment after the pattern formation. . Thereby, defects near the side surface of the oxide semiconductor thin film layer 12 can be further suppressed, and leakage current can be further suppressed.

第一保護絶縁膜１３の酸化処理後、図５（５）に示される如く、第一保護絶縁膜１３、酸化物半導体薄膜層１２及びゲート絶縁膜１１の全面を被覆するように第二保護絶縁膜１４を形成する。   After the oxidation treatment of the first protective insulating film 13, as shown in FIG. 5 (5), the second protective insulating film is formed so as to cover the entire surface of the first protective insulating film 13, the oxide semiconductor thin film layer 12, and the gate insulating film 11. A film 14 is formed.

第二保護絶縁膜１４の成膜後、図５（６）に示される如く、後述するソース・ドレイン電極１５と酸化物半導体薄膜層１２の接触部分として間隔を有して二つのコンタクトホールを形成する。
該コンタクトホールはフォトリソグラフィーとエッチングにより、第一保護絶縁膜１３及び第二保護絶縁膜１４を貫通して酸化物半導体薄膜層１２の表面に達する部分まで形成する。 After the formation of the second protective insulating film 14, as shown in FIG. 5 (6), two contact holes are formed at intervals as contact portions between the source / drain electrodes 15 and the oxide semiconductor thin film layer 12 described later. To do.
The contact hole is formed by photolithography and etching up to a portion that reaches the surface of the oxide semiconductor thin film layer 12 through the first protective insulating film 13 and the second protective insulating film 14.

コンタクトホールを形成した後、一対のソース・ドレイン電極１５を形成する。
一対のソース・ドレイン電極１５は前記コンタクトホール部をそれぞれ充填して、間隔を有して形成される。 After the contact holes are formed, a pair of source / drain electrodes 15 are formed.
The pair of source / drain electrodes 15 are formed with a space between the contact hole portions.

最後に、薄膜トランジスタ上に、オーバーコート絶縁膜１６を形成することで、第二実施例のTFTが完成する。   Finally, the overcoat insulating film 16 is formed on the thin film transistor, thereby completing the TFT of the second embodiment.

本発明に係る製法により得られた薄膜トランジスタは、優れた性能を有するものであり、液晶表示装置等の駆動素子として好適に使用可能なものである。   The thin film transistor obtained by the production method according to the present invention has excellent performance and can be suitably used as a driving element for a liquid crystal display device or the like.

本発明に係る製法により得られる薄膜トランジスタ（TFT）の第一実施例の形態を示す断面図である。It is sectional drawing which shows the form of the 1st Example of the thin-film transistor (TFT) obtained by the manufacturing method which concerns on this invention. 本発明に係る薄膜トランジスタ（TFT）の製法の第一実施例の一形態を経時的に示す断面図であり、（１）基板上にソース・ドレイン電極を成形した構造の断面図（２）酸化物半導体薄膜層を被膜した構造の断面図（３）第一ゲート絶縁膜を被覆した構造の断面図（４）フォトレジストを形成した構造の断面図よりなる。BRIEF DESCRIPTION OF THE DRAWINGS It is sectional drawing which shows one form of 1st Example of the manufacturing method of the thin-film transistor (TFT) based on this invention with time, (1) Sectional drawing of the structure which shape | molded the source / drain electrode on the board | substrate (2) Oxide Cross-sectional view of a structure coated with a semiconductor thin film layer (3) Cross-sectional view of a structure covered with a first gate insulating film (4) Cross-sectional view of a structure formed with a photoresist. 本発明に係る薄膜トランジスタ（TFT）の製法の第一実施例の図２の続きの一形態を経時的に示す断面図であり、（１）酸化物半導体薄膜層及び第一ゲート絶縁膜をパターニングした構造の断面図（２）第二ゲート絶縁膜及びコンタクトホールを形成した構造の断面図（３）ゲート電極、コンタクト部、ソース・ドレイン外部電極、表示電極を形成した構造の断面図よりなる。It is sectional drawing which shows one form of the continuation of FIG. 2 of the 1st Example of the manufacturing method of the thin-film transistor (TFT) based on this invention with time, (1) The oxide semiconductor thin film layer and the 1st gate insulating film were patterned Cross-sectional view of structure (2) Cross-sectional view of structure in which second gate insulating film and contact hole are formed (3) Cross-sectional view of structure in which gate electrode, contact portion, source / drain external electrode and display electrode are formed. 本発明の第二実施例に係る薄膜トランジスタ（TFT）の形態を示す断面図である。It is sectional drawing which shows the form of the thin-film transistor (TFT) based on the 2nd Example of this invention. 本発明の第二実施例に係る薄膜トランジスタ（TFT）の製法の一形態を経時的に示す断面図であり、（１）基板上にゲート電極を形成した構造の断面図（２）ゲート絶縁膜を被膜した構造の断面図（３）酸化物半導体薄膜層を被膜した構造の断面図（４）第一保護絶縁膜を被膜した構造の断面図（５）酸化物半導体薄膜層及び第一保護絶縁膜を形状加工した後、第二保護絶縁膜を形成した構造の断面図（６）ソース・ドレイン電極、オーバーコート絶縁膜を形成した構造の断面図よりなる。It is sectional drawing which shows one form of the manufacturing method of the thin-film transistor (TFT) based on 2nd Example of this invention over time, (1) Sectional drawing of the structure in which the gate electrode was formed on the board | substrate (2) Gate insulating film Cross-sectional view of structure coated (3) Cross-sectional view of structure coated with oxide semiconductor thin film layer (4) Cross-sectional view of structure coated with first protective insulating film (5) Oxide semiconductor thin film layer and first protective insulating film FIG. 6 is a cross-sectional view of the structure in which the second protective insulating film is formed after the shape processing is performed.

符号の説明Explanation of symbols

１、９ 基板
３、１２ 酸化物半導体薄膜層
４ 第一ゲート絶縁膜
６ 第二ゲート絶縁膜
１３ 第一保護絶縁膜
１４ 第二保護絶縁膜
１００ トップゲート型薄膜トランジスタ
１０１ ボトムゲート型薄膜トランジスタ
DESCRIPTION OF SYMBOLS 1, 9 Substrate 3, 12 Oxide semiconductor thin film layer 4 First gate insulating film 6 Second gate insulating film 13 First protective insulating film 14 Second protective insulating film 100 Top gate type thin film transistor 101 Bottom gate type thin film transistor

Claims (7)

基板上に酸化亜鉛を主成分とする酸化物半導体薄膜層を形成する工程と、該酸化物半導体薄膜層上に第一絶縁膜を形成する工程と、該第一絶縁膜上に第二絶縁膜を形成する工程を有する薄膜トランジスタの製法において、前記第二絶縁膜を成膜する前に、第一絶縁膜を酸化することを特徴とする薄膜トランジスタの製法。 Forming an oxide semiconductor thin film layer containing zinc oxide as a main component on a substrate; forming a first insulating film on the oxide semiconductor thin film layer; and a second insulating film on the first insulating film. A method of manufacturing a thin film transistor, comprising: oxidizing a first insulating film before forming the second insulating film. 前記第一絶縁膜を前記酸化物半導体薄膜層の上側表面のみを被覆するようにパターン形成し、その後、該第一絶縁膜及び該酸化物半導体薄膜層を酸化することを特徴とする請求項１記載の薄膜トランジスタの製法。 The first insulating film is patterned so as to cover only the upper surface of the oxide semiconductor thin film layer, and then the first insulating film and the oxide semiconductor thin film layer are oxidized. The manufacturing method of the thin-film transistor of description. 前記第一絶縁膜が炭素を含むことを特徴する請求項１又は２記載の薄膜トランジスタの製法。 The method of manufacturing a thin film transistor according to claim 1, wherein the first insulating film contains carbon. 前記第一絶縁膜が酸素を構成元素に含む化合物からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタの製法。 4. The method of manufacturing a thin film transistor according to claim 1, wherein the first insulating film is made of a compound containing oxygen as a constituent element. 前記第一絶縁膜が酸素を構成元素に含まない化合物からなることを特徴とする請求項１乃至３いずれか記載の薄膜トランジスタの製法。 4. The method of manufacturing a thin film transistor according to claim 1, wherein the first insulating film is made of a compound not containing oxygen as a constituent element. 前記第一絶縁膜の酸化を、少なくとも酸素を構成元素として含むプラズマに第一絶縁膜を暴露させることにより行うことを特徴とする請求項１乃至５いずれか記載の薄膜トランジスタの製法。 6. The method of manufacturing a thin film transistor according to claim 1, wherein the first insulating film is oxidized by exposing the first insulating film to plasma containing at least oxygen as a constituent element. 前記酸化物半導体薄膜層の形成と前記第一絶縁膜の形成を、真空中で連続して行うことを特徴とする請求項１乃至６いずれか記載の薄膜トランジスタの製法。




7. The method of manufacturing a thin film transistor according to claim 1, wherein the formation of the oxide semiconductor thin film layer and the formation of the first insulating film are continuously performed in a vacuum.




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