JP2008053517A - Array substrate manufacturing method and array substrate - Google Patents

Abstract

A method of manufacturing an array substrate in which a protection circuit for connecting scanning wirings and / or signal wirings to prevent destruction of switching elements from static electricity can be formed simultaneously with the switching elements by a small number of photolithography processes. Is to provide.
A simple configuration in which scanning wirings 2a and / or signal wirings 3a are connected to each other by a semiconductor film 10 to form protection circuits 5 and 6 is adopted, and a conductive film 3 provided to the signal wiring 3a and switching are used. In the case of simultaneously patterning the semiconductor film 10 provided for the element 8, when forming a resist with a predetermined pattern on the conductive film 3, the thickness t 2 of the predetermined portion of the resist 13, 14 in the protection circuit 5, 6 region. The thickness t1 of the resist 12 in the switching element 8 region is formed to be thinner than the thicknesses t2 and t3 of the thin portions 13a and 14b of the resists 13 and 14 in the protection circuit regions 5 and 6 as well as the thickness t1.
[Selection] Figure 9

Description

  The present invention relates to a method of manufacturing an array substrate having a protection circuit that protects switching elements and the like from static electricity.

  In recent years, liquid crystal display panels have been widely used as display units for home appliances such as computers and televisions. In general, a liquid crystal display panel is configured by causing an array substrate and a color filter substrate to face each other with a small gap, pasting them together at the periphery thereof, and sealing liquid crystal in the gap. On the array substrate, scanning lines and signal lines orthogonal to each other are arranged in a grid pattern, and a pixel electrode is arranged in each pixel region partitioned by the scanning line and the signal line. The pixel electrode and the signal wiring are connected via a switching element that is controlled to be turned on / off by the scanning wiring.

  As such a switching element, a TFT element is mainly used. In general, a thin film transistor such as a TFT element is weak against a strong electric field, and static electricity generated in a manufacturing process of a liquid crystal display device may destroy the TFT element. When the scanning wiring or signal wiring on the array substrate is charged by static electricity, it affects the crystal structure of the semiconductor film in the TFT element, and the threshold voltage of the gate voltage is shifted by several volts. Therefore, the switching operation by the TFT element is not normally performed, and the display of the pixel is defective.

  As a countermeasure against such a problem, for example, in the vicinity of the input terminals of the scanning line and the signal line, adjacent scanning lines and adjacent signal lines are connected by a protection circuit as described in Patent Document 1. It has been broken. As a result, when a voltage significantly higher than the actual driving voltage is applied to any of the wirings, the charge can be released to the other wirings through the protection circuit, and the above-described problems can be prevented. .

JP 2003-202599 A

  The array substrate is usually manufactured by a plurality of photolithography processes including a film forming process, resist coating, resist baking, exposure, development, etching, resist stripping, and the like. The number of such photolithography processes is expressed by the number of masks used and is called, for example, a five-mask process. In general, as the number of masks used in the photolithography process increases, there is a problem that defects due to adhesion of dust and the like are more likely to occur. In addition, the unit price of a single mask increases the cost due to the increase in size, and it is desired to reduce the number of masks used.

  However, although the array substrate described in Patent Document 1 is manufactured by five or six mask processes, it is difficult to reduce the number of masks used for manufacturing in the configuration of the protection circuit described.

  Therefore, the problem to be solved by the present invention is to form a protection circuit for connecting scanning wirings and / or signal wirings simultaneously with the switching elements with a small number of photolithography steps in order to prevent the switching elements from being destroyed due to static electricity. It is to provide a method of manufacturing an array substrate that can be used.

  In order to solve the above-described problems, a method of manufacturing an array substrate according to the present invention includes a protection circuit that connects scanning wirings and / or signal wirings on a substrate, and in the vicinity of an intersection between the scanning wiring and the signal wiring. A method for manufacturing an array substrate including a switching element provided, wherein a semiconductor film provided for the protection circuit and the switching element, and a conductive film provided for the signal wiring are arranged on the substrate in this order. Forming a resist having a predetermined pattern on the conductive film, forming a predetermined thickness of the resist in the protective circuit region, and reducing a thickness of the predetermined portion of the resist in the switching element region. The step of forming the resist thinner than the thin portion of the resist in the protective circuit region, the resist in the protective circuit region and the resist in the switching element region as a mask Removing the conductive film and the semiconductor film, reducing the thickness of the thin portion of the resist in the protection circuit region and reducing the thickness of the thin portion of the resist in the switching element region, and removing the thin portion Forming a source electrode and a drain electrode of the switching element by removing the conductive film exposed in a portion where the thin-walled part is removed using the resist of the switching element region from which the thin film is removed as a mask, A step of reducing the thickness of the thin portion of the resist in the protective circuit region, and removing the conductive film exposed in the portion where the thin portion has been removed, using the resist in the protective circuit region from which the thin portion has been removed as a mask A step of forming a protection circuit for connecting adjacent scanning wirings and / or signal wirings by removing It is an gist that it comprises.

  In this case, when a resist having a predetermined pattern is formed on the conductive film, the thickness of the predetermined portion of the resist in the protection circuit region is reduced, and the thickness of the predetermined portion of the resist in the switching element region is set to the protection circuit. It is preferable that the step of forming the region thinner than the thin portion of the resist is performed in the same step by using a halftone exposure mask having a predetermined pattern.

  In addition, the thickness of the thin portion of the resist in the protection circuit region is reduced, and the step of reducing and removing the thin portion of the resist in the switching element region is performed in the same step by ashing. good.

  Further, the semiconductor film may have a laminated structure in which an active semiconductor layer made of amorphous silicon and a low-resistance semiconductor layer made of amorphous silicon doped with phosphorus are laminated in this order.

  According to the method for manufacturing an array substrate having the above-described configuration, when forming a resist with a predetermined pattern on the conductive film, the thickness of the predetermined portion of the resist in the protection circuit region is reduced, and the switching element region Since the thickness of the predetermined portion of the resist is formed to be thinner than the thin portion of the resist in the protective circuit region, the thin portion of the resist in the switching element region is first removed by ashing, and then the thin portion of the resist in the protective circuit region. Can be removed, and a semiconductor film used for the protection circuit can be efficiently formed.

  In addition, as a protection circuit, a simple configuration in which a semiconductor film is interposed between scanning wirings and / or between signal wirings is adopted, and a mask used for patterning of the semiconductor film and signal wiring is shared. The protection circuit can be formed simultaneously with the formation of the switching element by the so-called four-mask process. Thereby, the manufacturing cost can be reduced.

  Embodiments of an array substrate manufacturing method according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view schematically showing a TFT array substrate used in a liquid crystal display panel as an array substrate according to an embodiment of the present invention.

  The liquid crystal display panel is configured by placing an array substrate 1 shown in the figure and a color filter substrate (not shown) facing each other through a small gap, bonding them together at the periphery thereof, and enclosing liquid crystal in the gap. On the array substrate 1, scanning wirings 2a and signal wirings 3a orthogonal to each other are arranged in a grid pattern, and a picture element portion 4 is formed in each region partitioned by the scanning wirings 2a and the signal wirings 3a. A scanning wiring input terminal 2d and a signal wiring input terminal 3e are formed at the ends of the scanning wiring 2a and the signal wiring 3a, respectively. The adjacent scanning lines 2a and 2a and the signal lines 3a and 3a are connected to each other by a scanning line side protection circuit 5 and a signal line side protection circuit 6, respectively.

  FIG. 2A is an enlarged plan view showing the outline of the picture element portion 4, and FIG. 2B is a cross-sectional view taken along line AA in FIG. As shown in the drawing, a picture element electrode 7 a is formed in the picture element section 4. Around the picture element electrode 7a, scanning wirings 2a and signal wirings 3a orthogonal to each other are arranged in a grid pattern. The scanning wiring 2a and the signal wiring 3a intersect at the intersection so that the signal wiring 3a is on the upper side and the scanning wiring 2a is on the lower side, and the scanning wiring 2a and the signal wiring 3a are electrically insulated at the intersection. Has been.

  A gate electrode 2b, which is a part of the scanning wiring 2a, is located at the intersection of the scanning wiring 2a disposed on the upper side of the picture element electrode 7a and the signal wiring 3a disposed on the left side of the picture element electrode 7a. A TFT (thin film transistor) 8 as a switching element connected to is formed.

  As shown in FIG. 2B, the TFT 8 includes a gate electrode 2b, a gate insulating film 9, a first semiconductor layer 10a having a channel portion 8a, a second semiconductor layer 10b, a source electrode 3b, on a glass substrate 1a. The drain electrode 3c and the protective film 11 are stacked. Further, a contact hole 11a reaching the drain electrode 3c from the surface of the protective film 11 is formed, and the pixel electrode 7a is connected to the drain electrode 3c of the TFT 8 by the contact hole 11a.

  FIG. 3A is an enlarged plan view schematically showing the scanning wiring side protection circuit 5, and FIG. 3B is a cross-sectional view taken along the line BB of FIG. The scanning wiring side protection circuit 5 is a circuit composed of a semiconductor film 10 arranged so as to overlap each scanning wiring 2a, 2a so as to bridge adjacent scanning wirings 2a, 2a. For example, when a voltage that is significantly higher than the actual driving voltage is applied to one scanning wiring 2 a due to static electricity by the semiconductor film 10, the charge may be released to the other scanning wiring 2 a through the semiconductor film 10. it can.

  As shown in FIG. 3B, the scanning wiring side protection circuit 5 is formed by laminating scanning wirings 2a and 2a, a gate insulating film 9, a semiconductor film 10, and a protective film 11 on a glass substrate 1a. Has been. In this case, the semiconductor film 10 is formed by laminating the same first semiconductor layer 10a and second semiconductor layer 10b as those used in the TFT 8 described above in this order.

  FIG. 4A is an enlarged plan view schematically showing the signal wiring side protection circuit 6, and FIG. 4B is a cross-sectional view taken along the line CC in FIG. 4A. The signal wiring side protection circuit 6 is a circuit composed of a semiconductor film 10 arranged so that the signal wirings 3a and 3a overlap each other so as to bridge adjacent signal wirings 3a and 3a. With this semiconductor film 10, for example, when a voltage that is significantly higher than the actual driving voltage is applied to one signal wiring 3 a due to static electricity, the charge may be released to the other signal wiring 3 a through the semiconductor film 10. it can.

  As shown in FIG. 4B, the scanning wiring side protection circuit 6 is formed by laminating a gate insulating film 9, a semiconductor film 10, signal wirings 3a and 3a, and a protective film 11 on a glass substrate 1a. Has been. In this case, the semiconductor film 10 is formed by laminating the same first semiconductor layer 10a and second semiconductor layer 10b as those used in the TFT 8 described above in this order.

  Next, a manufacturing method of the array substrate 1 including the TFT 8, the scanning wiring side protection circuit 5, and the signal wiring side protection circuit 6 shown in FIGS. 5 to 17 are cross-sectional views schematically showing the state of each step in manufacturing the array substrate 1. In this case, (a) in FIG. 5 to FIG. 17 is the AA cross section of the TFT 8 shown in FIG. 2 (a) similarly to FIG. 2 (b), and (b) in FIG. Similarly to FIG. 3A, the BB cross section of the scanning wiring side protection circuit 5 shown in FIG. 3A, and FIG. 5C to FIG. 17C are the signal wirings shown in FIG. The CC cross section of the side protection circuit 6 is shown in order of each process.

  FIG. 5 shows a state where the gate electrode 2b and the scanning wiring 2a are formed on the glass substrate 1a. First, the first conductive film 2 is formed on the glass substrate 1a. Then, the first conductive film 2 is patterned through a first photolithography process using the first mask. Thereby, as shown in FIGS. 5A and 5B, the gate electrode 2b and the scanning wiring 2a are formed. Specifically, a first conductive film 2 made of a metal such as Ti / Al / Ti is formed on the glass substrate 1a by sputtering, a resist pattern is formed by photolithography, and the resist pattern is used as a mask. 1 The conductive film 2 is etched, and then the resist is removed to form the gate electrode 2b and the scanning wiring 2a.

  In FIG. 6, a gate insulating film 9 made of silicon nitride (SiNx) or the like is formed on the glass substrate 1a shown in FIG. 5 so as to cover the gate electrode 2b and the scanning wiring 2a. Then, as shown in FIG. 7, chemical vapor deposition (CVD) is performed on the first semiconductor layer 10a as an active semiconductor made of amorphous silicon or the like and the second semiconductor layer 10b made of amorphous silicon or the like doped with phosphorus or the like. The film is formed at Thereafter, as shown in FIG. 8, a second conductive film 3 made of a metal such as Al / Ti is formed by sputtering.

  Then, a second photolithography process is performed using the second mask. Specifically, resist patterns 12, 13, and 14 having different thicknesses as shown in FIG. 9 are formed in the TFT 8 region, the scanning wiring side protection circuit 5 region, and the signal wiring side protection circuit 6 region, respectively.

  Specifically, after a resist is applied to the entire surface of the second conductive film 3 to form a resist layer, the exposure amount is adjusted using a slit mask or the like as a second mask, so that a half of the resist layer is formed. Apply tone exposure. As a result, resist patterns 12, 13, and 14 having different thicknesses are formed at the respective portions as shown in FIG. 9 by a single resist application and batch exposure.

  The resist pattern 12 in the TFT 8 region shown in FIG. 9A is a pattern for forming the semiconductor film 10, the source electrode 3 b, the drain electrode 3 c, and the signal wiring 3 a constituting the TFT 8. In this case, the halftone portion 15a of the mask 15 as shown in the figure forms a thin portion 12a having a thickness t1 of the resist located in the portion used as the channel portion 8a of the TFT 8.

  The resist pattern 13 in the scanning wiring side protection circuit 5 region shown in FIG. 9B is for forming the semiconductor film 10 used for the scanning wiring side protection circuit 5 so as to bridge the scanning wirings 2a and 2a. It is a pattern. In this case, the halftone portion 15b of the mask 15 as shown in the figure forms a thin portion 13a having a total thickness t2 of the resist located in the portion used as the protection circuit of the semiconductor film 10. The thickness t2 of the thin portion 13a is formed to be thicker than the thickness t1 of the thin portion 12a of the resist pattern 12 shown in FIG.

  The resist pattern 14 in the signal wiring side protection circuit 6 area shown in FIG. 9C is a pattern for forming the semiconductor film 10 used in the protection circuit 6 so as to bridge the signal wirings 3a and 3a. . In this case, the halftone portion 15c of the mask 15 as shown in the figure forms a thin portion 14a having a thickness t3 of the resist located in the portion used as the protection circuit of the semiconductor film 10. The thickness t3 of the thin portion 14a is formed to be thicker than the thickness t1 of the thin portion 12a of the resist pattern 12 shown in FIG. 9A.

  FIG. 10 shows a state where etching is performed using the resist patterns 12, 13, and 14 as masks. Etching is performed using the resist patterns 12, 13, and 14 as masks, respectively, and the second conductive film 3 and the semiconductor film 10 that are not covered with the resist pattern are removed. As a result, portions of the second conductive film 3 that are not used for the source electrode 3b, the drain electrode 3c, the signal wiring 3a, and the like, and the semiconductor film 10 thereunder are removed.

  Next, the resist patterns 12, 13, and 14 are ashed using oxygen plasma. Thereby, as shown in FIG. 11A, the resist of the thin portion 12a of the resist pattern 12 is removed. The second conductive film 3 is exposed at the portion where the thin portion 12a is removed. At this time, even if the thin portion 12a of the resist pattern 12 of FIG. 11A is removed, the thin portion 13a of the resist pattern 13 of FIG. 11B and the thin portion 14a of the resist pattern 14 of FIG. As shown, it is thinned by ashing, but remains unremoved.

  FIG. 12 shows a state in which etching is performed using the remaining resist patterns 12, 13, and 14 as masks. As shown in FIG. 12A, when the portion of the second conductive film 3 exposed by ashing is removed, the source electrode 3b and the drain electrode 3c connected in the TFT 8 region are separated. Further, the first semiconductor layer 10a of the semiconductor film 10 is partially etched to adjust the thickness, and the channel portion 8a of the TFT 8 is formed. Thereby, the TFT 8 is formed.

  Next, the resist patterns 12, 13, and 14 are ashed using oxygen plasma again. Thereby, as shown in FIG. 13B, the resist of the thin portion 13a of the resist pattern 13, that is, the entire resist pattern 13 is removed. In the portion where the resist pattern 13 is removed, the second conductive film 3 is exposed. Further, as shown in FIG. 13C, the resist of the thin portion 14a of the resist pattern 14 is removed. Similarly, the second conductive film 3 is exposed in the portion where the thin portion 14a is removed.

  FIG. 14 shows a state in which etching is performed using the remaining resist patterns 12 and 14 as a mask. As shown in FIG. 14B, when the portion of the second conductive film 3 exposed by the second ashing is removed, only the semiconductor film 10 used for the scanning wiring side protection circuit 6 remains. Thereby, the scanning wiring side protection circuit 5 is formed. Further, as shown in FIG. 14C, when the portion of the second conductive film 3 exposed by ashing is removed, the scanning wirings 3a and 3a connected in the signal wiring side protection circuit 6 region are separated. The Thereby, the signal wiring side protection circuit 6 is formed.

  FIG. 15 is a diagram showing a state in which the remaining resist patterns 12 and 14 are peeled off.

  Next, a protective film 11 is formed as shown in FIG. In this case, a third photolithography process is performed using the third mask, the protective film 11 is patterned, and a contact hole 11a reaching the drain electrode 3c as shown in FIG. 16A is formed. . Then, a transparent conductive film 7 made of ITO as shown in FIG. 17 is formed. In this case, a fourth photolithography process is performed using the fourth mask, the transparent conductive film 7 is patterned, and a pixel electrode 7a as shown in FIG. 17A is formed.

  Through the above steps, the array substrate 1 according to the embodiment of the present invention is completed.

  As described above, when forming a resist with a predetermined pattern on the second conductive film 3, the thickness of the predetermined portion of the resist in the protective circuit 5 and 6 regions is reduced and the thickness of the predetermined portion of the resist in the TFT 8 region is reduced. Since it is formed to be thinner than the thin resist portion in the protective circuit 5 and 6 regions, the thin resist portion in the TFT region is first removed by ashing, and then the thin resist portion in the protective circuit 5 and 6 regions is removed. Thus, the semiconductor film 10 used for the protection circuits 5 and 6 can be efficiently formed.

  In addition, as a protection circuit, a simple configuration in which a semiconductor film is interposed between scanning wirings and / or between signal wirings is adopted, and a mask used for patterning of the semiconductor film and signal wiring is shared. The protection circuit can be formed simultaneously with the formation of the switching element by the so-called four-mask process. Thereby, the manufacturing cost can be reduced.

  As mentioned above, although one Embodiment of this invention was described, this invention is not limited to such Embodiment at all, Of course, in the range which does not deviate from the summary of this invention, it can implement in a various aspect.

It is the top view which showed typically the array board | substrate which concerns on one Embodiment of this invention. (A) is the top view which showed schematic structure of the pixel part with which the array board | substrate which concerns on one Embodiment of this invention is equipped, (b) is the figure which showed the cross-sectional structure of the switching element shown by (a). (A) is a top view which showed schematic structure of the scanning wiring side protection circuit with which the array board | substrate concerning one Embodiment of this invention is provided, (b) shows the cross-sectional structure of the scanning wiring side protection circuit shown by (a). It is a figure. (A) is the top view which showed schematic structure of the signal wiring side protection circuit with which the array board | substrate concerning one Embodiment of this invention is provided, (b) shows the cross-sectional structure of the signal wiring side protection circuit shown by (a). It is a figure. FIG. 5 is a diagram showing a state in which a first conductive film is patterned in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. FIG. 5 is a diagram showing a state in which a gate insulating film is formed in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. FIG. 5 is a diagram showing a state in which a semiconductor film is formed in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. FIG. 5 is a diagram showing a state in which a second conductive film is formed in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. FIG. 5 is a diagram showing a state in which a resist is patterned in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. In the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4, the second conductive film and the semiconductor film are removed using the patterned resist as a mask. It is a figure. FIG. 5 is a view showing a state in which a patterned resist is ashed in a manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. In the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4, the second conductive film is removed using the ashed resist as a mask, and the semiconductor film is integrated. It is the figure which showed the state which removed a part. FIG. 5 is a view showing a state in which a patterned resist is ashed again in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. The figure which showed the state which removed the 2nd electrically conductive film by using the resist which was ashed again as a mask in the manufacturing process of the switching element shown in FIG.2, FIG.3, FIG.4, a scanning wiring side protection circuit, and a signal wiring side protection circuit It is. FIG. 5 is a diagram showing a state in which the ashed resist is removed again in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. FIG. 5 is a diagram showing a state in which a protective film is patterned in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4. FIG. 5 is a diagram showing a state in which a transparent conductive film is patterned in the manufacturing process of the switching element, the scanning wiring side protection circuit, and the signal wiring side protection circuit shown in FIGS. 2, 3, and 4.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Array substrate 1a Glass substrate 2 1st conductive film 2a Scanning wiring 2b Gate electrode 2d Scanning wiring input terminal 3 2nd conductive film 3a Signal wiring 3b Source electrode 3c Drain electrode 3e Signal wiring input terminal 4 Picture element part 5 Scanning wiring side protection Circuit 6 Signal wiring side protection circuit 7 Transparent conductive film 7a Picture element electrode 8 TFT
8a channel portion 9 gate insulating film 10 semiconductor film 10a first semiconductor layer 10b second semiconductor layer 11 protective film 11a contact hole 12 resist pattern 12a thin portion 13 resist pattern 13a thin portion 14 resist pattern 14a thin portion 15 masks 15a to 15c half Tone part

Claims (5)

A method of manufacturing an array substrate, comprising: a protection circuit that connects scanning wirings and / or signal wirings on a substrate; and a switching element provided in the vicinity of an intersection of the scanning wiring and the signal wiring,
A step of laminating a semiconductor film provided for the protection circuit and the switching element and a conductive film provided for the signal wiring on the substrate in this order;
When forming a resist having a predetermined pattern on the conductive film, the thickness of a predetermined portion of the resist in the protection circuit region is thinned, and the thickness of the predetermined portion of the resist in the switching element region is reduced. Forming a thinner than the thin-walled portion of
Removing the conductive film and the semiconductor film using the resist in the protective circuit region and the resist in the switching element region as a mask;
Reducing the thickness of the thin portion of the resist in the protective circuit region and reducing the thickness of the thin portion of the resist in the switching element region;
Forming a source electrode and a drain electrode of the switching element by removing the conductive film exposed in the portion from which the thin portion has been removed, using the resist in the switching element region from which the thin portion has been removed as a mask ,
Reducing the thickness of the thin portion of the resist in the protective circuit region and removing it,
Connect the adjacent scan lines and / or signal lines by removing the conductive film exposed in the part where the thin part is removed, using the resist in the protection circuit area where the thin part is removed as a mask A method of manufacturing an array substrate, comprising the step of forming a protective circuit.   When forming a resist having a predetermined pattern on the conductive film, the thickness of a predetermined portion of the resist in the protection circuit region is thinned, and the thickness of the predetermined portion of the resist in the switching element region is reduced. 2. The method of manufacturing an array substrate according to claim 1, wherein the step of forming the thin-walled portion is performed in the same step by using a halftone exposure mask having a predetermined pattern.   The step of reducing and removing the thin portion of the resist in the protection circuit region and reducing the thin portion of the resist in the switching element region is performed in the same step by ashing. The manufacturing method of the array substrate of Claim 1 or 2.   2. The semiconductor film according to claim 1, wherein the semiconductor film has a laminated structure in which an active semiconductor layer made of amorphous silicon and a low-resistance semiconductor layer made of amorphous silicon doped with phosphorus are laminated in this order. 4. A method for producing an array substrate according to any one of items 1 to 3.   An array substrate manufactured by the method for manufacturing an array substrate according to claim 1.

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