KR100466387B1 - Method for fabricating liquid crystal display using five mask processes - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a liquid crystal display using a five mask process. In the method for manufacturing a liquid crystal display panel, ITO deposition and deposition of gate metal, masking of ITO and gate, etching of gate metal, and patterning in the order of ITO etching A first step of doing; A second step proceeding in the order of multi-layer deposition, masking of the multi-layer, etching of the multi-layer, and etching of the gate metal; A third step of proceeding with source / drain metal deposition, source / drain masking, source / drain metal etching, and channel etching; A fourth step of proceeding with PVX deposition, PVX masking, and PVX etching; It consists of a fifth step process in which deposition of the second ITO, masking of the second ITO, etching of the second ITO is performed, and in the BCE type FFS method, the six mask process can be simplified to a five mask process. Due to the improvement of capacity and production cost can be reduced.

Description

5 Manufacturing method of liquid crystal display using mask process {METHOD FOR FABRICATING LIQUID CRYSTAL DISPLAY USING FIVE MASK PROCESSES}

The present invention relates to a method of manufacturing a liquid crystal display using a five-mask process, and more specifically, two films are etched through a mask in which ITO and gate metal are sequentially increased on glass and patterned with ITO pixels and gate lines. A method of manufacturing a liquid crystal display using a five-mask process for manufacturing a mask by etching a-Si: H, the gate insulator and the gate metal of the pixel portion through a multilayer mask.

BACKGROUND ART A known conventional liquid crystal display (LCD) is used as an information display device such as an information display window of a portable terminal device, a screen display of a notebook PC, a monitor of a laptop computer, and the like. In particular, the liquid crystal display is a display device that can replace the conventional CRT monitor, the industrial use is very high.

On the other hand, the FFS (Fringe Field Switching) method has the advantage that it is possible to implement a wide viewing angle and high opening rate, but there is a disadvantage that the process is increased due to the transparent electrode of two layers. In addition, even if the process is a simple BCE type, a total of six mask processes are required.

Brief description of each process of the BCE type of the liquid crystal display according to the prior art is as follows.

Although not shown in the drawing, the first pixel electrode is patterned using a first ITO mask, and the gate is patterned using a second gate mask. Next, an a-Si layer on the gate insulator is formed using a third active mask. After patterning, the source / drain is patterned using a fourth source / drain mask to form a channel. A contact hole is formed in the passivation film to form a contact between the second ITO and the drain using a fifth via hole mask. After that, the pixel electrode is finally patterned using the sixth ITO mask to complete the liquid crystal display.

As described above, according to the liquid crystal display according to the prior art, a total of six mask processes are required even when the process is a simple BCE type, there is a problem that the manufacturing rate is reduced due to the increase of the process.

Therefore, the present invention has been made to solve the above-mentioned problems of the prior art, it is possible to deposit the ITO and gate metal on the upper surface of the glass substrate and form a pattern of the first pixel electrode, the gate and the common electrode in the first mask step. It is an object of the present invention to provide a method for manufacturing a liquid crystal display using a five mask process that can simplify the manufacturing process requiring a six mask process to a five mask process.

1a, 1b, 1c, 1d illustrate a first mask process according to the invention, FIG.

2a, 2b, 2c, 2d show a second mask process according to the invention,

3A and 3B are side cross-sectional views illustrating a cross section after etching of a common electrode and a gate line according to the present invention;

4a, 4b, 4c, 4d, 4e illustrate a third mask process according to the invention,

5a, 5b, 5c, 5d, 5e illustrate a fourth mask process according to the present invention;

6A, 6B, 6C, 6D, and 6E illustrate a fifth mask process according to the present invention.

* Description of the symbols for the main parts of the drawings *

2: glass substrate, 4: first ITO,

6: gate metal, 8a, 8b, 8c, 8d, 8e: first, 2, 3, 4, 5 mask,

10 gate insulating film 12 a-Si layer,

14 source / drain metal, 16 passivation layer,

18: Second ITO.

According to a preferred embodiment of the present invention for achieving the above object, by sequentially stacking the first ITO and gate metal on a glass substrate and patterning the gate metal and ITO by using a first mask to simultaneously gate and common electrodes Forming a first step; A second step of laminating a gate insulating film and an amorphous layer on the upper surface of the entire structure after the first step, and then patterning the amorphous layer and the gate insulating film using a second mask to insulate the gate line and the common electrode; A third step of forming a source / drain by forming a source / drain metal on an upper surface of the entire structure after the second step, and then patterning the source / drain metal using a third mask; A fourth step of forming the via hole exposing the source / drain by patterning the passivation using a fourth mask after forming a passivation on the upper surface of the entire structure after the third step; And forming a second ITO on the upper surface of the entire structure after the fourth step, and then patterning the second ITO using a fifth mask. After patterning at the same time, the gate metal on the pixel electrode of the first ITO is removed at the time of masking the gate insulating film and the amorphous layer. The first ITO electrically connects the metals between the gate metal and the source / drain metal. In the passivation mask, a hole is formed in the gate and the common electrode to remove a-Si: H to remove a channel between adjacent data lines. In addition, the common electrode and the first electrode in the ITO-gate mask are removed. A hole is formed between the ITO pixel electrodes so that the first ITO and the second ITO do not come into contact with each other through the hole made for removing a-Si: H during the passivation mask. The.

Hereinafter, a method of manufacturing a liquid crystal display using a five mask process according to the present invention will be described in detail with reference to the accompanying drawings.

1A, 1B, 1C, and 1D show a first mask process according to the present invention, and FIGS. 2A, 2B, 2C, and 2D show a second mask process according to the present invention, and FIGS. 3A, 3B. Fig. 4 is a side cross-sectional view showing a cross section after etching of the common electrode and the gate line according to the present invention. Figs. 4A, 4B, 4C, 4D and 4E show a third mask process according to the present invention. 5b, 5c, 5d and 5e illustrate a fourth mask process according to the present invention, and FIGS. 6a, 6b, 6c, 6d and 6e illustrate a fifth mask process according to the present invention.

In the method of manufacturing a liquid crystal display using a five-mask process according to the present invention, as shown in Fig. 1A, the first ITO 4 and the gate metal 6 are laminated on the upper surface 2 of the glass substrate. As shown in FIGS. 1B, 1C, and 1D, the gate mask 8a, which is a first mask, is formed on the gate metal 6, and then the gate metal 6 is formed using the gate mask 8a. The first ITO 4 is sequentially patterned to simultaneously form a gate and a common electrode. Next, as shown in FIGS. 2A and 2B, the gate mask 8a is removed, and a gate insulating film ( 10) and an amorphous layer (a-Si: H, n + a-Si: H) 12 are laminated, and then a multi-layer mask 8b, which is a second mask, is formed thereon. 2D, 3A, and 3B, the amorphous layer 12 and the gate insulating film 10 are patterned by using the second mask 8b. It isolates the bit lines and the common electrode. In this case, as illustrated in FIG. 3A, the gate metal exposed to the outside of the gate insulating layer 10 and the amorphous layer 12 is etched to expose the pixel electrode. FIGS. 4A, 4B, 4C, 4D, and 4E illustrate the present invention. 3 is a view illustrating a third process according to an embodiment of the present invention.

In the process of forming a source / drain according to the present invention, as shown in FIGS. 4A, 4B, 4C, 4D, and 4E, first, the source / drain metal 14 is deposited, and the third mask 8C for source / drain formation is formed. ) On it.

Next, the source / drain metals 14 are patterned using the third mask 8c, and the n + a-Si: H 12 is removed by channel etching to define a channel region. At this time, since the a-Si: H layer 12 is present on the gate 6a and the common electrode 4a, a channel for generating a leakage current is formed between the neighboring data lines 14.

5A, 5B, 5C, 5D, and 5E illustrate a fourth process according to an embodiment of the present invention.

In the passivation forming process of the fourth mask process according to the present invention, as shown in FIGS. 5A to 5E, the passivation (PVX) 16 is deposited on the upper surface of the entire structure, and then the fourth mask is formed on the passivation 16. (8d). The passivation 16 is then patterned using the four masks 8d to pattern the via holes A for contact between the second ITO and the source / drain. At this time, the channel layer (part A) formed between the data lines 14 is removed. In other words, the via hole A is formed on the gate and the common electrode during the passivation mask, and then the a-Si layer is removed during the etching to destroy the channel between the data lines 14. FIG. 6A, 6B and 6C. , 6d and 6e illustrate a fifth mask process according to an embodiment of the present invention.

Formation of the fifth ITO, which is the fifth mask process according to the present invention, as shown in FIGS. 6A to 6E, first deposits the second ITO 18 on the upper surface of the entire structure, and then deposits the fifth mask 8e thereon. Form.

Then, the second ITO 18 is patterned using a fifth mask 8e, and a hole is formed between the common electrode and the pixel electrode of the first ITO in the gate-ITO process, so that it is common with the gate during the passivation mask. The large hole formed to remove the a-Si: H layer 12 on the electrode can prevent the attack of the first ITO during the etching of the second ITO 18.

In addition, the contact between the gate metal and the source metal is the first ITO 4 under the gate 6 when contact between the gate metal and the source / drain metal is required for the ESD configuration or the connection between the pad and the data or the gate line. Can be produced using).

As described above, the manufacturing method of the liquid crystal display panel using the 5 mask process according to the present invention can simplify the 6 mask process to 5 mask process in the BCE type FFS method, thereby improving capacity and reducing production cost On the other hand, the manufacturing method of the liquid crystal display panel using the five mask process according to an embodiment of the present invention is not limited to the above embodiment only, various modifications can be made without departing from the technical gist of the invention. Do.

Claims (5)

A first step of sequentially stacking a first ITO and a gate metal on a glass substrate and patterning the gate metal and the ITO using a first mask to simultaneously form a gate and a common electrode; A second step of laminating a gate insulating film and an amorphous layer on the upper surface of the entire structure after the first step, and then patterning the amorphous layer and the gate insulating film using a second mask to insulate the gate line and the common electrode; A third step of forming a source / drain by forming a source / drain metal on an upper surface of the entire structure after the second step, and then patterning the source / drain metal using a third mask; A fourth step of forming the via hole exposing the source / drain by patterning the passivation using a fourth mask after forming a passivation on the upper surface of the entire structure after the third step; And And forming a second ITO on the upper surface of the entire structure after the fourth step, and then patterning the second ITO using a fifth mask. 5. Manufacturing method. The liquid crystal display panel according to claim 1, wherein the gate metal on the pixel electrode of the first ITO is removed at the time of masking the gate insulating film and the amorphous layer after patterning the first ITO and the gate metal at the same time. Manufacturing method. The method of claim 1, wherein the first ITO is to allow electrical contact between the metals between the gate metal and the source / drain metal. 5. The liquid crystal display panel of claim 1, wherein a hole is formed in the gate and the common electrode during the passivation mask to remove a-Si: H to remove a channel between adjacent data lines. Manufacturing method. 2. The first and second ITO and second electrodes of claim 1, wherein a hole is formed between the common electrode and the first ITO pixel electrode during the ITO-gate mask to remove a-Si: H layer during the passivation mask. A method of manufacturing a liquid crystal display panel using a five mask process, characterized in that the ITO is not in contact with each other.