KR100635946B1 - Thin film transistor substrate for liquid crystal display device and manufacturing method thereof - Google Patents

Abstract

A gate wiring, a gate insulating film, and a semiconductor layer are sequentially formed on the insulating substrate, and a chromium layer and an aluminum-neodymium layer are successively deposited for data wiring. Then, a photosensitive film is applied and exposed and developed using a mask having a slit formed therein. On the electrode and the data pad, a photoresist pattern thinner than other portions is formed. The aluminum-neodymium layer is etched using the photoresist pattern as a mask, and the photoresist pattern is ashed to expose the drain electrode and the aluminum-neodymium layer of the data pad. The exposed aluminum-neodymium layer is etched and removed, and then a protective film is deposited and a contact hole is formed. Then, ITO is deposited and patterned to form a pixel electrode and an auxiliary pad. In this way, the connection through the contact hole between the data wiring layer and the pixel electrode layer is good, and it is possible to prevent the data wiring from being damaged in the process of forming the pixel electrode.

LCD, Thin Film Transistor Board, Data Wiring, Slit, Mask, IZO

Description

Thin film transistor substrate for liquid crystal display device and manufacturing method therefor {THIN FILM TRANSISTOR ARRAY PANEL FOR LIQUID CRYSTAL DISPLAY AND MANUFACTURING METHOD THEREOF}

1 is a cross-sectional view of a thin film transistor substrate for a liquid crystal display device according to the related art.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention.

3 and 4 are cross-sectional views taken along lines III-III 'and IV-IV' of FIG. 2, respectively.

5A is a layout view of a substrate in an intermediate step of a process of manufacturing a thin film transistor substrate according to an embodiment of the present invention;

5B and 5C are cross-sectional views taken along lines Vb-Vb 'and Vc-Vc' of FIG. 5A, respectively.

6A is a layout view of the substrate in the next step of FIGS. 5A-5C,

6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively.

7A and 7B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively, illustrating the steps of exposing to move from the steps of FIGS. 5A-5C to the steps of FIGS. 6A-6C. And

8A and 8B are cross-sectional views of lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively, and are cross-sectional views of the substrate in the next steps of FIGS. 7A and 7B;

9A and 9B are cross-sectional views taken along the lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively, and are cross-sectional views of the substrate in the next steps of FIGS. 8A and 8B.

The present invention relates to a liquid crystal display device, and more particularly, to a thin film transistor substrate for a liquid crystal display device.

In general, a liquid crystal display device injects a liquid crystal material between an upper substrate on which a common electrode, a color filter, and the like are formed, and a lower substrate on which a thin film transistor and a pixel electrode are formed. By applying a different potential to form an electric field to change the arrangement of the liquid crystal molecules, and through this to control the light transmittance is a device that represents the image.

In such a liquid crystal display device, wirings such as a gate line for supplying a scan signal to a thin film transistor and a data line for supplying an image signal are formed on a lower substrate on which a thin film transistor is formed.

Next, a method of manufacturing a thin film transistor substrate according to the related art will be described.

First, the chromium layer 210 and the aluminum-neodymium layer 220 are successively deposited and patterned on the insulating substrate 100 to form a gate wiring including the gate electrode 260, and the gate insulating layer 300 on the gate wiring. The semiconductor layer 400 and the contact layers 550 and 560 are sequentially deposited and patterned to form islands of the semiconductor layer 400 and the contact layers 550 and 560.

Next, the chromium layer 620 and the aluminum-neodymium layer 630 are successively deposited and patterned to form a data line including the source electrode 650 and the drain electrode 660, and the data line as an etch mask. The lower contact layers 550 and 560 are etched to separate the contact layer 550 under the source electrode 650 and the contact layer 560 under the drain electrode 660.

Subsequently, the protective layer 80 is deposited and patterned to form a contact hole 810 exposing the drain electrode 660, and the aluminum-neodymium layer 630 of the drain electrode 660 exposed through the contact hole 810. Is removed by etching, and then an indium tin oxide (ITO) is deposited and patterned to form a pixel electrode 700.

In this case, the aluminum-neodymium layer 630 is etched and removed before the ITO is deposited because the aluminum-neodymium is in contact with the ITO, which causes chemical reaction, which is not preferable.

At this time, the aluminum-neodymium layer 630 is excessively etched in the process of etching and removing the aluminum-neodymium layer 630 through the contact hole 810 exposing the drain electrode 660, thereby forming a cavity under the passivation layer 800. Is formed, which causes the next deposited ITO layer to be disconnected at this cavity, resulting in poor contact between the pixel electrode 700 and the drain electrode 660.

This problem also occurs in the data pad (not shown).

The technical problem to be achieved by the present invention is to improve the connection through the contact hole between the data wiring layer and the pixel electrode layer.

In order to solve this problem, in the present invention, the upper layer of the drain electrode is removed while forming data wirings through a single photolithography process in which the thickness of the photoresist pattern is formed in two stages.

Specifically, the method includes forming a gate wiring on an insulating substrate, forming a gate insulating film, forming a semiconductor layer, a data line, a source electrode, a drain electrode, and a data pad, and forming a double layer of an upper layer and a lower layer. The thin film transistor substrate is fabricated by forming a data line having a structure in which at least a portion of the upper layer of the drain electrode is removed, forming a passivation layer, and forming a pixel electrode.

In this case, the forming of the data wiring may include stacking the lower and upper layers of the data wiring, and applying, exposing and developing a photosensitive agent to form a photoresist pattern having a thickness thinner than other portions on at least the drain electrode of the data wiring. Etching the upper layer and the lower layer for data wiring using the photoresist pattern as an etch mask, exposing the upper layer of the drain electrode by ashing the photosensitive film pattern, or etching the exposed upper layer, or etching the lower layer and the upper layer for data wiring Laminating, applying, exposing and developing a photoresist to form a photoresist pattern having a thickness thinner than other portions of at least the drain electrode of the data wiring, etching the upper layer for data wiring using the photoresist pattern as an etch mask, Ash by photoresist pattern Exposing the top layer of electrodes, and etching the lower layer to the upper layer as an etch mask, it may comprise the step of etching the exposed top layer.

In addition, the pixel electrode is preferably formed of IZO.

Next, a structure of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention will be described with reference to the drawings.

2 is a layout view of a thin film transistor substrate for a liquid crystal display according to an exemplary embodiment of the present invention, and FIGS. 3 and 4 are cross-sectional views taken along lines III-III 'and IV-IV' of FIG. 2, respectively.

On the insulating substrate 10, a gate wiring including a double layer of a lower layer 21 made of a metal or a conductor such as chromium (Cr) and an upper layer 22 made of aluminum (Al) or aluminum-neodymium (Al-Nd) or the like is formed. It is. The gate wiring is connected to the scan signal line or the gate line 20 extending in the horizontal direction and the gate line 20, and the gate pad 24 and the gate which receive the scan signal from the outside and transmit the scan signal to the gate line 20. A gate electrode 26 of the thin film transistor that is part of the line 20.

The gate wirings may be formed in a single layer.

A gate insulating film 30 made of silicon nitride (SiN _x ) is formed on the gate wiring to cover the gate wiring.

A semiconductor pattern 40 made of a semiconductor such as hydrogenated amorphous silicon is formed on the gate insulating layer 30, and is heavily doped with n-type impurities such as phosphorus (P) on the semiconductor pattern 40. Ohmic contact layer patterns 55 and 56 made of amorphous silicon are formed. The contact layer patterns 55 and 56 lower the contact resistance between the lower semiconductor pattern 40 and the upper data lines 60, 64, 65, and 66.

On the contact layer patterns 55 and 56, a data line is formed by a double layer of a lower layer 62 made of Cr or the like and an upper layer 63 made of a conductive material such as Al or Al-Nd. The data line is a thin film transistor which is a branch of the data line 60 formed in the vertical direction, the data pad 64 connected to one end of the data line 60 to receive an image signal from the outside, and the data line 60. And a drain electrode 66 of the thin film transistor positioned opposite to the source electrode 65 with respect to the source electrode 65 and the gate electrode 26.

At this time, the upper layer 63 of the drain electrode 66 is removed except for a part. The upper layer 63 is also removed from the data pad 64. The upper layer 63 is formed to have a smaller width than the lower layer 62 in the remaining portions of the data lines 60, 64, 65, and 66.

A passivation film 80 made of an insulating material such as silicon nitride is formed on the data line, and the contact hole 81 exposing the gate pad 24, the data pad 64, and the drain electrode 66 is formed on the passivation film 80. 82 and 83 are formed. At this time, the contact hole 82 exposing the gate pad 24 also penetrates through the gate insulating film 30 under the protective film 80. On the other hand, the contact holes 81 and 83 exposing the drain electrode 66 and the data pad 64 are formed at portions where the drain electrode 66 and the upper layer 63 of the data pad 64 are removed, respectively. Only the lower layer 62 is exposed. Therefore, the upper layer 63 of the data lines 60, 64, 65, and 66 is completely surrounded by the lower layer 62 and the passivation layer 80 at all portions.

The pixel electrode 70, the auxiliary gate pad 73, and the auxiliary data pad 74 made of a transparent conductive material such as indium tin oxide (ITO) and indium zinc oxide (IZO) are formed on the passivation layer 80. In this case, the pixel electrode 70 is connected to the lower layer 62 of the drain electrode 66 through the contact hole 81, and the auxiliary gate pad 73 and the auxiliary data pad 74 are respectively contact holes 82. 83 is connected to the lower layer 21 of the gate pad 24 and the lower layer 62 of the data pad 64. The lower layers 21 and 62 of the pixel electrode 70 and the auxiliary pads 73 and 74 are removed from the portions in which the upper layers 22 and 63 of the gate pad 24, the data pad 64, and the drain electrode 66 are removed. ) Only because aluminum or aluminum alloy and ITO may cause chemical reactions and cause defects.

Next, a method of manufacturing a thin film transistor substrate having such a structure will be described.

5A is a layout view of a substrate at an intermediate stage of a process of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention, and FIGS. 5B and 5C are taken along lines Vb-Vb 'and Vc-Vc' of FIG. 5A, respectively. 6A is a layout view of the substrate in the next step of FIGS. 5A-5C, and FIGS. 6B and 6C are cross-sectional views taken along lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively.

First, as shown in FIGS. 5A to 5C, a lower layer 21 made of chromium (Cr) or the like and an upper layer 22 made of aluminum (Al) or aluminum-neodynium (Al-Nd) on the insulating substrate 10. Are deposited continuously and patterned using a mask to form a gate wiring. Next, the gate insulating film 30, the semiconductor layer 40, and the contact layer 50 were successively deposited to a thickness of 1,500 kPa to 5,000 kPa, 500 kPa to 1,500 kPa, and 300 kPa to 600 kPa using chemical vapor deposition. By using a mask, the contact layer 50 and the semiconductor layer 40 are patterned together to form islands of the contact layer 50 and the semiconductor layer 40 on the gate electrode 26.

6A to 6C, the lower layer 62 made of chromium or the like and the upper layer 63 made of aluminum-neodynium or the like are successively deposited by sputtering or the like, and then patterned using a mask. To form (60, 64, 65, 66). At this time, as described above, the data wires 60, 64, 65, and 66 are removed with only a portion of the upper layer 63 remaining in the drain electrode 66, and also removed in the data pad 64. The upper layer 63 may be removed from the entire drain electrode 66.

Next, the method of forming the data wiring of such a structure will be described in more detail.

7A and 7B are cross sectional views taken along the lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively, to show the step of exposing to move from the steps of FIGS. 5A-5C to the steps of FIGS. 6A-6C. 8A and 8B are cross sectional views taken along the lines VIb-VIb 'and VIc-VIc' of FIG. 6A, respectively, and are cross-sectional views of the substrate in the next steps of FIGS. 7A and 7B, and FIGS. 9A and 9B are respectively FIGS. Cross-sectional views of the VIb-VIb 'lines and the VIc-VIc' lines of Fig. 8A and 8B are cross-sectional views of the substrate in the next steps of Figs. 8A and 8B.

First, as shown in FIGS. 7A and 7B, the lower layer 62 made of chromium or the like and the upper layer 63 made of aluminum-neodynium or the like are successively stacked by sputtering or the like. Next, before applying the photoresist film PR, the surface of the upper layer 63 is washed and the photoresist film PR is applied. At this time, the photosensitive film PR is preferably coated with a positive photosensitive film in a thickness of 5,000 kPa to 30,000 kPa.

Next, the photosensitive film PR is exposed using the mask 4. At this time, the mask 4 is composed of only the portion (A) that does not transmit light and the transparent substrate (1) due to the opaque layer (2) made of chromium or the like covered on the transparent substrate 1 to transmit almost the light The slit pattern 3 is formed in the part B and the transparent substrate 1 by chromium etc., and has the part C which transmits only a part of light. Alignment of the mask 4 and the thin film transistor substrate 10 at the time of exposure corresponds to the portion where the slit pattern 3 is formed and the portion where the drain electrode and the data pad are to be formed, as shown in the figure. A portion in which 2) is formed corresponds to the portion where the remaining data wirings are to be formed. When exposed in this state, the portion of the photoresist film PR corresponding to the portion C responds to light only to a certain depth from the surface to decompose the polymer, and the polymer remains under the portion. Both react to light and the polymer decomposes. In the part corresponding to the A part not exposed to light, the polymer remains intact.

Subsequently, when the exposed photoresist film PR is developed, as shown in FIGS. 8A to 8B, a portion of the drain electrode 66 and an upper portion of the data pad 64 remain thin and the remaining data wirings 60, 65, 66) The photoresist film PR remains thick at the top. At this time, the thickness of the thin portion of the photoresist film PR may be about 1/4 to 1/7 level of the initial thickness, that is, 350 to 10,000 GPa, more preferably 1,000 to 6,000 GPa.

The photoresist PR pattern is hard baked and ashed to remove the photoresist PR residue remaining on the upper layer 63 other than the portion to be the data wiring, and then the photoresist PR pattern is etched. The upper layer 63 is etched and then the lower layer 62 is etched to complete the lower layer 62 of the data lines 60, 64, 65, and 66.

Next, as shown in FIGS. 9A and 9B, the photoresist pattern PR is once again ashed to remove a thin portion of the photoresist film PR to expose a portion of the upper layer of the drain electrode 66 and an upper layer of the data pad. Subsequently, the photoresist film PR is once again hard baked and the exposed upper layer 63 is etched. At this time, the upper layer 63 covered by the photoresist film PR may also be slightly etched away from the lower layer 62.

Next, the exposed contact layer 50 is etched and separated on both sides, thereby completing contact layer patterns 55 and 56 under the source electrode 65 and the drain electrode 66.

In this case, the process after forming the photoresist film PR pattern may be performed as follows.

That is, the photoresist film PR remaining on the upper layer 63 other than the portion to be data wired by ashing without ashing is removed, and the upper layer 63 is etched using the photoresist pattern PR as an etching mask. Next, the photoresist PR pattern is ashed to remove the thin portion of the photoresist PR pattern, the remaining photoresist PR pattern is hard-baked, and the lower layer 62 is etched using the upper layer 63 pattern as an etching mask. The lower layer 62 pattern of (60, 64, 65, 66) is completed. Next, the upper layer 63 pattern is completed by hard baking the photoresist layer PR pattern and etching the exposed upper layer 63.

The table below compares the two methods of forming the data wiring described above.

First method 2nd method One Cr / Al-Nd Deposition Cr / Al-Nd Deposition 2 washing washing 3 Photoresist coating Photoresist coating 4 Exposure Exposure 5 phenomenon phenomenon 6 Hard bake Ashing 7 Ashing Primary Top Layer Etch 8 Primary Top Layer Etch Ashing (thin film removal) 9 Bottom layer etching Hard bake 10 Ashing (thin film removal) Bottom layer etching 11 Hard bake Hard bake 12 Second Top Layer Etch Second Top Layer Etch 13 Photoresist removal Photoresist removal

In the first method, the upper layer may be disconnected at the data line part during the second upper layer etching due to the excitation of the photoresist film PR that may occur during the first upper layer etching and the lower layer etching. However, in the second method, the surface damaged by the etchant in the first upper layer etching process is recovered to some extent in the second ashing process, and the adhesion between the photoresist film (PR) and the upper layer is improved in the hard bake process, so that the photoresist film remains after the lower layer etching process. It is not excited

Next, as shown in FIGS. 2 to 4, all of the photoresist film PR is removed, and silicon nitride is deposited by CVD to form a protective film 80 having a thickness of 3,000 Å or more, and thereafter, the protective film 80 is formed using a mask. The gate insulating film 30 is patterned to form these patterns including the contact windows 81, 82, and 83.

Finally, ITO or IZO is deposited and patterned using a mask to form the pixel electrode 70, the auxiliary gate pad 73, and the auxiliary data pad 74.

IZO is etched with Cr etchant at an etching rate of 2160 ~ 2580Å / min. This is because the ITO shows the etching rate of about 1050 ~ 1450Å / min by the ITO etchant, and the Cr has an etching rate of about 3000 ~ 6000Å / min by Cr etchant is never low. Therefore, when IZO is used as the material of the pixel electrode 70, the IZO may be patterned by using a Cr etchant. However, Al or Al-Nd forming the upper layer is not etched well by Cr etchant. Therefore, it is possible to prevent the upper layer from being damaged in the etching process for forming the pixel electrode 70. At this time, the Cr etchant contains about 10.5 to 10.99 wt% of CAN (cerium ammonium nitrite) and about 7.8 to 8.2 wt% of HNO ₃ in deionized water.

Meanwhile, the deposition of IZO is performed by applying a power of ₅ Kw among Ar 183 sccm and O ₂ 2.0 sccm. The deposition thickness is 500 kPa when scanned four times and 1400 kPa when scanned 11 times.

When the thin film transistor substrate is manufactured in the above manner, the connection between the data wiring layer and the pixel electrode layer through the contact hole is good, and the data wiring can be prevented from being damaged during the formation of the pixel electrode.

Claims (15)

Insulation board, A gate wiring formed on the insulating substrate and including a gate line, a gate electrode connected to the gate line, and a gate pad connected to an end of the gate line; A gate insulating film formed on the gate wiring, A semiconductor layer formed over at least the gate electrode on the gate insulating film, A first data line formed over the gate insulating film, a first source electrode connected to the first data line, a first drain electrode facing the first source electrode, and a first data line connected to an end of the first data line; A first data wire comprising one data pad, A second data wire formed on the first data wire, A passivation layer formed on the second data line, a portion of which is in contact with an upper surface of the first data line, and has a first contact hole for exposing the first drain electrode; A pixel electrode contacting only the first drain electrode through the first contact hole Thin film transistor substrate for a liquid crystal display device comprising a. In claim 1, The passivation layer may further include an auxiliary data pad having a second contact hole exposing the first data pad and contacting only the first data pad through the second contact hole. The method of claim 1 or 2, The second data line is made of aluminum-neodymium (Al-Nd), and the first data line is made of chromium. In claim 3, The gate wiring is a thin film transistor substrate for a liquid crystal display device comprising a double layer of a chromium layer and an aluminum-neodymium layer. In claim 1, The pixel electrode is a thin film transistor substrate for a liquid crystal display device made of IZO. Insulation board, A gate wiring formed on the insulating substrate and including a gate line, a gate electrode connected to the gate line, and a gate pad connected to an end of the gate line; A gate insulating film formed on the gate wiring,  A semiconductor layer formed on the gate insulating film of the gate electrode; A source electrode formed on the gate insulating layer and connected to the data line, the source electrode extending to the top of the semiconductor layer, a drain electrode facing the source electrode on the semiconductor layer, and connected to an end of the data line. A data wiring comprising a data pad, wherein the upper and lower layers are double layers; A passivation layer formed on the data line and having first to third contact holes exposing the drain electrode, the gate pad, and the data pad, respectively; A pixel electrode connected to the drain electrode through the first contact hole, A thin film transistor substrate for a liquid crystal display device completely surrounding the upper layer of the data line, the passivation layer, and the lower layer of the data line. Forming a gate wiring on the insulating substrate, Forming a gate insulating film, Forming a semiconductor layer, And a data layer, a source electrode, a drain electrode, and a data pad, and including a lower layer and a double layer of an upper layer formed on an inner upper portion of the lower layer, and a part of the upper layer of the drain electrode removes the data line of the structure. Forming step, Forming a protective film, Forming a pixel electrode in contact only with a lower layer of the drain electrode Method of manufacturing a thin film transistor substrate for a liquid crystal display device comprising a. In claim 7, Forming the data line Stacking a lower layer and an upper layer for data wiring; Applying, exposing and developing a photoresist to form a photoresist pattern having a portion of the upper portion of the drain electrode having a thickness thinner than that of other portions; Etching the upper layer and the lower layer for data wiring using the photoresist pattern as an etching mask; Ashing the photoresist pattern to expose an upper layer of the drain electrode; Etching the exposed top layer The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 8, And further comprising a hard bake and an ashing process after developing the photoresist film, and exposing the upper layer of the drain electrode by ashing the photoresist pattern, further comprising a hard bake process. Way. In claim 7, Forming the data line Stacking a lower layer and an upper layer for data wiring; Applying, exposing and developing a photoresist to form a photoresist pattern having a thickness thinner than that of other portions of the drain electrode, Etching the upper layer for data wiring using the photoresist pattern as an etching mask; Ashing the photoresist pattern to expose an upper layer of the drain electrode; Etching the lower layer using the upper layer as an etching mask; Etching the exposed top layer The manufacturing method of the thin film transistor substrate for liquid crystal display devices. In claim 10, After the photoresist is developed, an ashing process may be further included, and the hard bake process may be performed by ashing the photoresist pattern to expose the upper layer of the drain electrode and etching the lower layer using the upper layer as an etching mask. The manufacturing method of the thin film transistor substrate for liquid crystal display devices containing further. In claim 7, And removing an upper layer of the data pad in the step of forming the data line, and forming an auxiliary pad covering the data pad in the step of forming the pixel electrode. In claim 7, The upper layer of the data line is made of aluminum-neodymium, the lower layer is made of a thin film transistor substrate for a liquid crystal display device. In claim 13, The gate wiring is a double layer of a chromium layer and an aluminum-neodymium layer manufacturing method of a thin film transistor substrate for a liquid crystal display device. In claim 7, The pixel electrode is a method of manufacturing a thin film transistor substrate for a liquid crystal display device made of IZO.

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