JP2008034531A - Method for fabricating compound semiconductor optical device - Google Patents

Abstract

A method of manufacturing a compound semiconductor optical device that enables buried growth without using a mask.
A semiconductor region is formed on a main surface of a predetermined plane orientation of an InP substrate, and a semiconductor mesa is formed by anisotropic dry etching using a mask extending in a predetermined crystal axis direction. Then, after removing the mask 25a, the buried InP semiconductor 29 is formed so as to cover the side surface and the upper surface of the semiconductor mesa 13a. Therefore, abnormal growth due to the mask 25a does not occur. The InP semiconductor deposited on the semiconductor mesa 13a is removed by anisotropic etching using a hydrochloric acid / acetic acid aqueous solution. When the buried InP semiconductor 29 and the InP semiconductor cap layer 23a are etched using a hydrochloric acid / acetic acid-based aqueous solution, the GaInAs semiconductor 21a is exposed.
[Selection] Figure 5

Description

  The present invention relates to a method for producing a compound semiconductor optical device.

Patent Document 1 describes a method for manufacturing a semiconductor laser. In this production method, a source gas to which hydrogen chloride (HCl) is added in a range of group III source gas ratio, for example, in the range of 0.1 to 1.0 is used by a reduced pressure metal organic vapor phase growth method of about 20 to 100 torr. A buried layer such as InP is formed around the mesa structure. At this time, the growth temperature is set to 625 degrees Celsius or less to prevent diffusion of impurities already introduced, and to prevent deterioration of the interface of the multilayer structure such as MQW, thereby avoiding deformation of the mesa structure due to mass transport. it can. According to this semiconductor laser manufacturing method, the characteristics can be made uniform and the yield can be improved, and no exhaust gas treatment is required in the step of embedding the mesa structure flatly.
JP-A-8-78793

  In the method of manufacturing a semiconductor laser described in Patent Document 1, an InP buried layer is formed around a mesa structure using a film forming gas composed of hydrogen chloride (HCl) and a group III source gas. However, this method requires a hydrogen chloride line and a hydrogen chloride source connected to a reduced pressure metalorganic vapor phase growth furnace. Further, in addition to the change in the shape of the embedding depending on the ratio of the etching gas and the source gas, the mask is used for the formation of the embedding, so that the shape varies due to the mask. Therefore, the shape of the buried region and the variation over the wafer surface of this shape are not small.

  The present invention has been made in view of such circumstances, and an object of the present invention is to provide a method of manufacturing a compound semiconductor optical device that enables burying growth without using a mask.

  One aspect of the present invention is a method for fabricating a compound semiconductor optical device. In this method, (a) a semiconductor region including a first conductivity type InP semiconductor layer, an active layer, a second conductivity type InP semiconductor layer, a GaInAs semiconductor layer, and an InP semiconductor cap layer is formed on a main surface made of InP having a predetermined plane orientation. (B) forming a mask extending in the direction of a predetermined crystal axis on the semiconductor region; and (c) anisotropic drying of the semiconductor region using the mask. A semiconductor comprising an etched first conductivity type InP semiconductor layer, an etched active layer, an etched second conductivity type InP semiconductor layer, an etched GaInAs semiconductor layer, and an etched InP semiconductor cap layer Forming a mesa; (d) removing the mask after forming the semiconductor mesa; and (e) removing the mask. And (f) etching the buried InP semiconductor and the InP semiconductor cap layer of the semiconductor mesa using a hydrochloric acid / acetic acid-based aqueous solution so as to cover a side surface and an upper surface of the semiconductor mesa. And a step of forming an InP region in which a semiconductor stripe extending in the direction of the predetermined crystal axis is embedded.

  According to this method, after a semiconductor region is formed on a main surface having a predetermined plane orientation of an InP substrate, a semiconductor mesa is formed by anisotropic dry etching using a mask extending in the direction of a predetermined crystal axis. Then, after removing the mask, a buried InP semiconductor is formed so as to cover the side surface and the upper surface of the semiconductor mesa. Therefore, abnormal growth due to the mask does not occur. The InP semiconductor deposited on the semiconductor mesa is removed using a hydrochloric acid / acetic acid-based aqueous solution.

  In the method of manufacturing the compound semiconductor optical device according to the present invention, the predetermined plane orientation is preferably in the range of plus 5 degrees minus 5 degrees in the [011] direction from the (001) plane. According to this method, the shape of the buried InP is improved. In the method for producing a compound semiconductor optical device according to the present invention, the predetermined crystal axis is preferably within a range of plus 5 degrees minus 5 degrees from the <011> axis. According to this method, the shape of the buried InP is improved.

  In the method of manufacturing a compound semiconductor optical device according to the present invention, in the step of forming a buried InP semiconductor, the buried InP semiconductor is grown so as to form a ridge shape so as to cover the semiconductor mesa. The ridge-shaped side surface of the InP semiconductor is inclined with respect to the main surface in a range of 35 degrees to 55 degrees.

  According to the present invention, since the crystal growth is performed so that the side surface of the ridge portion is inclined in the range of 35 degrees to 55 degrees with respect to the main surface of the InP substrate, the InP semiconductor deposited on the semiconductor mesa It is removed using an acetic acid-based aqueous solution.

  In the method for producing a compound semiconductor optical device according to the present invention, the hydrochloric acid / acetic acid aqueous solution contains hydrochloric acid and acetic acid, the ratio of the hydrochloric acid to the acetic acid is greater than 1, and the predetermined crystal axis is <011>. The predetermined plane orientation is in the range of plus 5 degrees minus 5 degrees from the (001) plane.

  According to this method, when InP is etched using an etchant having a ratio of hydrochloric acid and acetic acid greater than 1, the etching rate and etching characteristics for InP are suitable. In the etching using the above etchant, the etching rate of the GaInAs semiconductor is lower than the etching rate of the InP semiconductor. Therefore, the etched GaInAs semiconductor layer can be exposed after forming the InP region in which the semiconductor mesa is embedded.

  In the method of manufacturing the compound semiconductor optical device according to the present invention, after forming the InP region for embedding the etched GaInAs semiconductor layer of the semiconductor stripe, forming an electrode electrically connected to the semiconductor stripe Is preferably further provided.

  According to this method, since the semiconductor mesa includes a GaInAs semiconductor layer, a compound semiconductor optical device can be fabricated without growing an InP semiconductor layer and a GaInAs contact layer on the semiconductor mesa and the buried InP semiconductor.

  The above and other objects, features, and advantages of the present invention will become more readily apparent from the following detailed description of preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings.

  As described above, according to the present invention, there is provided a method for manufacturing a compound semiconductor optical device that enables burying growth without using a mask.

  The knowledge of the present invention can be easily understood by considering the following detailed description with reference to the accompanying drawings shown as examples. Subsequently, an embodiment relating to a method for producing a compound semiconductor optical device of the present invention will be described with reference to the accompanying drawings. Where possible, the same parts are denoted by the same reference numerals.

(First embodiment)
1A and 1B are drawings schematically showing steps of a method for manufacturing a compound semiconductor optical device according to the present embodiment. As a compound semiconductor optical device, for example, the structure of a semiconductor laser will be described as an example. As shown in FIG. 1A, a substrate 11 is prepared. The substrate 11 has a main surface 11a having a predetermined plane orientation and made of an InP semiconductor. The crystal plane orientation of the main surface 11a is in the range of plus 5 degrees to minus 5 degrees with reference to the (001) plane, and is preferably the (001) plane. In one example, the substrate 11 can be, for example, an InP substrate. The description “(001) plane” also indicates a crystallographically equivalent plane to the (001) plane.

  In the field of compound semiconductors, a compound semiconductor optical device may be manufactured using a substrate (off-angle substrate) having a surface slightly inclined from a specific crystal plane such as the (001) plane. FIG. 2A and FIG. 2B are drawings showing off angles with respect to the main surface of the InP substrate. Referring to FIG. 2A, an InP substrate SUB1 is shown. The InP substrate SUB1 has an orientation flat OF1. The reference surface Ref1 extends along the (001) plane of the InP substrate SUB1. The reference surface Ref1 forms an off angle Angle1 of 5 degrees in the [011] direction with the main surface SURF1 of the InP substrate SUB1. Further, referring to FIG. 2B, an InP substrate SUB2 is shown. The InP substrate SUB2 has an orientation flat OF2. The reference plane Ref2 extends along the (001) plane of the InP substrate SUB2. The reference surface Ref2 forms an off angle Angle2 of minus 5 degrees in the [011] direction, for example, with the main surface SURF2 of the InP substrate SUB2. The main surface 11a of the substrate 11 is located between the reference surface Ref1 and the reference surface Ref2.

  As shown in FIG. 1B, a plurality of semiconductor films of the semiconductor region 13 are formed in order on the substrate 11. The semiconductor region 13 includes a first conductivity type InP semiconductor layer 15, an active layer 17, a second conductivity type InP semiconductor layer 19, a GaInAs semiconductor layer 21 and an InP semiconductor cap layer 23. This growth is performed using, for example, a metal organic chemical vapor deposition method.

In one embodiment, the semiconductor stack is
Substrate 11: InP substrate, plane orientation (001) plus 0.1 degree to minus 0.1 degree First conductivity type InP semiconductor layer 15 (cladding layer):
n-type InP, thickness 0.5 μm, carrier concentration 1 × 10 ¹⁸ cm ⁻³
Active layer 17:
InGaAsP multiple quantum well structure, 0.3 micrometer thick second conductivity type InP semiconductor layer 19 (cladding layer):
p-type InP, thickness 2.0 μm, carrier concentration 1 × 10 ¹⁸ cm ⁻³
GaInAs semiconductor layer 21:
p-type GaInAs, thickness 0.2 μm, carrier concentration 1 × 10 ¹⁹ cm ⁻³
InP semiconductor cap layer 23:
p-type InP, thickness 0.2 μm, carrier concentration 1 × 10 ¹⁸ cm ⁻³
It is. In this semiconductor stack, a GaInAs semiconductor layer 21 for a contact layer is provided on a second conductivity type InP semiconductor layer 19.

  After the semiconductor region 13 is grown on the substrate 11, a mask for forming a mesa structure is formed. Subsequently, an example of mask formation will be described. As shown in FIG. 3A, a mask film 25 such as a silicon-based inorganic compound film is deposited on the semiconductor region 13. For example, a silicon oxide film, a silicon nitride film, or the like can be used as the silicon-based inorganic compound film. This mask film is made of a film thickness and material that can withstand subsequent dry etching. For example, a plasma SiN film having a thickness of 0.1 to 0.3 micrometers can be used as a mask film.

  As shown in FIG. 3B, a mask 25a is formed by photolithography. For example, the mask film 25 is selectively etched using the resist mask 27 to form the mask 25a. After forming the mask 25a, the resist mask 27 is removed. As a result, a mask 25 a extending in the direction of a predetermined crystal axis is formed on the semiconductor region 13. The orientation of the predetermined crystal axis is in the range of plus 5 degrees to minus 5 degrees with reference to the <011> direction, and preferably the <011> direction. According to this, the shape of the buried InP is improved. The description “<011>” also indicates a crystallographically equivalent direction to the <011> direction. For example, in an InP substrate having a (001) plane, the direction is perpendicular to the orientation flat of the InP substrate, as shown in FIGS. 2 (a) and 2 (b).

  FIG. 4A is a drawing schematically showing a process of dry etching a semiconductor region. The semiconductor region 13 is dry-etched by reactive ion etching using the mask 25a to form a semiconductor region 13a having a mesa structure (referred to as “semiconductor mesa”). By anisotropically etching the semiconductor region 13, the etched first conductivity type InP semiconductor layer 15a, the etched active layer 17a, the etched second conductivity type InP semiconductor layer 19a, and the etched GaInAs semiconductor layer A semiconductor mesa 13a including 21a and an etched InP semiconductor cap layer 23a is formed. The semiconductor mesa 13a extends in the direction of the predetermined crystal axis. Since the semiconductor mesa 13 a is formed by dry etching, the side surface of the semiconductor mesa 13 a is substantially perpendicular to the main surface of the substrate 11. The width of the semiconductor mesa 13a is, for example, about 0.8 to 1.5 micrometers. If the width of the semiconductor mesa 13a is 0.8 micrometers or more, the transverse mode single condition is satisfied. If the width of the semiconductor mesa 13a is 1.5 micrometers or less, the transverse mode single condition is satisfied.

  Next, as shown in FIG. 4B, after the semiconductor mesa 13a is formed, the mask 25a is removed. This removal can remove the SiN mask using a hydrofluoric acid based etchant.

  FIG. 5A is a drawing showing a process of performing the buried growth. After removing the mask 25a, a buried InP semiconductor 29 is deposited. This deposition is performed using, for example, a metal organic chemical vapor deposition method. The thickness of the buried InP semiconductor 29 is approximately the same as the height of the semiconductor mesa 13a. During this deposition, the InP semiconductor is deposited on the side surface of the semiconductor mesa 13a to embed the semiconductor mesa 13a and rise up on the semiconductor mesa 13a. As a result, the buried InP semiconductor 29 is formed so as to cover the side surface and the upper surface of the semiconductor mesa 13a. For example, Fe-doped InP can be used as a semiconductor for buried growth.

  The buried InP semiconductor 29 has a ridge portion 29a that rises so as to cover the semiconductor mesa 13a, and a buried portion 29b in which the semiconductor mesa 13a is buried. The ridge portion 29a of the buried InP semiconductor 29 has a side surface that is inclined at an angle Angle3 in a range of 35 degrees to 55 degrees with respect to the main surface 11a. In a III-V compound semiconductor grown on a substrate 11 having a predetermined plane orientation, when a crystal plane in the above angle range appears, stable crystal growth becomes possible, and as a result, abnormal growth occurs during buried growth. The possibility of occurrence is reduced. Therefore, the uniformity of embedding is improved.

  FIG. 5B is a diagram illustrating a process of etching a buried InP semiconductor. When a hydrochloric acid / acetic acid aqueous solution is used, the embedded InP semiconductor 29 is partially etched and the InP semiconductor cap layer 23a of the semiconductor mesa 13a is etched. In this way, the InP region 31 is formed in which the semiconductor stripe 13b extending in the direction of the predetermined crystal axis is embedded.

  According to this method, after forming the semiconductor region 13 on the main surface of the substrate 11 in a predetermined plane orientation, the semiconductor mesa 13a is formed by anisotropic dry etching using a mask extending in the direction of the predetermined crystal axis. . Then, after removing the mask 25a, the buried InP semiconductor 29 is formed so as to cover the side surface and the upper surface of the semiconductor mesa 13a. Therefore, abnormal growth due to the mask 25a does not occur. The InP semiconductor deposited on the semiconductor mesa 13a is removed by anisotropic etching using a hydrochloric acid / acetic acid aqueous solution. When the buried InP semiconductor 29 and the InP semiconductor cap layer 23a are etched using a hydrochloric acid / acetic acid-based aqueous solution, the GaInAs semiconductor 21a is exposed and a semiconductor stripe buried by the InP region 31 is produced.

The hydrochloric acid / acetic acid aqueous solution of the preferred embodiment is
Hydrochloric acid: acetic acid = 1: x
5 <x <7. When the ratio x is smaller than 5, the etching amount in the side surface direction becomes small, and irregularities remain on the surface. When the ratio x is larger than 7, the etching amount in the surface direction becomes small, and InP remains on the contact layer (GaInAs layer). In one embodiment, hydrochloric acid: acetic acid: water = 1: 6: 1. When this anisotropic etchant is used, the etching rate on the side surface of the InP semiconductor 29a grown on the semiconductor mesa 13a is large, and the etching rate of the InP semiconductor 29b on the substrate surface (for example, (001) plane) is small. As a result, the InP semiconductor grown on the semiconductor mesa 13a can be selectively removed. Further, in this etchant, the etching rate of InGaAs is high, but the etching rate of InGaAs is low. Etching can be stopped using the InGaAs contact layer 23a in the semiconductor mesa 13a.

  FIG. 6 is a drawing showing an SEM photograph of a cross section of a semiconductor product in the step of performing the buried growth. As shown in this drawing, since the side surface of the ridge portion 29a is inclined with respect to the main surface 11a of the InP substrate 11 within a range of 35 degrees to 55 degrees, the InP semiconductor 29 deposited on the semiconductor mesa 13a is hydrochloric acid. -Isotropically etched with acetic acid aqueous solution. Referring to FIG. 6, the inclination angle of the side surface in the vicinity of the ridge of the ridge portion 29a is relatively small and is close to 35 degrees. Further, the inclination angle of the side surface close to the top of the ridge portion 29a is relatively large and is an angle close to 55 degrees.

  FIG. 7A illustrates a step of forming an insulating film. An insulating film 33 is deposited on the semiconductor stripe 13 b and the buried InP region 31. The insulating film can be made of, for example, silicon oxide. The insulating film 33 has an opening 33a extending along the semiconductor stripe 13b. The InGaAs semiconductor layer 23a is exposed in the opening 33a.

  As shown in FIG. 7B, after forming an InP region 31 that embeds the etched GaInAs semiconductor layer (contact layer) 23a of the semiconductor stripe 13b, an electrode 35 electrically connected to the semiconductor stripe 13b is formed. To do. Further, another electrode 37 is formed on the back surface 11 b of the substrate 11. The electrode 35 is, for example, an anode electrode, and the electrode 37 is, for example, a cathode electrode.

  In this compound semiconductor optical device, since the semiconductor mesa 13a includes the GaInAs semiconductor layer 23a, the compound semiconductor optical device is grown without growing the InP semiconductor cladding layer and the GaInAs semiconductor contact layer on the semiconductor stripe 13b and the embedded InP semiconductor 31. Can be made. Therefore, the manufacturing process is shortened.

  In the method according to the present embodiment, the hydrochloric acid / acetic acid aqueous solution contains hydrochloric acid and acetic acid. The ratio of hydrochloric acid to acetic acid is greater than 1. The predetermined crystal axis is in the range of plus 5 degrees minus 5 degrees from the <011> axis, and the predetermined plane orientation is in the range of plus 5 degrees minus 5 degrees from the (001) plane. For this reason, when InP is etched using an etchant having a ratio of hydrochloric acid and acetic acid larger than 1, the etching rate and etching anisotropy with respect to InP are suitable. In the etching using the above etchant, the etching rate of the GaInAs semiconductor is smaller than the etching rate of the InP semiconductor. Therefore, after forming the InP region in which the semiconductor mesa is embedded, the GaInAs semiconductor layer in the semiconductor stripe 13b is exposed. it can.

  As described above, unlike Patent Document 1, the crystal growth apparatus does not require a hydrogen chloride supply line. Further, since the buried growth is performed after the mask is removed, abnormal growth due to the use of the mask does not occur. Further, since a stable crystal plane appears in the embedment growth, it is possible to realize a embedment shape with small in-plane variation and excellent uniformity and reproducibility.

  While the principles of the invention have been illustrated and described in the preferred embodiments, it will be appreciated by those skilled in the art that the invention can be modified in arrangement and detail without departing from such principles. In the present embodiment, for example, a compound semiconductor optical device such as a semiconductor laser has been described. However, the present invention is not limited to the specific configuration disclosed in the present embodiment. In this embodiment, the semiconductor laser is described as an example, but the present invention can also be applied to a semiconductor optical modulator, an integrated element of the semiconductor optical modulator and the semiconductor laser, and the like. We therefore claim all modifications and changes that come within the scope and spirit of the following claims.

1A and 1B are drawings schematically showing steps of a method for manufacturing a compound semiconductor optical device according to the present embodiment. FIG. 2A and FIG. 2B are diagrams schematically showing an off-angle with respect to the main surface of the InP substrate. FIG. 3A is a drawing schematically showing a process of depositing a mask film 25 such as a silicon-based inorganic compound film on a semiconductor region. FIG. 3B is a drawing schematically showing a process of forming the mask 25a using a photolithography method. FIG. 4A is a drawing schematically showing a step of dry etching a semiconductor region. FIG. 4B schematically shows a process of removing the mask 25a after forming the semiconductor mesa. FIG. 5A is a drawing schematically showing a process of performing the buried growth. FIG. 5B is a drawing schematically showing a process of etching a buried InP semiconductor. FIG. 6 is a drawing showing an SEM photograph of a cross section of a semiconductor product in the step of performing the buried growth. FIG. 7A is a drawing schematically showing a step of forming an insulating film. FIG. 7B is a drawing schematically showing a process of forming an electrode electrically connected to the semiconductor stripe and an electrode connected to the back surface of the substrate.

Explanation of symbols

SUB1, SUB2 ... InP substrate, OF1, OF2 ... Orientation flat, Ref1, Ref2 ... Reference plane, SURF1, SURF2 ... InP substrate main surface, 11 ... Substrate, 11a ... InP semiconductor main surface, 13 ... Semiconductor region, 13a ... Semiconductor mesa , 13b ... semiconductor stripe, 15 ... first conductivity type InP semiconductor layer, 15a ... etched first conductivity type InP semiconductor layer, 17 ... active layer, 17a ... etched active layer, 19 ... second conductivity type InP semiconductor. Layer, 19a ... etched second conductivity type InP semiconductor layer, 21 ... GaInAs semiconductor layer, 21a ... etched GaInAs semiconductor layer, 23 ... InP semiconductor cap layer, 23a ... etched InP semiconductor cap layer, 25 ... mask Membrane, 25a ... mask, 27 ... resist mask, 29 Buried InP semiconductor, 29a ... ridge, 29 b ... buried section, 31 ... InP region 33 ... insulating film, 33a: insulating film opening, 35, 37 ... electrode

Claims (6)

A method for producing a compound semiconductor optical device, comprising:
A semiconductor region including a first conductivity type InP semiconductor layer, an active layer, a second conductivity type InP semiconductor layer, a GaInAs semiconductor layer, and an InP semiconductor cap layer is sequentially grown on a substrate having a main surface made of InP having a predetermined plane orientation. And a process of
Forming a mask extending in the direction of a predetermined crystal axis on the semiconductor region;
Using the mask, anisotropic dry etching of the semiconductor region is performed to etch the first conductivity type InP semiconductor layer, the etched active layer, the etched second conductivity type InP semiconductor layer, and the etched GaInAs. Forming a semiconductor mesa including a semiconductor layer and an etched InP semiconductor cap layer;
Removing the mask after forming the semiconductor mesa;
Forming a buried InP semiconductor so as to cover a side surface and an upper surface of the semiconductor mesa after removing the mask;
Etching the buried InP semiconductor and the InP semiconductor cap layer of the semiconductor mesa with a hydrochloric acid / acetic acid aqueous solution to form an InP region in which a semiconductor stripe extending in the direction of the predetermined crystal axis is buried. A method characterized by.   2. The method according to claim 1, wherein the predetermined plane orientation is within a range of plus 5 degrees and minus 5 degrees in the [011] direction from the (001) plane.   The method according to claim 1 or 2, wherein the predetermined crystal axis is in a range of plus 5 degrees minus 5 degrees from the <011> axis.   In the step of forming the buried InP semiconductor, the buried InP semiconductor is grown so as to form a ridge shape so as to cover the semiconductor mesa, and the side surface of the ridge shape of the buried InP semiconductor is in relation to the main surface. The method according to claim 1, wherein the inclination is in the range of not less than 35 degrees and not more than 55 degrees. The hydrochloric acid / acetic acid aqueous solution contains hydrochloric acid and acetic acid,
The ratio of hydrochloric acid to acetic acid is greater than 1,
The predetermined crystal axis is in the range of plus 5 degrees minus 5 degrees from the <011> axis,
5. The method according to claim 4, wherein the predetermined plane orientation is in a range of plus 5 degrees minus 5 degrees from the (001) plane. The method of claim 1, further comprising: forming an electrode electrically connected to the etched GaInAs semiconductor layer of the semiconductor stripe after forming the InP region that embeds the semiconductor stripe. Item 6. The method according to any one of Items 5.

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