CN100407374C - Nitride semiconductor substrate and nitride semiconductor device using same - Google Patents

Abstract

Polycrystalline AlN 3 is deposited on the surface of the SiO ₂ film (2) by sputtering method, and forms a mask. Then, Si-doped n-GaN layer 5 is formed on the formed mask. Subsequently, an n-type coating (6) formed of Si-doped n-type Al _0.1 Ga _0.9 N (silicon content 4×10 ¹⁷ cm ^-3 , thickness 1.2 μm) is grown sequentially; n-type light trapping layer (7) formed by doped n-type GaN; multiple quantum well layer (8) formed by In _0.2 Ga _0.8 N potential well layer and Si-doped In _0.05 Ga _0.95 N barrier layer; A protective layer (9) formed of Mg-doped p-type Al _0.2 Ga _0.8 N; a p-type light-trapping layer (10) formed of Mg-doped p-type GaN; a Mg-doped a p-type cladding layer (11) formed of p-type Al _0.1 Ga _0.9 N; and a p-type contact layer (12) formed of Mg-doped p-type GaN, thereby forming an LD layer structure.

Description

Nitride semiconductor substrate and nitride semiconductor device using same

technical field

The present invention relates to a nitride semiconductor substrate and a nitride semiconductor device using the nitride semiconductor substrate.

Background technique

When forming a device using a nitride semiconductor, it is important to suppress threading dislocations in the semiconductor layer. As a technique for suppressing such threading dislocations, well known is the method disclosed in Japanese Laid-Open Patent Publication 11-251253, in which selective growth is performed using a masking material. The method disclosed in Japanese Laid-Open Patent Publication No. 11-251253 will be explained below with reference to FIG. 7 .

According to the method disclosed in this publication, a substrate having a 1.2 μm-thick GaN single film 112 previously formed on a (0001) plane sapphire substrate 111 was prepared. A 200 nm-thick SiO ₂ film is formed on the surface of GaN film 112 , and the SiO ₂ film is separated into mask 114 and growth region 113 by photolithography process and wet etching. Growth region 113 and mask 114 are formed in stripes with widths of 5 μm and 2 μm, respectively. The orientation of these stripes is <11-20> (Fig. 7(a)).

The GaN film 115 grown in the growth region 113 is formed by the hydride VPE method using ammonia (NH ₃ ) gas as a group V starting material and gallium chloride (GaCl), which is hydrogen chloride (HCl) and The reaction product of the Group III starting material gallium (Ga). Dichlorosilane (SiH ₂ Cl ₂ ) was used as n-type dopant material. The substrate 111 was placed in a hydride grower, and then the temperature was raised to a growth temperature of 1000° C. under a hydrogen atmosphere. After the growth temperature stabilized, a plane structure including {1-101} planes of GaN film 115 was grown in growth region 113 by supplying HCl at a flow rate of 20 cc/min for about 5 minutes ( FIG. 7( b )). Growth continued until the layer thickness reached 140 μm and passed through the n-type dopant dichlorosilane ( FIG. 7 ( c ), ( d ), ( e )). According to this technology, even when a GaN film of several hundreds of micrometers is to be formed, a 2-inch-sized wafer with no cracks on the entire surface can be provided. The dislocation density of the substrate is greatly reduced, and the dislocation density of the GaN monolayer film 112 can be reduced from about 10 ⁹ /cm ² to about 1×10 ⁷ -2×10 ⁷ /cm ² .

Contents of the invention

However, even if the dislocation density is reduced by the above techniques, dislocations of 1×10 ⁷ to 2×10 ⁷ /cm ² still exist. When considering a semiconductor with 2 μm wide stripes and 500 μm long resonators, a dislocation density of 1×10 ⁷ to 2×10 ⁷ /cm ² corresponds to 100–200 dislocations per stripe of an LD device . Dislocations are known to shorten the lifetime of devices, so further dislocation reductions are needed.

It is an object of the present invention to provide a substrate or device comprising a Group III semiconductor layer having reduced dislocations and good quality.

In order to reduce the dislocation of the Group III nitride semiconductor layer, it can be considered to use the low dislocation substrate obtained by the process shown in Figure 7, it can also be considered to form a similar mask pattern on it, and it can be considered to grow by metal-organic vapor phase epitaxy ( MOVPE) for growth. FIG. 8 shows a diagram of the semiconductor layer structure obtained by this method. This layer structure can be formed as follows.

First, a SiO ₂ stripe mask 117 is formed in the <11-20> direction using the substrate 116 described with reference to FIG. 7 . The dislocation density near the surface of the substrate 116 is about 2×10 ⁷ /cm ² . The width of the mask opening 117a is 2 μm, and the SiO ₂ mask area is 18 μm. In the MOVPE apparatus, Si-doped GaN is formed in the opening 117a of the wafer on which the above-mentioned mask is formed. The grown GaN layer in the opening of the mask continues to grow laterally, and passes through the mask to combine adjacent GaN layers (hereinafter, this part is referred to as a connection part).

The GaN layer is planarized in this manner, forming n-GaN layer 118 . An n-type cladding layer 119 made of Si-doped n-type Al _0.1 Ga _0.9 N (silicon content of 4×10 ¹⁷ cm ^-3 , thickness 1.2 μm), the n-type light trapping layer 120 is formed of Si-doped n-type GaN (silicon content 4×10 ¹⁷ cm ^-3 , thickness 0.1 μm) . Then sequentially grow an In _0.2 Ga _0.8 N potential well layer (thickness 4nm) and a Si-doped In _0.05 Ga _0.95 N barrier layer (silicon content 5×10 ¹⁸ cm ^-3 , thickness 6nm) on it The formed multiple quantum well (MQW) layer 121 (the number of potential wells is 3); the protective layer (cap layer) 122 formed by Mg-doped p-type Al _0.2 Ga _0.8 N; the Mg-doped p-type p-type light trapping layer 123 formed of GaN (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.1 μm); p-type Al _0.1 Ga _0.9 N doped with Mg (Mg content 2×10 ¹⁷ cm ^-3 , a thickness of 0.5 μm) formed of a p-type plating layer 124; and a p-type contact layer formed of Mg-doped p-type GaN (Mg content of 2×10 ¹⁷ cm ^-3 , thickness of 0.1 μm) 125, thus forming the LD structure.

In order to study the dislocation behavior of the thus formed LD layer structure, a cross-sectional cathode luminescence (CL) image was studied, and the results obtained are shown in FIG. 9 . As can be clearly seen from FIG. 9, a large number of black dots and black lines appeared in the layer formed on the substrate. In CL images, for example in Sugahara, M.Hao, T.Wang, D.Nakagawa, Y.Naoi, K.Nishino and S.Sakai, Jpn.J.Appl.Phys.vol.37, no.10B, L1195- As described on page L1198, October 1998, the places where dislocations are present appear as black spots because dislocations favor light that is not emitted. Therefore, the black lines and dots are considered to represent dislocations. From the above, it can be found that new dislocations are generated as a result of the selective growth using the second mask pattern. This phenomenon is considered to occur even in the case of using the first mask pattern in Fig. 7, but since the dislocation density in the base of the first mask pattern is very high, it is impossible to CL observations identify the presence or absence of newly generated dislocations.

Fig. 10 is a planar CL image in which an InGaN luminescence image was observed from the above-mentioned sample of Fig. 8 when an electron beam was applied. In Fig. 10, a large number of black lines can be observed in the planar CL image. This situation indicates the presence of dislocations in the InGaN layer 121 formed of InGaN.

However, when the sample of FIG. 9 is actually examined using a transmission electron microscope, dislocations also exist in the in-plane direction of other layers besides the multiple potential well (MQW) layer 121 . Therefore, it is clear that for the layer structure of Fig. 8, there is still room for further improvement of device properties and device lifetime.

The behavior and reasons why these dislocations occur are explained below. Many dislocations that exist near the mask are thought to be caused by many reasons, for example, dislocation bending due to lateral growth of dislocations inherited from the substrate, and generation of dislocations at the interface between the mask and the laterally grown nitride semiconductor crystal. Dislocations, and dislocations are generated on the growth surface of the nitride semiconductor during lateral growth. The first dislocation extending down from the substrate depends on the dislocation density of the substrate, but the occurrence of other dislocations and the reason why these dislocations are introduced into the device layer structure are considered to depend on the interaction between the masking material and the nitride semiconductor crystal. affinity and stress during growth. When the sample of FIG. 8 is subjected to cross-sectional TEM observation in the <11-20> direction, it can be confirmed that a large number of dislocations appear in the <11-20> direction of the nitride semiconductor near the masking material. Therefore, it is presumed that all dislocations present in the mask are bent in the <11-20> direction due to the influence of the stress caused by the mask or the like. A dislocation that was once bent in the <11-20> direction traverses in the horizontal plane of the substrate and, for various reasons, in another direction in the horizontal plane (e.g., in a direction corresponding to the <1-100> direction Direction > slip. It can be speculated that this is the dislocation identified in Figure 9 and confirmed in cross-sectional TEM observations.

As a result of the inventors' studies, it was found in the sample of FIG. 8 that dislocations grow in the horizontal plane as described above, and that such dislocations were also introduced into the InGaN layer belonging to the active layer.

That is, the research results of the present inventors are set forth below;

(i) When a mask is placed on a low-dislocation substrate and a Group III nitride semiconductor is grown thereon, many dislocations develop from the vicinity of the mask, and

(ii) The development of such dislocations is more pronounced when using a substrate with a low dislocation density.

This phenomenon becomes more pronounced for substrates where dislocations have been reduced below 10 ⁷ /cm ² .

Although the reason for the above phenomenon is not completely clear, it can be speculated that when the substrate dislocation density is high, many dislocations appear around the mask due to regrowth, and these dislocations relieve the crystal strain, while at low dislocation density In substrates (eg, below 10 ⁷ /cm ² ), this relief of crystalline strain occurs only slightly.

On the basis of this assumption, the present inventors conceived the idea that when a group III nitride semiconductor is a mask for growth on a low-dislocation substrate, intentionally forming The region is an effective way, therefore, the present invention is accomplished.

According to the present invention, there is provided a nitride semiconductor substrate comprising a group III nitride semiconductor substrate; a mask formed on the group III nitride semiconductor substrate and a semiconductor multilayer film formed on the mask, wherein A polycrystalline material is deposited on the mask surface.

Furthermore, according to the present invention, there is provided a nitride semiconductor device including a group III nitride semiconductor substrate, a mask formed on the group III nitride semiconductor substrate, and a mask including an active layer formed on the mask. A semiconductor multilayer film, wherein polycrystalline material is deposited on the mask surface.

According to the present invention, crystalline strain on the mask is relieved by the polycrystalline material deposited on the surface of the mask, thereby improving the crystalline quality of the semiconductor multilayer film formed on the mask. In such a semiconductor device, since the mask having the polycrystalline material deposited on its surface is disposed under the active layer, the quality of the active layer can be significantly improved.

As described above, according to the present inventors' studies, when a substrate having fewer dislocations such as a Group III nitride semiconductor substrate is used, dislocations occurring near the mask on the substrate become a problem. According to the present invention, since such dislocations can be effectively reduced, this difficult feature of using a group III nitride semiconductor substrate can be effectively solved while utilizing the benefits of the group III nitride semiconductor substrate.

The Group III nitride semiconductor substrate of the present invention preferably has a dislocation density of 1×10 ⁷ /cm ² or less in the vicinity of its surface. The present invention effectively solves the difficult feature when growing a semiconductor layer from a mask on such a low-dislocation substrate, that is, the problem of developing new dislocations near the mask, and when using such a substrate, can exhibit more Excellent effect. The dislocation density of the substrate can be measured by a method in which the surface of the substrate is treated with a liquid reagent to form etch pits and then the density thereof is measured; a method in which a cross-section of a structure having formed Semiconductors on substrates; methods for detecting cathodoluminescence images; etc. Among them, a method using cathodoluminescence is preferably used because it has high measurement accuracy.

As described above, according to the present invention, there is provided a substrate or a device including a group III nitride semiconductor layer having reduced dislocations and good quality.

Description of drawings

The above objects, other objects, features and advantages will be apparent from the following description of the preferred embodiments described with reference to the accompanying drawings.

[ Fig. 1 ] A cross-sectional view of a semiconductor device related to an embodiment.

[ Fig. 2 ] A cross-sectional view of a semiconductor device related to an embodiment.

[ Fig. 3 ] A cross-sectional view of a semiconductor device related to an embodiment.

[ Fig. 4 ] A cross-sectional view of a semiconductor device related to an embodiment.

[ Fig. 5 ] A cross-sectional view of a semiconductor device related to an embodiment.

[ Fig. 6 ] A cross-sectional view of a semiconductor device related to an embodiment.

[ Fig. 7 ] Cross-sectional views showing process steps of manufacturing a conventional semiconductor device.

[ Fig. 8 ] shows a layer structure obtained by growing a semiconductor layer on a low-dislocation substrate through a mask opening.

[ Fig. 9 ] shows the result of examining a cross-sectional cathodoluminescence (CL) image of the structure shown in Fig. 8 .

[ Fig. 10 ] shows the result of examining a planar cathodoluminescence (CL) image of the structure shown in Fig. 8 .

Detailed ways

In the present invention, various materials can be used as the polycrystalline material. For example, it may be a material containing aluminum and nitrogen as basic elements. For example, materials such as AlGaN, AlN, or InAlGaN may be used. When such a material is selected, a structure suitable for reducing crystallographic strain can be obtained.

The surface of the mask on which the polycrystalline material is formed preferably has a void structure. In this way, through the role of voids, the crystallization strain can be reduced more effectively.

In the present invention, the mask may be provided directly on the surface of the Group III nitride semiconductor substrate, or disposed via a semiconductor layer or an insulating layer. When the mask is provided directly on the surface of the substrate, the effect of reducing crystal strain can be more reliably obtained.

The present invention exhibits more excellent effects when using a Group III nitride semiconductor substrate whose dislocation density near the surface is 1×10 ⁷ or less. As described above, the present invention is effective in suppressing dislocations that would develop from the vicinity of the mask on the low-dislocation substrate. As for a substrate with a dislocation density of 1×10 ⁷ or less, although the dislocation originating from the substrate can be reduced, there is still a problem of causing other dislocations due to crystal strain occurring near the mask. Such a problem is particularly prominent in the case of the above-mentioned low dislocation density substrate, but according to the present invention, this problem can be effectively solved, while the problematic characteristics when using a low dislocation substrate can be solved, the characteristics of the low dislocation substrate can also be utilized. advantage.

(Example)

Hereinafter, the present invention is explained in further detail with reference to Examples. The following examples use a substrate obtained by growing a GaN film using a method similar to that explained in FIG. 7 and using a mask thicker than conventional. This mask has a mask width of 2 μm and a mask height of 1.7 μm, and can obtain a substrate with smaller surface dislocations than that obtained by the method of FIG. 7 .

Next, preferred embodiments of the nitride semiconductor substrate according to the present invention and a semiconductor laser produced using the nitride semiconductor substrate are explained with reference to Examples.

Example 1

FIG. 1 shows the structure of a semiconductor laser according to this embodiment.

Such a semiconductor laser can be produced as follows. First, SiO ₂ film 2 is deposited on GaN substrate 1 with a dislocation density of 9×10 ⁶ /cm ² in the vicinity of the substrate by CVD method or plasma CVD method. Subsequently, polycrystalline AlN3 was deposited by sputtering, and a resist stripe mask was formed in the <11-20> direction. The mask has a width of 18 μm and an opening width of 2 μm.

When forming polycrystalline AlN3, the following steps are performed.

(i) After forming the _SiO2 film 2, the wafer was ultrasonically cleaned with methyl ethyl ketone and ethanol, washed with pure water, etched with buffered hydrochloric acid for 1 second, washed with pure water, and then dried with nitrogen gas.

(ii) Subsequently, the wafer was inserted into a sputtering apparatus, and deposition was performed by AlN sputtering while maintaining the substrate temperature at 50° C. or higher.

The polycrystalline AlN3 and _SiO2 film 2 is then etched by dry and wet etching to expose the substrate surface at the opening 4.

Subsequently, in the MOVPE apparatus, using the above-mentioned mask-formed wafer, silicon-doped GaN was formed at the opening. As for the MOVPE growth after the opening is formed, the substrate is first kept at 600°C for 5 minutes while passing ammonia gas, then heated to the GaN growth temperature of 1080°C for 30 seconds, and then the growth starts.

The GaN layer grown from the opening of the mask is then grown laterally, and adjacent GaN layers are bonded together through the mask (hereinafter, this portion is referred to as a connection portion).

The GaN layer is planarized in this way, forming the n-GaN layer 5, and forming the semiconductor substrate including a mask having polycrystalline AlN3 formed thereon. Voids are introduced in the n-GaN layer 5 around the region where polycrystalline AlN3 is formed.

In this embodiment, the growth of the semiconductor layer then proceeds sequentially to form the device. First, the n-type coating 6 formed of Si-doped n-type Al _0.1 Ga _0.9 N (silicon content 4×10 ¹⁷ cm ^-3 , thickness 1.2 μm) is sequentially grown; the Si-doped n-type light trapping layer 7 formed of n-type GaN (silicon content 4×10 ¹⁷ cm ^-3 , thickness 0.1 μm); potential well layer 7 composed of In _0.2 Ga _0.8 N (thickness 4nm) and Si-doped In _0.05 Ga _0.95 N (silicon content 5×10 ¹⁸ cm ^-3 , thickness 6nm) barrier layer to form a multiple quantum well (MQW) layer 8 (the number of potential wells is 3); p-type Al doped with Mg Protective layer 9 formed of _0.2 Ga _0.8 N; p-type light-trapping layer 10 formed of Mg-doped p-type GaN (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.1 μm); Mg-doped p-type coating 11 formed of p-type Al _0.1 Ga _0.9 N (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.5 μm); and p-type GaN doped by Mg (Mg content 2× 10 ¹⁷ cm ⁻³ , with a thickness of 0.1 μm) to form a p-type contact layer 12 , thereby forming an LD layer structure. A resist stripe mask is subsequently formed in the <11-20> direction by standard exposure techniques, and then etched by dry etching to form ridges 13 . Then, a p-electrode 14 composed of Ni/Pt/Au is formed on the p-contact layer side, and an n-electrode 15 composed of Ti/Al is formed on the n-substrate side.

In this way, wafers in which polycrystalline AlN was deposited on a _SiO2 masking material followed by selective growth had a very low dislocation density on the mask. Therefore, the dislocations in the <11-20> direction are also reduced, and the dislocations present in the laser structure layer on the mask can be reduced.

Example 2

The structure of the semiconductor laser according to this embodiment is shown in FIG. 2 .

A semiconductor laser can be produced as follows. First, a SiO ₂ film 17 was deposited on a GaN substrate 16 with a dislocation density of 5×10 ⁵ /cm ² near the substrate surface, and a resist stripe mask was formed in the <11-20> direction. The mask width is 18 μm, and the opening width is 2 μm. The _SiO2 film 17 is etched by wet etching to form a mask, so that the substrate surface is exposed at the opening 19.

The mask thus formed was ultrasonically cleaned with methyl ethyl ketone and ethanol, and washed with pure water. Then, the wafer was etched with buffered hydrofluoric acid for 1 second, washed with pure water, then washed with nitric acid at 100° C. for 30 minutes, washed with pure water, and dried by blowing nitrogen gas.

Using an MOVPE apparatus, a Si-doped n-type Al _0.05 Ga _0.95 N layer 18 was formed at the opening of the wafer on which the mask was formed as described above. In this process, the growth conditions are set such that the polycrystalline AlGaN material is deposited on the _SiO2 mask. That is, the substrate is fixed and heated to the AlGaN growth temperature of 1080° C., and ammonia gas is passed through at the same time, and the growth starts after waiting for 60 seconds while passing through silane. In this way, polycrystalline AlGaN material is deposited on the mask. Voids are introduced in the vicinity of the AlGaN polycrystalline material.

In this step, the substrate can be taken out from the film formation chamber for forming the nitride semiconductor substrate, but in this embodiment, the growth of the semiconductor layer is continuously performed to form the device.

The substrate temperature is set at 1050°C, the AlGaN layer grows laterally, combines with the adjacent AlGaN layer, and then planarizes to form an n-coating layer 20 composed of n-Al _0.08 Ga _0.92 N (silicon content is 4×10 ¹⁷ cm ^{- 3} with a thickness of 2 μm).

Subsequently, an n-type light-trapping layer 21 formed of Si-doped n-type GaN (silicon content 4×10 ¹⁷ cm ^-3 , thickness _{0.1 μm} ) was sequentially grown; 4nm) potential well layer and a Si-doped In _0.05 Ga _0.95 N (silicon content of 5×10 ¹⁸ cm ^-3 , thickness of 6nm) barrier layer formed of a multiple quantum well (MQW) layer 22 (the number of potential wells is 3 ); the protective layer 23 formed ^of Mg-doped p-type Al _0.2 Ga _0.8 N; ^the p -type light-trapping layer 24; p-type plating layer 25 formed of Mg-doped p-type Al _0.1 Ga _0.9 N (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.5 μm); and Mg-doped The p-type contact layer 26 is formed of p-type GaN (with a Mg content of 2×10 ¹⁷ cm ⁻³ , and a thickness of 0.1 μm), thereby forming an LD layer structure. Subsequently, a resist stripe mask is formed in the <11-20> direction by standard exposure techniques, and then etched by dry etching to form ridges 27 . Then, a p-electrode 28 composed of Ni/Pt/Au is formed on the p-contact layer side, and an n-electrode 29 composed of Ti/Al is formed on the n-substrate side.

As such, wafers in which polycrystalline AlGaN growth is deposited on a _SiO2 masking material followed by selective growth have very low dislocation densities on the mask. Therefore, the dislocations in the <11-20> direction are also reduced, and the dislocations present in the laser structure layer on the mask can be reduced.

Example 3

The structure of the semiconductor laser according to this embodiment is shown in FIG. 3 . This semiconductor laser can be formed as follows. First, a _SiO2 film 31 was deposited on a GaN substrate 30 with a dislocation density of 5× ¹⁰⁶ / ^cm2 near the substrate surface, and a resist stripe mask was formed in the <11-20> direction. The mask width is 20 μm, and the opening width is 2 μm. The _SiO2 film 31 is etched by wet etching to form a mask, so that the substrate surface is exposed at the opening 32. Using an MOVPE apparatus, at the opening of the wafer with the above mask, a Si-doped n-type Al _0.05 Ga _0.95 N layer 33 was formed. In this process, the substrate temperature is set at 500°C or higher to allow polycrystalline AlGaN material to be deposited on the _SiO2 mask. The formed mask was subjected to the same process as in Embodiment 2, so that polycrystalline material was properly deposited. In this way, polycrystalline AlGaN material is deposited on the mask. Voids are again introduced in the region around the polycrystalline AlGaN material.

In this step, the substrate can be taken out from the film formation chamber for forming the nitride semiconductor substrate, but in this embodiment, the growth of the semiconductor layer is continuously performed to form the device.

Then, the substrate temperature is set to 1050° C., the AlGaN layer grows laterally, combines with adjacent AlGaN layers, and is planarized to form the n-AlGaN layer 34 . Subsequently, a Si-doped n-type In _0.1 Ga _0.9 N (silicon content of 4×10 ¹⁷ cm ^-3 , thickness 0.1 μm) intermediate layer 35 is sequentially grown, made of Si-doped n-type Al _0.07 n-type coating 36 formed by Ga _0.93 N (silicon content 4×10 ¹⁷ cm ^-3 , thickness 0.8 μm); Si-doped n-type GaN (silicon content 4×10 ¹⁷ cm ^-3 , a silicon-doped n-type light-trapping layer 37 formed with a thickness of 0.1 μm); a potential well layer made of In _0.2 Ga _0.8 N (thickness 4 nm) and Si-doped In _0.05 Ga _0.95 N (a silicon content of 5×10 ¹⁸ cm ^-3 , thickness is 6nm) barrier layer formed multiple quantum well (MQW) layer 38 (potential well number is 3); protective layer 39 formed by Mg-doped p-type Al _0.2 Ga _0.8 N; doped by Mg The p-type light-trapping layer 40 is formed of doped p-type GaN (with a Mg content of 2×10 ¹⁷ cm ^-3 and a thickness of 0.1 μm); p-type Al _0.1 Ga _0.9 N doped with Mg (with a Mg content of 2×10 ¹⁷ cm ^-3 , with a thickness of 0.5 μm); and a p-type plating layer 41 formed of Mg-doped p-type GaN (with a Mg content of 2×10 ¹⁷ cm ^-3 and a thickness of 0.1 μm). The p-type contact layer 42, thereby forming the LD layer structure.

Subsequently, a resist stripe mask is formed in the <11-20> direction by standard exposure techniques, and then etched by dry etching to form ridges 43 . Then, a p-electrode 44 composed of Ni/Pt/Au was formed on the p-contact layer side, and an n-electrode 45 composed of Ti/Al was formed on the n-substrate side.

As such, wafers in which polycrystalline AlGaN is grown deposited on a _SiO2 masking material and subsequently selectively grown have very low dislocation densities on the mask. Therefore, the dislocations in the <11-20> direction are also reduced, and the dislocations present in the laser structure layer on the mask can be reduced.

Example 4

This embodiment shows the case where grooves for device isolation are formed by selective growth. The structure of the semiconductor laser according to this embodiment is shown in FIG. 4 . Such a semiconductor laser can be produced as follows. First, a SiO ₂ film 47 is deposited by CVD on a GaN substrate 46 with a dislocation density of 9×10 ⁶ /cm ² near the substrate surface. Subsequently, polycrystalline AlN 48 is deposited by sputtering, and a resist stripe mask is formed in the <11-20> direction. The mask width is 30 μm, and the opening width is 200 μm.

For the formation of polycrystalline AlN 48, the following steps were performed.

(i) After forming the _SiO2 film 2, the wafer was ultrasonically cleaned with methyl ethyl ketone and ethanol, washed with pure water, etched with buffered hydrofluoric acid for 1 second, washed with pure water, and then dried with nitrogen gas. (ii) Subsequently, the wafer was inserted into a sputtering apparatus, and deposition was performed by AlN sputtering while maintaining the substrate temperature at 50° C. or higher.

The polycrystalline AlN 48 and SiO ₂ film 47 are then etched by dry and wet etching methods, so that the substrate surface is exposed on the opening 49 . Using a MOVPE device, silicon-doped GaN is formed at the opening of the wafer on which the above-mentioned mask is formed, and then the GaN layer is grown laterally, bonded with adjacent GaN layers, and planarized to form n-GaN Layer 50.

In this way, the GaN layer is planarized, forming the n-GaN layer 50, and forming the semiconductor substrate including the mask with polycrystalline AlN 48 thereon. Voids are introduced into the n-GaN layer 50 around the region where the polycrystalline AlN 48 is formed.

Subsequently, an n-type clad layer 51 formed of Si-doped n-type Al _0.1 Ga _0.9 N (silicon content 4×10 ¹⁷ cm ^-3 , thickness 1.2 μm) is sequentially grown; Si-doped n-type light trapping layer 52 formed of n-type GaN (silicon content 4×10 ¹⁷ cm ^-3 , thickness 0.1 μm); potential well layer 52 made of In _0.2 Ga _0.8 N (thickness 4nm) and Si-doped In _0.05 Ga _0.95 N (silicon content 5×10 ¹⁸ cm ^-3 , thickness 6nm) barrier layer to form a multiple quantum well (MQW) layer 53 (the number of potential wells is 3); p-type Al doped with Mg Protective layer 54 formed of _0.2 Ga _0.8 N; p-type light-trapping layer 55 formed of Mg-doped p-type GaN (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.1 μm); Mg-doped p-type coating 56 formed of p-type Al _0.1 Ga _0.9 N (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.5 μm); and p-type GaN doped with Mg (Mg content 2× 10 ¹⁷ cm ⁻³ , with a thickness of 0.1 μm) to form a p-type contact layer 57 , thereby forming an LD layer structure. Ridges 58 are formed by standard exposure techniques followed by resist stripe masking in the <11-20> direction and dry etching. Subsequently, SiO ₂ dielectric film 91 and p-electrode 59 composed of Ni/Pt/Au are formed on the p side, and n-electrode 60 composed of Ti/Al is formed on the n base side. Then, the device is separated at the separation groove to form a semiconductor laser device.

Thus, wafers in which polycrystalline AlN was deposited on a _SiO2 masking material and then selectively grown had a very low dislocation density on the mask. Therefore, the dislocations in the <11-20> direction are also reduced, and the dislocations present in the laser structure layer above the mask are also reduced. Although the region where the masking material is present and the region where the device is formed are separated from each other by about 100 μm, once a dislocation is formed, it is introduced into the layer plane, so this has a large influence. In fact, when the plane CL image of the sample without the polycrystalline layer on the mask was examined, as shown in FIG. 10 , there were dislocations in the plane.

Example 5

The structure of the semiconductor laser according to this embodiment is shown in FIG. 5 . Such a semiconductor laser can be produced as follows. A SiO ₂ film 62 is deposited on a GaN substrate 61 with a dislocation density of 2×10 ⁶ /cm ² near the substrate surface, and a resist stripe mask is formed in the <11-20> direction. The mask has a width of 40 μm and an opening width of 260 μm. A mask is formed by etching the SiO ₂ film 62 by wet etching so that the substrate surface is exposed at the opening 64 .

The mask thus formed was ultrasonically cleaned with methyl ethyl ketone and ethanol, and washed with pure water. Then the wafer was etched with buffered hydrofluoric acid for 1 second, washed with pure water, then washed with nitric acid at 100° C. for 30 minutes, washed with pure water again, and then dried with nitrogen gas.

Using an MOVPE apparatus, an n-type Al _0.06 Ga _0.94 N layer doped with Si (silicon content 4×10 ¹⁷ cm ^-3 , thickness 2.5 μm) of the coating 65 . In this process, growth conditions such as substrate temperature are set such that polycrystalline AlGaN 63 is deposited on the SiO ₂ mask. That is, the substrate was fixed and heated to the growth temperature of AlGaN, 1080° C., while passing ammonia gas, and after waiting for 60 seconds and passing silane, growth started. In this way, polycrystalline AlGaN material is deposited on the mask. Voids are introduced in the vicinity of the AlGaN polycrystalline material.

At this stage, the substrate can be taken out from the film formation chamber for forming the nitride semiconductor substrate, but in this embodiment, the growth of the semiconductor layer continues to form the device.

Subsequently, an n-type light-trapping layer 66 formed of Si-doped n-type GaN (silicon content 4×10 ¹⁷ cm ⁻³ , thickness _{0.1 μm} ) is sequentially grown; 4nm) potential well layer and a Si-doped In _0.05 Ga _0.95 N (silicon content of 5×10 ¹⁸ cm ^-3 , thickness of 6nm) barrier layer formed of a multiple quantum well (MQW) layer 67 (the number of potential wells is 3 ); a protective layer 68 formed of Mg ^- doped p-type Al _0.2 Ga _0.8 N; ^a p -type light-trapping layer 69; p-type plating layer 70 formed of Mg-doped p-type Al _0.1 Ga _0.9 N (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.5 μm); and Mg-doped The p-type contact layer 71 is formed of p-type GaN (with a Mg content of 2×10 ¹⁷ cm ⁻³ , and a thickness of 0.1 μm), thereby forming an LD layer structure. Subsequently, a resist stripe mask is formed in the <11-20> direction by standard exposure techniques, and then etched by dry etching to form ridges 72 . Subsequently, a _SiO2 dielectric film 92 is deposited on the p-side, a p-electrode 73 composed of Ni/Pt/Au is formed on the p-contact layer side, and an n-electrode composed of Ti/Al is formed on the n-base side 74. Then, the device is separated at the separation groove to form a semiconductor laser device.

In this way, wafers in which polycrystalline AlGaN is deposited on a _SiO2 masking material as it grows and then selectively grown have a very low dislocation density on the mask. Thus, dislocations in the <11-20> direction are also reduced, and the presence of dislocations in the laser structure layer above the mask is also reduced. Although the region where the masking material is present and the region where the device is formed are separated from each other by about 130 μm, once a dislocation is formed, it is introduced into the layer plane, so this has a large influence.

Example 6

The structure of the semiconductor laser according to this embodiment is shown in FIG. 6 . In this embodiment, a _SiO2 film 76 is deposited on a GaN substrate 75 with a dislocation density of 9× ¹⁰⁶ / ^cm2 near the substrate surface, and a resist stripe mask is formed in the <11-20> direction . The mask width is 50 μm, and the opening width is 300 μm. The SiO ₂ film 76 is etched by wet etching so that the substrate surface is exposed at the opening 78, thereby forming a mask.

The mask thus formed was ultrasonically cleaned with methyl ethyl ketone and ethanol, and washed with pure water. Then the wafer was etched with buffered hydrofluoric acid for 1 second, washed with pure water, then washed with nitric acid at 100° C. for 30 minutes, washed with pure water, and then dried with nitrogen gas.

Using an MOVPE apparatus, at the opening of the wafer having the above-mentioned mask formed thereon, n-type Al _0.05 Ga _0.95 N doped with Si was formed. In this process, the substrate temperature was set to 500°C or higher, so that polycrystalline AlGaN 77 was deposited on the _SiO2 mask. Specifically, the substrate was fixed and heated at a growth temperature of AlGaN of 1080° C. while passing ammonia gas, and after waiting for 60 seconds and passing silane, growth started. In this way, polycrystalline AlGaN material is deposited on the mask. Voids are again introduced in the vicinity of the polycrystalline AlGaN material.

At this stage, the substrate can be taken out from the film formation chamber for forming the nitride semiconductor substrate, but in this embodiment, the growth of the semiconductor layer is continuously performed to form the device.

The substrate temperature was then set to 1050° C., and an n-Al _0.05 Ga _0.95 N layer 79 was formed. Subsequently, an intermediate layer 80 of Si-doped n-type In _0.1 Ga _0.9 N (silicon content 4×10 ¹⁷ cm ^-3 , thickness 0.1 μm) is sequentially grown; Si-doped n-type Al n-type coating 81 formed of _0.07 Ga _0.93 N (silicon content 4×10 ¹⁷ cm ^-3 , thickness 0.8 μm); Si-doped n-type GaN (silicon content 4×10 ¹⁷ cm ^-3 , with a thickness of 0.1 μm) to form an n-type light-trapping layer 82; a potential well layer of In _0.2 Ga _0.8 N (thickness 4 nm) and Si-doped In _0.05 Ga _0.95 N (silicon content of 5×10 ¹⁸ cm ^-3 , thickness is 6nm) barrier layer formed multiple quantum well (MQW) layer 83 (potential well number is 3); protective layer 84 formed by Mg doped p-type Al _0.2 Ga _0.8 N; by Mg doped p-type light-trapping layer 85 formed of p-type GaN (Mg content 2×10 ¹⁷ cm ^-3 , thickness 0.1 μm); p-type Al _0.1 Ga _0.9 N doped with Mg (Mg content 2× 10 ¹⁷ cm ^-3 , with a thickness of 0.5 μm) formed ^of a p-type cladding layer ⁸⁶ ; and a p- Type contact layer 87, thus forming the LD layer structure.

Subsequently, a resist stripe mask is formed in the <11-20> direction by standard exposure techniques, followed by dry etching to form ridges 88 . Subsequently, a SiO ₂ dielectric film 93 is deposited on the p side, and a p-electrode 89 composed of Ni/Pt/Au is formed on the p contact layer side, and an n electrode 89 composed of Ti/Al is formed on the n substrate side. - electrode 90 . Then, the device is separated at the separation groove to form a semiconductor laser device.

In this way, wafers in which polycrystalline AlGaN is deposited on a _SiO2 masking material as it grows and then selectively grown have a very low dislocation density on the mask. Thus, dislocations in the <11-20> direction are also reduced, and the presence of dislocations in the laser structure layer above the mask is also reduced.

As explained above with reference to the examples, when a nitride semiconductor is grown on a wafer with a patterned mask material ( _SiO2, etc.), forming poly on the mask greatly reduces the dislocation density on the mask . Therefore, since dislocations are bent in the <11-20> direction by the influence of mask stress, etc., the dislocations are reduced, and in addition, the dislocations bent from the <11-20> direction in the layer plane are also reduced, so that The presence of dislocations in the laser layer structure on the mask is reduced. Among these embodiments, some embodiments use a growth device as a method of forming poly on a mask, which is effective for reducing the number of steps.

Although one embodiment of the present invention is explained on the basis of referring to the drawings, this is only an illustration of the present invention, and various other constitutions can be used in the present invention.

For example, in the above embodiments, _SiO2 is used as the masking material, but another masking material such as _SiNx or aluminum oxide may also be used. The shape of the mask is a stripe pattern in the <11-20> direction, but it may be rectangular, circular, hexagonal, etc.

Furthermore, in order to reduce dislocations, polycrystalline AlGaN was formed on the mask, but the present invention should not be considered limited to this, _and it can also use polycrystalline _{AlxInyGa1 -xyN} (0≤x≤1, 0≤y≤1).

Also, in the above embodiments, the semiconductor layer is explained as an example, but the present invention can be applied to other light emitting devices such as light emitting diodes, and can be applied to photoreceptors and electronic devices.

In the above embodiment, InGaN is used for the intermediate layer, but the present invention should not be construed as being limited thereto, and _{AlxInyGa1 -xyN} ( _0≤x≤1 , 0≤y≤1) may be used.

Claims (17)

1. A nitride semiconductor substrate comprising: Group III nitride semiconductor substrate; a mask formed over the III-nitride semiconductor substrate; and a semiconductor multilayer film formed over the mask; wherein the group III nitride semiconductor substrate has a dislocation density near its surface of 1×10 ⁷ /cm ² or less, and The mask has polycrystalline material deposited on its surface. 2. The nitride semiconductor substrate according to claim 1, wherein the polycrystalline material is formed of a material containing aluminum and nitrogen as main elements. 3. The nitride semiconductor substrate according to claim 1, wherein voids are formed on the surface of the mask having the polycrystalline material. 4. The nitride semiconductor substrate according to claim 1, wherein the mask is provided on a surface of the group III nitride semiconductor substrate. 5. A nitride semiconductor device comprising the following: Group III nitride semiconductor substrate; a mask formed on the III-nitride semiconductor substrate; and a semiconductor multilayer film formed on the mask, the semiconductor multilayer film including an active layer; wherein the group III nitride semiconductor substrate has a dislocation density near its surface of 1×10 ⁷ /cm ² or less, and The mask has polycrystalline material deposited on its surface. 6. The nitride semiconductor device according to claim 5, wherein the polycrystalline material is formed of a material containing aluminum and nitrogen as main elements. 7. The nitride semiconductor device according to claim 5, wherein voids are formed on the surface of the mask having the polycrystalline material. 8. The nitride semiconductor device according to claim 5, wherein the mask is provided on a surface of the group III nitride semiconductor substrate. 9. The nitride semiconductor device according to claim 5, wherein the mask is provided near a device isolation groove of the nitride semiconductor device. 10. A method for preparing a nitride semiconductor substrate, the method comprising the steps of: the step of forming a mask on the III-nitride semiconductor substrate; the step of depositing polycrystalline material on said mask surface; and the step of forming a semiconductor multilayer film on said mask, Wherein the III-nitride semiconductor substrate has a dislocation density near its surface of 1×10 ⁷ /cm ² or lower. 11. The method for producing a nitride semiconductor substrate according to claim 10, wherein the step of depositing the polycrystalline material on the mask surface includes the step of depositing the polycrystalline material after contacting the mask surface with an acid. 12. The method for producing a nitride semiconductor substrate according to claim 10, wherein in the step of depositing the polycrystalline material on the surface of the mask, voids are formed on the surface of the mask. 13. The method for producing a nitride semiconductor substrate according to claim 10, wherein the mask is provided on a surface of the group III nitride semiconductor substrate. 14. A method for preparing a nitride semiconductor device, the method comprising the steps of: the step of forming a mask on the III-nitride semiconductor substrate; the step of depositing polycrystalline material on said mask surface; and the step of forming a semiconductor multilayer film on said mask, said semiconductor multilayer film including an active layer, Wherein the III-nitride semiconductor substrate has a dislocation density near its surface of 1×10 ⁷ /cm ² or lower. 15. The method for producing a nitride semiconductor device according to claim 14, wherein the step of depositing a polycrystalline material on the mask surface includes a step of depositing a polycrystalline material after contacting the mask surface with an acid. 16. The method for producing a nitride semiconductor device according to claim 14, wherein in the step of depositing the polycrystalline material on the surface of the mask, voids are formed on the surface of the mask. 17. The method for producing a nitride semiconductor device according to claim 14, wherein the mask is provided on a surface of the group III nitride semiconductor substrate.

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