JP2007335501A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to reduce leakage current when a transistor is off without impairing current driving capability.
A hetero semiconductor region 3 heterojunction with an N type drain region 2 formed on an N type substrate region 1 is used as a source region, and adjacent to a hetero junction between the drain region 2 and the hetero semiconductor region 3. In the field effect transistor in which the gate electrode 5 is formed through the gate insulating film 4 and the driving point 9 of the transistor is a place where the gate insulating film 4, the hetero semiconductor region 3, and the drain region 2 are in contact with each other, A P-type semiconductor region 10 is formed on the surface so as to be in contact with and surround the drive point 9 of the transistor.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor semiconductor device having a heterojunction and a method of manufacturing the same.

Conventionally, as this type of technology, for example, those described in the following documents are known (see Patent Document 1). In the technique described in this document, an N ⁻ type polycrystalline silicon region is in contact with one main surface of a semiconductor substrate in which an N ⁻ type silicon carbide epitaxial region is formed on an N ⁺ type silicon carbide substrate. The epitaxial region and the N ⁻ -type polycrystalline silicon region form a heterojunction. A gate electrode is formed adjacent to the junction between the epitaxial region and the N ⁻ -type polycrystalline silicon region via a gate insulating film.

The N ⁻ type polycrystalline silicon region is connected to the source electrode, and a drain electrode is formed on the back surface of the N ⁺ type silicon carbide substrate.

The semiconductor device having such a structure functions as a switch of a field effect transistor by controlling the potential of the gate electrode in a state where the source electrode is grounded and a predetermined positive potential is applied to the drain electrode. In other words, when the gate electrode is grounded, a reverse bias is applied to the heterojunction between the N ⁻ -type polycrystalline silicon region and the epitaxial region, and no current flows between the drain electrode and the source electrode, and the transistor is turned off. It becomes. On the other hand, when a predetermined positive voltage is applied to the gate electrode, a gate electric field acts on the heterojunction interface between the N ⁻ -type polycrystalline silicon region and the epitaxial region, resulting in a heterojunction at the gate oxide film interface. The thickness of the energy barrier formed by the surface is reduced, current flows between the drain electrode and the source electrode, and the transistor is turned on.

In such a semiconductor device, a heterojunction is used as a current cutoff / conduction control channel, and the channel length functions at the thickness of the heterobarrier, so that low resistance conduction characteristics can be obtained. At this time, lower resistance conduction is obtained as the gate electric field is higher at the heterojunction interface between the N ⁻ -type polycrystalline silicon region and the epitaxial region which are in contact with the gate electrode through the gate insulating film.
JP 2003-318398 A

In the transistor having the above structure, the triple point where the gate insulating film, the hetero semiconductor region, and the semiconductor substrate are in contact with each other is a driving point of the transistor. The conductivity type of the semiconductor substrate at this driving point is N ⁻ type, and the effective N-type impurity concentration is the same as the concentration of the epitaxial layer. Further, the source hetero semiconductor region which is an electron supply source needs to be N-type.

  In such a configuration, a good current driving force can be obtained, but there is a concern that a leakage current increases when the transistor is turned off because the potential barrier between the hetero semiconductor region and the semiconductor substrate is low and thin.

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device having a heterojunction in which a leakage current at the time of off is reduced without impairing the current driving capability, and the semiconductor device It is to provide a manufacturing method.

  In order to achieve the above object, the means for solving the problems of the present invention includes a semiconductor substrate of a first conductivity type, a hetero semiconductor region heterojunction with the semiconductor substrate, a heterostructure of the semiconductor substrate and the hetero semiconductor region. A gate electrode disposed adjacent to the junction through a gate insulating film; a drain electrode connected to the semiconductor substrate; and a source electrode connected to the hetero semiconductor region; and the gate insulating film and the hetero In a semiconductor device in which a portion where a semiconductor region and the semiconductor substrate are in contact with each other is a driving point of a transistor, an impurity concentration more effective than the second conductivity type formed on at least a part of the surface of the semiconductor substrate or the semiconductor substrate. The semiconductor region has a low first conductivity type, and the semiconductor region is in contact with the driving point.

  According to the present invention, it is possible to significantly reduce the leakage current when the transistor is in an off state, with almost no decrease in current driving capability.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best embodiment for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a field effect transistor of a semiconductor device according to Embodiment 1 of the present invention, and corresponds to a cross section in which two unit cells of a transistor are arranged opposite to each other in parallel. In practice, a plurality of these unit cells are connected in parallel to form a transistor. In the following description, this sectional structure will be described as a representative example.

In FIG. 1, an impurity concentration lower than that of the substrate region 1, for example, an impurity concentration of 1 × is formed on one main surface of the substrate region 1 having a thickness of about several hundred μm of N-type high concentration (N ⁺ ) made of SiC. An N-type (N ⁻ ) drain region 2 made of SiC having a thickness of about 10 ¹⁶ cm ⁻³ and a thickness of about 10 μm is formed. In FIG. 1, the concept of the thickness of the substrate region 1 and the drain region 2 is omitted. The drain region 2 is formed by an epitaxial layer grown on the substrate region 1, and the drain region 2 and the substrate region 1 constitute a semiconductor substrate. There are several polytypes (crystal polymorphs) of SiC, but here, it will be described as representative 4H—SiC.

An N ⁺ type hetero semiconductor region 3 made of polycrystalline silicon is formed on one main surface side of the drain region 2. SiC and polycrystalline silicon have different band gaps and different electron affinities. Thereby, a heterojunction is formed at both junction interfaces. (This is why polycrystalline silicon is used as a hetero semiconductor region.)
A gate electrode 5 is formed on the drain region 2 via a gate insulating film 4 adjacent to the junction between the drain region 2 and the hetero semiconductor region 3. The hetero semiconductor region 3 is directly connected to the source electrode 6. A drain electrode 7 is electrically ohmically connected to the back surface of the substrate region 1 with a low resistance. The gate electrode 5 is insulated from the source electrode 6 by the interlayer insulating film 8.

As a characteristic configuration in the first embodiment, a portion where the drain region 2, the hetero semiconductor region 3, and the gate insulating film 4 are in contact constitutes a driving point 9 of the transistor. A semiconductor region 10 is formed in the surface layer of the drain region 2 so as to surround the periphery. The semiconductor region 10 is made of P ⁻ -type SiC, and functions as a semiconductor layer that suppresses a leakage current flowing through the driving point 9 and its vicinity when the transistor is turned off.

  Next, the effect obtained by forming such a semiconductor region 10 will be described with reference to the results of device simulation shown in FIGS.

First, the case where the transistor is on will be described. FIG. 2 is a band diagram of the gate electrode 5 / gate insulating film 4 / drain region 2 in the configuration shown in FIG. In FIG. 2, the characteristic of the conventional structure that does not employ the P ⁻ type semiconductor region 10 is indicated by a broken line, and the impurity concentration is, for example, about 3 × 10 ¹⁶ cm ^{−3 on} the surface of the drain region 2. The characteristic in the case of Example 1 in which the P ⁻ type semiconductor region 10 having a thickness of about 0.3 μm is provided is indicated by a solid line. As is clear from FIG. 2, when the semiconductor region 10 is provided, the energy at the conductor edge is higher from the surface of the drain region 2 to the junction depth of the semiconductor region 10 than when the semiconductor region 10 is not provided. I understand.

  FIG. 3 is a band diagram when a drive voltage of, for example, about 40 V is applied to the gate electrode 5 with respect to the band diagram of FIG. In FIG. 3, the relationship between the broken line and the solid line is the same as in FIG. In FIG. 3, since the semiconductor region 10 has a low impurity concentration and a small thickness, the electric field from the gate electrode 5 completely reverses the depth direction and the energy at the conductor end is reduced. . In the vicinity of the driving point 9 of the transistor, electrons tunneling through the potential barrier sufficiently lowered at the heterojunction by the gate electric field flow in the vertical direction (depth direction). Further, as can be seen from the band diagram of FIG. 3, since the potential barrier of the semiconductor region 10 is also very low, there is almost no deterioration in the current driving force despite the presence of the P-type layer of the semiconductor region 10. Conceivable.

Next, the case where the transistor is off will be described. FIG. 4 is a band diagram of the hetero semiconductor region 3 / drain region 2 in the structure shown in FIG. Also in FIG. 3, as in FIG. 2, the characteristics of the conventional structure that does not employ the P ⁻ -type semiconductor region 10 are indicated by broken lines, and the impurity concentration is 3 × 10 ¹⁶ cm ^{−3 on} the surface of the drain region 2. The solid line shows the characteristics of Example 1 in which the P ⁻ type semiconductor region 10 having a junction depth of about 0.3 μm is provided.

  In the band characteristic shown in FIG. 4, when the semiconductor region 10 indicated by the broken line is not provided, the potential barrier at the heterojunction portion is low, so that when a positive voltage is applied to the drain electrode 7, It is expected that a tunnel current will flow on the second side. On the other hand, when the semiconductor region 10 indicated by the solid line is provided, the potential barrier is high because the surface is P-type.

  FIG. 5 is a diagram showing current-voltage characteristics when a positive voltage is applied to the drain electrode 7 with respect to such band characteristics. Also in FIG. 5, the relationship between the broken line and the solid line is the same as in FIGS. As can be seen from FIG. 5, in the characteristics indicated by the broken line, the tunnel current flows even when the drain voltage is low, whereas in the characteristics indicated by the solid line, the tunnel current is significantly suppressed.

  As described above, by forming the P-type semiconductor region 10 having an appropriate impurity concentration and junction depth in the drain region 2 around the drive point 9 (current path), the current drive capability when the transistor is on. The leakage current when the transistor is turned off can be greatly suppressed without substantially reducing the current.

  In the above simulation, a one-dimensional result is shown, but it is assumed that the same effect can be obtained even with a two-dimensional structure such as an actual driving point 9.

In the first embodiment, the case where the P ⁻ type semiconductor region 10 is provided in the surface layer of the drain region 2 below the driving point 9 has been described. However, the impurity concentration lower than the impurity concentration of the drain region 2 is provided at the same location. Even in the case where the semiconductor region made of N ⁻⁻ type SiC is formed, the leakage current at the off time can be suppressed without substantially degrading the current driving capability at the on time of the transistor as in the first embodiment. . The reason will be described below.

First, the case where the transistor is on will be described. The N ⁻⁻ type semiconductor region has lower energy at the conductor edge than the P ⁻ type semiconductor region 10. Therefore, as shown in FIG. 2, P ^- for type well potential barrier by even gate field in a case where the provided semiconductor region 10 is reduced, N ^- more time on the type of semiconductor region It is clear that the potential barrier of the is lowered. Thereby, the current driving force is not impaired.

Next, the case where the transistor is off will be described. Since the N ⁻ -type semiconductor region has a lower impurity concentration than the N ⁻ -type drain region 2, the depletion layer is easily extended. Therefore, the potential barrier at the heterojunction interface between the drain region 2 and the hetero semiconductor region 3 becomes thick, so that the tunnel current, that is, the leakage current can be reduced as compared with the case where no N ⁻⁻ type semiconductor region is provided.

FIG. 6 is a sectional view showing a configuration of a field effect transistor of a semiconductor device according to Example 2 of the present invention. The feature of the second embodiment is that it is the same as the semiconductor region 10 described in the first embodiment between the drain region 2 and the hetero semiconductor region 3 and the gate insulating film 4 as compared with the first embodiment. This is because the layer of the P ⁻ type semiconductor region 11 having a function is formed, and the others are the same as in the first embodiment.

  By adopting such a configuration, not only the driving point 9 of the transistor but also the tunnel leakage current in the entire junction interface between the drain region 2 and the hetero semiconductor region 3 can be suppressed. In addition, by disposing the semiconductor region 11 at the junction interface between the drain region 2 and the gate insulating film 4, the drain electric field applied to the gate insulating film 4 can be relaxed, and the breakdown of the gate insulating film 4 can be suppressed.

  Further, when the semiconductor region 11 is formed, ion implantation of impurities is performed on the entire surface, so that a patterning process by photolithography can be omitted as compared with the first embodiment. Since the semiconductor region 11 may be formed on the entire surface of the drain region 2, not only ion implantation but also an epitaxial growth method can be used, and a high-quality SiC layer with few crystal defects can be obtained.

Instead of the semiconductor region 11, a semiconductor region made of N ⁻⁻ type SiC having an impurity concentration lower than that of the drain region 2 may be formed at the same position. In this case, the reason described in the first embodiment is used. As a result, the leakage current when the transistor is off can be suppressed without substantially degrading the current driving capability when the transistor is on.

FIG. 7 is a cross-sectional view showing a configuration of a field effect transistor of a semiconductor device according to Example 3 of the present invention. The feature of the third embodiment is that, compared with the second embodiment, a part of the semiconductor region 11 below the gate electrode 5 is deleted and a separated portion is provided below the gate electrode 5 to drive the transistor. The P ⁻ type semiconductor region 12 separated by a predetermined distance is formed in the drain region 2 in the periphery of 9 and in the lower part of the hetero semiconductor region 3, and the others are the same as in the second embodiment.

  By adopting such a structure, even when only the surface of the semiconductor region 12 is inverted by the gate electric field when the transistor is turned on, electrons can flow along the path indicated by the arrow in FIG. Therefore, the impurity concentration of the semiconductor region 12 is increased and the junction depth is increased without reducing the current driving capability of the transistor as compared with the case where the semiconductor region 12 is completely inverted in the depth direction to flow electrons. This makes it possible to further reduce the off-state leakage current.

  FIG. 8 is a sectional view showing a configuration of a field effect transistor of a semiconductor device according to Example 4 of the present invention. The feature of the fourth embodiment is that an electric field relaxation layer 13 made of P-type SiC is provided in contact with the hetero semiconductor region 3 in the surface layer of the drain region 2 as compared with the first embodiment. Others are the same as in the first embodiment.

  By adopting such a configuration, the built-in potential from the electric field relaxation layer 13 formed at the junction interface between the drain region 2 and the hetero semiconductor region 3 shields the drain electric field applied to the driving point 9 of the transistor, A breakdown voltage and a low leakage current can be realized.

Note that the fourth embodiment can be applied even when the N ⁻⁻ type semiconductor region described in the first embodiment is provided instead of the semiconductor region 10, and even in this case, The same effect as described above can be obtained.

  FIG. 9 is a cross-sectional view showing a configuration of a field effect transistor of a semiconductor device according to Example 5 of the present invention. The feature of the fifth embodiment is that an electric field relaxation layer 14 similar to the electric field relaxation layer 13 is additionally provided in contact with the gate insulating film 4 in the surface layer of the drain region 2 as compared with the fourth embodiment. In particular, the rest is the same as in the fourth embodiment.

  By adopting such a configuration, the same effect as in the fourth embodiment can be obtained.

Note that the fifth embodiment can be applied even when the N ⁻⁻ type semiconductor region described in the first embodiment is provided instead of the semiconductor region 10. The same effect as described above can be obtained.

  Next, a method for manufacturing the device shown in FIG. 9 will be described with reference to the manufacturing process sectional views shown in FIGS.

First, the drain region 2 made of N ⁻ type SiC is formed on the N ⁺ type SiC substrate region 1 by epitaxial growth or the like (FIG. 10A (a)).

Thereafter, a P ⁻ type semiconductor region 10 is formed by ion implantation of a P type impurity such as aluminum or boron into the drain region 2. At this time, it is possible to suppress the occurrence of crystal defects by implanting impurities in a state where the temperature of the substrate is raised to, for example, about 600 ° C. Alternatively, the semiconductor region 10 made of P ⁻ type SiC may be formed on the drain region 2 by epitaxial growth. In this case, it is possible to suppress a defect from entering the crystal due to ion implantation. In this step, the semiconductor region 10 is formed on the entire surface of the drain region 2, but it may be formed only in a predetermined region including the lower portion of the driving point 9 of the transistor. Subsequently, in order to activate the P-type impurity, a heat treatment is performed for about 10 minutes at a temperature of about 1700 ° C., for example, in an argon atmosphere. Note that in the case where the activation heat treatment is performed when the electric field relaxation layers 13 and 14 are formed, the heat treatment here can be omitted (FIG. 10A (b)).

  Next, a resist pattern is formed on the semiconductor substrate by photolithography, and a P-type impurity such as aluminum or boron is ion-implanted only in a predetermined region excluding the periphery of the transistor driving point 9 using the resist pattern as a mask. Electric field relaxation layers 13 and 14 are formed. At this time, it is possible to suppress the occurrence of crystal defects by ion implantation with the substrate temperature raised to, for example, about 600 ° C. When ion implantation is performed at a high temperature, a hard mask such as a silicon oxide film or a silicon nitride film having higher heat resistance than the resist may be used as a mask at the time of ion implantation. After removing the register pattern after ion implantation, heat treatment is performed for about 10 minutes at a temperature of about 1700 ° C., for example, in an argon atmosphere in order to activate the impurities. Note that a high-resistance layer can be used as the electric field relaxation layer. In this case, for example, boron can be formed by ion implantation at room temperature and then without performing an activation heat treatment (FIG. 10-). A (c)).

  Subsequently, a polycrystalline silicon layer 15 constituting the hetero semiconductor region 3 is deposited on the entire surface by, eg, CVD. The deposition temperature of the polycrystalline silicon layer 15 is, for example, about 620 ° C., and the film thickness is, for example, about 5000 mm (FIG. 10A (d)).

Thereafter, the polycrystalline silicon layer 15 is doped with N-type impurities to form an N ⁺ -type polycrystalline silicon layer 15. As an impurity doping method, for example, ion implantation can be used, and arsenic, phosphorus, or the like can be used as the impurity. As a doping method, a diffusion method or the like may be used other than ion implantation. After introducing these impurities, for example, heat treatment is performed for about 20 minutes at a temperature of about 950 ° C. in a nitrogen atmosphere to activate the impurities (FIG. 10B (e)).

  Next, a resist pattern 16 is formed on the polycrystalline silicon layer 15 by photolithography, and the polycrystalline silicon layer 15 is selectively removed by dry etching using the register pattern 16 as a mask to pattern the hetero semiconductor region 3. It forms (FIG. 10-B (f)).

Subsequently, after removing the resist pattern 16, an oxide film to be the gate insulating film 4 is deposited and formed on the entire surface by a CVD method to a thickness of about 1000 mm, for example. Subsequently, polycrystalline silicon is deposited on the oxide film to be the gate insulating film 4 to a thickness of, for example, about 5000 mm and doped with N-type impurities. As a method for doping impurities, for example, ion implantation can be used. Arsenic, phosphorus, or the like can be used as the impurity. The doping method may be a diffusion method other than ion implantation. After the implantation of these impurities, for example, a heat treatment is performed for about 20 minutes at a temperature of about 950 ° C. in a nitrogen atmosphere, thereby activating the impurities and forming an N ⁺ type polycrystalline silicon layer. A resist pattern is formed on the polycrystalline silicon layer thus formed by photolithography, and the polycrystalline silicon is selectively removed by dry etching using the resist pattern as a mask, followed by patterning to form the gate electrode 5. (FIG. 10-B (g)).

  Finally, an interlayer insulating film 8 is deposited and formed on the entire surface by, for example, the CVD method, and the interlayer insulating film 8 is selectively removed to open a contact hole, and then contact the hetero semiconductor region 3 through the contact hole. Then, the source electrode 6 is formed, and then the drain electrode 7 is formed on the other main surface side of the substrate region 1 to complete the semiconductor device according to the fifth embodiment shown in FIG.

  Thus, it becomes possible to manufacture easily by combining and implementing the conventional manufacturing method.

  In each of the above embodiments, the semiconductor substrate can be composed of any one of gallium nitride and diamond in addition to silicon carbide, and the hetero semiconductor region 3 can be formed of silicon germanium, It can also be composed of any one of germanium and gallium arsenide.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 1 of this invention. It is a figure which shows the band characteristic of this invention and the conventional transistor. It is a figure which shows the other band characteristic of this invention and the conventional transistor. It is a figure which shows the other band characteristic of this invention and the conventional transistor. It is a figure which shows the current characteristic of this invention and the conventional transistor. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 2 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 3 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 4 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 5 of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 5 of this invention. It is process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on Example 5 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate region 2 ... Drain region 3 ... Hetero semiconductor region 4 ... Gate insulating film 5 ... Gate electrode 6 ... Source electrode 7 ... Drain electrode 8 ... Interlayer insulating film 9 ... Drive point 10, 11, 12 ... Semiconductor region 13, 14 ... Electric field relaxation layer 15 ... Polycrystalline silicon layer 16 ... Resist pattern

Claims (28)

A first conductivity type semiconductor substrate;
A hetero semiconductor region heterojunction to the semiconductor substrate;
A gate electrode disposed via a gate insulating film adjacent to a heterojunction between the semiconductor substrate and the hetero semiconductor region;
A drain electrode connected to the semiconductor substrate;
A source electrode connected to the hetero semiconductor region,
In the semiconductor device in which the gate insulating film, the hetero semiconductor region, and the semiconductor substrate are in contact with each other, the driving point of the transistor,
A second conductivity type semiconductor region formed on at least a part of the surface of the semiconductor substrate;
The semiconductor device, wherein the second conductivity type semiconductor region is in contact with the driving point. A first electric field relaxation region formed in a part of the surface of the semiconductor substrate immediately below the hetero semiconductor region;
The semiconductor device according to claim 1, wherein the first electric field relaxation region is in contact with a part of the hetero semiconductor region except for the driving point. The semiconductor device according to claim 2, wherein the first electric field relaxation region is of a second conductivity type. The semiconductor device according to claim 2, wherein the first electric field relaxation region is a high resistance layer. 5. The semiconductor device according to claim 2, wherein at least a part of the semiconductor region of the second conductivity type and the first electric field relaxation region are in contact with each other. A second electric field relaxation region formed on a part of the surface of the semiconductor substrate where the gate insulating film and the semiconductor substrate are in contact with each other;
The semiconductor device according to claim 1, wherein the second electric field relaxation region is in contact with a part of the gate insulating film except for the driving point. The semiconductor device according to claim 6, wherein the second electric field relaxation region is of a second conductivity type. The semiconductor device according to claim 6, wherein the second electric field relaxation region is a high resistance layer. 9. The semiconductor device according to claim 6, wherein at least a part of the second conductivity type semiconductor region and the second electric field relaxation region are in contact with each other. The semiconductor region of the second conductivity type has at least a surface inverted by an electric field from the gate electrode,
10. The semiconductor region of the second conductivity type is selectively formed in a region excluding a part of a joint surface between the gate insulating film and the semiconductor substrate. 2. A semiconductor device according to item 1. The semiconductor device according to claim 1, wherein the semiconductor region of the second conductivity type is completely inverted in a depth direction by an electric field from the gate electrode. A first conductivity type semiconductor substrate;
A hetero semiconductor region heterojunction to the semiconductor substrate;
A gate electrode disposed via a gate insulating film adjacent to a heterojunction between the semiconductor substrate and the hetero semiconductor region;
A drain electrode connected to the semiconductor substrate;
A source electrode connected to the hetero semiconductor region,
In the semiconductor device in which the gate insulating film, the hetero semiconductor region, and the semiconductor substrate are in contact with each other, the driving point of the transistor,
An effective first conductivity type impurity concentration having a first conductivity type semiconductor region having a lower concentration than the semiconductor substrate;
The semiconductor device according to claim 1, wherein the semiconductor region of the first conductivity type is in contact with the driving point. A first electric field relaxation region formed in a part of the surface of the semiconductor substrate immediately below the hetero semiconductor region;
The semiconductor device according to claim 12, wherein the first electric field relaxation region is in contact with a part of the hetero semiconductor region except for the driving point. The semiconductor device according to claim 12, wherein the first electric field relaxation region is of a second conductivity type. The semiconductor device according to claim 12, wherein the first electric field relaxation region is a high resistance layer. The semiconductor device according to claim 13, wherein at least a part of the semiconductor region of the first conductivity type and the first electric field relaxation region are in contact with each other. A second electric field relaxation region formed on a part of the surface of the semiconductor substrate where the gate insulating film and the semiconductor substrate are in contact with each other;
17. The semiconductor device according to claim 12, wherein the second electric field relaxation region is in contact with a part of the gate insulating film except for the driving point. The semiconductor device according to claim 17, wherein the second electric field relaxation region is of a second conductivity type. The semiconductor device according to claim 17, wherein the second electric field relaxation region is a high resistance layer. The semiconductor device according to claim 17, wherein at least a part of the first conductivity type semiconductor region and the second electric field relaxation region are joined. 21. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of any one of silicon carbide, gallium nitride, and diamond. The semiconductor device according to claim 1, wherein the hetero semiconductor region is made of any one of silicon, silicon germanium, germanium, and gallium arsenide. A first step of selectively forming a second conductivity type semiconductor region on the first conductivity type semiconductor substrate;
A second step of selectively forming a semiconductor region of the second conductivity type and a hetero semiconductor region forming a heterojunction with the semiconductor substrate on the semiconductor substrate;
A third step of forming a gate insulating film in contact with the semiconductor substrate, the second conductivity type semiconductor region, and the hetero semiconductor region;
A fourth step of forming a gate electrode through the gate insulating film;
A fifth step of forming a source electrode connected to the hetero semiconductor region;
And a sixth step of forming a drain electrode connected to the semiconductor substrate. 24. The method of manufacturing a semiconductor device according to claim 23, wherein the second conductivity type semiconductor region is formed by implanting second conductivity type impurity ions into the semiconductor substrate. 24. The method of manufacturing a semiconductor device according to claim 23, wherein the second conductivity type semiconductor region is formed by epitaxial growth. A first step of selectively forming a semiconductor region of the first conductivity type having a lower concentration than the impurity concentration of the semiconductor substrate on the semiconductor substrate of the first conductivity type;
A second step of selectively forming on the semiconductor substrate a semiconductor region of the first conductivity type and a hetero semiconductor region forming a heterojunction with the semiconductor substrate;
A third step of forming a gate insulating film in contact with the semiconductor substrate, the first conductivity type semiconductor region and the hetero semiconductor region;
A fourth step of forming a gate electrode through the gate insulating film;
A fifth step of forming a source electrode connected to the hetero semiconductor region;
And a sixth step of forming a drain electrode connected to the semiconductor substrate. 27. The method of manufacturing a semiconductor device according to claim 26, wherein the semiconductor region of the first conductivity type is formed by counter doping in which impurity ions of the second conductivity type are implanted into the semiconductor substrate. 27. The method of manufacturing a semiconductor device according to claim 26, wherein the semiconductor region of the first conductivity type is formed by epitaxial growth.

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