JP2003318398A - Silicon carbide semiconductor device - Google Patents

Abstract

(57) [Problem] To provide a normally-off voltage-driven type high-breakdown-voltage field-effect transistor having a low on-resistance and a simple manufacturing process. Kind Code: A1 An N ⁺ -type SiC substrate, an N ⁻ -type epitaxial region on the substrate, and an N ⁻ -type epitaxial region.
An N ⁻ -type polycrystalline silicon layer 60 heterojunctioning on
A gate electrode 40 provided adjacent to a junction between the N ⁻ type epitaxial region 20 and the N ⁻ type polycrystalline silicon layer 60 via the gate insulating film 30 and a back surface of the N ⁺ type SiC substrate 10 are provided. Drain electrode 90 and a source electrode 80 in contact with N ⁻ type polycrystalline silicon layer 60.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a silicon carbide semiconductor device having a field effect transistor using a silicon carbide semiconductor.

[0002]

2. Description of the Related Art Silicon carbide (hereinafter referred to as SiC) has a wide band gap and has a maximum dielectric breakdown electric field that is an order of magnitude larger than that of silicon (hereinafter referred to as Si). Further, the natural oxide of SiC is SiO ₂ , and a thermal oxide film can be easily formed on the surface of SiC by the same method as for Si. Therefore, SiC is expected to be a very excellent material when used as a high-speed / high-voltage switching element of an electric vehicle, particularly a high-power uni / bipolar element.

FIG. 20 shows a conventional SiC planar type MOS.
It is a sectional view showing a FET structure, for example, Japanese Patent Laid-Open No. 10-2
It is disclosed in Japanese Patent No. 33503. As shown in the figure,
An N ⁻ -type SiC epitaxial region 20 is formed on a high-concentration N type (hereinafter, high concentration is described as ⁺ and low concentration is described as ⁻ ) SiC substrate 10. Then, a P ⁻ type base region 150 and an N ⁺ type source region 160 are formed in a predetermined region in the surface layer portion of the epitaxial region 20. In addition, the N ⁻ type SiC epitaxial region 20
A gate electrode 40 is arranged on the above with a gate insulating film 30 interposed therebetween, and the gate electrode 40 is covered with an interlayer insulating film 110. A source electrode 80 is formed in contact with the P ⁻ type base region 150 and the N ⁺ type source region 160, and a drain electrode 90 is formed on the back surface of the N ⁺ type SiC substrate 10.

The operation of this planar type MOSFET is such that when a positive voltage is applied to the gate electrode 40 in a state where a voltage is applied between the drain electrode 90 and the source electrode 80, it opposes the gate electrode 40. P ^- type base region 1
The inversion type channel region 100 is formed on the surface layer of 50,
A current can be passed from the drain electrode 90 to the source electrode 80. Further, by removing the voltage applied to the gate electrode 40, the drain electrode 90 and the source electrode 80 are electrically insulated from each other, and a switching function is exhibited.

[0005]

However, as shown in FIG.
It is known that in the SiC planar type MOSFET as shown in (1), an incomplete crystal structure, that is, a large amount of interface states exists at the interface between the gate insulating film 30 and the inversion type channel region 100 (VV Afanasev. , M. Bassler,
G. Pensl and M. Schulz, Phys. Stat. Sol. (A) 162 (1
997) 321.). Therefore, a large amount of interface states exist in the inversion type channel in the surface layer of the channel region 100 formed by applying a voltage to the gate electrode 40, and these act as electron traps, so that the channel mobility can be increased. However, there is a problem that the on-resistance of the SiC planar MOSFET increases as a result.

The present invention has been made in order to solve the problems of the prior art as described above, and an object thereof is to provide a high breakdown voltage field effect transistor having a low on-resistance.
In particular, it is an object of the invention to provide a normally-off voltage drive type silicon carbide semiconductor device having a simple manufacturing process.

[0007]

In order to solve the above-mentioned problems, the present invention has a structure as described in the claims.

That is, a silicon carbide semiconductor device according to a first aspect of the present invention comprises a first conductivity type silicon carbide semiconductor substrate, a hetero semiconductor region hetero-junctioned to the semiconductor substrate, the semiconductor substrate and the hetero semiconductor region. A gate electrode disposed adjacent to the junction via a gate insulating film, a drain electrode of the first conductivity type provided on the semiconductor substrate, and a source electrode in contact with the hetero semiconductor region (Corresponding to the first to fourth embodiments).

A silicon carbide semiconductor device according to a second aspect is the silicon carbide semiconductor device according to the first aspect, wherein a part of a surface of the semiconductor substrate facing the gate electrode via the gate insulating film is provided. A second conductive type semiconductor region is formed (corresponding to the second to fourth embodiments).

According to a third aspect of the present invention, in a silicon carbide semiconductor device, a silicon carbide semiconductor substrate of the first conductivity type, a groove formed in the semiconductor substrate, and the semiconductor substrate filled in the groove with the semiconductor substrate are provided. A hetero semiconductor region to be joined, a gate electrode provided adjacent to a junction between the semiconductor substrate and the hetero semiconductor region via a gate insulating film, and a drain of the first conductivity type provided in the semiconductor substrate. An electrode and a source electrode in contact with the hetero semiconductor region are provided (corresponding to the fifth to ninth embodiments).

A silicon carbide semiconductor device according to a fourth aspect is the silicon carbide semiconductor device according to the third aspect, wherein a part of the semiconductor substrate is of the second conductivity type so as to be connected to the hetero semiconductor region. A semiconductor region is formed (corresponding to the sixth embodiment).

A silicon carbide semiconductor device according to a fifth aspect of the present invention is a silicon carbide semiconductor substrate of the first conductivity type, a hetero semiconductor region hetero-junctioned to the semiconductor substrate, and the hetero semiconductor region penetrating in the depth direction. A groove formed to reach the semiconductor substrate, a gate electrode filled in the groove via an insulating film, a source electrode in contact with the hetero semiconductor region, and a first electrode provided on the semiconductor substrate. And a drain electrode of one conductivity type (corresponding to the eighth and ninth embodiments).

Further, a silicon carbide semiconductor device according to a sixth aspect is the silicon carbide semiconductor device according to any one of the first to fifth aspects, wherein the semiconductor substrate is opposed to the gate electrode via the gate insulating film. A second first-conductivity-type semiconductor region having a different concentration from that of the semiconductor substrate, and the second first-conductivity-type semiconductor region is in contact with the hetero semiconductor region. (Corresponding to the fourth and seventh embodiments).

A silicon carbide semiconductor device according to a seventh aspect is the silicon carbide semiconductor device according to any one of the first to sixth aspects, wherein the hetero semiconductor region has regions having different impurity concentrations ( Embodiments 3, 5,
7).

A silicon carbide semiconductor device according to claim 8 is the silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the hetero semiconductor region is at least one of silicon, amorphous silicon, or polycrystalline silicon. (Embodiments 1 to 9)
Corresponding to).

[0016]

According to the invention described in claim 1, if a positive voltage is applied to the gate electrode to reduce the thickness of the energy barrier of the heterojunction, carriers can pass through the reduced barrier. Can (tunnel phenomenon). That is, with the positive voltage applied to the drain, the thickness of the energy barrier can be controlled by the electric field from the gate electrode, and the main current flowing through this semiconductor device can be controlled. therefore,
In the semiconductor device according to the present invention, since the channel structure in the MOSFET (channel region 100 in FIG. 20) does not exist, the ON resistance is correspondingly reduced, and moreover, it can be used as a voltage-driven element similarly to the MOSFET.

Further, in the production of the basic element structure, the present semiconductor device does not require conductivity control to the silicon carbide semiconductor substrate, and the production process thereof is simple. The fact that conductivity control is not necessary means that, for example, 1700 for activating the ions implanted into the silicon carbide semiconductor substrate.
Since it is not necessary to anneal at a high temperature of about 0 ° C., it is possible to reduce the load on the manufacturing process and avoid problems such as surface roughness that occur during the high temperature anneal.

Further, for example, since the well region (P ⁻ type base region 150 in FIG. 20) and the contact region of the well region in the MOSFET are not required, it is convenient for miniaturization as compared with such an element structure (implementation). Form 1
Corresponding to ~ 4).

According to the second aspect of the present invention, the second conductivity type semiconductor region is formed on a part of the surface of the semiconductor substrate facing the gate electrode with the gate insulating film interposed therebetween.
Since the electric field applied to the gate insulating film is relaxed, the reliability of the gate insulating film is improved (corresponding to the second to fourth embodiments).

According to the third aspect of the present invention, the hetero semiconductor region is filled in the groove provided in the semiconductor substrate, and the gate insulating film is orthogonal to the heterojunction interface direction.
The length of the line of electric force from the gate electrode to the heterojunction interface can be shortened. Therefore, the controllability of the thickness of the energy barrier by the electric field from the gate electrode can be further improved. That is, the tunnel current of the barrier can be made to flow with a low gate voltage, and the control of the energy main current by the gate current becomes easy (corresponding to the fifth to ninth embodiments).

According to the fourth aspect of the invention, due to the second conductivity type semiconductor region connected to the hetero semiconductor region, the breakdown voltage of the device is the diode reverse direction breakdown voltage between this region and the first conductivity type semiconductor substrate. Since it can be designed to be determined, a high breakdown voltage element can be obtained (corresponding to the sixth embodiment).

According to the invention of claim 5, the device can be miniaturized by the trench gate structure (corresponding to the eighth and ninth embodiments).

According to the sixth aspect of the invention, the second first-conductivity-type semiconductor region formed in contact with the hetero semiconductor region is formed at a higher concentration than the first-conductivity-type semiconductor substrate. . For this reason, the spread of the depletion layer to the second semiconductor region due to the diffusion potential between the hetero semiconductor region and the second semiconductor region becomes small, and the energy barrier is formed thin. As a result, the tunnel current of the barrier can be passed at a low gate voltage, and the energy main current can be easily controlled by the gate voltage (corresponding to the fourth and seventh embodiments).

According to the seventh aspect of the invention, there is an advantage that regions having different impurity concentrations can be arbitrarily set inside the heterojunction semiconductor region, and the application range of the element can be widened (third and fifth embodiments). , 7).

According to the invention described in Claim 8, the material of silicon, amorphous silicon or polycrystalline silicon forming the hetero-semiconductor region hetero-junction to the silicon carbide semiconductor substrate has a band gap smaller than that of silicon carbide. To form a heterojunction with. Therefore, in the silicon carbide semiconductor device according to any one of claims 1 to 8, when these materials are used for the hetero semiconductor region, the above-described effects are easily obtained. Further, in the case of silicon, amorphous silicon, or polycrystalline silicon, deposition on a silicon carbide substrate, or oxidation, patterning, selective etching, selective conductivity control, etc. are easy (corresponding to the first to eighth embodiments). .

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. In the embodiments below, polycrystalline silicon (Poly-Si) is formed in the hetero semiconductor region.
However, the material for forming the hetero semiconductor region is not limited to this. The polytype of silicon carbide (SiC) used here is typically 4H, but other polytypes such as 6H and 3C may be used. Furthermore, it goes without saying that modifications are included without departing from the spirit of the present invention.

Further, in the present embodiment, the description has been given of the silicon carbide semiconductor device having a structure in which the drain electrode is formed on the back surface of the semiconductor substrate, the source electrode is arranged on the substrate surface, and a current is passed in the element in the vertical direction. For example, the present invention can be applied to a field effect transistor having a structure in which a drain electrode and a source electrode are arranged on the surface of a substrate so that a current flows laterally.

First Embodiment FIG. 1 is a diagram showing a first embodiment of a silicon carbide semiconductor device according to the present invention. This figure is a cross-sectional view showing a structure in which two unit cells are continuous. Actually, many unit cells are connected in parallel.

N serving as a drain region⁺Type SiC substrate 10
On top, N⁻The type epitaxial regions 20 are stacked. D
In a predetermined area on the axial area 20, N⁻Type polycrystal
A silicon layer 60 is formed. With a polycrystalline silicon layer 60
Heterojunction with the epitaxial region 20
An energy barrier exists at the interface. Also epi
Junction of the axial region 20 and the polycrystalline silicon layer 60
Adjacent to the gate electrode 40 via the gate insulating film 30
Is formed. The gate electrode 40 is formed on the interlayer insulating film 110.
To be covered. The polycrystalline silicon layer 60 is formed on the source electrode 80.
Connected. N ⁺On the back surface of the die-type SiC substrate 10.
An electrode 90 is formed.

This silicon carbide semiconductor device has a source electrode 8
0 is grounded and a positive voltage V _d is applied to the drain electrode 90 for use. Then, at this time, if the gate electrode 40 is grounded, the characteristics of the element will be the N ⁻ -type polycrystalline silicon layer 6
0 and the SiC epitaxial region 20 have a reverse bias characteristic of a heterojunction diode. That is, no current flows between the drain electrode 90 and the source electrode 80 until the drain voltage V _d becomes a sufficiently high voltage V _b .
However, when the drain voltage V _d exceeds V _b , a current suddenly starts to flow due to a tunnel phenomenon. On the other hand, when a positive voltage is applied to the gate electrode 40, an electric field acts on the heterojunction interface between the N ⁻ type polycrystalline silicon layer 60 and the SiC epitaxial region 20, and an electric field concentration causes an energy barrier of the heterojunction surface. The thickness becomes thin. As a result, even if the drain voltage V _d is equal to or lower than the predetermined voltage V _b , a tunnel phenomenon occurs and current starts flowing.

That is, in the silicon carbide semiconductor device according to the present invention, the drain voltage V _d is kept below V _b , and a positive voltage is applied to the gate electrode 40 in this state, so that the drain electrode 90 and the source electrode 80 are separated from each other. The current is controlled between them.

<< Heterojunction Characteristics >> Next, the characteristics of the heterojunction between polycrystalline silicon and SiC will be described with reference to FIGS.
It will be described in detail with reference to FIG. 17 to 19 are diagrams showing the energy band structure of a semiconductor. In the figure, the left side is N
^- type silicon, the right the N ^- a type 4H-SiC. Polycrystalline silicon is used in the first embodiment, but an explanation will be given by using an energy band of silicon in the figure.

FIG. 17 shows a state in which they are not in contact with each other.
You In the figure, χ is the electron affinity of silicon.₁, Work function (true
Energy from the empty level to the Fermi level) φ₁, H
Ermi energy (energy from conduction band to Fermi level)
Ruggy) to δ₁, The bandgap is E_G1And As well
And the electron affinity of 4H-SiC is χ_Two, Work function
φ _Two, Fermi energy δ_Two, The bandgap is E
_G2I will keep it.

Both are brought into contact with each other, and silicon and 4H--SiC
18 is formed, the energy band structure becomes as shown in FIG. Due to the difference in electron affinity χ between the silicon and 4H-SiC, the energy barrier Δ
E _c is present.

ΔE _c = χ ₁ −χ ₂ (1) For simplicity, let us consider the energy level of a semiconductor heterojunction, that is, an ideal heterojunction, in the case where no interface level exists at the heterojunction interface.

Now, in the semiconductor device shown in FIG.
Connect the drain electrode 90 to the drain electrode 90 with the gate electrode 40 grounded.
When the voltage Vd of⁻Type polycrystalline silicon layer 60
And N ⁻Bonding with type 4H-SiC epitaxial region 20
The energy band diagram of the interface is approximately the solid line in FIG.
As shown. 4H-SiC epitaxial region 20
Drain voltage V_dThe depletion layer expands accordingly. one
On the other hand, the electrons on the polycrystalline silicon layer 60 side are
Wall △ E_cCannot be exceeded and electrons accumulate at the junction interface.
However, almost no element current flows. And SiC epi
Electric lines of force corresponding to the depletion layer extending to the side of the axial region 20
Ends in this electron accumulation layer, and the polycrystalline silicon layer 60 side
In, the electric field is shielded. Therefore, the polycrystalline
It doesn't mean that the con layer 60 breaks down.
Drain voltage V_dIs the predetermined voltage V _bFor the first time
A current suddenly flows from the rain electrode 90 to the source electrode 80.
Start to get lost.

When a positive voltage is applied to the gate electrode 40,
An electric field acts on the heterojunction interface between the N ⁻ type polycrystalline silicon layer 60 and the SiC epitaxial region 20, and the thickness of the energy barrier formed by the heterojunction surface becomes thin as shown by the dotted line in FIG. When the thickness of this energy barrier becomes sufficiently thin as about 100 Å, electrons pass through the barrier due to the tunnel phenomenon, and as a result, the drain voltage V _d becomes the predetermined voltage V _b.
Even if it is below, a tunnel phenomenon occurs and current starts to flow.

The heterojunction characteristics described above have characteristics very similar to the junction characteristics of a semiconductor and a Schottky metal, so-called Schottky junction characteristics. But,
For example, the heterojunction characteristics of polycrystalline silicon and SiC are as follows.
It has properties superior to the bonding properties of.

The heterojunction characteristics of polycrystalline silicon and SiC will be described in more detail with reference to FIG.

When silicon is brought into contact with 4H-SiC,
Since electrons move from the 4H-SiC side to the silicon side,
It is assumed that an electron accumulation layer having a width W1 is formed on the junction interface on the silicon side, while a depletion layer having a width W2 is formed on the 4H-SiC side. The diffusion potential generated at both junction interfaces is V
_D, when the diffusion potential components of the silicon side diffusion potential components of _V 1, 4H-SiC side and _{V 2, V D} because is the energy difference between the Fermi level of the _{two, V D = (δ 1 +} △ E _{c -δ 2) / q (2} ) V D = V 1 + V 2 (3) depletion width is formed in the 4H-SiC side W2 is, W2 = {(2 · ε0 · ε2 · V 2) / (q N2)} ^1/2 (4) Here, ε0 represents a dielectric constant in vacuum, ε2 represents a relative dielectric constant of 4H—SiC, and N2 represents an ionized impurity concentration of 4H—SiC. Note that these equations consider the ideal state for simplicity and do not consider the effect of distortion, and the model of band discontinuity is based on Anderson's electron affinity.

In the semiconductor device of the present invention shown in FIG. 1, the width of the energy barrier is narrowed by applying a voltage to the gate electrode to control the main current as shown in FIG. Therefore, if W2 shown in the equation (4) is increased, it becomes difficult to control the tunnel current by the gate voltage. On the other hand, when W2 is made thin, the tunnel current of the barrier can be passed at a low gate voltage, and the control of the energy main current by the gate voltage becomes easy. However, the breakdown voltage _{Vb of the} device becomes small, and a high drain breakdown voltage device cannot be obtained.

The formula (4), W2 is a function of _{V 2, V 2} is 4H-S of the diffusion potential _{V D} generated at the heterojunction
Since it is the diffusion potential component on the iC side (Equation 3), increasing V _D also increases V ₂ , and vice versa. Since V _D is the energy difference of the Fermi level of the semiconductor that is heterojunction, it can be controlled by changing the ionized impurity concentration of the semiconductor that is heterojunction.

That is, for example, polycrystalline silicon and SiC
In the heterojunction, the width W2 of the depletion layer formed on the SiC side can be controlled by changing the concentration of ionized impurities in the polycrystalline silicon. As a result, W2 can be changed so that the tunnel current can be controlled by the gate voltage while obtaining a desired heterojunction breakdown voltage. This is a great advantage of the heterojunction of polycrystalline silicon and SiC.

Because, Schottky metal and SiC
This is because the work function of Schottky metal is a value peculiar to the substance in the junction with and, and the material itself of the Schottky metal must be changed in order to change W2.

Although the above description has been given by taking N-type polycrystalline silicon and N-type SiC as examples, P-type polycrystalline silicon and N-type SiC may be used. Alternatively, P-type polycrystalline silicon and P-type SiC may be used. Further, amorphous silicon is not limited to silicon and polycrystalline silicon (corresponding to claim 8).

<< Manufacturing Method >> Next, an example of a method of manufacturing the silicon carbide semiconductor device according to the first embodiment will be described with reference to FIGS.
It demonstrates using (c) and sectional drawing of FIG.11 (d)-(f). First, in the step of FIG. 10A, an impurity concentration of, for example, 10 ¹⁴ to 10 − is formed on the N ⁺ type SiC substrate 10.
10 ¹⁸ cm ⁻³ , N ⁻ type Si having a thickness of 1 to 100 μm
A C epitaxial region 20 is formed.

In the step of FIG. 10B, after sacrificial oxidation is performed on the epitaxial region 20 to remove the sacrificial oxide film, the polycrystalline silicon layer 60 is depressurized to a thickness of, for example, about 0.1 to 10 μm. It is deposited using the CVD method. After that, desired impurities are introduced into the polycrystalline silicon layer 60 to form the N ⁻ -type polycrystalline silicon layer 60. As a method of introducing impurities, a highly-doped deposition film is deposited on the deposited polycrystalline silicon layer 60, and 6
The impurities in the deposit film are thermally diffused into the polycrystalline silicon layer 60 by a heat treatment at about 100 to 1000 ° C., or the impurities are directly injected into the polycrystalline silicon layer 6 by ion implantation.
It may be introduced at 0.

In the step of FIG. 10C, the polycrystalline silicon layer 60 is patterned to form the N ^-- type polycrystalline silicon layer 60.

In the step of FIG. 11D, for example, C
A VD oxide film is deposited to form a gate insulating film 30, and a polycrystalline silicon layer 40 ′ is deposited again on the gate insulating film 30 to a thickness of, for example, about 0.1 to 10 μm by the low pressure CVD method. After that, desired impurities are introduced into the polycrystalline silicon layer 40 '.

In the step of FIG. 11E, the polycrystalline silicon layer 40 'is patterned to form the gate electrode 40.
To form.

In the first embodiment, the polycrystalline silicon layers 60 and 40 'are deposited and then the impurities are doped into the polycrystalline silicon layers 60 and 40'. However, for example, the polycrystalline silicon is used. The layers 60, 40 'may be patterned first and then doped with impurities. In order to improve carrier mobility in the polycrystalline silicon layer, for example, the N ⁻ -type polycrystalline silicon layer 60 is annealed to make the polycrystalline silicon layer 60 single crystal or increase the grain size of the polycrystalline silicon. Good. The polycrystalline silicon layer 60 may be crystallized by irradiating it with laser light.

After that, the interlayer insulating film 110 is formed and patterned, and the interlayer insulating film 110 and the gate insulating film 30 are etched using, for example, an HF solution to open contact holes.

In the step of FIG. 11F, the source electrode 80 made of, for example, a metal film is formed so as to come into contact with the N ⁻ type polycrystalline silicon layer 60, and the metal film is formed as the drain electrode 90 on the back surface of the SiC substrate 10. Is vapor-deposited, for example 600
Heat treatment is performed at about 1300 ° C. to form an ohmic electrode.
Thus, the silicon carbide semiconductor device shown in FIG. 1 is completed.

That is, the semiconductor device according to the first embodiment includes a silicon carbide semiconductor substrate of the first conductivity type (N ⁺ type SiC substrate 10 and N ⁻ type epitaxial region 20 thereon).
A hetero semiconductor region (N
^{A −} type polycrystalline silicon layer 60), a gate electrode (40) disposed adjacent to a junction between the semiconductor substrate and the hetero semiconductor region via a gate insulating film (30), and the semiconductor substrate. A drain electrode (90) of the first conductivity type provided and a source electrode (80) in contact with the hetero semiconductor region are provided (corresponding to claim 1).

In this silicon carbide semiconductor device, if a positive voltage is applied to gate electrode 40 to thin the energy barrier of the heterojunction, carriers can pass through the thin barrier (tunnel). phenomenon).
That is, with a positive voltage applied to the drain, the thickness of the energy barrier can be controlled by the electric field from the gate electrode 40, and the main current flowing through this semiconductor device can be controlled. Therefore, in the semiconductor device according to the first embodiment, the MOS
Channel structure in FET (channel region 1 in FIG. 20)
00) does not exist, the ON resistance is correspondingly reduced, and it can be used as a voltage-driven element similarly to a MOSFET.

Further, the semiconductor device of the first embodiment is
In manufacturing a basic device structure, it is not necessary to control the conductivity to the silicon carbide semiconductor substrate, and the manufacturing process thereof is simple. The fact that conductivity control is not necessary means that high temperature annealing at about 1700 ° C. for activating the ions implanted into the silicon carbide semiconductor substrate does not have to be performed, so that the load of the manufacturing process can be reduced and It is also possible to avoid problems such as surface roughness caused by high temperature annealing.

Further, for example, the well region (P ^-- type base region 150 of FIG. 20) and the contact region of the well region in the MOSFET are not required, which is convenient for miniaturization as compared with such an element structure.

Second Embodiment FIG. 2 is a sectional view similar to FIG. 1, showing a structure of a silicon carbide semiconductor device according to a second embodiment of the present invention. The difference from the first embodiment shown in FIG. 1 is that the S immediately below the gate insulating film 30 is different.
That is, the P ⁻ type SiC region 120 was formed in the portion of the iC epitaxial region 20. That is, a semiconductor region of the second conductivity type (P ⁻ -type SiC) is formed on a part of the surface of the semiconductor substrate that faces the gate electrode 40 with the gate insulating film 30 interposed therebetween.
A region 120) is formed (corresponding to claim 2). As a result, the electric field applied to the gate insulating film 30 with respect to the drain voltage is relaxed, so that the reliability of the gate insulating film 30 is improved. However, conductivity control is required to form the P ⁻ type SiC region 120.

Third Embodiment FIG. 3 is a sectional view similar to FIG. 1, showing a structure of a silicon carbide semiconductor device according to a third embodiment of the present invention. 2 is different from that of the second embodiment in that the region where the polycrystalline silicon layer 60 is adjacent to the gate insulating film 30 is formed in the N ⁺ -type polycrystalline silicon 5
It means 0. That is, the hetero semiconductor region is a region having a different impurity concentration (N ⁻ type polycrystalline silicon layer 6
0 and an N ⁺ -type polycrystalline silicon layer 50) are provided (corresponding to claim 7).

The N ⁺ type polycrystalline silicon layer 50 is replaced with N ⁻ type 4H.
When the hetero junction is formed in the —SiC epitaxial region 20, the diffusion potential V _D generated in the junction can be made smaller than that in the case where the N ⁻ type polycrystalline silicon layer 60 is joined. Therefore, the width W2 of the depletion layer that spreads in the N ⁻ type 4H—SiC epitaxial region 20 becomes small, and the tunnel current of the barrier can flow at a low gate voltage, so that the energy main current can be easily controlled by the gate voltage. At this time, the N ⁺ type polycrystalline silicon layer 50 and the N ⁻ type 4H—SiC are used.
Although the breakdown voltage of the junction with the epitaxial region 20 is low, N ⁻
From the junction interface of the N ^- type polycrystalline silicon layer 60 to the N ⁻ -type 4H-S
A depletion layer extending to the iC epitaxial region 20 and N ⁺
Since the electric field applied to the junction between the type polycrystalline silicon layer 50 and the N ⁻ type 4H—SiC epitaxial region 20 is shielded, it is possible to prevent the drain breakdown voltage from decreasing.

That is, in the silicon carbide semiconductor device of the third embodiment, in addition to the effect described in the second embodiment, the effect of improving the controllability of the element main current by the gate voltage can be obtained.

Embodiment 4 FIG. 4 shows a silicon carbide semiconductor device according to a fourth embodiment of the present invention.
It is sectional drawing similar to FIG. 1 which shows a structure. Form of implementation of FIG.
The difference in configuration from state 2 is N⁻Type polycrystalline silicon layer 60
At the end of the junction surface between⁻Type SiC region 1
That is, 30 is formed. This N⁻Type SiC region
130 is N⁻Type SiC epitaxial region 20
The ionized impurities are formed to have a high concentration. this
Therefore, N ⁻Type polycrystalline silicon layer 60 and N⁻Type SiC region
From the junction interface with 130, N⁻Type Si
The width of the depletion layer that spreads to the C region 130 becomes smaller,
The rugie barrier is formed thin. As a result,
Gate voltage allows the tunnel current of the barrier to flow.
It becomes easy to control the energy main current by the voltage.

That is, in the silicon carbide semiconductor device according to the fourth embodiment, a part of the semiconductor substrate facing the gate electrode via the gate insulating film has a second first concentration different from that of the semiconductor substrate. Conductive type semiconductor region (N ⁻ type Si
C region 130) is formed, and the second semiconductor region of the first conductivity type is in contact with the hetero semiconductor region (corresponding to claim 6).

Fifth Embodiment FIG. 5 is a sectional view showing a silicon carbide semiconductor device according to a fifth embodiment of the present invention. This figure is a cross-sectional view showing a structure in which three unit cells are continuous. Actually, many unit cells are connected in parallel.

N ⁺ type SiC substrate 10 which becomes the drain region
An N ⁻ type epitaxial region 20 is stacked on top. A groove 70 is formed in a predetermined region of the epitaxial region 20, and the inside of the groove 70 is filled with the N ⁻ type polycrystalline silicon layer 60 and the N ⁺ type polycrystalline silicon layer 50. These polycrystalline silicon layers 60, 50 and the SiC epitaxial region 20 are heterojunctioned with each other, and an energy barrier exists at the junction interface. In addition, the epitaxial region 2
A gate electrode 40 is formed adjacent to the junction between 0 and the N ⁺ -type polycrystalline silicon layer 50 with the gate insulating film 30 interposed therebetween. The gate electrode 40 is covered with the interlayer insulating film 110.
The N ⁺ -type polycrystalline silicon layer 60 is connected to the source electrode 80. A drain electrode 90 is formed on the back surface of the N ⁺ type SiC substrate 10.

The operation of this silicon carbide semiconductor device is basically the same as that of the first embodiment shown in FIG. That is, the source electrode 80 is grounded, and the positive voltage V is applied to the drain electrode 90.
_d is applied and used. Then, at this time, when the gate electrode 40 is grounded, the device characteristic becomes the reverse bias characteristic of the heterojunction diode between the N ⁻ type polycrystalline silicon layer 60 and the SiC epitaxial region 20. On the other hand, when a positive voltage is applied to the gate electrode 40, an electric field acts on the heterojunction interface between the N ⁺ type polycrystalline silicon 50 and the SiC epitaxial region 20, and the thickness of the energy barrier formed by the heterojunction surface due to electric field concentration. Becomes thin. As a result, even if the drain voltage V _d is equal to or lower than the predetermined voltage V _b , a tunnel phenomenon occurs and current starts flowing.

The structural difference between the first embodiment shown in FIG. 1 and the fifth embodiment shown in FIG. 5 is that a groove 70 is formed, and the N ⁻ type polycrystalline silicon layer 60 and the N ⁺ are formed in the groove 70. The point is that the type polycrystalline silicon layer 50 is filled.

As described above, by making the gate insulating film 30 orthogonal to the direction of the heterojunction interface between polycrystalline silicon and SiC, the length of the line of electric force from the gate electrode 40 to the heterojunction interface can be shortened. it can. Therefore, the controllability of the thickness of the energy barrier by the electric field from the gate electrode 40 can be further improved. In other words, the barrier tunnel current can flow at a low gate voltage,
It becomes easy to control the energy main current by the gate current.

The region where the N ⁺ -type polycrystalline silicon layer 50 and the N ⁻ -type polycrystalline silicon layer 60 have different concentrations as described above is provided because the N ⁺ -type polycrystalline silicon layer 50 has a low gate voltage. This is because the tunnel current is passed and the N ⁻ -type polycrystalline silicon layer 60 has a high drain breakdown voltage. As described above, the advantage that the regions having different impurity concentrations can be arbitrarily set inside the heterojunction semiconductor region can greatly improve the device characteristics.

<< Manufacturing Method >> Next, an example of a method of manufacturing the silicon carbide semiconductor device according to the fifth embodiment will be described with reference to FIGS.
It demonstrates using (c) and sectional drawing of FIG.13 (d)-(f). First, in the step of FIG. 12A, an impurity concentration of, for example, 10 ¹⁴ to 10 − is formed on the N ⁺ type SiC substrate 10.
10 ¹⁸ cm ⁻³ , N ⁻ type Si having a thickness of 1 to 100 μm
A C epitaxial region 20 is formed.

In the step of FIG. 12B, the mask material 170 is used to form the groove 7 having a depth of, for example, 0.1 to 10 μm.
Form 0.

In the step of FIG. 12C, after sacrificial oxidation is performed on the epitaxial region 20 to remove the sacrificial oxide film, the polycrystalline silicon layer 180 is depressurized to a thickness of, for example, about 0.1 to 10 μm. It is deposited using the CVD method. After that, desired impurities are introduced into the polycrystalline silicon layer 180 to form the N ⁻ -type polycrystalline silicon layer 180. As a method of introducing impurities, the deposited polycrystalline silicon layer 180 is used.
Further, a highly-deposited deposition film is deposited, and the impurities in the deposition film are thermally diffused into the polycrystalline silicon layer 180 by heat treatment at about 600 to 1000 ° C., or the impurities are ion-implanted. May be directly introduced into the polycrystalline silicon layer 180.

In the step of FIG. 13D, for example, C
The poly-crystalline silicon layer 180 is mechanically and chemically researched using the MP method.
Polishing leaves polycrystalline silicon layer 180 inside trench 70. Next
For example, by using the mask material 171, the N in the groove 70 is⁻Type
A desired impurity is doped to a predetermined depth of the polycrystalline silicon layer 180.
Introduced, N⁺A type polycrystalline silicon layer 50 is formed. this
When N⁺Type polycrystalline silicon layer 50
Recon layer 180, N ⁻Type polycrystalline silicon layer 60
It

In the step of FIG. 13E, for example, C
A VD oxide film is deposited to form a gate insulating film 30, and a polycrystalline silicon layer is again deposited on the gate insulating film 30 to a thickness of, for example, about 0.1 to 10 μm by the low pressure CVD method. After that, desired impurities are introduced into the polycrystalline silicon layer. Next, the polycrystalline silicon layer is patterned to form the gate electrode 40.

In the fifth embodiment, an example has been described in which the polycrystalline silicon layer (180 or for forming the gate electrode 40) is deposited and then the impurity is doped into the polycrystalline silicon layer. The layer may be patterned first, and then the impurities may be doped. Further, in order to improve the mobility of carriers in the polycrystalline silicon layer, for example, the N ⁺ -type polycrystalline silicon layer 50 is annealed to make the polycrystalline silicon layer 50 single crystal or increase the grain size of the polycrystalline silicon. Good. The polycrystalline silicon layer 50 may be crystallized by irradiating it with laser light.

After that, the interlayer insulating film 110 is formed and patterned, and the interlayer insulating film 110 and the gate insulating film 30 are etched using, for example, an HF solution to open contact holes.

In the step of FIG. 13F, a source electrode 80 made of, for example, a metal film is formed so as to come into contact with the N ⁺ type polycrystalline silicon layer 50, and a metal film is formed as a drain electrode 90 on the back surface of the SiC substrate 10. Is vapor-deposited, for example 600
Heat treatment is performed at about 1300 ° C. to form an ohmic electrode.
Thus, the silicon carbide semiconductor device shown in FIG. 5 is completed.

That is, in the silicon carbide semiconductor device of the fifth embodiment, the first conductivity type silicon carbide semiconductor substrate, the groove (70) formed in the semiconductor substrate, and the groove filled with the above A hetero semiconductor region (N ⁻ type polycrystal silicon layer 60 and N ⁺ type polycrystal silicon layer 50) that heterojunctions with the semiconductor substrate, and a gate insulating film (adjacent to the junction between the semiconductor substrate and the hetero semiconductor region). 30) provided with a gate electrode (40), a drain electrode (90) of the first conductivity type provided on the semiconductor substrate, and a source electrode (80) in contact with the hetero semiconductor region. (Corresponding to claim 3).

Sixth Embodiment FIG. 6 is a sectional view showing a structure of a silicon carbide semiconductor device according to a sixth embodiment of the present invention. The difference in the configuration of the fifth embodiment shown in FIG. 5 is that the N ⁻ -type polycrystalline silicon layer 60 is replaced by P ^−.
The point is that the type SiC region 140 is formed. That is, a second conductivity type semiconductor region (P ⁻ type SiC region 140) is formed in a part of the semiconductor substrate so as to be connected to the hetero semiconductor region (N ⁺ type polycrystalline silicon layer 50). (Corresponding to item 4). The breakdown voltage of the device is this P ^- type SiC
Since the diode reverse breakdown voltage between the region 140 and the N ⁻ type SiC epitaxial region 20 determines the breakdown voltage, a high breakdown voltage element can be obtained.

However, conductivity control is required to form the P ^-- type SiC region 140.

Seventh Embodiment FIG. 7 is a sectional view showing a structure of a silicon carbide semiconductor device according to a seventh embodiment of the present invention. The difference in the configuration of the fifth embodiment shown in FIG. 5 is that the N ⁺ type polycrystalline silicon 51 is formed so as to be covered with the N ⁻ type polycrystalline silicon layer 61.
^The N ⁻ type SiC region 13 is provided between the ⁻ type polycrystalline silicon layers 61.
0 is formed.

This N ^-- type SiC region 130 is made up of N ^-- type S.
The ionized impurities are formed to have a higher concentration than the iC epitaxial region 20. Therefore N ^- from the bonding interface of the type SiC region 130, N by diffusion potential ^{- -} -type polycrystalline silicon layer 61 and the N width of the depletion layer extending into -type SiC region 130 is reduced, the thickness of the thin energy barrier To be done. As a result, the tunnel current of the barrier can be made to flow at a low gate voltage, and the control of the energy main current by the gate voltage becomes easy.

Incidentally, in FIG. 7, the gate electrode 40 is
It is formed so as to reach the N ⁺ -type polycrystalline silicon layer 51 in the substrate surface direction, but it does not have to reach it separately. However, when the threshold voltage is reached, the resistance of the N ⁻ type polycrystalline silicon layer 61 when the element is turned on by applying a positive voltage to the gate becomes smaller.

Eighth Embodiment FIG. 8 is a sectional view showing a structure of a silicon carbide semiconductor device according to an eighth embodiment of the present invention. This figure is a cross-sectional view in which two structural unit cells are continuous.

N ⁺ type SiC substrate 10 which becomes the drain region
An N ⁻ type epitaxial region 20 is stacked on top. A groove 71 is formed in a predetermined region on the epitaxial region 20, and the N ⁻ -type polycrystalline silicon layer 60 is filled in the groove 71. An N ⁺ type polycrystalline silicon layer 50 is deposited on the N ⁻ type polycrystalline silicon layer 60, and a groove 72 is formed so as to penetrate the N ⁺ type polycrystalline silicon layer 50 and reach the N ⁻ type SiC region 20. Has been done. The inside of the groove 72 is filled with the gate electrode 40 via the gate insulating film 30. The gate electrode 40 is covered with the interlayer insulating film 110. The N ⁺ type polycrystalline silicon layer 50 is connected to the source electrode 80.
A drain electrode 90 is formed on the back surface of the N ⁺ type SiC substrate 10.

The operation of this silicon carbide semiconductor device is basically the same as that of the fifth embodiment shown in FIG. That is, the source electrode 80 is grounded, and the positive voltage V is applied to the drain electrode 90.
_d is applied and used. Then, at this time, when the gate electrode 40 is grounded, the device characteristics are the reverse bias characteristics of the heterojunction diode between the N ⁻ type polycrystalline silicon layer 60 and the SiC epitaxial region 20. On the other hand, when a positive voltage is applied to the gate electrode 40, an electric field acts on the heterojunction interface between the N ⁺ -type polycrystalline silicon layer 50 and the SiC epitaxial region 20 and the energy barrier of the heterojunction surface is formed by the electric field concentration. The thickness becomes thin. As a result, even if the drain voltage V _d is equal to or lower than the predetermined voltage V _b , a tunnel phenomenon occurs and current starts flowing.

The structural difference between the fifth embodiment shown in FIG. 5 and the eighth embodiment shown in FIG. 8 is that a groove 72 is formed and the gate electrode 40 is filled in the groove 72. Such UMOS gate (or trench MOS gate)
With the structure, the element efficiency with respect to the device area can be increased and the current density can be increased.

<< Manufacturing Method >> Next, an example of a method of manufacturing the silicon carbide semiconductor device of the eighth embodiment will be described with reference to FIGS.
(C), FIG.15 (d)-(f), and FIG.16 (g),
This will be described with reference to the sectional view of (h). First, FIG. 14 (a)
In the step of, the impurity concentration is, for example, 10 ¹⁴ to 10 ¹⁸ cm ⁻³ , and the thickness is 1 on the N ⁺ type SiC substrate 10.
An N ⁻ -type SiC epitaxial region 20 of ˜100 μm is formed.

In the step of FIG. 14B, the mask material 172 is used to form the groove 7 having a depth of, for example, 0.1 to 10 μm.
1 is formed.

In the step of FIG. 14C, after sacrificial oxidation is performed on the epitaxial region 20 to remove the sacrificial oxide film, the polycrystalline silicon layer 181 is depressurized to a thickness of, for example, about 0.1 to 10 μm. It is deposited using the CVD method. After that, desired impurities are introduced into the polycrystalline silicon layer 181, thereby forming the N ⁻ type polycrystalline silicon layer 181. As a method of introducing impurities, the deposited polycrystalline silicon layer 181 is used.
On top of it, a highly-doped deposition film is deposited, and the impurities in the deposition film are thermally diffused into the polycrystalline silicon layer 181 by heat treatment at about 600 to 1000 ° C., or
Alternatively, impurities may be directly introduced into the polycrystalline silicon layer 181 by ion implantation.

In the step of FIG. 15D, for example, C
The polycrystalline silicon layer 181 is mechanically and chemically polished by using the MP method, and the polycrystalline silicon layer 181 is left inside the groove 71.

In the step of FIG. 15 (e), the polycrystalline silicon layer 50 has a thickness of, for example, about 0.1 to 5 μm and a reduced pressure C.
Deposit using the VD method. Then, the polycrystalline silicon layer 5
0 into which desired impurities are introduced, and N ⁺ type polycrystalline silicon layer 5 is formed.
Set to 0. As a method of introducing impurities, a highly-deposited deposition film is deposited on the deposited polycrystalline silicon layer 50, and the impurities in the deposition film are removed by heat treatment at about 600 to 1000 ° C. Impurities may be introduced directly into the polycrystalline silicon layer 50 by thermal diffusion therein or by ion implantation.

In the step of FIG. 15F, the mask material
173 is used to form the groove 7 having a depth of, for example, 0.1 to 10 μm.
1 for N⁺Through the polycrystalline silicon layer 50 in the depth direction
N ⁻It is formed so as to reach the type SiC region.

In the step of FIG. 16G, for example, C
A VD oxide film is deposited to form a gate insulating film 30, and polycrystalline silicon is deposited again on the gate insulating film 30 to a thickness of, for example, about 0.1 to 10 μm using a low pressure CVD method. After that, desired impurities are introduced into the polycrystalline silicon layer. Next, the polycrystalline silicon layer is patterned to form the gate electrode 40.

In the eighth embodiment, the polycrystalline silicon layer (181, 50, or for forming the gate electrode 40) is used.
Although the description has been given of the example in which the polycrystalline silicon layer is doped with the impurities after the deposition, the polycrystalline silicon layer may be patterned, for example, and then the impurities may be doped. Further, in order to improve the mobility of carriers in the polycrystalline silicon layer, for example, the N ⁺ -type polycrystalline silicon layer 50 is annealed to make the polycrystalline silicon layer 50 single crystal or increase the grain size of the polycrystalline silicon. Good. The polycrystalline silicon layer 50 may be crystallized by irradiating it with laser light.

In the step of FIG. 16H, the interlayer insulating film 110 is formed and patterned, and the interlayer insulating film 110 and the gate insulating film 30 are etched using, for example, an HF solution to form the contact holes. Make a hole.

A source electrode 80 made of, for example, a metal film is formed so as to come into contact with the N ⁺ -type polycrystalline silicon layer 50,
A metal film is vapor-deposited as a drain electrode 90 on the back surface of the SiC substrate 10 and heat-treated at about 600 to 1300 ° C. to form an ohmic electrode. Thus, the silicon carbide semiconductor device shown in FIG. 8 is completed.

That is, in the silicon carbide semiconductor device of the eighth embodiment, a silicon carbide semiconductor substrate of the first conductivity type and a hetero semiconductor region (N ⁻ type polycrystalline silicon layer 60 and its heterojunction on the semiconductor substrate) are formed. An upper N ⁺ -type polycrystalline silicon layer 50) and a groove (72) formed so as to penetrate the hetero semiconductor region in the depth direction to reach the semiconductor substrate,
Gate electrode (40) filled in the groove through an insulating film
And a source electrode (8
0) and a drain electrode (90) of the first conductivity type provided on the semiconductor substrate (corresponding to claim 5).

Ninth Embodiment FIG. 9A is a sectional perspective view showing the structure of a silicon carbide semiconductor device according to a ninth embodiment of the present invention, and FIG. 9B is a top view of FIG. 9A.

The structural difference from the eighth embodiment shown in FIG. 8 is that
The point is that the N ⁻ type polycrystalline silicon layer 60 is formed so as to fill the inside of the groove 75 formed in a region not shown in the cross-sectional view of FIG.

With such a structure, it is possible to increase the element efficiency with respect to the device area and increase the current density.

Although the present invention has been specifically described above based on the embodiments, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Is.

[Brief description of drawings]

FIG. 1 is a sectional view showing a structure of a silicon carbide semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a sectional view showing a structure of a silicon carbide semiconductor device according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a structure of a silicon carbide semiconductor device according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a structure of a silicon carbide semiconductor device according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a structure of a silicon carbide semiconductor device according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a structure of a silicon carbide semiconductor device according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a structure of a silicon carbide semiconductor device according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view showing a structure of a silicon carbide semiconductor device according to an eighth embodiment of the present invention.

9A is a sectional perspective view showing the structure of a silicon carbide semiconductor device according to a ninth embodiment of the present invention, and FIG. 9B is a top view.

FIG. 10 is a process cross-sectional view showing the method of manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention.

FIG. 11 is a process cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device of the first embodiment of the present invention.

FIG. 12 is a process cross-sectional view showing the method of manufacturing the silicon carbide semiconductor device of the fifth embodiment of the present invention.

FIG. 13 is a process cross-sectional view showing the method of manufacturing the silicon carbide semiconductor device of the fifth embodiment of the present invention.

FIG. 14 is a process cross-sectional view showing the method for manufacturing the silicon carbide semiconductor device of the eighth embodiment of the present invention.

FIG. 15 is a process cross-sectional view showing the method of manufacturing the silicon carbide semiconductor device of the eighth embodiment of the present invention.

FIG. 16 is a process cross-sectional view showing the method of manufacturing the silicon carbide semiconductor device of the eighth embodiment of the present invention.

FIG. 17 is an energy band diagram of Si and 4H—SiC before contact.

FIG. 18 is an energy band diagram of Si and 4H—SiC after contact.

FIG. 19 is an energy band diagram of Si and 4H—SiC when a drain voltage is applied.

FIG. 20 is a cross-sectional view of a conventional SiC planar MOSFET.

[Explanation of symbols]

10 ... N ⁺ type SiC substrate 20 ... N ^-- type SiC epitaxial region 30 ... Gate insulating film 40 ... Gate electrode 50 ... N ⁺ type polycrystalline silicon layer 60 ... N ^-- type polycrystalline silicon layer 70, 71, 72, 73, 74, 75 ... Groove 80 ... Source electrode 90 ... Drain electrode 100 ... Channel region 110 ... Interlayer insulating film 120 ... P ^-- type SiC region 130 ... N ^-- type (darker concentration than the SiC epi region 20)
SiC region 140 ... P ^-- type SiC region 150 ... P ^-- type SiC region 160 ... N ⁺ type SiC region (source region) 170, 171, 172, 173 ... Mask material 180, 181 ... Polycrystalline silicon layer

Claims (8)

[Claims] 1. A silicon carbide semiconductor substrate of the first conductivity type, a hetero semiconductor region hetero-junctioning on the semiconductor substrate, and a gate insulating film adjacent to a junction between the semiconductor substrate and the hetero semiconductor region. A gate electrode arranged in a line, a first conductivity type drain electrode provided on the semiconductor substrate,
A silicon carbide semiconductor device, comprising: a source electrode in contact with the hetero semiconductor region. 2. The semiconductor region of the second conductivity type is formed on a part of the surface of the semiconductor substrate which faces the gate electrode with the gate insulating film interposed therebetween. Silicon carbide semiconductor device. 3. A first-conductivity-type silicon carbide semiconductor substrate, a groove formed in the semiconductor substrate, a hetero-semiconductor region filled in the groove, which heterojunctions with the semiconductor substrate, and the semiconductor substrate. A gate electrode disposed adjacent to the junction with the hetero semiconductor region via a gate insulating film, and a drain electrode of the first conductivity type provided on the semiconductor substrate,
A silicon carbide semiconductor device, comprising: a source electrode in contact with the hetero semiconductor region. 4. A silicon carbide semiconductor device according to claim 3, wherein a second conductivity type semiconductor region is formed on a part of said semiconductor substrate so as to be connected to said hetero semiconductor region. 5. A first-conductivity-type silicon carbide semiconductor substrate, a hetero semiconductor region hetero-junctioned to the semiconductor substrate, and a hetero semiconductor region formed so as to penetrate the hetero semiconductor region in the depth direction to reach the semiconductor substrate. A groove, a gate electrode filled in the groove via a gate insulating film, a source electrode in contact with the hetero semiconductor region, and a first-conductivity-type drain electrode provided in the semiconductor substrate. A silicon carbide semiconductor device characterized by the above. 6. A second conductivity type semiconductor region having a concentration different from that of the semiconductor substrate is formed in a part of the semiconductor substrate facing the gate electrode with the gate insulating film interposed therebetween. 6. A silicon carbide semiconductor device according to claim 1, wherein a second semiconductor region of the first conductivity type is in contact with the hetero semiconductor region. 7. The silicon carbide semiconductor device according to claim 1, wherein the hetero semiconductor region has regions having different impurity concentrations. 8. The silicon carbide semiconductor device according to claim 1, wherein the hetero semiconductor region is made of at least one of silicon, amorphous silicon and polycrystalline silicon.