JP2007323712A - Sense amplifier, semiconductor memory device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a sense amplifier which is little influenced by noise in reading when readout voltage is large, also can accurately read information without causing sneak current even when a transistor for amplification is turned on, and to provide a semiconductor memory device and electronic equipment. <P>SOLUTION: In the sense amplifier 104, a P type transistor P2 for driving is connected between a P type transistor P0 for amplification and a first node 1, an N type transistor N2 for driving is connected between an N type transistor N0 for amplification and the first node 1. In the sense amplifier 104, a P type transistor P3 for driving is connected between a P type transistor P1 for amplification and a second node 2, and an N type transistor N3 for driving is connected between an N type transistor N1 for amplification and a first node 2. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a sense amplifier, a semiconductor memory device, and an electronic apparatus. The present invention particularly relates to a sense amplifier that performs a read operation by voltage comparison. The present invention also relates to a semiconductor memory device including a sense amplifier and a memory cell for determining information based on the magnitude of current, such as a flash memory cell or a mask ROM (read only memory) cell. The present invention also relates to an electronic apparatus having a semiconductor memory device.

  In recent years, non-volatile semiconductor memory elements such as flash memory, ferroelectric memory or mask ROM have been used in semiconductor memory devices for data storage such as mobile phones and digital cameras, or code (program) storage. Yes. Here, the nonvolatile memory cell is configured to determine information using a change in cell current according to the storage state. Conventionally, in order to read information in a nonvolatile memory cell, a reading method is used in which a reference current using a reference cell or the like is compared with a current flowing in the memory cell (Japanese Patent Laid-Open No. 2003-242793 (Patent Document 1)). ). However, reading by current comparison requires a DC path to be provided in the circuit, which causes a problem that power consumption increases and it is difficult to design a product with low power consumption.

  On the other hand, when a DRAM (Dynamic Random Access Memory) is used as a semiconductor memory element, information reading is generally performed by voltage comparison. This information reading method based on voltage comparison has the advantages of low power consumption and easy amplification of a weak reading voltage, but avoids the following two problems (A) and (B). There is a problem that it is difficult.

  (A) When the read voltage is large, noise at the time of reading is large and information cannot be read accurately. For example, in the circuit diagram showing an example of the conventional sense amplifier shown in FIG. 16, when the voltage change of the bit lines BL0 and BL1 is large, the parasitic capacitances Cp0 between the gates and drains of the amplifying transistors P100, P101, N100, and N101, The charges accumulated in Cp1, Cn0, and Cn1 or the accumulated charges greatly affect the potential difference between the bit line BL0 and the bit line BL1, making it difficult to read out information accurately.

(B) When the charge / discharge amplitude is increased, the amplification transistor is turned on, and a sneak current is generated due to the amplification transistor being turned on. For example, in the circuit diagram shown in FIG. 16, if the bit line BL0 and the bit line BL1 are charged from 0 V, the P-type amplification transistors P100 and P101 are initially in the on state, so A sneak current is generated between the bit lines. On the other hand, when the bit line BL0 and the bit line BL1 are discharged from Vcc or the like, the N-type amplifying transistors N100 and N101 are first turned on, and again pass between the bit lines via the node N. Contamination current is generated. In addition, when all of bit line BL0 and bit line BL1, and node N and node P are precharged to Vcc / 2, the amplification transistor is cut off, so that a sneak current similar to that generated in DRAM is generated. On the other hand, in this case, charging from Vcc / 2 to Vcc, or discharging from Vcc / 2 to 0V, the amplitude of charging or discharging is reduced, and the amplitude before the amplification is reduced by the amount of decrease. The initial read voltage is reduced and the read margin is deteriorated.
JP 2003-242793 A

  Therefore, the problem of the present invention is that, when the read voltage is large, the influence of noise at the time of reading is small, and even if the amplification transistor is turned on, no sneak current is generated and information can be read accurately. It is another object of the present invention to provide a sense amplifier with a low power consumption due to voltage comparison in a reading method, a semiconductor memory device having the sense amplifier, and an electronic device having the semiconductor memory device.

In order to solve the above problems, the sense amplifier of the present invention provides:
A first sense node and a second sense node;
A first conductivity type first transistor having a control terminal connected to the first sense node and a first input / output terminal connected to a power supply or a ground;
A second transistor of the first conductivity type having a control terminal connected to the second sense node and a first input / output terminal connected to the power supply or ground;
A first conductivity type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to a second input / output terminal of the first transistor of the first conductivity type. A transistor,
A first conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second transistor of the first conductivity type. And a transistor.

  In this specification, the first conductivity type and the second conductivity type are P-type or N-type. When the first conductivity type is P type, the second conductivity type is N type. When the first conductivity type is N type, the second conductivity type is P type.

  According to the present invention, there is provided the third transistor capable of connecting and disconnecting the second input / output terminal of the first transistor and the second sense node, and the second input / output terminal of the second transistor and the first sense. Since the fourth transistor that can be connected to and disconnected from the node is provided, the third and fourth transistors in a state before the voltages of the first sense node and the second sense node as input signals are determined And the second input / output terminal of the first transistor and the second sense node are not connected to each other and the second input / output terminal of the second transistor and the first sense node are not connected to each other. When the voltages at the first sense node and the second sense node are determined, the third and fourth transistors are driven to connect the second input / output terminal of the first transistor and the second sense node. With connecting the over-de, can be connected to the second output terminal and the first sense node of the second transistor. Therefore, even when the read voltage is large, the influence of noise during reading can be reduced. Even if the first and second transistors, which are amplifying transistors, are turned on, a correct read can be performed without generating a sneak current.

In addition, the sense amplifier of one embodiment
A first transistor of a second conductivity type having a control terminal connected to the first sense node and a first input / output terminal connected to the ground or the power source;
A second conductivity type second transistor having a control terminal connected to the second sense node and a first input / output terminal connected to the ground or the power source;
A second conductive type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to the second input / output terminal of the second conductive type first transistor. A transistor,
A second conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second conductivity type second transistor. A transistor.

  According to the embodiment, the sense amplifier can be operated at high speed.

The sense amplifier of the present invention
A first sense node and a second sense node;
A first conductivity type first transistor having a control terminal connected to the first sense node;
A second transistor of the first conductivity type having a control terminal connected to the second sense node;
A first conductivity type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to a second input / output terminal of the first transistor of the first conductivity type. A transistor,
A first conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second transistor of the first conductivity type. A transistor,
A first conductivity type fifth transistor having a first input / output terminal connected to a power supply or a ground and a second input / output terminal connected to the first input / output terminal of the first conductivity type first transistor; ,
A first conductivity type sixth transistor having a first input / output terminal connected to a power supply or ground and a second input / output terminal connected to the first input / output terminal of the first conductivity type second transistor; It is characterized by having.

  According to the present invention, there is provided the third transistor capable of connecting and disconnecting the second input / output terminal of the first transistor and the second sense node, and the second input / output terminal of the second transistor and the first sense. Since the fourth transistor that can be connected to and disconnected from the node is provided, the third and fourth transistors in a state before the voltages of the first sense node and the second sense node as input signals are determined And the second input / output terminal of the first transistor and the second sense node are not connected to each other and the second input / output terminal of the second transistor and the first sense node are not connected to each other. When the voltages at the first sense node and the second sense node are determined, the third and fourth transistors are driven to connect the second input / output terminal of the first transistor and the second sense node. With connecting the over-de, can be connected to the second output terminal and the first sense node of the second transistor. Therefore, even when the read voltage is large, the influence of noise during reading can be reduced. Even if the first and second transistors, which are amplifying transistors, are turned on, a correct read can be performed without generating a sneak current.

  Further, according to the present invention, the fifth transistor capable of connecting / separating the power supply or ground and the first input / output terminal of the first transistor, and the power supply / ground and the second conductivity type second transistor are connected / separated. Having a sixth transistor that can be applied, a voltage accumulated at an intermediate node between the first transistor and the fifth transistor, a voltage accumulated at an intermediate node between the first transistor and the third transistor, A voltage stored at an intermediate node between the transistor and the sixth transistor and a voltage stored at an intermediate node between the second transistor and the fourth transistor are used to drive the first and second transistors. It can be lowered to about the threshold value Vth of the transistor. Therefore, the read operation margin can be improved.

In addition, the sense amplifier of one embodiment
A first transistor of a second conductivity type having a control terminal connected to the first sense node;
A second transistor of a second conductivity type having a control terminal connected to the second sense node;
A second conductive type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to the second input / output terminal of the second conductive type first transistor. A transistor,
A second conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second conductivity type second transistor. A transistor,
A second conductivity type fifth transistor having a first input / output terminal connected to the ground or the power source and a second input / output terminal connected to the first input / output terminal of the second conductivity type first transistor. When,
A second conductivity type sixth transistor having a first input / output terminal connected to the ground or the power source and a second input / output terminal connected to the first input / output terminal of the second conductivity type second transistor. With.

  According to the embodiment, the sense amplifier can be operated at high speed.

Further, the semiconductor memory device of the present invention is
A sense amplifier of the present invention;
A memory cell array in which a plurality of memory cells each having a first input / output terminal, a second input / output terminal, and a control terminal are aligned;
A word line connected to control terminals of the plurality of memory cells;
A bit line connected to at least one of the first input / output terminal and the second input / output terminal;
A first switching unit for connecting and separating the first sense node and the bit line;
A second switching unit that contacts and separates the second sense node and the bit line is provided.

  According to the present invention, since the current difference between the left and right of the memory cell can be compared, a read operation can be performed without using a reference voltage generation circuit or a reference cell. In addition, the read operation can be performed in a system in which 1-bit information is stored by switching the cell currents of the two memory cells.

Further, the semiconductor memory device of the present invention is
A sense amplifier of the present invention;
A memory cell array in which a plurality of memory cells each having a first input / output terminal, a second input / output terminal, and a control terminal are aligned;
A reference cell having a first input / output terminal, a second input / output terminal, and a control terminal, in which predetermined information is written;
A first bit line connected to at least one of the first input / output terminal of the memory cell and the second input / output terminal of the memory cell;
A second bit line connected to one of the first input / output terminal of the reference cell and the second input / output terminal of the reference cell or connected to an output terminal of a reference voltage generating circuit;
A first switching unit that contacts and separates the first sense node and the first bit line;
A second switching unit that contacts and separates the second sense node and the second bit line is provided.

  According to the present invention, the information written in the memory cell can be determined by comparing the cell current of the memory cell with the cell current of the reference cell.

  In one embodiment, the memory cell includes a sidewall memory.

  Here, the sidewall memory includes a source region, a drain region, a channel region formed between the source region and the drain region, a gate formed on the channel region, and both sides of the gate. It refers to a memory having a charge holding region provided on each wall.

  In the sidewall memory, by controlling the potentials of the source region, the drain region, and the gate, the charge holding states of the two charge holding regions are separately controlled, and information is stored in each.

  Since the memory cell including the sidewall memory has two charge holding regions, that is, two storage portions in one memory cell, the degree of integration of the semiconductor memory device can be effectively increased.

  An electronic apparatus according to the present invention includes the semiconductor memory device according to the present invention.

  Here, the electronic device refers to a portable information terminal such as a mobile phone, a liquid crystal display device, a DVD device, a video device, an audio device, a copying device, and the like.

  According to the present invention, since the semiconductor memory device according to the present invention that can determine information with high accuracy with a relatively simple configuration is provided, the reliability of the electronic device can be improved. Specifically, in a readout method based on voltage comparison with low power consumption, even if the readout voltage is large, the influence of noise during readout is reduced, and even if the amplification transistor is turned on, no sneak current is generated. Since a sense amplifier capable of correct reading and a semiconductor memory device using the sense amplifier are provided, an electronic device with low power consumption can be obtained.

  According to the sense amplifier of the present invention, the third transistor capable of connecting and disconnecting the second input / output terminal of the first transistor and the second sense node is provided, and the second input / output terminal of the second transistor is connected to the second transistor. Since the fourth transistor capable of connecting and disconnecting with the first sense node is provided, the influence of noise at the time of reading can be reduced even when the reading voltage is large. Even if the first and second transistors, which are amplifying transistors, are turned on, a correct read can be performed without generating a sneak current.

  Further, according to the sense amplifier of the present invention, the fifth transistor capable of connecting or separating the power supply or ground and the first input / output terminal of the first transistor, the power supply or ground, and the second transistor of the second conductivity type, And a sixth transistor that can be connected to and separated from each other, so that a voltage accumulated at an intermediate node between the first transistor and the fifth transistor and a voltage accumulated at an intermediate node between the first transistor and the third transistor A third voltage for driving the first and second transistors with a voltage accumulated at an intermediate node between the second transistor and the sixth transistor and a voltage accumulated at an intermediate node between the second transistor and the fourth transistor. To the threshold Vth of the sixth transistor. Therefore, the read operation margin can be improved.

  Further, according to the semiconductor memory device of the present invention, even when the read voltage is large, the influence of noise at the time of reading is reduced, and the amplification transistor is turned on in the read method by voltage comparison with low power consumption. Since a sense amplifier that can perform correct reading without causing a sneak current is provided, power consumption can be reduced as compared with the conventional case.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. This semiconductor memory device includes a memory cell array 100 in which a large number of nonvolatile memory cells MC0, MC1,. In the row direction of the memory cell array 100, a plurality of word lines WL0 to WLn extending in the row direction and connected to the control gates of the memory cells arranged in the same row are arranged in a state separated from each other in the column direction. ing. Further, in the column direction of the memory cell array 100, a plurality of bit lines BL0, BL1, BL2, BL3,... Extending in the column direction and connecting input / output terminals, ie, source / drains, of memory cells arranged in the same column. Are arranged in a state of being separated from each other in the row direction.

  The word lines WL0 to WLn are connected to a row decoder 102 that selects an arbitrary word line. The bit lines BL0, BL1, BL2, BL3,... Are sense amplifiers by a transistor group selected by output signals SEL0 to SEL4 from the bit line selection circuit 103 and a transistor group switched by signals CUT0 and CUT1. 104 is connected. Here, the transistor T1 switched by the signal CUT0 constitutes a first switching unit, and the transistor T2 switched by the signal CUT1 constitutes a second switching unit.

  The sense amplifier 104 includes a first sense node 1 and a second sense node 2, a gate terminal 11 as an example of a control terminal connected to the first sense node 1, and a first input / output terminal connected to a power supply 15. P-type first transistor P <b> 1 as a first conductivity type having 12, a gate terminal 21 as an example of a control terminal connected to the first sense node 1, and a first input / output terminal connected to the ground 25 22 and an N-type first transistor N1 as a second conductivity type.

  The sense amplifier 104 includes a P-type second transistor P 0 having a gate terminal 31 as an example of a control terminal connected to the second sense node 2 and a first input / output terminal 32 connected to the power supply 15. A gate terminal 41 as an example of a control terminal connected to the second sense node 2, and an N-type second transistor N 0 having a first input / output terminal 42 connected to the ground 25.

  The sense amplifier 104 includes a first input / output terminal 52 connected to the second sense node 2, and a second input / output terminal 53 connected to the second input / output terminal 13 of the P-type first transistor P1. The P-type third transistor P3 having the gate terminal 51, the first input / output terminal 62 connected to the second sense node 2, and the second input / output terminal 23 of the N-type first transistor N1. And an N-type third transistor N3 having a second input / output terminal 63 and a gate terminal 61.

  The sense amplifier 104 includes a first input / output terminal 72 connected to the first sense node 1 and a second input / output terminal 73 connected to the second input / output terminal 33 of the P-type second transistor P0. , A P-type fourth transistor P2 having a gate terminal 71, a first input / output terminal 82 connected to the first sense node 1, and a second input / output terminal 43 of the N-type second transistor N0. And an N-type fourth transistor N2 having a second input / output terminal 83 and a gate terminal 81.

  A signal SAP is externally input to the gate terminal 51 of the P-type third transistor P3 and the gate terminal 71 of the P-type fourth transistor P4. A signal SAN is input from the outside to the gate terminal 61 of the N-type third transistor N3 and the gate terminal 81 of the N-type fourth transistor N2.

  In the first embodiment, every four memory cells are connected to one set of sense amplifiers. However, the number of memory cells connected to one set of sense amplifiers is not limited to four. Absent. Note that the capacitance Cs at the two input ends of each sense amplifier indicates a parasitic capacitance at the input end of the sense amplifier that is separated from the bit line by CUT0 and CUT1.

  In the memory cell array of this semiconductor memory device, the connection method of the bit lines BL0, BL1, BL2, BL3,... Is a virtual ground method, and one of the four memory cells is operated under the operation of the bit line selection circuit 103. Are read at the same time. However, the bit line connection method may be a fixed ground method, any kind of bit line selection circuit may be used, and there may be no bit line selection circuit.

  FIG. 2 is a diagram for explaining the sidewall memory used as the memory in the first embodiment.

  FIG. 2 is a cross-sectional view of the sidewall memory 2000 used as a memory cell in the first embodiment.

  The sidewall memory 2000 includes a first silicon nitride film 2003 serving as a first storage region that functions as a charge holding region and a second silicon nitride film 2004 serving as a second storage region. The sidewall memory 2000 stores 1-bit information of data 0 and data 1 by writing information to either one of the first silicon nitride film 2003 and the second silicon nitride film 2004. A word line 2005 functioning as a gate electrode is formed on a substrate 2001 via a gate insulating film 2002, and first and second silicon nitride films are formed on both sides of the word line 2005 via a silicon oxide film 2006. 2003, 2004 are formed. The first and second silicon nitride films 2003 and 2004 are connected to the vertical portion extending substantially parallel to the side wall of the word line 2005 and the lower end of the vertical portion, and are substantially parallel to the surface of the substrate 2001 and away from the word line 2005. And a lateral portion extending to the side, and has a substantially L-shaped cross-sectional shape. On the far side of the first and second silicon nitride films 2003 and 2004 from the word line 2005, silicon oxide films 2007 and 2007 are provided. Thus, by sandwiching the first and second silicon nitride films 2003 and 2004 between the silicon oxide film 2006 and the silicon oxide film 2007, the charge injection efficiency during the rewrite operation is increased, and a high-speed operation is realized. Yes. Two diffusion regions are formed on the substrate 2001 adjacent to the first and second silicon nitride films 2003 and 2004. Specifically, the diffusion layer 2009 is formed so as to overlap a part of the lateral part of the first silicon nitride film 2003 and so as to overlap a part of the lateral part of the silicon nitride film included in the adjacent memory cell. . Further, a diffusion layer 2010 is formed so as to overlap a part of the lateral part of the second silicon nitride film 2004 and so as to overlap a part of the lateral part of the silicon nitride film included in the adjacent memory cell. The diffusion layer 2010 functions as the second bit line 2012. The diffusion layer 2009 and the second bit line 2012 function as a source region or a drain region, respectively. A channel region is defined between the diffusion layer 2009 functioning as the source region or the drain region and the second bit line 2012. The second bit line 2012 is connected to a wiring layer (not shown) formed above the memory cell, and the diffusion layer 2009 is connected to the first bit line 2011 formed above the memory cell 2000. The side wall memory has the same conductivity type as that of one of the diffusion layers 2009 on both sides of one of the two diffusion layers 2009 and 2010 in addition to the configuration of FIG. The structure shown in FIG. 17 in which the second diffusion layer 2013 is formed may be used.

  FIG. 3 is a diagram showing a cell current distribution for each state of the storage node (storage area) of the sidewall memory shown in FIG.

  In the example shown in FIG. 3, writing is performed on the silicon nitride film 2003 on the right side of the memory cell (electrons are injected), and the silicon nitride film 2004 on the left side is left in the erased state (state where electrons are extracted). Data 0 is written in the silicon nitride film 2004 on the left side of the memory cell (electrons are injected), and the state in which the silicon nitride film 2003 on the right side is in an erased state (state in which electrons are extracted) is defined as data 1. Of course, the reverse, that is, writing is performed on the silicon nitride film 2003 on the right side of the memory cell (electrons are injected), and the silicon nitride film 2004 on the left side is left in the erased state (state where electrons are extracted). Data 1 is defined as data 0 when data is written to the silicon nitride film 2004 on the left side of the memory cell (injecting electrons) and the silicon nitride film 2003 on the right side is left in an erased state (state in which electrons are extracted). It doesn't matter.

  The curve indicated by y1 in FIG. 3 indicates that in all the memory cells connected to one word line, a current is passed through each memory cell from the right side to the left side in the direction indicated by A in FIG. The distribution of data 1 when the current value (cell current value of right reading) is taken on the x-axis and the number of cells is taken on the y-axis. Further, the curve indicated by y2 in FIG. 3 indicates that in all the memory cells connected to one word line, a current was passed through each memory cell from the right side to the left side of each memory cell in the direction indicated by A in FIG. In this case, the distribution of data 0 when the current value (right-read cell current value) is taken on the x-axis and the number of cells is taken on the y-axis.

  As is apparent from these curves, the distribution of data 0 and data 1 may overlap. However, when attention is paid to one memory cell, a right-reading cell current value (marked with ●) that flows current from right to left as indicated by A in FIG. 3 and leftward in the direction opposite to the direction indicated by A in FIG. There is always a difference in the left-reading cell current value (marked with a circle) when current flows from right to left. Therefore, when the cell current is passed from the bit line connected to one input / output terminal of the selected memory cell to the bit line connected to the other input / output terminal, and vice versa. By comparing, data 0 and data 1 are determined.

  FIG. 4 is a timing chart for explaining the read operation of the semiconductor memory device according to the first embodiment. The signal names in FIG. 4 correspond to the signal names given to the signal lines in FIG.

  Here, a case where the memory cell MC0 connected to the word line WL0 is read will be described as an example.

  First, at time t1, the signal WL0 is raised to smoothly change the potential of the word line WL0 from GND to VWL. Subsequently, at time t2, the signal SEL0 and the signal CUT0 are raised. As a result, the bit line BL0 is connected to the left input terminal SAL of the sense amplifier 104. At time t3, the bit line charge / discharge circuit 101 sets the bit line BL0 to the high impedance (HiZ) of GND, and charges the bit line BL1 with VBL (for example, 1.2 V). At time t4, the signal SEL0 and the signal CUT0 are lowered. The bit line BL0 is disconnected, and the potential of the bit line BL0 at that time as an example of the first output is held in the parasitic capacitance Cs at the input terminal SAL (first sense node 1) on the left side of the sense amplifier 104. .

  Next, at time t5, the bit lines BL0 and BL1 are discharged to GND. Here, since the gate voltages of the amplifying transistors P1 and N1 of the sense amplifier rise due to charging, noise enters each drain via a parasitic capacitance between the gate and the drain. However, since the driving transistors P3 and N3 are off, noise does not get on the SAR (second sense node 2). In addition, since the driving transistors P2 and P3 are off regardless of whether the amplifying transistors P0 and P1 are on or off, there is no leakage from Vcc to SAL or SAR. Further, since the driving transistors N2 and N3 are off regardless of whether the amplifying transistors N0 and N1 are on or off, there is no leakage from SAL or SAR to GND. Of course, no sneak current occurs between SAL and SAR.

  Next, at time t6, the signal SEL1 and the signal CUT1 are raised. As a result, the bit line BL1 is connected to the input terminal SAR on the right side of the sense amplifier 104. At time t7, the bit line charging / discharging circuit 101 sets the bit line BL1 to the high impedance (HiZ) of GND and charges the bit line BL0 with VBL (for example, 1.2 V). At time t8, the signal SEL1 and the signal CUT1 fall. The bit line BL1 is disconnected, and the potential of the bit line BL1 at that time as an example of the second output is held in the parasitic capacitance Cs at the input terminal SAR on the right side of the sense amplifier 104. At time t9, the bit line BL0 and the bit line BL1 are discharged to GND. Here, since the gate voltages of the amplifying transistors P0 and N0 of the sense amplifier rise due to charging, noise enters each drain via a parasitic capacitance between the gate and the drain. However, since the driving transistors P2 and N2 are off, no noise is added to the SAL. In addition, since the driving transistors P2 and P3 are off regardless of whether the amplifying transistors P0 and P1 are on or off, there is no leakage from Vcc to SAL or SAR. Further, since the driving transistors N2 and N3 are off regardless of whether the amplifying transistors N0 and N1 are on or off, there is no leakage from SAL or SAR to GND. Of course, no sneak current occurs between SAL and SAR. In this way, the voltage (potential) input to each input terminal of the sense amplifier is determined. Thereafter, the signal SAP is lowered at time t10, the signal SAN is raised at time t11, and the sense amplifier is operated.

  Here, in the timing chart shown in FIG. 4, since the potential of SAL when the bit line BL0 is disconnected is higher than the potential of SAR when the bit line BL1 is disconnected, the sense amplifier output after amplification by SAP and SAN Is output as data 1 with SAL being High and SAR being Low. As described above, in the present invention, even if the read voltage is large, the influence of noise at the time of reading is reduced, and even if the amplification transistor is turned on, the driving transistor is turned off, so that a sneak current is generated. Thus, correct reading can be performed.

  In the semiconductor memory device of the first embodiment, the parasitic capacitance at the input end of the sense amplifier is used. However, it is possible to positively provide a capacitance equivalent element. It is preferable to increase the capacitance by providing a capacitance-corresponding element because it can increase the noise margin (noise resistance) against various noises that occur during the read time difference between the left and right directions (time t5 to time t9 in FIG. 4). .

  In the semiconductor memory device of the first embodiment, the sidewall memory whose cross-sectional structure is shown in FIG. 2 is used. However, the semiconductor memory device of the present invention has two storage nodes (storage layers and storage layers) at both ends of the channel region. The memory cell having any structure can be used as long as it has a memory cell. 5 to 9 are cross-sectional views showing the structure of a memory that can be used in the present invention. Hereinafter, several examples of memories that can be used in the semiconductor memory device of the present invention will be described with reference to FIGS.

  As shown in FIG. 5, the memory of the present invention is a first storage region in which an oxide film 1405 and a gate 1400 are sequentially stacked on a substrate 1406 and are substantially symmetrical on the oxide film 1405 and on both sides of the gate 1400. A first storage layer 1401 and a second storage layer 1402 which is a second storage region are stacked, and further, a first storage layer 1401 is overlapped between the substrate 1406 and the oxide film 1405 in the stacking direction. The first diffusion layer 1403 is formed, and the second diffusion layer 1404 is formed so as to overlap the second accumulation layer 1402 in the stacking direction and not intersect the first diffusion layer 1403. Also good.

  Further, as shown in FIG. 6, the memory of the present invention has an oxide film 1505 and a gate 1500 sequentially stacked on a substrate 1506, and a quadrant of a cross section that is symmetrical to two corners of the gate 1500 on the oxide film 1505 side. A first storage layer 1501 as a first storage region having a shape and a second storage layer 1502 as a second storage region having a quadrant in cross section are formed. Further, between the substrate 1506 and the oxide film 1505, The first diffusion layer 1503 is formed so as to overlap the first accumulation layer 1501 in the stacking direction, and the second diffusion layer 1502 is overlapped in the stacking direction so as not to intersect the first diffusion layer 1503. A structure in which the second diffusion layer 1504 is formed may be used.

  Further, as shown in FIG. 7, the memory according to the present invention includes an oxide film 1605 having a substantially concave cross section formed on a substrate 1606, a gate 1600 formed in a recess of the oxide film 1605, and a substrate. An oxide film 1607, a first storage layer 1608 as a first memory region, an oxide film 1609, and a gate 1610 are stacked on the oxide film 1605 on one side of the oxide film 1605, and on the other side of the oxide film 1605 on the substrate 1606. Are stacked with an oxide film 1611, a second storage layer 1612 which is a second memory region, an oxide film 1613, and a gate 1614, and a first storage layer 1608 in the stacking direction between the substrate 1606 and the oxide film 1607. A first diffusion layer 1617 is formed so as to overlap with the second accumulation layer 1612 in the stacking direction between the substrate 1606 and the oxide film 1611, and So as not to intersect the first diffusion layer 1617 may have a structure in which the second diffusion layer 1618 is formed.

  Further, as shown in FIG. 8, the memory included in the present invention has an oxide film 1705 formed on a substrate 1706 and the convex side of the convex cross section is in contact with the entire upper surface of the oxide film 1705. A gate 1700 is formed, and an oxide film 1708, a first storage layer 1709 as a first memory region, and an oxide film 1710 are sequentially formed on one side of the oxide film 1705 and between the substrate 1706 and the gate 1700. At the same time, an oxide film 1711, a second storage layer 1712 which is a second memory region, and an oxide film 1713 are sequentially formed on the other side of the oxide film 1705 and between the substrate 1706 and the gate 1700. A first diffusion layer 1715 is formed between the substrate 1706 and the oxide film 1711 so as to overlap the first accumulation layer 1709 in the stacking direction between the substrate 1706 and the film 1708. In, so as to overlap with the second storage layer 1712 in the stacking direction, and so as not to intersect with the first diffusion layer 1715 may have a structure in which the second diffusion layer 1716 is formed.

  In the memory of the present invention, as shown in FIG. 9, an oxide film 1806, a silicon nitride film 1807, an oxide film 1808, and a gate 1800 are formed in this order on a substrate 1805, and between the substrate 1805 and the oxide film 1806. In addition, a first diffusion layer 1803 is formed so as to overlap the silicon nitride film 1807 in the stacking direction, and overlaps the silicon nitride film 1807 in the stacking direction between the substrate 1805 and the oxide film 1806, and A structure in which the second diffusion layer 1804 is formed so as not to cross the diffusion layer 1803 may be employed. In the structure shown in FIG. 7, one side of the sandwich structure composed of the oxide film 1806, the silicon nitride film 1807, and the oxide film 1808 in the cross section is used as the first storage portion 1801 as the first storage region. The other side of the sandwich structure is used as a second storage unit 1802 as a second storage area.

  In the first embodiment, the first conductivity type is P type and the second conductivity type is N type. However, in the present invention, the first conductivity type is N type and the second conductivity type. The mold may be P-type. In this case, it goes without saying that the left and right outputs of the sense amplifier are reversed as compared with the first embodiment.

  In the first embodiment, the sense amplifier 104 has two P-type transistors and two N-type transistors as amplification transistors. However, in the present invention, the four N-type transistors in FIG. The type transistor may be omitted. In FIG. 1, four P-type transistors may be omitted. As a transistor that can be used in the sense amplifier of the present invention, for example, there are a MOS field effect transistor and a junction field effect transistor.

(Second Embodiment)
FIG. 10 is a diagram showing a semiconductor memory device according to the second embodiment of the present invention. The semiconductor memory device of the second embodiment is different from the semiconductor memory device of the first embodiment in that driving transistors P14, P15, N14, and N15 are provided in the sense amplifier 1004. Moreover, about the read-out operation | movement of 2nd Embodiment, the substantially same thing as 1st Embodiment can be used and the timing diagram shown in FIG. 4 can be used. In FIG. 10, the transistor T1 switched by the signal CUT0 constitutes a first switching unit, and the transistor T2 switched by the signal CUT1 constitutes a second switching unit.

  In the semiconductor memory device of the second embodiment, the same components as those of the semiconductor memory device of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the semiconductor memory device of the second embodiment, the description of the operation and effect common to the semiconductor memory device of the first embodiment will be omitted, and the configuration and operation different from those of the semiconductor memory device of the first embodiment. Only the effects and modifications will be described.

  As shown in FIG. 10, the sense amplifier 1004 included in the semiconductor memory device of the second embodiment includes a first sense node 1001, a second sense node 1002, and a control terminal connected to the first sense node 1001. A P-type first transistor P11 as a first conductivity type having a gate terminal 111 and an N-type first transistor as a second conductivity type having a gate terminal 121 as a control terminal connected to the first sense node 1001. N11.

  The sense amplifier 1004 includes a P-type second transistor P14 having a gate terminal 131 as an example of a control terminal connected to the second sense node 1002, and an example of a control terminal connected to the second sense node 1002. And an N-type second transistor N10 having a gate terminal 141.

  The sense amplifier 1004 includes a first input / output terminal 152 connected to the second sense node 1002 and a second input / output terminal 153 connected to the second input / output terminal 113 of the P-type first transistor P11. And a P-type third transistor P13 having a gate terminal 151, a first input / output terminal 162 connected to the second sense node 1001, and a second input / output terminal 123 of the N-type first transistor N11. And an N-type third transistor N13 having a second input / output terminal 163 and a gate terminal 161.

  The sense amplifier 1004 includes a first input / output terminal connected to the first sense node 1001, a second input / output terminal 173 connected to the second input / output terminal 133 of the P-type second transistor P10, A P-type fourth transistor P12 having a gate terminal 171; a first input / output terminal 182 connected to the first sense node 1001; and a second input / output terminal 143 of the N-type second transistor N10. An N-type fourth transistor N12 having a second input / output terminal 183 and a gate terminal 181 is included.

  The sense amplifier 1004 includes a first input / output terminal 192 connected to the power source 1006, a second input / output terminal 193 connected to the first input / output terminal 112 of the P-type first transistor P11, and a gate terminal. P-type fifth transistor P15 having 191; a first input / output terminal connected to the ground 1007; and a second input / output terminal 203 connected to the first input / output terminal 122 of the N-type first transistor N11. And an N-type fifth transistor N15 having a gate terminal 201.

  The sense amplifier 1004 includes a first input / output terminal 212 connected to the power source 1006, a second input / output terminal connected to the first input / output terminal 132 of the P-type second transistor P10, and a gate terminal 213. P-type sixth transistor P14 having 211, a first input / output terminal 222 connected to the ground 1007, and a second input / output terminal connected to the first input / output terminal 142 of the N-type second transistor N10. 223 and an N-type sixth transistor N14 having a gate terminal 221.

  In the first embodiment, since Vcc is precharged at the intermediate node between the amplifying transistors P10 and P11 and the driving transistors P12 and P13, the charge accumulated in the parasitic capacitance of the intermediate node is reduced. It is difficult to avoid the noise from flowing into the input terminals SAR and SAL during the sensing operation. However, in the second embodiment, since the driving transistors P14, P15, N14, and N15 are provided, the voltage of the intermediate node can be lowered from Vcc to about the threshold value VthP of the P-type transistor at the time of precharging. Noise can be reduced.

  FIG. 11 is a timing diagram illustrating a precharge operation of the semiconductor memory device according to the second embodiment. Here, the signal names in FIG. 11 correspond to the signal names given to the signal lines in FIG.

  First, SAP0 is caused to fall at time t1. Here, since the amplifying transistors P10 and P11 are on, the two nodes of the driving transistors P12 and P14 and the amplifying transistor P10 are charged to Vcc, and P13 and P15 and the amplifying transistor are charged. Two nodes with P11 are charged to Vcc. Thus, the voltage of the previous read cycle is reset. Thereafter, SAP0 is raised at time t2, and the driving transistors P14 and P15 are turned off. Subsequently, at time t3, SAP1 is lowered and SAN0 and SAN1 are raised. As a result, two nodes of the driving transistors N12 and N14 and the amplifying transistor N10 are discharged to GND, and two nodes of the driving transistors N13 and N15 and the amplifying transistor N11 are discharged to GND. Is done. On the other hand, the two nodes of the driving transistors P12 and P14 and the amplifying transistor P10 and the two nodes of P13 and P15 and the amplifying transistor P11 are discharged to VthP because SAL and SAR are GND. . In this way, since the voltage at the intermediate node can be lowered to about VthP, noise can be reduced.

  In the first embodiment and the second embodiment, the bit lines BL0 and BL1 of one read memory cell are connected to the input terminals SAL and SAR of the sense amplifier, but one of them is connected to the bit line of the reference cell. Alternatively, it may be connected to a bit line of another read memory cell and compared.

  In the first embodiment and the second embodiment described above, the memory cell has been described using a sidewall memory having two storage nodes in one cell. Any memory cell that stores information is not particularly limited.

(Third embodiment)
In the first embodiment, a memory cell having two storage nodes in one cell is used. However, a general non-volatile memory or mask ROM having one storage node can also be used. FIG. 12 is a diagram illustrating a semiconductor memory device according to the third embodiment, and FIG. 13 is a timing diagram illustrating a read operation of the semiconductor memory device according to the third embodiment. In FIG. 12, 224 indicates a first bit line and 333 indicates a second bit line. In FIG. 12, the transistor T1 switched by the signal CUT0 constitutes a first switching unit, and the transistor T2 switched by the signal CUT1 constitutes a second switching unit. In the third embodiment, a flash memory having a floating gate below the word line as a storage node is used as the memory.

  In the semiconductor memory device of the third embodiment, the memory cell information is determined by comparing the current flowing through the reference cell RC of the reference cell array 1301 with one of the memory cells MC0, MC1,. It is like that. The semiconductor memory device of the fourth embodiment operates in the same manner as in the first embodiment except that the signal SEL0 to SEL4 of the bit line selection circuit is not used for selection of the reference cell.

  In the third embodiment, since the signals SEL0 to SEL4 of the bit line selection circuit are not used for the selection of the reference cell, the reading from the memory cell MC0 and the reading from the reference cell RC can be performed at the same time. Since signals can be input simultaneously to two terminals, for example, as shown in FIG. 13, CUT0 and CUT1 can be started up simultaneously. Therefore, the timing can be remarkably shortened compared with the first embodiment.

(Fourth embodiment)
FIG. 14 is a diagram illustrating a semiconductor memory device according to the fourth embodiment. The semiconductor memory device of the fourth embodiment is obtained by replacing the sense amplifier 104 in the semiconductor memory device of the third embodiment with the sense amplifier 1004 used in the second embodiment. In FIG. 14, 444 indicates a first bit line and 555 indicates a second bit line. In FIG. 14, the transistor T1 switched by the signal CUT0 constitutes a first switching unit, and the transistor T2 switched by the signal CUT1 constitutes a second switching unit.

  As the timing diagram, a timing diagram substantially similar to that of the third embodiment can be used. Specifically, the SAP of FIG. 13 is used as SAP0 and SAP1 of FIG. 14, the SAN of FIG. 13 is used for SAN0 and SAN1 of FIG. 14, and other signals (such as WL0) are shown in FIG. A timing diagram that is identical to that shown can be used. In addition, the precharge timing shown in FIG. 11 is used.

  In the third and fourth embodiments, the embodiment in which the memory cell and the reference cell are compared has been described. However, two memory cells may be compared. In addition, all of the above embodiments have a virtual ground type array configuration, but it goes without saying that a fixed ground type array configuration may be used.

  FIG. 15 is a block diagram showing a digital camera which is an embodiment of the electronic apparatus of the present invention. In FIG. 15, reference numeral 317 denotes an optical system driving unit.

  This digital camera includes nonvolatile memories 308 and 319 which are semiconductor memory devices of the present invention. The nonvolatile memory 308 is used for storing captured images, and the nonvolatile memory 319 is used for storing variation correction values for the liquid crystal panel 322.

  In this digital camera, when the power switch 301 is turned on by the operator, the power supplied from the battery 302 is transformed to a predetermined voltage by the DC / DC converter 303 and supplied to each component. Light entering from the lens 316 is converted into current by the CCD 318, converted into a digital signal by the A / D converter 320, and input to the data buffer 311 of the video processing unit 310. The signal input to the data buffer 311 is processed by the MPEG processing unit 313 to become a video signal through the video encoder 314, and is displayed on the liquid crystal panel 322 through the liquid crystal driver 321. At this time, the liquid crystal driver 321 corrects variations in the liquid crystal panel 322 (for example, variations in hues that differ for each liquid crystal panel) using data in the built-in nonvolatile memory 319. When the shutter 304 is pressed by the operator, the information in the data buffer 311 is processed as a still image via the JPEG processing unit 312 and recorded in the flash memory 308 which is a nonvolatile memory. In the flash memory 308, system programs and the like are recorded in addition to photographed image information. The DRAM 307 is used for temporary storage of data generated in various processes of the CPU 306 and the video processing unit 310.

  Here, since the nonvolatile memories 308 and 319 can accurately read out information of the memory cell using a reading method based on voltage comparison with low power consumption, an electronic device including the semiconductor memory device of the present invention has low power consumption. Power consumption can be achieved.

  In the above embodiment, the semiconductor memory device of the present invention is mounted on a digital camera. However, the semiconductor memory device of the present invention is preferably mounted on a mobile phone. A flash memory used in a cellular phone records a communication protocol in addition to image data, and therefore requires high reliability. Therefore, when the semiconductor memory device of the present invention is mounted on a mobile phone, the quality of the mobile phone can be remarkably improved. The semiconductor memory device of the present invention is applied to electronic devices other than digital cameras and mobile phones, such as digital audio recorders, DVD devices, color tone adjustment circuits for liquid crystal display devices, music recording / playback devices, video devices, audio devices, copying devices, etc. Needless to say, it may be installed.

1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. It is a figure for demonstrating the sidewall memory used as a memory in 1st Embodiment. FIG. 3 is a diagram showing a cell current distribution for each state of a storage node (storage area) of the sidewall memory shown in FIG. 2. FIG. 4 is a timing diagram illustrating a read operation of the semiconductor memory device according to the first embodiment. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is a figure which shows the semiconductor memory device of 2nd Embodiment of this invention. FIG. 10 is a timing diagram illustrating a precharge operation of the semiconductor memory device of the second embodiment. It is a figure which shows the semiconductor memory device of 3rd Embodiment. FIG. 10 is a timing diagram illustrating a read operation of the semiconductor memory device according to the third embodiment. It is a figure which shows the semiconductor memory device of 4th Embodiment. It is a block diagram which shows the digital camera which is one Embodiment of the electronic device of this invention. It is a circuit diagram which shows an example of the conventional sense amplifier. It is sectional drawing which shows the structure of the memory which can be used by this invention.

Explanation of symbols

100, 1300 Memory cell array 101 Bit line charge / discharge circuit 102 Row decoder 103 Bit line selection circuit 104, 1004 Sense amplifier 300 Digital camera 301 Power switch 302 Battery 303 DC / DC converter 304 Shutter 306 CPU
307 DRAM
308 Flash memory 310 Video processing unit 311 Data buffer 312 JPEG processing unit 313 MPEG processing unit 314 Video encoder 316 Lens 317 Optical system driving unit 318 CCD
319 Nonvolatile memory 320 A / D converter 321 Liquid crystal driver 322 Liquid crystal panel 1301 Reference cell array 2000 Side wall memory

Claims (8)

A first sense node and a second sense node;
A first conductivity type first transistor having a control terminal connected to the first sense node and a first input / output terminal connected to a power supply or a ground;
A second transistor of the first conductivity type having a control terminal connected to the second sense node and a first input / output terminal connected to the power supply or ground;
A first conductivity type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to a second input / output terminal of the first transistor of the first conductivity type. A transistor,
A first conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second transistor of the first conductivity type. A sense amplifier comprising a transistor. The sense amplifier according to claim 1.
A first transistor of a second conductivity type having a control terminal connected to the first sense node and a first input / output terminal connected to the ground or the power source;
A second conductivity type second transistor having a control terminal connected to the second sense node and a first input / output terminal connected to the ground or the power source;
A second conductive type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to the second input / output terminal of the second conductive type first transistor. A transistor,
A second conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second conductivity type second transistor. A sense amplifier comprising a transistor. A first sense node and a second sense node;
A first conductivity type first transistor having a control terminal connected to the first sense node;
A second transistor of the first conductivity type having a control terminal connected to the second sense node;
A first conductivity type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to a second input / output terminal of the first transistor of the first conductivity type. A transistor,
A first conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second transistor of the first conductivity type. A transistor,
A first conductivity type fifth transistor having a first input / output terminal connected to a power supply or a ground and a second input / output terminal connected to the first input / output terminal of the first conductivity type first transistor; ,
A first conductivity type sixth transistor having a first input / output terminal connected to a power supply or ground and a second input / output terminal connected to the first input / output terminal of the first conductivity type second transistor; A sense amplifier comprising: The sense amplifier according to claim 3,
A first transistor of a second conductivity type having a control terminal connected to the first sense node;
A second transistor of a second conductivity type having a control terminal connected to the second sense node;
A second conductive type third having a first input / output terminal connected to the second sense node and a second input / output terminal connected to the second input / output terminal of the second conductive type first transistor. A transistor,
A second conductivity type fourth having a first input / output terminal connected to the first sense node and a second input / output terminal connected to a second input / output terminal of the second conductivity type second transistor. A transistor,
A second conductivity type fifth transistor having a first input / output terminal connected to the ground or the power source and a second input / output terminal connected to the first input / output terminal of the second conductivity type first transistor. When,
A second conductivity type sixth transistor having a first input / output terminal connected to the ground or the power source and a second input / output terminal connected to the first input / output terminal of the second conductivity type second transistor. And a sense amplifier. A sense amplifier according to any one of claims 1 to 4,
A memory cell array in which a plurality of memory cells each having a first input / output terminal, a second input / output terminal, and a control terminal are aligned;
A word line connected to control terminals of the plurality of memory cells;
A bit line connected to at least one of the first input / output terminal and the second input / output terminal;
A first switching unit for connecting and separating the first sense node and the bit line;
A semiconductor memory device, comprising: a second switching unit that contacts and separates the second sense node and the bit line. A sense amplifier according to any one of claims 1 to 4,
A memory cell array in which a plurality of memory cells each having a first input / output terminal, a second input / output terminal, and a control terminal are aligned;
A reference cell having a first input / output terminal, a second input / output terminal, and a control terminal, in which predetermined information is written;
A first bit line connected to at least one of the first input / output terminal of the memory cell and the second input / output terminal of the memory cell;
A second bit line connected to one of the first input / output terminal of the reference cell and the second input / output terminal of the reference cell or connected to an output terminal of a reference voltage generating circuit;
A first switching unit that contacts and separates the first sense node and the first bit line;
A semiconductor memory device, comprising: a second switching unit that contacts and separates the second sense node and the second bit line. The semiconductor memory device according to claim 5 or 6,
The memory cell includes a sidewall memory.   An electronic apparatus comprising the semiconductor memory device according to claim 5.

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