JP2009277273A - Semiconductor storage and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor storage capable of speedily and precisely determining the information of a memory cell with low power consumption while avoiding read disturbance even in the memory cell where a voltage applicable between input and output terminals is restricted. <P>SOLUTION: The semiconductor storage has, a memory array 100 having memory cells M11-Mnm, a bit line charge and discharge circuit 102, a bit line selection circuit 103, and a load circuit 105 connected between a data line DL connected to the bit line selection circuit 103 and a sense amplifier 104. The load circuit 105 has a series resistor RL and a parallel capacitor CL connected to the data line DL in series. By the load circuit 105, a sufficient read margin can be secured while a voltage applied between the input and output terminals of the memory cell is kept low to prevent the read disturbance from occurring, thus enabling fast read with low power consumption. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device and an electronic device, and more specifically, for example, formed on a flash memory, RRAM (Resisitance Random Access Memory) or a glass substrate for storing data depending on the magnitude of the cell current flowing in the memory cell. The present invention relates to a semiconductor memory device including a memory cell such as a nonvolatile memory.

  In recent years, flash memory has been widely used as a semiconductor storage device for data storage or code (program) storage such as mobile phones and digital cameras. In the future, new memories such as RRAM (registered trademark) and glass substrate memory will be used. Will also be applied. In addition, in order to increase the storage capacity per unit area and lower the bit unit price, the storage system is rapidly changing from binary to multivalued.

  In such a semiconductor memory device, information is determined using a change in a memory cell current in accordance with a memory state. However, the semiconductor memory device is structurally stored in the memory cell with a voltage applied to the memory cell at the time of reading. There is a lead disturb that information is gradually lost. For this reason, it is not possible to apply a very high voltage between the input / output terminals of the memory cell. As a result, it is necessary to reduce the read margin without taking a large memory cell current, or to reduce the read speed. There is a problem that arises.

  As a typical technique in the conventional read operation, a nonvolatile semiconductor memory device adopting a technique in which a data line from a memory cell is biased and converted into a voltage and compared with a reference voltage by a sense amplifier is disclosed in Patent Document 1 JP-A-6-223587).

However, in the conventional semiconductor memory device described in Patent Document 1, the charge voltage cannot be increased in order to avoid read disturb. As a result, since the memory cell current cannot be increased, there is a problem that the read margin is reduced and the read speed is decreased.
Japanese Patent Laid-Open No. 6-223587

  Accordingly, an object of the present invention is to provide a semiconductor capable of determining memory cell information with low power consumption, high speed and high accuracy while avoiding read disturb even in a memory cell in which a voltage that can be applied between input and output terminals is limited. To provide a storage device.

In order to solve the above problems, a semiconductor memory device of the present invention includes a memory cell that stores information with a magnitude of a current flowing between an input terminal and an output terminal;
A bit line to which one of the input terminal or output terminal of the memory cell is connected;
A bit line charge / discharge circuit for charging / discharging the bit line;
A bit line selection circuit for selecting the bit line;
A sense amplifier in which data output from the bit line selection circuit is input through a data line;
A load circuit connected between the data line and the sense amplifier and including at least one of a resistance component between the data line and the sense amplifier and a capacitance component between the data line and the ground It is characterized by comprising.

  According to the semiconductor memory device of the present invention, the resistance component and the capacitance component included in the load circuit are sufficient to suppress a voltage applied between the input and output terminals of the memory cell so that read disturbance does not occur. A read margin can be secured, and high-speed reading can be performed with low power consumption. In particular, when the parasitic resistance of the data line is large, a sufficient effect can be obtained with a load circuit including only the capacitance component of the resistance component and the capacitance component.

  In one embodiment, the load circuit includes a capacitive element as a capacitive component between the data line and the ground.

  According to the semiconductor memory device of this embodiment, a sufficient read margin is ensured while the voltage applied between the input and output terminals of the memory cell is kept low so that read disturb does not occur due to the capacitive element included in the load circuit. Thus, high-speed reading is possible with low power consumption.

  In one embodiment, the load circuit includes a resistance element or a transistor as a resistance component between the data line and the sense amplifier.

  According to the semiconductor memory device of this embodiment, with the resistance element or transistor as a resistance component included in the load circuit, the voltage applied between the input and output terminals of the memory cell is kept low so that read disturbance does not occur. A sufficient read margin can be ensured, and high-speed reading can be performed with low power consumption. In particular, when the parasitic capacitance of the data line is large, a sufficient effect can be obtained by inserting only a resistance element or a transistor as a resistance component in series. On the other hand, particularly when the parasitic capacitance and parasitic resistance of the data line are small, a sufficient effect can be obtained by a load circuit including both the resistor element (or transistor) and the capacitor element.

  In one embodiment, the semiconductor memory device includes a read operation control unit that sets the potential of the data line to be lower than the potential of the bit line before the read operation.

  According to the semiconductor memory device of this embodiment, when the parasitic capacitance of the data line is larger than the capacitance of the bit line or common line in the memory cell array, charging before the read operation can be performed at high speed, and power consumption can be reduced. Less.

  In one embodiment, the semiconductor memory device includes a read operation control unit that sets the potential of the data line higher than the potential of the bit line before the read operation.

  According to the semiconductor memory device of this embodiment, when the parasitic capacitance of the data line is smaller than the capacitance of the bit line or common line in the memory cell array, charging before the read operation can be performed at high speed and power consumption is reduced. Less.

  In one embodiment, the memory cell includes an RRAM.

  According to the semiconductor memory device of this embodiment, it is possible to perform high-speed reading by securing a sufficient read margin while suppressing the voltage applied between the input and output terminals to the memory cell including the RRAM. Since the RRAM has only two terminals to which a voltage can be applied, the difference between the write operation or erase operation and the read operation is not only the difference in voltage applied between the input and output terminals of the memory cell, but also the read disturb. However, in this embodiment, read disturb can be avoided.

  In one embodiment, the memory cell includes a nonvolatile memory having a charge storage layer.

  According to the semiconductor memory device of this embodiment, a sufficient read margin can be secured and high-speed reading can be performed only by flowing a current necessary for charging / discharging for a certain period of time with respect to the memory cell including the nonvolatile memory. . In the non-volatile memory having the charge storage layer, read disturb is likely to occur due to electron injection into the storage layer when a current flows for a long time, but in this embodiment, read disturb can be avoided.

  In one embodiment, the memory cell includes a nonvolatile memory formed on a glass substrate.

  According to the semiconductor memory device of this embodiment, for a memory cell including a nonvolatile memory formed on the glass substrate, a sufficient read margin is ensured while suppressing a voltage applied between the input and output terminals at a low speed. Reading is possible. In the nonvolatile memory formed on the glass substrate, punch-through occurs when a large voltage is applied between the input and output terminals, and the current cannot be controlled by the gate voltage. Thus, a sufficient read margin can be ensured while keeping the voltage applied to low, and high-speed reading can be performed.

  An electronic apparatus according to an embodiment includes the semiconductor memory device.

  According to the electronic device of this embodiment, a sufficient read margin is ensured while keeping the voltage applied between the input and output terminals of the memory cell low so as not to cause read disturb related to the reliability of data retention. Since high-speed reading is possible with low power consumption, a highly reliable electronic device with high speed and low power consumption can be obtained.

  According to the semiconductor memory device of the present invention, since a load circuit composed of a capacitance component and a resistance component of an appropriate value is connected to the data line or the sense amplifier input terminal, read disturb becomes a problem. Even for a memory cell in which a voltage that can be applied between input terminals is limited, the information of the memory cell can be determined with high accuracy, low power consumption, and high speed.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 shows a semiconductor memory device according to the first embodiment of the present invention. This semiconductor memory device includes a memory cell array 100 in which a plurality of memory cells M11, M12,..., Mnm are arranged in a matrix. In the row direction of the memory cell array 100, a plurality of word lines WL1 to WLn connected to the control gates of the memory cells arranged in the same row extend. The memory cells M11 to Mnm are RRAM.

  Further, in the column direction of the memory cell array 100, a plurality of bit lines BL1 to BLm are connected to connect one ends of input / output terminals of memory cells arranged in the same column. The word lines WL1 to WLm are connected to a row decoder 101 that selects an arbitrary word line.

  The bit lines BL1 to BLm are connected to the common line CML by a transistor group including transistors Q1 to Qm selected by signals PRE1 to PREm of the bit line charge / discharge circuit 102. The bit lines BL1 to BLm are connected to the input terminal of the load circuit 105 via the data line DL by a transistor group including transistors Q11 to Q1m selected by the signals SEL1 to SELm of the bit line selection circuit 103. . The common line CML is commonly connected to one end of the input / output terminals of the cell transistor groups T11 to Tnm for selecting the memory cells M11 to Mnm. The common line CML is connected to a power supply (not shown) that supplies a charging voltage VPRE via a transistor Q0 whose signal RON is input to the gate.

  On the other hand, the output terminal of the load circuit 105 is connected to a node SIN connected to one input terminal of the sense amplifier 104. The other input terminal of the sense amplifier 104 is connected to a power supply (not shown) that supplies a reference voltage VREF for comparison. The output of the sense amplifier 104 becomes read data DATA. A transistor QS is connected between the node SIN and the ground. A signal RON is input to the gate of the transistor QS. This signal RON is output from the control signal generation circuit 107. The transistor QS and the control signal generation circuit 107 constitute a read operation control unit.

  Here, the load circuit 105 is configured by the series resistor RL and the parallel capacitor CL. However, the load circuit may be configured by only one of the series resistor RL and the parallel capacitor CL. In particular, when the parasitic capacitance and parasitic resistance of the data line DL are small, a sufficient effect can be obtained by configuring the load circuit 105 with both the series resistor RL and the parallel capacitor CL. On the other hand, when the parasitic resistance of the data line DL is large, a sufficient effect can be obtained by configuring the load circuit 105 with only the parallel capacitor CL. On the other hand, when the parasitic capacitance of the data line DL is large, a sufficient effect can be obtained by configuring the load circuit 105 with only the series resistor RL. Further, the series resistor RL and the parallel capacitor CL may be constituted by transistors.

  FIG. 2 is a timing chart for explaining the read operation of the semiconductor memory device of this embodiment. The “WL1” column in FIG. 2 shows the signal waveform on the word line WL1 in FIG. 1, the “RON” column in FIG. 2 shows the signal waveform of the signal RON in FIG. 1, and the “PRE1” column in FIG. Indicates the signal waveform of the signal PRE1 in FIG. 2 shows the signal waveforms of the signals PRE2 to PREm in FIG. 1, and the “SEL1” column in FIG. 2 shows the signal waveform of the signal SEL1 in FIG.

  Here, a case where the memory cell M11 connected to the word line WL1 is read will be described with reference to FIG.

  First, before the time t1, since the signal RON has risen, the node SIN is discharged and becomes 0V. Next, at time t1, the word line WL1 is raised and simultaneously the signal RON and the signals PRE1 to PREm are lowered to charge the common line CML and all the bit lines BL1 to BLm to the charging voltage VPRE. Subsequently, at time t2, the signal SEL1 and the signal PRE1 are raised, and the node SIN is charged through the data line DL and the load circuit 105. At this time, in the bit line charge / discharge circuit 102, the transistor Q1 having the gate supplied with the signal PRE1 is turned off. At this time, in the bit line selection circuit 103, only the transistor Q11 whose gate is inputted with the signal SEL1 is turned on. Therefore, charging of the node SIN is performed only through the memory cell M11. After an appropriate time from time t2, the sense amplifier 104 is operated to compare the voltage of the node SIN and the reference voltage VREF, thereby outputting the data DATA of the memory cell M11.

  Next, FIG. 3 shows a voltage applied to one of the memory cells M11 to Mnm, which is the RRAM, by a characteristic curve 300. In FIG. 3, the read voltage when one of the memory cells M11 to Mnm as the RRAM has a high resistance and one memory cell among the memory cells M11 to Mnm as the RRAM are low. A characteristic curve 301 shows the time change of the potential difference from the read voltage when it is a resistor. The potential difference corresponds to the potential difference of the node SIN.

  In the characteristics shown in FIG. 3, the charging voltage VPRE = 3 V, the capacitance of the bit line BL1 is 1 pF, the series resistance RL of the load circuit 105 is 100Ω, and the parallel capacitance CL is 0.14 pF. Further, the resistance value in the low resistance state varies among the memory cells M11 to Mnm, and the resistance value in the high resistance state varies among the memory cells M11 to Mnm. For this reason, the maximum resistance value of the memory cells M11 to Mnm at low resistance is assumed to be 10 kΩ, the minimum resistance value of the memory cells M11 to Mnm at high resistance is assumed to be 50 kΩ, and the memory cells M11 to Mnm The maximum resistance value at high resistance was assumed to be 200 kΩ.

  In the characteristic diagram of FIG. 3, the voltage applied to both ends of the memory cell in the high resistance state having the maximum resistance value of 200 kΩ at the time of reading is shown by a characteristic curve 300. As indicated by the characteristic curve 300, the voltage applied to both ends of the memory cell having the maximum resistance value remains at 0.5V at the maximum. This is because the voltage applied to both ends of the memory cell is suppressed by the load circuit 105 to a much lower value than the charging voltage VPRE = 3V.

  On the other hand, as shown by the characteristic curve 301 in FIG. 3, the voltage of the node SIN when reading the memory cell having the maximum resistance value of 10 kΩ at the low resistance and the memory cell having the minimum resistance value of 50 kΩ at the high resistance. The difference from the voltage of the node SIN when reading out, that is, the read margin, is about 0.20 V at the read time of 15 ns with the time (t2) in FIG. 2 as the reference (0 ns).

(First comparative example)
Next, FIG. 4 shows a first comparative example as a comparative example with respect to the first embodiment of FIG. The first comparative example differs from the first embodiment only in that the bias circuit 400 in FIG. 4 is provided instead of the load circuit 105 in FIG. 1 and the transistor QS is not provided. Differences from the first embodiment will be described. The bias circuit 400 included in the first comparative example includes a transistor Tr400 that receives a signal VBIAS at its gate.

  In the first comparative example shown in FIG. 4, the bias circuit 400 determines the voltage of the node SIN. In this first comparative example, when the signal VBIAS is set such that the on-resistance value of the transistor Tr400 is 30 kΩ, the voltage applied to both ends of the high resistance state memory cell having the maximum resistance value of 200 kΩ is shown in FIG. A characteristic curve 500 is shown in the characteristic diagram. In the characteristic diagram of FIG. 5, the setting conditions except that the charging voltage VPRE is set to a low value of 0.58 V so that the characteristic curve 500 does not exceed 0.5 V are the same as those in the characteristic diagram of FIG. The setting conditions were the same as the setting conditions. The on-resistance value 30 kΩ of the transistor Tr400 is intermediate between the maximum resistance value 10 kΩ when the memory cells M11 to Mnm are low resistance and the minimum resistance value 50 kΩ when the memory cells M11 to Mnm are high resistance. Resistance value.

  Then, as shown by the characteristic curve 501 in FIG. 5, the voltage of the node SIN when reading the memory cell having the maximum resistance value of 10 kΩ at the low resistance and the memory cell having the minimum resistance value of 50 kΩ at the high resistance. The difference from the voltage of the node SIN when reading is read, that is, the read margin is only 0.06 V at the read time of 15 ns, and is 0.188 V even after 150 ns.

  As can be seen by comparing the characteristic curve 501 in the first comparative example and the characteristic curve 301 in the first embodiment, the load circuit 105 is connected to the input terminal of the data line DL or the sense amplifier 104 in the first embodiment. It can be seen that the read margin and the read speed can be greatly improved by connecting.

  Further, in the first comparative example of FIG. 4, since the current continues to flow through the bias circuit 400, the average current up to the read time of 150 ns is 13.4 μA, whereas in the first embodiment of FIG. Since it is a charging method by 105, only a current necessary for charging the load capacitor CL flows, and the average current until the read time of 150 ns is 2.8 μA. Therefore, in the said 1st Embodiment, it turns out that reduction in power consumption can be promoted markedly.

  As described above, according to the first embodiment, the load circuit 105 secures a sufficient read margin while keeping the voltage applied between the input and output terminals of the memory cell low so that read disturb does not occur. Thus, high-speed reading is possible with low power consumption.

  In the bias circuit 400 of the first comparative example shown in FIG. 4, one end of the transistor Tr400 is connected to GND (ground). However, in the second comparative example shown in FIG. 600. One end of the transistor Tr600 of the bias circuit 600 may be connected to a power source such as a charging voltage VPRE. The second comparative example has an N-type transistor Z0 instead of the P-type transistor Q0 of the first embodiment, and one end of the N-type transistor Z0 is connected to GND. Further, this second comparative example has a bit line charge / discharge circuit 602 instead of the bit line charge / discharge circuit 102, and this bit line charge / discharge circuit 602 is constituted by a transistor group including N-type transistors Z1 to Zm. Yes. Further, the second comparative example has a bit line selection circuit 603 instead of the bit line selection circuit 103, and the bit line selection circuit 603 is constituted by a transistor group including P-type transistors Z11 to Z1m. In the second comparative example, a signal RON # obtained by inverting the signal RON of the first comparative example is input to the gate of the N-type transistor Z0, and the first comparative example is input to the gates of the N-type transistors Z1 to Zm. The signals PRE1 # to PREm # obtained by inverting the signals PRE1 to PREm of the first comparative example are input, and the signals SEL1 # to SELm # obtained by inverting the signals SEL1 to SELm of the first comparative example to the gates of the P-type transistors P11 to Z1m. Was entered. In the first and second comparative examples, the transistors are used as the bias circuits 400 and 600. However, other than the transistors, load elements corresponding to resistors may be used.

(Second embodiment)
Next, FIG. 7 shows a semiconductor memory device according to the second embodiment of the present invention. The second embodiment differs from the first embodiment only in that a memory cell array 700 is provided instead of the memory cell array 100 provided in the first embodiment of FIG. That is, the memory cell array 700 provided in the second embodiment includes memory cells M11 to Mnm made up of a plurality of RRAMs constituting the memory cell array 100 provided in the first embodiment described above, and memory cells F11 to Fm made up of a general flash memory. It is replaced with Fnm. The storage portion of the memory cells F11 to Fnm may be a floating gate type or a nitride film type.

  The second embodiment including the memory cell array 700 can perform the same operation as that described in the first embodiment, and significantly improves the read margin and the read speed as in the first embodiment. In addition, it is possible to achieve the effect of significantly promoting the reduction of power consumption.

(Third embodiment)
Next, FIG. 8 shows a semiconductor memory device according to a third embodiment of the present invention. The third embodiment differs from the first embodiment only in that a memory cell array 800 is provided instead of the memory cell array 100 provided in the first embodiment of FIG. That is, in the memory cell array 800 provided in the third embodiment, the memory cells M11 to Mnm composed of a plurality of RRAMs constituting the memory cell array 100 of FIG. 1 are replaced with nonvolatile memories G11 to Gnm formed on a glass substrate. Is.

  The third embodiment including the memory cell array 800 can perform the same operation as that described in the first embodiment, and significantly improves the read margin and the read speed as in the first embodiment. In addition, it is possible to achieve the effect of significantly promoting the reduction of power consumption.

  Incidentally, since the RRAM constituting the memory cell array 100 of the first embodiment has only two terminals to which a voltage can be applied, the difference between the write operation or erase operation and the read operation is that the memory cells M11 to M11 It is only the difference in voltage applied between the input and output terminals of Mnm. That is, since the RRAM is structurally susceptible to read disturb, the present invention is very effective.

  On the other hand, when the memory cell array 700 of the second embodiment includes the memory cells F11 to Fnm made of a nonvolatile memory having a charge storage layer, if a current flows through the memory cell for a long time, the memory cell array 700 is caused by electron injection into the storage layer. Read disturb occurs. Here, since the DC bias can be made in the conventional bias method, the current continues to flow through the memory cell for a long time, whereas in the charge / discharge method of the present invention, the current for charging / discharging the node SIN is as described above. Since it only flows for a certain period of time, read disturb is unlikely to occur.

  Further, when the memory cells G11 to Gnm are nonvolatile memories formed on a glass substrate as in the third embodiment, punch-through occurs when a large voltage is applied between the input and output terminals of the memory cells. Although the current cannot be controlled by the gate voltage, in this embodiment, it is possible to perform high-speed reading by securing a sufficient reading margin while keeping the voltage applied between the input and output terminals of the memory cell low.

(Fourth embodiment)
Next, FIG. 9 shows a semiconductor memory device according to the fourth embodiment of the present invention. The fourth embodiment employs a discharging method from the node SIN, unlike the first embodiment that employs a charging method to the node SIN. That is, the fourth embodiment differs from the first embodiment described above in the following points (1) to (3).

  (1) A bit line charge / discharge circuit 802 and a bit line selection circuit 803 are provided in place of the bit line charge / discharge circuit 102 and the bit line selection circuit 103 of the first embodiment.

  (2) Instead of the P-type transistor Q0 and N-type transistor QS of the first embodiment, an N-type transistor Z0 having one end connected to GND and a P-type transistor ZS having one end connected to the power source of the charging voltage VREF Points to prepare.

  (3) A control signal generation circuit 807 is provided instead of the control signal generation circuit 107, and this control signal generation circuit 807 inputs a signal RON # obtained by inverting the signal RON to the N-type transistor Z0 and the P-type transistor ZS.

  The bit line charge / discharge circuit 802 provided in the fourth embodiment has a transistor group including N-type transistors Z1 to Zm, and the signal PRE1 in the first embodiment is connected to the gates of the N-type transistors Z1 to Zm. Signals PRE1 # to PREm # obtained by inverting ~ PREm are input. The bit line selection circuit 803 provided in the fourth embodiment has a transistor group including P-type transistors Z11 to Z1m. The gates of the P-type transistors Z11 to Z1m are connected to the signals in the first embodiment. Signals SEL1 # to SELm # obtained by inverting SEL1 to SELm are input.

  FIG. 10 is a timing chart for explaining the read operation of the semiconductor device according to the fourth embodiment. 10 shows the signal waveform at the word line WL1 in FIG. 9, the “RON #” column in FIG. 10 shows the signal waveform of the signal RON # in FIG. 10, and “PRE1 #” in FIG. "" Shows the signal waveform of the signal PRE1 # in FIG. Further, the “PRE2 # to PREm #” column in FIG. 10 shows the signal waveforms of the signals PRE2 # to PREm # in FIG. 9, and the “SEL1” column in FIG. 10 shows the signal waveform of the signal SEL1 # in FIG. Show.

  Here, a case where the memory cell M11 connected to the word line WL1 is read will be described with reference to FIG.

  First, before the time t1, since the signal RON # falls, the node SIN is charged and becomes the charging voltage VPRE. Next, at time t1, the word line WL1 is raised, and at the same time, the signal RON # and the signals PRE1 # to PREm # are raised to discharge the common line CML and all the bit lines BL1 to BLm from the charging voltage VP. Subsequently, at time t2, the signal SEL1 # and the signal PRE1 # are lowered and discharged from the node SIN via the data line DL and the load circuit 105. At this time, in the bit line charge / discharge circuit 802, the transistor Z1 to which the signal PRE1 # is input to the gate is turned off. At this time, in the bit line selection circuit 803, only the transistor Z11 whose gate is inputted with the signal SEL1 # is turned on. Therefore, the node SIN is discharged only through the memory cell M11. After an appropriate time from time t2, the sense amplifier 104 is operated to compare the voltage of the node SIN and the reference voltage VREF, thereby outputting the data DATA of the memory cell M11.

  According to the fourth embodiment, as in the first embodiment described above, a sufficient read margin is ensured while keeping the voltage applied between the input and output terminals of the memory cell low so that read disturb does not occur. High-speed reading is possible with low power consumption.

  When the parasitic capacitance of the data line DL is larger than the capacitances of the bit lines BL1 to BLm and the common line CML in the memory cell array, the first embodiment is more prior to the read operation than the fourth embodiment. Since charging can be performed at high speed, power consumption can be reduced. On the contrary, when the parasitic capacitance of the data line DL is smaller than the capacitance of the bit lines BL1 to BLm and the common line CML in the memory cell array, the read operation of the fourth embodiment is more than the first embodiment described above. Previous charging can be performed at high speed and power consumption can be reduced.

(Fifth embodiment)
Next, a block diagram of FIG. 11 shows a digital camera as an electronic apparatus according to the fifth embodiment of the present invention. This digital camera includes nonvolatile memories 908 and 919 which are semiconductor memory devices of the present invention. The non-volatile memory 908 is configured by any one of the first to fourth embodiments, for example. The nonvolatile memory 908 is used for storing captured images, and the nonvolatile memory 919 is used for storing variation correction values for the liquid crystal panel 922.

  In this digital camera, when the power switch 901 is turned on by the operator, the power supplied from the battery 902 is transformed to a predetermined voltage by the DC / DC converter 903 and supplied to each component. Light entering from the lens 916 driven by the optical system driving unit 917 is converted into current by the CCD 918, converted into a digital signal by the A / D converter 920, and input to the data buffer 911 of the video processing unit 910. The signal input to the data buffer 911 is processed by an MPEG processing unit 913 that performs processing based on the MPEG (Moving Picture Expert Group) standard, becomes a video signal through the video encoder 914, passes through the liquid crystal driver 921, and then passes through the liquid crystal panel 922. Is displayed.

  At this time, the liquid crystal driver 921 corrects variations in the liquid crystal panel 922 (for example, variations in hues that differ for each liquid crystal panel) using data in the built-in nonvolatile memory 919. When the operator presses the shutter 904, information in the data buffer 911 is processed as a still image through a JPEG processing unit 912 that performs processing based on the JPEG (Joint Photographic Expert Group) standard, and flash memory that is a nonvolatile memory Recorded in 908. In the flash memory 908, system programs and the like are recorded in addition to the captured image information. The DRAM 907 is used for temporary storage of data generated in various processing processes of the CPU 906 and the video processing unit 910.

  The non-volatile memories 908 and 919 of the digital camera need to reduce the chip area in order to reduce the bit unit price, and to reduce the power consumption in order to reduce the size of the battery 902 and extend the continuous operation time. . Furthermore, since an image stored in the non-volatile memory 908 causes a decrease in image quality if there is an error even in one pixel, the reliability of data accompanying the storage must be increased. Furthermore, it is necessary to increase the reliability of data when storage is performed for a long time. In addition, non-volatile memories used in other electronic devices such as mobile phones record a communication protocol when storing image data, and therefore require a high degree of reliability.

  Here, by adopting the embodiment of the present invention in the nonvolatile memories 908 and 919, read disturb related to the reliability of data retention is suppressed, a read margin is secured, and high-speed reading is low. This is possible with power consumption. Therefore, an electronic device including the semiconductor memory device of the present invention can achieve high speed, low power consumption, and high reliability.

  In the fifth embodiment, the embodiment of the semiconductor memory device of the present invention is mounted on a digital camera. However, it is also preferable that the semiconductor memory device of the present invention is mounted on a mobile phone. That is, a nonvolatile memory used in a cellular phone records a communication protocol in addition to image data, and therefore requires high reliability. Therefore, by installing the semiconductor memory device of the present invention in a mobile phone, the quality of the mobile phone can be remarkably improved.

  The semiconductor memory device of the present invention is applied to electronic devices other than digital cameras and mobile phones, such as digital audio recorders, DVD devices, color tone adjustment circuits for liquid crystal display devices, music recording / playback devices, video devices, audio devices, copying devices, etc. Needless to say, it may be installed.

1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. FIG. 6 is a timing diagram of a read operation in the first embodiment. FIG. 6 is a characteristic diagram showing a time change of a voltage applied to a memory cell of the semiconductor device of the first embodiment and a time change of a difference between read voltages when the memory cell has a high resistance and a low resistance. It is a figure which shows the semiconductor memory device using the bias circuit as a 1st comparative example with respect to the said 1st Embodiment. FIG. 6 is a characteristic diagram showing a time change of a voltage applied to a memory cell of the semiconductor memory device of the first comparative example and a time change of a difference between read voltages when the memory cell has a high resistance and a low resistance. It is a figure which shows the semiconductor memory device using the bias circuit as a 2nd comparative example with respect to the said 1st Embodiment. It is a figure which shows the semiconductor memory device of 2nd Embodiment of this invention. It is a figure which shows the semiconductor memory device of 3rd Embodiment of this invention. It is a figure which shows the semiconductor memory device of 4th Embodiment of this invention. It is a timing diagram of the read-out operation of the said 4th Embodiment. It is a block diagram which shows the digital camera which is an electronic device of 5th Embodiment of this invention.

Explanation of symbols

100, 700, 800 Memory cell array 101 Row decoder 102, 602, 802 Bit line charge / discharge circuit 103, 603, 803 Bit line selection circuit 104 Sense amplifier 105 Load circuit 300, 500 Characteristic curve (voltage applied to both ends of 200 kΩ cell)
301, 501 Characteristic curve (readout margin)
400, 600 Bias circuit 900 Digital camera 901 Power switch 902 Battery 903 DC / DC converter 904 Shutter 906 CPU
907 DRAM
908 Non-volatile memory 910 Video processing unit 911 Data buffer 912 JPEG processing unit 913 MPEG processing unit 914 Video encoder 916 Lens 917 Optical system driving unit 918 CCD
919 Non-volatile memory 920 A / D converter 921 Liquid crystal driver 922 Liquid crystal panel

Claims (9)

A memory cell for storing information with a magnitude of a current flowing between the input terminal and the output terminal;
A bit line to which one of the input terminal or output terminal of the memory cell is connected;
A bit line charge / discharge circuit for charging / discharging the bit line;
A bit line selection circuit for selecting the bit line;
A sense amplifier in which data output from the bit line selection circuit is input through a data line;
A load circuit connected between the data line and the sense amplifier and including at least one of a resistance component between the data line and the sense amplifier and a capacitance component between the data line and the ground A semiconductor memory device comprising: The semiconductor memory device according to claim 1,
The load circuit includes a capacitive element as a capacitive component between the data line and the ground. The semiconductor memory device according to claim 1 or 2,
The load circuit includes a resistance element or a transistor as a resistance component between the data line and the sense amplifier. The semiconductor memory device according to claim 1,
A semiconductor memory device comprising: a read operation control unit that sets a potential of the data line lower than a potential of the bit line before a read operation. The semiconductor memory device according to claim 1,
A semiconductor memory device comprising: a read operation control unit that sets a potential of the data line higher than a potential of the bit line before a read operation. The semiconductor memory device according to any one of claims 1 to 5,
The semiconductor memory device, wherein the memory cell includes an RRAM. The semiconductor memory device according to any one of claims 1 to 5,
The memory cell includes a nonvolatile memory having a charge storage layer. The semiconductor memory device according to any one of claims 1 to 5,
The memory cell includes a nonvolatile memory formed on a glass substrate.   An electronic apparatus comprising the semiconductor memory device according to claim 1.

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