JP4809169B2 - Semiconductor memory device and electronic device - Google Patents

Description

  The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a rewritable nonvolatile memory cell such as a flash memory cell having a function capable of independently storing near both ends of one channel region. The present invention also relates to an electronic apparatus having a semiconductor memory device.

  In recent years, a nonvolatile semiconductor memory device such as a flash memory or a ferroelectric memory is often used as a semiconductor memory element for data storage such as a mobile phone or a digital camera, or a code (program) storage. Yes.

  Such a non-volatile memory cell determines information by using a change in cell current (current flowing through the memory cell) according to the storage state, but a plurality of memory cells storing the same information due to its structure. It is difficult to make the cell currents completely match. Therefore, even if the same information is stored for a plurality of memory cells, the cell current values are usually distributed with a certain width. However, when the distribution of cell current values overlaps between memory cells storing different information, it is difficult to determine correct information. Therefore, the memory cells storing different information are adjusted by the program verify operation so that the cell current distributions do not overlap each other, that is, a gap is generated between the distributions. However, with the recent progress in miniaturization, voltage reduction, and the like, there is a problem that the gap separating the cell current distributions is becoming narrower. In addition, disturbance (disturbance caused by access to other memory cells), endurance (deterioration of the rewrite characteristics of the memory cell due to an increase in the number of rewrites), retention (retention characteristics of stored information due to changes in temperature, changes over time, etc.), etc. The influence affects the plurality of memory cells to different degrees. From the above, the spread of the cell current value distribution of each memory cell becomes large, and the gap separating the distribution of the cell current values of data 0 and data 1 becomes extremely narrow or overlaps each other, and the data There arises a problem that 0 and data 1 cannot be distinguished.

  As a typical method in the conventional read operation, there is a semiconductor memory device in which a reference cell is provided, and the current value or average current value is used as a reference current value to compare information with the cell current value of the memory cell to be read. Yes (see Patent Document 1: Japanese Patent Application Laid-Open No. 2004-273093). Specifically, data 0 and data 1 are stored in two reference cells, and their average current value is used as the reference current value.

However, when the gap between the distributions of data 0 and data 1 is extremely narrow or even overlaps (the gap disappears), the above conventional semiconductor memory device cannot correctly read the information in the memory cell. could not.
JP 2004-273093 A

  Therefore, the problem of the present invention is that the gap between the distributions of the cell current values of the data 0 and data 1 of the plurality of memory cells in the memory cell array may be extremely narrow, or the distributions may overlap. However, it is an object of the present invention to provide a semiconductor memory device capable of discriminating memory cell information with high accuracy.

In order to solve the above problems, a semiconductor memory device according to the present invention provides:
A voltage sense amplifier having a first input terminal and a second input terminal;
A storage area capable of storing information, a first memory cell having a first input / output terminal and a second input / output terminal;
A second memory cell having a storage area capable of storing information, a first input / output terminal connected to the second input / output terminal of the first memory cell, and a second input / output terminal;
A first bit line connected to the first input / output terminal of the first memory cell;
A second bit line connected to the second input / output terminal of the second memory cell;
A third bit line connected to the second input / output terminal of the first memory cell and the first input / output terminal of the second memory cell;
A bit line charge / discharge circuit for charging or discharging the first bit line, the second bit line, and the third bit line;
The first input terminal of the voltage sense amplifier having a first terminal connected to the first bit line, a second terminal connected to the first input terminal of the voltage sense amplifier, and a control terminal. A first switching element that contacts and separates the first bit line;
The second input terminal of the voltage sense amplifier having a first terminal connected to the second bit line, a second terminal connected to the second input terminal of the voltage sense amplifier, and a control terminal. A second switching element that contacts and separates the second bit line;
A first output terminal connected to the control terminal of the first switching element; a second output terminal connected to the control terminal of the second switching element; the control terminal of the first switching element; A pulse signal generator for outputting a pulse signal to the control terminal of the second switching element;
1 bit information is stored in the first memory cell and the second memory cell ;
The pulse signal generator is
In the read operation, a signal for taking in the voltage of the first bit line to the first input terminal of the sense amplifier is output to the control terminal of the first switching element, and the second bit line is While a signal for taking in the voltage to the second input terminal of the sense amplifier is output to the control terminal of the second switching element,
At the time of write verification, a pulse signal having a first pulse width is output to the control terminal of the first switching element, while a pulse signal having a second pulse width different from the first pulse width is output to the second switching element. It outputs to the said control signal of a switching element, It is characterized by the above-mentioned .

  The control terminal of the switching element refers to a terminal to which a current or voltage is applied in order to control the current flowing between the first terminal and the second terminal.

  According to the present invention, since the first memory cell and the second memory cell are paired to store 1-bit information, the difference between the states of the two pairs of memory cells can be used. A read operation can be performed. In addition, information stored in the memory cell can be accurately read without using a reference voltage or a reference cell. In addition, since one of the pair of memory cells used for the read operation can be used as a verify cell at the time of writing to the other, it is possible to use an endurance as compared with a conventional method in which a fixed reference voltage and a small number of verify cells are shared. Characteristics and retention characteristics can be improved.

  In one embodiment, the storage area of the first memory cell includes a first storage area and a second storage area in which information can be stored independently of each other, and the storage area of the second memory cell. Comprises a first storage area and a second storage area that can store information independently of each other.

  According to the above embodiment, the storage area can be limited to a narrow range of memory cells by limiting the storage area actually used to one of the first storage area and the second storage area. Therefore, the amount of charge necessary for reading data can be reduced, and power consumption during writing and erasing can be reduced.

The semiconductor memory device according to one embodiment
The pulse signal generator is
A first pulse generation circuit that outputs a pulse signal having a first pulse width;
A second pulse generating circuit for outputting a pulse signal having a second pulse width different from the first pulse width;
A first multiplexer having a first input terminal to which a signal from the first pulse generation circuit is input, a second input terminal to which a signal from the second pulse generation circuit is input, and a control signal input terminal;
A second multiplexer having a first input terminal to which a signal from the first pulse generation circuit is input, a second input terminal to which a signal from the second pulse generation circuit is input, and a control signal input terminal;
A first output terminal connected to the control signal input terminal of the first multiplexer; and a second output terminal connected to the control signal input terminal of the second multiplexer. The first multiplexer outputs the first output terminal. Controls whether a signal is a signal from the first pulse generation circuit or a signal from the second pulse generation circuit, and outputs a signal output from the second multiplexer to the first pulse generation A pulse width control circuit for controlling whether the signal is output from the circuit or the signal from the second pulse generation circuit.

  According to the embodiment, a small circuit can easily generate signals having different pulse widths from the two output terminals at the time of writing, while it can easily generate the same pulse width from the two output terminals at the time of reading. A signal can be output.

The semiconductor memory device according to one embodiment
A first pulse generation circuit capable of outputting a first pulse signal and a second pulse signal having a pulse width different from that of the first pulse signal;
A second pulse generation circuit identical to the first pulse generation circuit;
Controls whether the signal output from the first pulse generation circuit is the first pulse signal or the second pulse signal, and the signal output from the second pulse generation circuit is the first pulse signal. And a pulse width control circuit for controlling whether to use one pulse signal or the second pulse signal.

  According to the embodiment, a small circuit can easily generate signals having different pulse widths from the two output terminals at the time of writing, while it can easily generate the same pulse width from the two output terminals at the time of reading. A signal can be output. In addition, the driving capability of the circuit can be made uniform between the case of different pulse widths and the case of the same pulse width.

  In one embodiment, the memory cell is a sidewall memory.

  Here, the sidewall memory includes a source region, a drain region, a channel region formed between the source region and the drain region, a gate formed on the channel region, and both sides of the gate. It refers to a memory having a charge holding region provided on each wall.

  In the sidewall memory, by controlling the potentials of the source region, the drain region, and the gate, the charge holding states of the two charge holding regions are separately controlled, and information is stored in each.

  Since the memory cell including the sidewall memory has two charge holding regions, that is, two storage portions in one memory cell, the degree of integration of the semiconductor memory device can be effectively increased. In a sidewall memory having two storage units, the current when reading information from one storage unit is affected by the charge retention state of the other storage unit. Therefore, it has a characteristic that the variation in the value of the cell current is larger than that of a memory cell having one memory portion. However, since this semiconductor memory device is configured to compare the states of the first memory cell and the second memory cell, from the first input / output terminals in a plurality of memory cells selected by one word line. Current distribution when current flows through the second input / output terminal and current distribution when current flows from the second input / output terminal to the first input / output terminal in a plurality of memory cells selected by one word line Even if there is a variation, a deviation occurs with the passage of time, or the two current distributions overlap, the information of the memory cell can be accurately determined.

  The electronic device of the present invention includes the semiconductor memory device of the present invention.

  Here, the electronic device refers to a portable information terminal such as a mobile phone, a liquid crystal display device, a DVD device, a video device, an audio device, a copying device, and the like.

  According to the present invention, since the semiconductor memory device according to the present invention that can determine information with high accuracy with a relatively simple configuration is provided, the reliability of the electronic device can be improved.

  According to the semiconductor memory device of the present invention, since the read operation can be performed by utilizing the difference between the states of the first memory cell and the second memory cell, the reference voltage, the reference current, the reference cell, and the like are used. Therefore, the information stored in the memory cell can be read accurately. In addition, since one of the first memory cell and the second memory cell of the pair used for the read operation is used as a verify cell at the time of writing to the other, a conventional constant reference voltage or reference current is used or a small number of verify cells are shared. The endurance characteristics and retention characteristics can be improved as compared to the system that performs this.

  Hereinafter, the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. This semiconductor memory device includes a memory cell array 100 in which nonvolatile memory cells MC0, MC1,... Are arranged in a matrix. In the row direction of the memory cell array 100, a plurality of word lines WL connected to the control gates of the memory cells arranged in the same row extend.

  Further, in the column direction of the memory cell array 100, the memory cell array 100 includes two memory cells arranged adjacent to each other in the same column, and is connected to an input / output terminal on one side of one memory cell in all different sets. A bit line BLL as a connected first bit line, and a third bit line connected to an input / output terminal on the other side of the one memory cell and an input / output terminal on one side of the other memory cell. A bit line BLC and a bit line BLR as a second bit line connected to the input / output terminal on the other side of the other memory cell extend.

  Bit lines BLL, BLC, and BLR are connected to bit line charge / discharge circuit 101. The output signal CUT of the CUT signal generation circuit 102 is input to the first and second pulse generation circuits 103 and 104, and the single pulse signal CUTD 1 is output from the first pulse generation circuit 103 and the single pulse signal CUTD 1 is output from the second pulse generation circuit 104. The pulse signal CUTD2 is output respectively.

  Both the one-shot pulse signal CUTD1 and the one-shot pulse signal CUTD2 are input to the first multiplexer 105 and to the second multiplexer 106. The output signal PW1 of the pulse width control circuit 111 is input to the first multiplexer 105, and the output signal PW2 of the pulse width control circuit 111 is input to the second multiplexer 106. ing.

  When the selection control of the first multiplexer 105 is set to 0 by the control signal PW1 of the pulse width control circuit 111, the signal CUTD1 is selected as the output signal CUT1 of the first multiplexer 105. On the other hand, when the selection control of the first multiplexer 105 is set to 1 by the control signal PW1 of the pulse width control circuit 111, the signal CUTD2 is selected as the output signal CUT1 of the first multiplexer 105.

  When the selection control of the second multiplexer 106 is set to 0 by the control signal PW2 of the pulse width control circuit 111, the signal CUTD1 is selected as the output signal CUT2 of the second multiplexer 106. On the other hand, when the selection control of the second multiplexer 106 is set to 1 by the control signal PW2 of the pulse width control circuit 111, the signal CUTD2 is selected as the output signal CUT2 of the second multiplexer 106.

  The signal CUT1 from the first multiplexer 105 is input to the control terminal of the transistor Q1 as the first switching element, while the signal CUT2 from the second multiplexer 106 is input to the control terminal of the transistor Q2 as the second switching element. It has come to be. The transistor Q1 connects and disconnects the bit line BLL and the input terminal SAL of the voltage sense amplifier 107, while the transistor Q2 connects and disconnects the bit line BLR and the input terminal SAR of the voltage sense amplifier 107. Yes. The memory cells MC0, MC1,... Are side wall memories described later.

  At the time of reading, this device first discharges all of the bit lines BLL, BLC, and BLR to 0V, and then discharges the word line WL to Vcc (not shown in FIG. 1, for example, 3.3V) and the bit line BLC. The voltage is raised to Vd (not shown in FIG. 1, for example, 1.2 V). Then, after taking the voltages of the bit lines BLL and BLR as input voltages, the signals CUT1 and CUT2 are set to Low, and the voltages are confined to the input terminal SAL and the input terminal SAR of the voltage sense amplifier 107. Thereafter, an amplification operation of the voltage sense amplifier 107 is performed. The operation conforms to that of a conventional DRAM sense amplifier. The data is output as signal DATA.

  FIG. 2 is a schematic diagram showing the sidewall memory used as the memory cells MC0, MC1,... In the first embodiment.

  The side wall memory includes a first silicon nitride film 2003 as a first storage region that functions as a charge holding region and a second silicon nitride film 2004 as a second storage region. The sidewall memory 2000 stores 1-bit information of data 0 and data 1 by writing information to either one of the first silicon nitride film 2003 and the second silicon nitride film 2004. A word line 2005 functioning as a gate electrode is formed on a substrate 2001 via a gate insulating film 2002, and first and second silicon nitride films are formed on both sides of the word line 2005 via a silicon oxide film 2006. 2003, 2004 are formed. The first and second silicon nitride films 2003 and 2004 are connected to the vertical portion extending substantially parallel to the side wall of the word line 2005 and the lower end of the vertical portion, and are substantially parallel to the surface of the substrate 2001 and away from the word line 2005. And a lateral portion extending to the side, and has a substantially L-shaped cross-sectional shape. On the far side of the first and second silicon nitride films 2003 and 2004 from the word line 2005, silicon oxide films 2007 and 2007 are provided. Thus, by sandwiching the first and second silicon nitride films 2003 and 2004 between the silicon oxide film 2006 and the silicon oxide film 2007, the charge injection efficiency during the rewrite operation is increased, and a high-speed operation is realized. Yes. Two diffusion regions are formed on the substrate 2001 adjacent to the first and second silicon nitride films 2003 and 2004. Specifically, the diffusion layer 2009 is formed so as to overlap a part of the lateral part of the first silicon nitride film 2003 and so as to overlap a part of the lateral part of the silicon nitride film included in the adjacent memory cell. . Further, a diffusion layer 2010 is formed so as to overlap a part of the lateral part of the second silicon nitride film 2004 and so as to overlap a part of the lateral part of the silicon nitride film included in the adjacent memory cell. The diffusion layer 2010 functions as the second bit line 2012. The diffusion layer 2009 and the second bit line 2012 function as a source region or a drain region, respectively. A channel region is defined between the diffusion layer 2009 functioning as the source region or the drain region and the second bit line 2012. The second bit line 2012 is connected to a wiring layer (not shown) formed above the memory cell, and the diffusion layer 2009 is connected to the first bit line 2011 formed above the memory cell 2000. In the sidewall memory, since the storage area is limited to a narrow range near one end of the channel area, the amount of charge required for reading data can be reduced, and power consumption during writing and erasing can be reduced. it can.

  FIG. 3 is a diagram showing a part of the circuit configuration of the voltage sense amplifier 107.

  The voltage sense amplifier 107 includes a first sense node 6 and a second sense node 7, a gate terminal 11 as an example of a control terminal connected to the signal line 8, and a first terminal 12 connected to a power supply 15. Second conductivity having a P-type first transistor P1 as the first conductivity type, a gate terminal 21 as an example of a control terminal connected to the signal line 9, and a first terminal 22 connected to the ground 25. And an N-type first transistor N1 as a type.

  The voltage sense amplifier 107 includes a P-type second transistor P0 having a gate terminal 31 as an example of a control terminal connected to the signal line 8, a first terminal 32 connected to the power supply 15, and a signal. It has an N-type second transistor N 0 having a gate terminal 41 as an example of a control terminal connected to the line 9 and a first terminal 42 connected to the ground 25.

  The voltage sense amplifier 107 includes a first terminal 52 connected to the second sense node 7, a second terminal 53 connected to the second terminal 13 of the P-type first transistor P1, and a first sense node. P-type third transistor P3 having a gate terminal 51 connected to 6, a first terminal 62 connected to the second sense node 7, and a second terminal 23 of the N-type first transistor N1. And an N-type third transistor N3 having a second terminal 63 and a gate terminal 61 connected to the first sense node 6.

  The voltage sense amplifier 107 includes a first terminal 72 connected to the first sense node 6, a second terminal 73 connected to the second terminal 33 of the P-type second transistor P0, and a second sense node. 7 is connected to a P-type fourth transistor P2 having a gate terminal 71 connected to 7, a first terminal 82 connected to the first sense node 6, and a second terminal 43 of the N-type second transistor N0. And an N-type fourth transistor N2 having a second terminal 83 and a gate terminal 81 connected to the second sense node 7.

  A signal SAP is externally input to the gate terminal 11 of the P-type first transistor P1 and the gate terminal 31 of the P-type second transistor P0. A signal SAN is input from the outside to the gate terminal 21 of the N-type first transistor N1 and the gate terminal 41 of the N-type second transistor N0.

  The voltage sense amplifier 107 inputs the input signal to the first sense node 6 and the second sense node 7, and then lowers the signal SAP from High to Low, and further changes the signal SAN from Low to High. It is set up to perform amplification operation.

  FIG. 4 is a diagram illustrating an example of the first pulse generation circuit 103, and FIG. 5 is a diagram illustrating an example of the second pulse generation circuit 104. In FIG. 4, 103a represents an inverter (NOT circuit), and 103b represents a NAND circuit. In FIG. 5, reference numeral 104a denotes an inverter (NOT circuit), and 104b denotes a NAND circuit.

  When the signal CUT indicating High is input to the first pulse generation circuit 103, the signal CUTD1 having a pulse width corresponding to the delay time of the inverter train 500 is output, while the signal CUT indicating High is output from the second pulse generation circuit 104. Is input, a signal CUTD1 having a pulse width corresponding to the delay time of the inverter train 600 is output. In the first embodiment, the inverter train 500 of the first pulse generation circuit 103 shown in FIG. 4 has more stages than the inverter train 600 of the second pulse generation circuit 104 shown in FIG. The delay time is larger, and the output pulse width of CUTD1 is longer than the output pulse width of CUTD2.

  Next, each operation in the read from the memory cell and the write verify mode in the first embodiment will be described.

  In the first embodiment, 1-bit information is stored by pairing two memory cells MC0 and MC1. At this time, for example, data 0 is stored in the storage node 1 of the left memory cell MC0 in an erased state (the erased state is defined as a state in which the storage node is in an erased state, that is, a state in which electrons are extracted from the storage node). The storage node 4 of the memory cell MC1 on the right side is set to a write state (the write state is defined as a state where the storage node is in a programmed state, that is, a state where electrons are injected into the storage node). Is in an erased state (or a virgin state immediately after manufacture). Further, for example, in the data 1, the storage node 1 of the left memory cell MC0 is in the write state, the storage node 4 of the right memory cell MC1 is in the erase state, and the storage nodes 2 and 3 are in the erase state (or virgin immediately after manufacture). State).

  The definitions of data 0 and data 1 may be reversed from the above definitions. In addition, the storage nodes 1 and 2 or the storage nodes 3 and 4 may be written together. However, the endurance characteristic is better when writing to only one of the storage nodes (in the above example, the storage nodes 1 and 4). Is excellent.

  In the read operation, the bit line charge / discharge circuit 101 is used to discharge all of the bit lines BLL, BLC, and BLR to 0 V, and the word line WL is raised to Vcc (for example, 3.3 V). Subsequently, the bit lines BLL and BLR are set to a high impedance (HiZ) state, for example, Vd = 1.2 V is applied to the bit line BLC, and the bit lines BLL and BLR are charged via the memory cells. At the same time, the signal CUT1 and the signal CUT2 are raised, the signal CUT1 and the signal CUT2 are simultaneously set to Low at an appropriate timing, the voltage of the bit line BLL is taken into the input terminal SAL, and the voltage of the bit line BLR is input to the input terminal. Import into SAR.

  This timing is set by the pulse widths of the signal CUT1 and the signal CUT2. Here, the control signals of the first and second multiplexers 105 and 106 are both set to 0, for example, so as to have the same pulse width. Thereafter, the signal SAP is lowered from High to Low, and further the signal SAN is raised from Low to High, so that the voltage sense amplifier 107 performs an amplification operation.

  In the first embodiment, the bit lines BLL and BLR are charged and the information written in the memory cells is read. However, in the present invention, conversely, the bit lines BLL and BLR are discharged. The information written in the memory cell may be read out. For example, a method of discharging from 1.2 V may be used. However, in this case, in the side wall memory, it is better to use the storage nodes 2 and 3 instead of the storage nodes 1 and 4 in terms of read characteristics.

  Next, the write verify mode will be described. In the nonvolatile memory, not all the memory cells reach a desired level (a current value equal to or less than a certain value or a threshold value or a threshold value) by one write operation. Therefore, whether or not writing has been performed to a desired level is confirmed by comparing with the current value and threshold value of the reference verifying memory cell. This is generally called a write verify operation.

  In the first embodiment, since 1 bit is stored in two memory cells, among the storage nodes used for writing information, the storage node that does not perform writing (in the example shown in FIG. A memory cell having the storage node 4) is used as a memory cell for verification.

  For example, when writing data 0, the storage node 1 writes to the storage node 4 while remaining in the erased state. In the charging and reading method described above, since the lower voltage taken into the voltage sense amplifier 107 is in the writing state, the control signal of the first multiplexer 105 is 1, the control signal of the second multiplexer 106 is 0, and the signal CUT1 is a short pulse. The width signal CUTD2 is set, and the signal CUT2 is set to a long pulse width signal CUTD1 used in a normal read operation. Then, since the voltage of the input terminal SAL becomes low, data 1 is output from the voltage sense amplifier 107 while writing is not sufficient. When sufficient writing can be performed, the voltage at the input terminal SAR becomes lower than that at the input terminal SAL, and the data from the voltage sense amplifier 107 changes to 0.

  When writing data 1, the storage node 4 writes to the storage node 1 while remaining in the erased state. In the charging and reading method described above, since the lower voltage taken into the voltage sense amplifier 107 is in the writing state, the control signal of the first multiplexer 105 is 0, the control signal of the second multiplexer 106 is 1, and the signal CUT2 is a short pulse. The width signal CUTD2 is set, and the signal CUT1 is set to a long pulse width signal CUTD1 used in a normal read operation. Then, since the voltage of the input terminal SAR becomes low, data 0 is output from the voltage sense amplifier 107 while writing is not sufficient. When sufficient writing is possible, the voltage of the input terminal SAL becomes lower than that of the input terminal SAR, and the data from the voltage sense amplifier 107 changes to 1, so that the writing ends at that time.

  How much the pulse width of the signal CUTD2 is made shorter than the pulse width of the signal CUTD1 is set according to the endurance characteristic (rewrite characteristic) and retention characteristic (holding characteristic) of the memory cell.

  In the semiconductor memory device of the first embodiment, the sidewall memory whose cross-sectional structure is shown in FIG. 2 is used. However, the semiconductor memory device of the present invention has two storage nodes (storage layers and storage layers) at both ends of the channel region. The memory cell having any structure can be used as long as it has a memory cell. 6 to 11 are cross-sectional views showing the structure of a memory that can be used in the present invention. Several examples of memories that can be used in the semiconductor memory device of the present invention will be described below with reference to FIGS.

  As shown in FIG. 6, the memory of the present invention is a first storage region that is formed by sequentially laminating an oxide film 1405 and a gate 1400 on a substrate 1406, and is substantially bilaterally symmetrical on the oxide film 1405 and on both sides of the gate 1400. A first storage layer 1401 and a second storage layer 1402 which is a second storage region are stacked, and further, a first storage layer 1401 is overlapped between the substrate 1406 and the oxide film 1405 in the stacking direction. The first diffusion layer 1403 is formed, and the second diffusion layer 1404 is formed so as to overlap the second accumulation layer 1402 in the stacking direction and not intersect the first diffusion layer 1403. Also good.

  In the memory of the present invention, as shown in FIG. 7, an oxide film 1505 and a gate 1500 are sequentially stacked on a substrate 1506, and a quadrant of a cross-section is formed symmetrically in two corners of the gate 1500 on the oxide film 1505 side. A first storage layer 1501 as a first storage region having a shape and a second storage layer 1502 as a second storage region having a quadrant in cross section are formed. Further, between the substrate 1506 and the oxide film 1505, The first diffusion layer 1503 is formed so as to overlap the first accumulation layer 1501 in the stacking direction, and the second diffusion layer 1502 is overlapped in the stacking direction so as not to intersect the first diffusion layer 1503. A structure in which the second diffusion layer 1504 is formed may be used.

  Further, as shown in FIG. 8, the memory according to the present invention includes an oxide film 1605 having a substantially concave cross section formed on a substrate 1606, a gate 1600 formed in a recess of the oxide film 1605, and a substrate. An oxide film 1607, a first storage layer 1608 as a first memory region, an oxide film 1609, and a gate 1610 are stacked on the oxide film 1605 on one side of the oxide film 1605, and on the other side of the oxide film 1605 on the substrate 1606. Are stacked with an oxide film 1611, a second storage layer 1612 which is a second memory region, an oxide film 1613, and a gate 1614, and a first storage layer 1608 in the stacking direction between the substrate 1606 and the oxide film 1607. A first diffusion layer 1617 is formed so as to overlap with the second accumulation layer 1612 in the stacking direction between the substrate 1606 and the oxide film 1611, and So as not to intersect the first diffusion layer 1617 may have a structure in which the second diffusion layer 1618 is formed.

  Further, as shown in FIG. 9, the memory included in the present invention has an oxide film 1705 formed on a substrate 1706, and the convex side of the convex cross section is in contact with the entire upper surface of the oxide film 1705. A gate 1700 is formed, and an oxide film 1708, a first storage layer 1709 as a first memory region, and an oxide film 1710 are sequentially formed on one side of the oxide film 1705 and between the substrate 1706 and the gate 1700. At the same time, an oxide film 1711, a second storage layer 1712 which is a second memory region, and an oxide film 1713 are sequentially formed on the other side of the oxide film 1705 and between the substrate 1706 and the gate 1700. A first diffusion layer 1715 is formed between the substrate 1706 and the oxide film 1711 so as to overlap the first accumulation layer 1709 in the stacking direction between the substrate 1706 and the film 1708. In, so as to overlap with the second storage layer 1712 in the stacking direction, and so as not to intersect with the first diffusion layer 1715 may have a structure in which the second diffusion layer 1716 is formed.

  In the memory of the present invention, as shown in FIG. 10, an oxide film 1806, a silicon nitride film 1807, an oxide film 1808, and a gate 1800 are formed in this order on a substrate 1805, and between the substrate 1805 and the oxide film 1806. In addition, a first diffusion layer 1803 is formed so as to overlap the silicon nitride film 1807 in the stacking direction, and overlaps the silicon nitride film 1807 in the stacking direction between the substrate 1805 and the oxide film 1806, and A structure in which the second diffusion layer 1804 is formed so as not to cross the diffusion layer 1803 may be employed. In the structure shown in FIG. 10, one side of the sandwich structure composed of the oxide film 1806, the silicon nitride film 1807, and the oxide film 1808 in the cross section is used as the first accumulation unit 1801 as the first storage region, and the cross section The other side of the sandwich structure is used as a second storage unit 1802 as a second storage area.

  Further, as shown in FIG. 11, in addition to the configuration of FIG. 2, the memory of the present invention has one diffusion layer 2009 on both sides of one diffusion layer 2009 of two diffusion layers 2009 and 2010. A configuration in which a second diffusion layer 2013 having the same conductivity type as that of the conductivity type is formed may be used. That is, the second diffusion layer 2013 may be injected into one channel end of the sidewall memory (generally called an LDD structure), and only the second silicon nitride film 2004 may be used as a charge storage node. In this case, since there is the second diffusion layer 2013, the amount of current flowing through the channel does not depend on the state of the first silicon nitride film 2003.

  The memory cell of the present invention may have a configuration in which the storage node is formed of a floating gate made of a material typified by polysilicon and there is only one storage node.

  For example, as shown in FIG. 12, the memory cell 2200 is embedded in the substrate 201 in a cross-sectional view in a direction perpendicular to the substrate 2201, and is provided with a diffusion layer 2209 and a diffusion layer 2210 arranged at intervals. A gate insulating film 2202 formed on part of the substrate 2201, part of the diffusion layer 2209, and part of the diffusion layer 2210, and a material typified by polysilicon while being formed on the gate insulating film 2202 A structure including a floating gate 2208 made of, a silicon oxide film 2206 formed on the floating gate 2208, and a word line 2205 formed on the silicon oxide film 2206 may be employed.

  Further, for example, as shown in FIG. 13, the memory cell 2300 is embedded in the substrate 2301 in a cross-sectional view perpendicular to the substrate 2301, and the diffusion layer 2309 and the diffusion layer 2310 are arranged at intervals. A gate insulating film 2302 formed on part of the substrate 2301 and part of the diffusion layer 2209; a floating gate 2308 formed on the gate insulating film and made of a material typified by polysilicon; The structure includes a silicon oxide film 2306 formed on the floating gate 2308, a part of the substrate 2301, and a part of the diffusion layer 2310, and a word line 2305 formed on the silicon oxide film 2306. Also good. In the case of a memory cell having only one storage node as shown in FIGS. 12 and 13, for example, data 0 is stored in the erased state of the storage node of the left memory cell MC0 and stored in the right memory cell MC1. Of course, if the node is in the write state and the data is 1, the reverse is sufficient.

(Second Embodiment)
FIG. 14 is a diagram showing a semiconductor memory device according to the second embodiment of the present invention.

  The semiconductor memory device of the second embodiment is different from the semiconductor memory device of the first embodiment only in the configuration of the pulse signal generator 3110.

  In the semiconductor memory device of the second embodiment, the same components as those of the semiconductor memory device of the first embodiment are denoted by the same reference numerals, and the description thereof is omitted. In the semiconductor memory device of the second embodiment, the description of the operation and effect common to the semiconductor memory device of the first embodiment will be omitted, and the configuration and operation different from those of the semiconductor memory device of the first embodiment. Only the effect will be described.

  In the second embodiment, the pulse signal generation unit 3110 directly controls the pulse width output from the first pulse generation circuit 112 by the output signal PW1 of the pulse width control circuit 111 and outputs the signal output from the pulse width control circuit 111. The pulse width output from the second pulse generation circuit 113 is directly controlled by PW2. The first pulse generation circuit 112 is the same as the second pulse generation circuit 113.

  FIG. 15 is a diagram illustrating an example of the first pulse generation circuit 112. Since the first pulse generation circuit 112 is the same as the second pulse generation circuit 113, it is a matter of course that FIG. 15 also shows an example of the second pulse generation circuit 113. In FIG. 15, 112a indicates an inverter (NOT circuit), and 112b indicates a NAND circuit.

  The third pulse generation circuit 112 determines whether the pulse passes through the upper path (two inverters in FIG. 15) of the inverter train 900 or the lower path (0 inverters in FIG. 15) of the inverter train 900. The width changes.

  If this method is used, the driving capability of the circuit can be made uniform between the case of different pulse widths and the case of the same pulse width. All other operations are the same as in the first embodiment.

(Third embodiment)
FIG. 16 is a diagram showing a semiconductor memory device according to the third embodiment of the present invention.

  The semiconductor memory device of the third embodiment is different from the semiconductor memory device of the first embodiment in that a current sense amplifier 109 is used as a sense amplifier.

  In the semiconductor memory device according to the third embodiment, the same components as those of the semiconductor memory device according to the first embodiment are denoted by the same reference numerals, and description thereof is omitted. Further, in the semiconductor memory device of the third embodiment, the description of the operation and effect common to the semiconductor memory device of the first embodiment is omitted, and the configuration and operation different from those of the semiconductor memory device of the first embodiment are omitted. Only the effect will be described.

  In the third embodiment, each of the bit lines BLL and BLR to which the memory cell to be read is connected is connected to the current sense amplifier 109 via the bit line selection circuit 108. Further, the potential of the bit line BLC connected to the second input / output terminal of the first memory cell MC0 and the first input / output terminal of the second memory cell MC1 is set to 0V, for example.

  FIG. 17 is a diagram showing an example of the circuit configuration of the current sense amplifier 109. As shown in FIG. In FIG. 17, reference numerals 2400 to 2406 denote transistors. When the bit line BLL is connected to the input terminal SAL, the voltage of the input terminal SAL is a division ratio of the resistance of the transistor 2400 that is a switching element to which BIASL is input and the resistance of the memory cell MC0 (reciprocal of current). Determined. Similarly, when the bit line BLR is connected to the input terminal SAR, the voltage at the input terminal SAR is the resistance of the transistor 2401 which is a switching element to which BIASR is input and the resistance of the memory cell MC1 (reciprocal of current). Determined by the split ratio.

  In a normal read operation, the resistance of the transistor 2400 to which the signal BIASL is input is made equal to the resistance of the transistor 2401 to which the signal BIASR is input. In the case of data 0, since the current (resistance) of the memory cell MC1 is smaller (larger) than the current (resistance) of the memory cell MC0, the voltage of the input terminal SAR becomes higher than the input terminal SAL, and the output signal DATA becomes Low. On the other hand, in the case of data 1, since the current (resistance) of the memory cell MC0 is smaller (larger) than the current (resistance) of the memory cell MC1, the voltage of the input terminal SAL becomes higher than the input terminal SAR, and the output signal DATA becomes High.

  In the third embodiment, since one bit is stored in two memory cells, among the storage nodes used for writing information, the storage node that does not perform writing (in the example shown in FIG. 16, for example, the storage node The memory cell having 1 or 4) is used as a memory cell for verification.

  Next, a case where data is written will be described. For example, when data 0 is written, the storage node 1 is set in the erased state, and the storage node 4 is written. In the current sense amplifier 109 of FIG. 17, the higher one of the input terminal SAL and the input terminal SAR is in the writing state. The current of 2400 is set to be larger than the current of the P-channel transistor 2401 which is a switching element. That is, the determination reference value is changed by increasing the bias current on the left side. Then, since the voltage of the input terminal SAL increases, data 1 is output from the current sense amplifier 109 while writing is not sufficient. When sufficient writing is possible, the voltage of the input terminal SAR becomes higher than that of the input terminal SAL, and the data from the current sense amplifier 109 changes to 0, so that the writing ends at that time.

  On the other hand, when data 1 is written, storage node 4 is erased and data is written to storage node 1. In the current sense amplifier 109 in FIG. 17, the higher one of the input terminal SAL and the input terminal SAR is in the writing state. Therefore, the voltage of the signal BIASR is made lower than the signal BIASL, and the current of the transistor 2401 is Set more. That is, the determination reference value is changed by increasing the right side bias current. As a result, the voltage at the input terminal SAR increases, so that data 0 is output from the current sense amplifier 109 while writing is not sufficient. When sufficient writing is possible, the voltage of the input terminal SAL becomes higher than that of the input terminal SAR, and the data from the current sense amplifier 109 changes to 1, so that the writing ends at that time.

  The transistor 2400, the transistor 2401, a signal transmission device (not shown) that applies the signal BIASL to the control terminal of the transistor 2401, and a signal transmission device (not shown) that applies the signal BIASL to the control terminal of the transistor 2401 It constitutes a bias current application unit which is a block prevention unit. As described above, by making the left-side bias current larger than the right-side bias current by the erroneous information write prevention unit, a sufficient amount of electrons are stored in the storage node 4 so that no erroneous determination is made. On the other hand, by making the right-side bias current larger than the left-side bias current, a sufficient amount of electrons can be injected into the storage node 1 so that no erroneous determination is made. Therefore, it is possible to write clear information having no risk of being read erroneously in the memory cells MC0 and MC1 that store two pieces of 1-bit information.

  How much the voltage difference between the voltage of the signal BIASL and the voltage of the signal BIASR is set can be determined according to the endurance characteristic (rewriting characteristic) and the retention characteristic (holding characteristic) of the memory cell. Since the voltage of the signal BIASL and the voltage of the signal BIASR, that is, the respective bias currents can be continuously controlled, the determination criterion can be arbitrarily set. In the above, the voltage of the signal BIASL and the voltage of the signal BIASR are set lower than those at the time of normal reading. Conversely, the voltage of the signal BIASR and the voltage of the signal BIASL are set higher than at the time of normal reading. It doesn't matter.

(Fourth embodiment)
FIG. 18 is a diagram showing a current sense amplifier 2500 used in the semiconductor memory device according to the fourth embodiment of the present invention.

  The semiconductor memory device according to the fourth embodiment has a configuration in which the current sense amplifier 109 is replaced with a current sense amplifier 2500 in the semiconductor memory device according to the third embodiment. In FIG. 18, reference numerals 2501 to 2512 denote transistors.

  The current sense amplifier 2500 included in the semiconductor memory device according to the fourth embodiment performs the same operation as the current sense amplifier 109 according to the third embodiment. When the bit line BLL is connected to the input terminal SAL, the voltage of the input terminal SAL is obtained by dividing the resistance of the transistor 2501 which is a switching element to which the signal BIAS is input and the resistance of the memory cell MC0 (reciprocal of current). Determined by. Similarly, when the bit line BLR is connected to the input terminal SAR, the voltage of the input terminal SAR is such that the resistance of the transistor 2502 which is a switching element to which the signal BIAS is input and the resistance of the memory cell MC1 (reciprocal of current). Determined by the split ratio. In this embodiment, the resistance of the transistor 2501 which is a switching element and the resistance of the transistor 2502 which is a switching element are set to be the same.

  As shown in FIG. 18, the current sense amplifier 2500 includes a three-point branching node 2514 and three points, except that the control terminal of the transistor 2503 and one input terminal of the transistor 2503 are connected by wiring. The configuration with the branch node 2515 is symmetrical.

  In a normal read operation, in the transistors 2505 and 2506 arranged symmetrically, both the signal VRYL input to the control terminal of the transistor 2505 and the signal VRYR input to the control terminal of the transistor 2506 are set to High. In the case of data 0, since the current (resistance) of the memory cell MC1 is smaller (larger) than the current (resistance) of the memory cell MC0, the voltage of the input terminal SAR is higher than that of the input terminal SAL. The current flowing in the circuit part on the input terminal SAR side in the two symmetrical circuit parts shown in FIG. 18 is applied to the circuit part on the input terminal SAL side in the two symmetrical circuit parts shown in FIG. It becomes smaller than the flowing current. Then, the output signal DATA of the current sense amplifier 2500 becomes Low. On the other hand, in the case of data 1, since the current (resistance) of the memory cell MC0 is smaller (larger) than the current (resistance) of the memory cell MC1, the voltage at the input terminal SAL becomes higher than the input terminal SAR. IL becomes larger than the current IR. The output signal DATA is High. In the fourth embodiment, 1 bit is stored in 2 memory cells. Then, a memory cell having a storage node (for example, storage node 1 or 4 in the example shown in FIG. 16) that does not perform writing among storage nodes used for writing information is used as a memory cell for verification.

  Next, writing will be described. For example, when writing data 0, the storage node 1 remains in the erased state, and the storage node 4 is written. In the current sense amplifier 2500, of the current IL and the current IR, the one with the larger current is the write state, so the signal VRYL is set to High and the signal VRYR is set to Low. That is, a part of the current path of the circuit part on the right side (input terminal SAL side) of the two symmetrical circuit parts is cut off, and the determination reference value is changed. Then, since the current IR decreases, data 1 is output from the current sense amplifier 2500 while writing is not sufficient. When sufficient writing can be performed, the current IR becomes larger than the current IL, and the data from the current sense amplifier 2500 changes to 0, so that the writing is terminated at that time.

  On the other hand, when data 1 is written, data is written to the storage node 1 while the storage node 4 remains in the erased state. In the current sense amplifier 2500, the larger one of the current IL and the current IR is in the write state, so the signal VRYR is set to High and the signal VRYL is set to Low. That is, a part of the current path on the left side (input terminal SAL side) of the two symmetrical circuit parts is cut off, and the determination reference value is changed. Then, since the current IL decreases, data 0 is output from the current sense amplifier 2500 while writing is not sufficient. If sufficient writing can be performed, the current IL becomes larger than the current IR, and the data from the current sense amplifier 2500 changes to 1. Therefore, the writing is terminated at that time.

  A transistor 2505 that is a switching element, a transistor 2506 that is a switching element, a signal transmission device (not shown) that applies a signal VRVL to a control terminal of the transistor 2505, and a signal transmission device that applies a signal VRVR to a control terminal of the transistor 2506 ( (Not shown) constitutes a current path interrupting unit which is an erroneous information writing preventing unit.

  The resistance ratio (or current ratio) of the transistor 2508 which is a switching element (transistor 2509 which is a switching element) and the transistor 2510 which is a switching element (the transistor 2511 which is a switching element) depends on the endurance of the memory cell. It is set according to characteristics (rewriting characteristics) and retention characteristics (holding characteristics). In the above, the signal VRYL and the signal VRYR are both set to High during normal reading and one is set to Low during write verification. Conversely, VRYL and VRYR are both set to Low during normal reading. At the time of write verification, the other may be made High.

(Fifth embodiment)
FIG. 19 is a diagram showing a current sense amplifier used in the semiconductor memory device according to the fifth embodiment of the present invention.

  The semiconductor memory device of the fifth embodiment has a configuration in which the current sense amplifier 109 is replaced with a current sense amplifier 2600 in the semiconductor memory device of the third embodiment. In FIG. 19, reference numerals 2601 to 2611 denote transistors.

  The current sense amplifier 2600 also performs the same operation as the current sense amplifier 109 of the third embodiment in FIG. When the bit line BLL is connected to the input terminal SAL, the voltage of the input terminal SAL is a division ratio of the resistance of the transistor 2601 which is a switching element to which BIAS is input and the resistance of the memory cell MC0 (reciprocal of current). Determined. Similarly, when the bit line BLR is connected to the input terminal SAR, the voltage of the input terminal SAR is the resistance of the transistor 2602 which is a switching element to which BIAS is input and the resistance of the memory cell MC1 (reciprocal of current). Determined by the split ratio. The resistance of the transistor 2601 is set to be the same as the resistance of the transistor 2602.

  In the normal reading operation, in the transistors 2609 and 2610 arranged symmetrically, the input signal SAENL input to the control terminal of the transistor 2609 on the input terminal SAL side and the control terminal of the transistor 2610 on the input terminal SAR side are input. Both the input signals SAENR are set to High simultaneously with the input signal SAEN input to the control terminal of the transistor 2611.

  In the case of data 0, since the current (resistance) of the memory cell MC1 is smaller (larger) than the current (resistance) of the memory cell MC0, the voltage of the input terminal SAR is higher than that of the input terminal SAL. The current flowing in the circuit portion on the input terminal SAR side of the two symmetrical circuit portions shown in FIG. 19 is applied to the circuit portion on the input terminal SAL side in the two symmetrical circuit portions shown in FIG. It becomes smaller than the flowing current. Then, the output signal DATA becomes Low. On the other hand, in the case of data 1, since the current (resistance) of the memory cell MC0 is smaller (larger) than the current (resistance) of the memory cell MC1, the voltage of the input terminal SAL becomes higher than the voltage of the input terminal SAR. The current IR is larger than the current IL. The output signal DATA is High. In the fifth embodiment as well, 1 bit is stored in two memory cells. Then, a memory cell having a storage node (for example, storage node 1 or 4 in the example shown in FIG. 16) that does not perform writing among storage nodes used for writing information is used as a memory cell for verification.

  Next, writing will be described. For example, when writing data 0, the storage node 1 remains in the erased state, and the storage node 4 is written. In the current sense amplifier 2600 of FIG. 19, the signal SAENR is kept low because the larger of the current IL and current IR is in the write state. That is, a part of the current path on the right side is cut off, and the determination reference value is changed. Then, since the current IR decreases, data 1 is output from the current sense amplifier 2600 while writing is not sufficient. If sufficient writing can be performed, the current IR becomes larger than the current IL, and the data from the current sense amplifier 2600 changes to 0, so that the writing ends at that time.

  On the other hand, when data 1 is written, data is written to the storage node 1 while the storage node 4 remains in the erased state. In the current sense amplifier 2600 of FIG. 19, among the current IL and current IR, the one with the larger current is in the write state, so SAENL is kept low. That is, a part of the current path on the left side is cut off, and the determination reference value is changed. Then, since the current IL decreases, data 0 is output from the current sense amplifier 2600 while writing is not sufficient. If sufficient writing can be performed, the current IL becomes larger than the current IR, and the data from the current sense amplifier 2600 changes to 1. Therefore, the writing ends at that time.

  A transistor 2609 that is a switching element, a transistor 2610 that is a switching element, a signal transmission device (not shown) that applies a signal SAENL to the control terminal of the transistor 2609, and a signal transmission device that applies a signal SAENR to the control terminal of the transistor 2610 ( (Not shown) constitutes a current path interrupting unit which is an erroneous information writing preventing unit.

  The endurance of the memory cell depends on the resistance ratio (or current ratio) between the transistor 2605 which is a switching element (transistor 2606 which is a switching element) and the transistor 2607 which is a switching element (the transistor 2608 which is a switching element). It is set according to characteristics (rewriting characteristics) and retention characteristics (holding characteristics). In the above, both the signal SAENL and the signal SAENR are set to High during normal reading and one of them is set to Low at the time of writing verification. Conversely, the signal SAENL and the signal SAENR are both set to Low during normal reading. At the time of write verification, the other may be made High.

  As is apparent from any of the above-described embodiments, the verification memory cell is a pair of memory cells that perform normal reading, and therefore, a certain reference value or a specific verification memory cell is used. The margin for endurance and retention can be increased as compared with the case where the memory cell is shared for verification operations of a large number of memory cells.

  FIG. 20 is a block diagram showing a digital camera 300 which is an embodiment of the electronic apparatus of the present invention.

  The digital camera 300 includes a nonvolatile memory 308 and a nonvolatile memory 319 made of the semiconductor storage device of the present invention. In the digital camera 300, the nonvolatile memory 308 is used for storing captured images, while the nonvolatile memory 319 is used for storing variation correction values for the liquid crystal panel 322.

  In the digital camera 300, when the power switch 301 is turned on by an operator, the power supplied from the battery 302 is transformed to a predetermined voltage by the DC / DC converter 303 and supplied to each component. Light entering from the lens 316 is converted into current by the CCD 318, converted into a digital signal by the A / D converter 320, and input to the data buffer 311 of the video processing unit 310. In FIG. 20, reference numeral 317 denotes an optical system driving unit. The signal input to the data buffer 311 is processed by the MPEG processing unit 313 to become a video signal through the video encoder 314, and is displayed on the liquid crystal panel 322 through the liquid crystal driver 321. At this time, the liquid crystal driver 321 corrects variations in the liquid crystal panel 322 (for example, variations in hues that differ for each liquid crystal panel) using data in the built-in nonvolatile memory 319. When the shutter 304 is pressed by the operator, the information in the data buffer 311 is processed as a still image via the JPEG processing unit 312 and recorded in the flash memory 308 which is a nonvolatile memory. In the flash memory 308, system programs and the like are recorded in addition to photographed image information. The DRAM 307 is used for temporary storage of data generated in various processes of the CPU 306 and the video processing unit 310.

  The nonvolatile memories 308 and 319 of the digital camera 300 need to have high data reliability over long-term storage. Here, since the nonvolatile memories 308 and 319 compare the current values in the left and right directions, the gap between the distributions of the cell current values of data 0 and data 1 becomes extremely narrow or overlaps. Even if this happens, the memory cell information can be read accurately. Therefore, the digital camera 300 including the nonvolatile memories 308 and 319 can achieve cost reduction, downsizing, and high reliability.

  In the above embodiment, the semiconductor memory device of the present invention is mounted on the digital camera 300. However, it is preferable that the semiconductor memory device of the present invention is mounted on a mobile phone. A flash memory used in a cellular phone records a communication protocol in addition to image data, and therefore requires high reliability. Therefore, when the semiconductor memory device of the present invention is mounted on a mobile phone, the quality of the mobile phone can be remarkably improved. The semiconductor memory device of the present invention is applied to electronic devices other than digital cameras and mobile phones, such as digital audio recorders, DVD devices, color tone adjustment circuits for liquid crystal display devices, music recording / playback devices, video devices, audio devices, copying devices, etc. Needless to say, it can be installed.

1 is a diagram showing a semiconductor memory device according to a first embodiment of the present invention. It is a schematic diagram which shows the side wall memory used as a memory cell in 1st Embodiment. It is a figure which shows a part of circuit structure of the voltage sense amplifier used in 1st Embodiment. It is a figure which shows an example of the 1st pulse generation circuit which the voltage sense amplifier used by 1st Embodiment has. It is a figure which shows an example of the 2nd pulse generation circuit which the voltage sense amplifier used by 1st Embodiment has. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is sectional drawing which shows the structure of the memory which can be used by this invention. It is a figure which shows the semiconductor memory device of 2nd Embodiment of this invention. It is a figure which shows an example of the 1st pulse generation circuit which the voltage sense amplifier used by 2nd Embodiment has. It is a figure which shows the semiconductor memory device of 3rd Embodiment of this invention. It is a circuit diagram which shows the current sense amplifier used in 3rd Embodiment. It is a circuit diagram which shows the current sense amplifier used for the semiconductor memory device of 4th Embodiment of this invention. It is a circuit diagram which shows the current sense amplifier used for the semiconductor memory device of 5th Embodiment of this invention. It is a block diagram which shows the digital camera which is one Embodiment of the electronic device of this invention.

DESCRIPTION OF SYMBOLS 100 Memory cell array 101 Bit line charging / discharging circuit 102 CUT signal generation circuit 103 1st pulse generation circuit 104 2nd pulse generation circuit 105 1st multiplexer 106 2nd multiplexer 107 Voltage sense amplifier 108 Bit line selection circuit 109, 2500, 2600 Current sense Amplifier 110 Pulse signal generation unit 111 Pulse width control circuit 112 First pulse generation circuit 113 Second pulse generation circuit 300 Digital camera 301 Power switch 302 Battery 303 DC / DC converter 304 Shutter 306 CPU
307 DRAM
308 Flash memory 310 Video processing unit 311 Data buffer 312 JPEG processing unit 313 MPEG processing unit 314 Video encoder 316 Lens 317 Optical system driving unit 318 CCD
319 Nonvolatile memory 320 A / D converter 321 Liquid crystal driver 322 Liquid crystal panel 500,600,900 Inverter array 2000 Side wall memory 2001 Substrate 2002 Gate insulating film 2003 First silicon nitride film 2004 Second silicon nitride film 2005 Word line 2006,2007 Silicon oxide film 2009, 2010 Diffusion layer 2011 First bit line 2012 Second bit line 2013 Second diffusion layer

Claims (6)

A voltage sense amplifier having a first input terminal and a second input terminal;
A storage area capable of storing information, a first memory cell having a first input / output terminal and a second input / output terminal;
A second memory cell having a storage area capable of storing information, a first input / output terminal connected to the second input / output terminal of the first memory cell, and a second input / output terminal;
A first bit line connected to the first input / output terminal of the first memory cell;
A second bit line connected to the second input / output terminal of the second memory cell;
A third bit line connected to the second input / output terminal of the first memory cell and the first input / output terminal of the second memory cell;
A bit line charge / discharge circuit for charging or discharging the first bit line, the second bit line, and the third bit line;
The first input terminal of the voltage sense amplifier having a first terminal connected to the first bit line, a second terminal connected to the first input terminal of the voltage sense amplifier, and a control terminal. A first switching element that contacts and separates the first bit line;
The second input terminal of the voltage sense amplifier having a first terminal connected to the second bit line, a second terminal connected to the second input terminal of the voltage sense amplifier, and a control terminal. A second switching element that contacts and separates the second bit line;
A first output terminal connected to the control terminal of the first switching element; a second output terminal connected to the control terminal of the second switching element; the control terminal of the first switching element; A pulse signal generator for outputting a pulse signal to the control terminal of the second switching element;
1 bit information is stored in the first memory cell and the second memory cell ;
The pulse signal generator is
In the read operation, a signal for taking in the voltage of the first bit line to the first input terminal of the sense amplifier is output to the control terminal of the first switching element, and the second bit line is While a signal for taking in the voltage to the second input terminal of the sense amplifier is output to the control terminal of the second switching element,
At the time of write verification, a pulse signal having a first pulse width is output to the control terminal of the first switching element, while a pulse signal having a second pulse width different from the first pulse width is output to the second switching element. A semiconductor memory device that outputs the control signal of the switching element . The semiconductor memory device according to claim 1,
The storage area of the first memory cell includes a first storage area and a second storage area capable of storing information independently of each other, and the storage area of the second memory cell includes a first storage capable of storing information independently of each other. A semiconductor memory device comprising a storage area and a second storage area. The semiconductor memory device according to claim 1,
The pulse signal generator is
A first pulse generation circuit that outputs a pulse signal having a first pulse width;
A second pulse generating circuit for outputting a pulse signal having a second pulse width different from the first pulse width;
A first multiplexer having a first input terminal to which a signal from the first pulse generation circuit is input, a second input terminal to which a signal from the second pulse generation circuit is input, and a control signal input terminal;
A second multiplexer having a first input terminal to which a signal from the first pulse generation circuit is input, a second input terminal to which a signal from the second pulse generation circuit is input, and a control signal input terminal;
A first output terminal connected to the control signal input terminal of the first multiplexer; and a second output terminal connected to the control signal input terminal of the second multiplexer. The first multiplexer outputs the first output terminal. Controls whether a signal is a signal from the first pulse generation circuit or a signal from the second pulse generation circuit, and outputs a signal output from the second multiplexer to the first pulse generation A semiconductor memory device comprising: a pulse width control circuit that controls whether a signal is output from a circuit or a signal from the second pulse generation circuit. The semiconductor memory device according to claim 1,
The pulse signal generator includes a first pulse generation circuit capable of outputting a first pulse signal and a second pulse signal having a pulse width different from that of the first pulse signal;
A second pulse generation circuit identical to the first pulse generation circuit;
Controls whether the signal output from the first pulse generation circuit is the first pulse signal or the second pulse signal, and the signal output from the second pulse generation circuit is the first pulse signal. A semiconductor memory device comprising: a pulse width control circuit that controls whether to use one pulse signal or the second pulse signal. The semiconductor memory device according to claim 2 ,
The semiconductor memory device, wherein the first memory cell and the second memory cell are sidewall memories. An electronic apparatus comprising the semiconductor memory device according to any one of claims 1 to 5.

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