JP2007140152A - Image display device, driving circuit for display, and driving method for display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique that suitably improves the picture quality of a display image by excellently correcting the picture quality in processing wherein odd-numbered pixels and even-numbered pixels of a full-HD signal are separated into two phases. <P>SOLUTION: In the image display device equipped with a plurality of scanning lines, a scanning line control circuit, a plurality of signal lines, a signal line control circuit, an electron source connected to intersections of the plurality of scanning lines and the plurality of signal lines, and a correcting circuit which corrects a video signal to compensate a signal line current and a voltage drop caused by wiring resistance included in a scanning line, the correcting circuit inputs RGB signals separated into the two phases of the even-numbered pixels and odd-numbered pixels and computes correction quantities in units of N (N≥1) groups each comprising electron sources of RGB for a plurality of pixels including even-numbered pixels and odd-numbered pixels to which a driving voltage corresponding to an input video signal is applied in the same timing. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an image quality correction technique for an image display device such as a matrix type image display device (hereinafter abbreviated as “FED”) using an electron-emitting device such as a thin film electron source, and includes a correction circuit. The present invention relates to an image display device, a display drive circuit, and a display drive method.

  In the FED, an electron source is arranged at each intersection of a plurality of scanning lines extending in the horizontal direction and a plurality of signal lines extending in the vertical direction, and applied to the scanning voltage applied to the scanning line and the signal line (to the video signal). The electron source is configured to be driven by a signal voltage (accordingly).

  In such an FED, a voltage drop occurs mainly due to the wiring resistance of the scanning line, so that image quality deterioration such as luminance unevenness occurs. As a conventional technique for correcting the image quality deterioration, for example, a technique described in Patent Document 1 is known.

Patent Document 1 discloses a technique in which one scanning line is divided into a plurality of blocks (four blocks), a voltage drop amount is calculated based on an image signal for each block, and correction corresponding to this is performed.
JP 2002-229506 A

  On the other hand, in recent years, the resolution of display panels has been increased, and LCDs and PDP panels corresponding to full HD images with horizontal 1920 pixels and vertical 1080 lines have been shipped, and full HD resolution is also required in FEDs.

  In a full HD video signal, the sampling clock (hereinafter referred to as dot clock) of the video signal is generally as high as 148 MHz, and it is necessary to use an expensive LSI process in order to perform signal processing with the dot clock. Therefore, in order to enable full HD signal processing even with an inexpensive LSI process, the video signal is separated into two phases of odd pixels and even pixels, and the process of dropping the dot clock to 1/2 (74 MHz) of 148 MHz is normally performed. Yes.

  However, in Patent Document 1, since one scanning line is divided into four blocks, highly accurate correction cannot be performed. Further, no consideration is given to how the correction amount is calculated in the process of separating the odd and even pixels into two phases as described above.

  An object of the present invention is to provide a technique suitable for improving the image quality of a display image by satisfactorily correcting the image quality even in the process of separating the odd and even pixels of a full HD signal into two phases.

  According to the present invention, a plurality of scanning lines, a scanning line control circuit that is connected to at least left and right ends of the plurality of scanning lines and sequentially applies a scanning voltage to the plurality of scanning lines, and a plurality of signal lines, A signal line control circuit that is connected to the plurality of signal lines and applies a drive voltage corresponding to the input video signal to the plurality of signal lines, and an intersection of the plurality of scanning lines and the plurality of signal lines And an electron source that emits electrons according to a potential difference between the scanning voltage and the driving voltage, a signal line current flowing from the electron source to the scanning line, and a voltage drop caused by a wiring resistance included in the scanning line. And a correction circuit that corrects the video signal. The correction circuit receives an RGB signal separated into two phases of an even pixel and an odd pixel, and a drive voltage corresponding to the input video signal is applied at the same timing. Even pixels and odd numbers The RGB electron sources of a plurality of pixels including the element as one group, characterized by calculating a correction amount the first group of N (N ≧ 1) combined units. The range of N is preferably 1 to 5. The upper limit of this range is a detection limit of human image change, that is, a range in which the luminance drop caused by the wiring resistance is 1% or less of the maximum gradation.

  According to the present invention, it is possible to perform good image quality correction in the two-phase separation processing of the odd and even pixels of the full HD signal, and it is possible to display a high-quality image.

  The best mode for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 shows a first embodiment of an electron-emitting device type image display apparatus according to the present invention. In the present embodiment, an electron emission element type image display device of a passive matrix drive type having an MIM (Metal-Insulator-metal) type electron source as an electron source will be described as an example. However, the present invention can be similarly applied to electron sources other than MIM, for example, an SCE (Surface Conduction Electron Emitter) type, a carbon nanotube type, a BSD (Ballistic electron Surface-emitting Device) type, and a Spindt type. In the following, an example in which two scanning line control circuits 501 and 502 are provided at both ends of a scanning line will be described. However, it goes without saying that the present invention can be applied even if only one of the scanning line control circuits is used.

  The video signal is input to the video signal input terminal 3 and supplied to the signal processing circuit 8. The signal processing circuit 8 includes a correction circuit 10 that corrects the voltage drop described in detail in FIG. The correction circuit 10 functions to compensate for a voltage drop generated by the wiring resistance of the scanning lines 51 to 55. Details of this operation will be described later.

  Horizontal and vertical synchronization signals corresponding to the input video signal are input to the synchronization signal input terminal 1 and supplied to the timing controller 2. The timing controller 2 generates timing pulses synchronized with the horizontal and vertical synchronization signals and supplies them to the scanning line control circuits 501 and 502.

  On the other hand, the display panel 6 has a plurality of scanning lines 51 to 55 formed so as to extend in the horizontal direction of the screen (left and right direction of the paper surface) and are arranged in the vertical direction of the screen (up and down direction of the paper surface). Further, a plurality of signal lines 41 to 45 formed so as to extend in the vertical direction of the screen (up and down direction of the paper surface) are arranged side by side in the horizontal direction of the screen (left and right direction of the screen). The scanning lines 51 to 55 and the signal lines 41 to 45 are orthogonal to each other, and an electron source (electron emitting element) connected to each scanning line and each signal line is disposed at each intersection. . As a result, the plurality of electron sources are arranged in a matrix.

  Scan line control circuits 501 and 502 are connected to the left and right ends of the scan lines 51 to 55. The scanning line control circuits 501 and 502 respectively apply scanning voltages for selecting the scanning lines 51 to 55 to the scanning lines 51 to 55 in synchronization with the timing pulse from the timing controller 2. Supply against. In other words, the scanning line control circuits 501 and 502 sequentially apply a horizontal period scanning voltage to the scanning lines 51 to 55 to select one or two rows of electron sources sequentially from the top in the horizontal period and perform vertical scanning. Is what you do.

  A signal line control circuit 4 that is a signal voltage supply circuit is connected to the upper ends of the signal lines 41 to 45. The signal line control circuit 4 generates a signal corresponding to each signal line (electron source) based on the video signal supplied from the signal processing circuit 10 and supplies the signal line to each signal line.

  When a signal voltage from the signal line control circuit 4 is applied to each electron source connected to the scanning line selected by the scanning voltage, a potential difference between the scanning voltage and the signal voltage is given to each electron source. When this potential difference exceeds a predetermined threshold, the electron source emits electrons. The amount of electrons emitted from the electron source is approximately proportional to the potential difference when the potential difference is greater than or equal to a threshold value. When the signal voltage is positive, the scanning voltage is negative. When the signal voltage is negative, the scanning voltage is positive. A phosphor and an accelerating electrode (not shown) are provided at positions facing each electron source. The space between the electron source and the phosphor is a vacuum atmosphere. The electrons emitted from the electron source are accelerated by the high voltage applied to the accelerating electrode by the high voltage control circuit 7, travel in the vacuum, and collide with the phosphor. As a result, the phosphor is excited to emit light, and the light is emitted to the outside through a transparent glass substrate (not shown). As a result, an image is formed on the FED.

  FIG. 3 shows the change characteristic of the scanning voltage with respect to the horizontal position of each electron source in the FED having such a configuration. The solid line in FIG. 3 indicates the scanning voltage supplied from the scanning line control circuits 501 and 502, and the dotted line indicates the horizontal position-scanning voltage characteristic of the electron source. As shown in FIG. 3, a voltage drop occurs in the scanning voltage according to the horizontal position of the electron source, and the voltage drop is the largest in the central portion.

  Here, the voltage drop in the scanning voltage according to the horizontal position is caused by the voltage drop due to the wiring resistance of the scanning line. That is, when the potential difference between the scanning voltage Vscan and the signal voltage Vdata exceeds a predetermined threshold, a current flows from the signal line to the scanning line, and a voltage drop occurs due to this current and the wiring resistance of the scanning line. In addition, as the amount of information displayed in one horizontal period, such as horizontal line display, the current to the scanning line increases and the amount of voltage drop also increases.

  The details of the correction circuit according to the present invention for compensating for such a voltage drop will be described below with reference to FIG. FIG. 2 is a block diagram for explaining a specific example of the correction circuit 10 included in the signal processing circuit 8. The correction circuit 10 shown in FIG. 2 is configured to correct the wiring resistance of the scanning line. In FIG. 2, RGB signals separated into two phases of odd pixels and even pixels are input to video signal input terminals 31o to 33o and 31e to 33e, respectively. In FIG. 2, a block with “o” in the symbol means an odd pixel processing system, and a block with “e” in the symbol means an even pixel processing system. Blocks with the same prefix number have the same function.

  Next, the gradation current conversion blocks 11o and 11e convert the digital gradation signals of the RGB image signals input to the image signal input terminals 31o to 33o and 31e to 33e into current values (iro, igo, ibo, ire, image, ibe). The addition operation block 17 adds these two-phase RGB current values.

  Here, an equivalent model of an electron source is used in FIG. 4 to explain the purpose of adding the current values of two-phase RGB. FIG. 4A shows a normal electron source model in which current values are not added. Reference numerals 20R, 20G, 20B, 21R, 21G, and 21B are signal lines, which are connected to the signal line control circuit 4, and a signal voltage corresponding to the display video signal is supplied to each signal line. Each signal line is connected to an electron source, and the electron source generates a current when a voltage is applied as shown in FIG. Accordingly, in FIG. 4, the electron sources are the current sources 22R, 22G, 22B, 23R, 23G, and 23B. Each electron source is commonly connected to the scanning line 28, but wiring resistors 24R, 24G, 24B, 25R, 25G, and 25B exist between the contact points of the respective electron sources and the scanning line 28. The current sources 22R, 23R correspond to the R color, the current sources 22G, 23G correspond to the G color, the current sources 22B, 23B correspond to the B color, and the current sources 22R, 22G, 22B correspond to the odd pixels, and the current sources 23R, 23G, 23B It corresponds to even pixels. When the signal voltage Vdata corresponding to the video signal is applied to each of the current sources 22R, 22G, 22B, 23R, 23G, and 23B from the signal line control circuit 4, and the scanning voltage is applied to the scanning line 28, the signal voltage The signal line currents iro, igo, ibo, ire, ige and ibe corresponding to the above are generated and flow into the scanning line 28. Each signal line current is divided in the left-right direction when viewed from the contact point between the electron source and the scanning line 28, and the ratio follows the Kirchhoff's theorem. That is, it can be calculated by the wiring resistance ratio viewed from the contact point between the electron source and the scanning line 28. The scanning line currents Iro, Igo, Ibo, Ire, Ige, and Ibe are determined by adding all these signal line currents. The product of the scanning line current and the scanning line resistance is a voltage drop amount. For example, the voltage drop amount of the R pixel of the odd pixel is Iro × R1, the G color is Igo × R1, and the B color is Ibo × R1, and the total voltage drop amount of the odd pixel is Iro × R1 + Igo × R1 + Ibo × R1. Similarly, the total voltage drop amount of even pixels is Ire × R1 + Ige × R1 + Ibe × R1. If these are arranged, it becomes (Iro + Igo + Ibo + Ire + Ige + Ibe) × R1. Adjacent Iro, Igo, Ibo, Ire, Ige, and Ibe can be considered to have substantially the same current value, so that Iro≈Igo≈Ibo≈Ire≈Ige≈Ibe, and therefore can be approximated as 6 × Iro × R1. From a different viewpoint, this indicates that the amount of voltage drop seen in units of two pixels can be calculated by the scanning line current (Iro × (R1 × 6)) flowing through six scanning line resistors R1. By applying this concept, an electron source model in which current values are added as shown in FIG. 4B can be assumed.

  In FIG. 4B, the signal line and the current source are the same, and the difference is the contact point between the current source and the scanning line 28. In FIG. 4B, the contact points of the six current sources for two pixels to the scanning line 28 are made common, and the wiring resistance 26 is combined into one R1 × 6. Further, since the contact points of the six current sources to the scanning line 28 are made common, the current irgb (n) flowing to the scanning line 28 is iro + igo + ibo + ire + ige + ibe. Each signal line current is divided in the left-right direction when viewed from the contact point between the electron source and the scanning line 28, and the ratio follows the Kirchhoff's theorem as in FIG. The scanning line current Irgb (n) is determined by adding all these signal line currents. The product of the scanning line current and the scanning line resistance is a voltage drop amount. For example, the amount of voltage drop for odd and even pixels is Irgb (n) × R1 × 6. Since the models of FIGS. 4A and 4B are electrically equivalent, the correction circuit 10 for calculating the voltage drop amount may be designed based on FIG. 4B. As described above, when the electron source is viewed in units of two pixels, the signal line currents of the six current sources of RGB may be added (iro + igo + ibo + ire + ige + ibe).

  The addition operation block 17 in FIG. 2 uses this concept and adds the RGB signals converted into current values (iro, igo, ibo, ire, ige, ibe) by the gradation current conversion blocks 11o and 11e. FIG. 6 is a timing chart showing the operation. iro is a signal line current of an odd-numbered pixel of R color, and ire is a signal line current of an even-numbered pixel of R color, and has the same reference numerals as those in FIGS. Assuming that the leftmost pixel of the display panel 6 is the first pixel, iro is an odd pixel, so signal line currents of odd-numbered pixels are sequentially output in the order of first, third, and fifth. Similarly, since ire is an even-numbered pixel, signal line currents of even-numbered pixels are sequentially output in the order of No. 2, No. 4, and No. 6. In addition, No. 1 and No. 2 are output at the same timing, and No. 3, No. 4, No. 5, No. 6 and the like are the same. By separating the pixels into even and odd numbers in parallel as described above, the dot clock frequency can be halved. The same applies to other igo, ige, ibo, and ibe. Next, the result of adding the signal line currents is irgb (n). In FIG. 6, for example, the result of adding the first and second pixels is irgb (1), and the logical timing is set so that the delay amount by the addition operation is zero. In addition, since a substantial delay amount is generated in the addition operation, latch processing by the D flip-flop is generally performed after the addition operation in consideration of the setup / hold time with the subsequent circuit, but is omitted here.

  In the scanning line current calculation block 13 of FIG. 2, based on Kirchhoff's theorem, all signal line currents irgb (n) of one horizontal period calculated by the gradation current conversion blocks 11o and 11e, that is, one scanning line. Product-sum operation is performed on all signal line currents flowing from all the signal lines 41 to 45 connected to, and a scanning line current Irgb (n) flowing to one scanning line resistor R1 is calculated. Next, the voltage drop calculation block 14 multiplies the scanning line resistance I1 by the scanning line current Irgb (n) calculated by the scanning line current calculation block 13 to calculate the voltage drop amount ΔV (n). On the other hand, the RGB current values of the gradation current conversion blocks 11o and 11e are sent to the addition operation block 17 and are also input to the delay circuits 12o and 12e. The delay circuits 12o and 12e are composed of FIFO memories, store each RGB current value for one horizontal period, and output the current value stored in the next horizontal period, thereby delaying each RGB current value by one horizontal period. Let This is because when the scanning line current calculation block 13 calculates all signal line currents in one horizontal period, the calculation result of the scanning line current calculation block 13 is one horizontal period later. In order to synchronize, each of the RGB current values is also delayed by one horizontal period by the delay circuits 12o and 12e. In the current-voltage conversion blocks 15o and 15e, each RGB current value delayed by one horizontal period is converted into a voltage value, and in the addition calculation blocks 16Ro, 16Go, 16Bo, 16Re, 16Ge, and 16Be, the same voltage drop amount as each RGB voltage value Add ΔV (n). The voltage drop can be corrected by adding the voltage drop amount ΔV (n) to the video signal. Finally, each RGB voltage value after adding the voltage drop amount in the voltage gradation conversion block is returned to the digital gradation signal.

  As described above, in the first embodiment of the present invention, RGB signals separated into two phases of even pixels and odd pixels are input, and drive voltages according to the input video signals are applied at the same timing. A plurality of RGB electron sources including even pixels and odd pixels are combined into one signal line as a group, and the voltage drop amount is calculated in units of the combined signal lines. Since the phase-separated RGB signal is processed, the calculation can be easily performed at the same timing. In particular, when drive voltages are applied to adjacent RGB signal lines, that is, six RGB signal lines for two pixels at the same timing, adjacent RGB signal lines, that is, RGB signal lines for two pixels. It is possible to process RGB signals separated into two phases such as full HD at high speed by virtually summing six signals into one signal line and calculating a voltage drop amount in units of the summed signal lines. Can be operated with an inexpensive LSI.

  Moreover, what is virtually assumed as one signal line may be, for example, for each adjacent RGB, and the correction amount can be calculated as a single signal line by combining a plurality of adjacent RGB units.

  Next, a specific example of the voltage correction amount in this embodiment is shown in FIG. First, FIG. 7A illustrates a case where the voltage drop amount is calculated for each of RGB and the correction amount is obtained, and the correction amount may be different for each RGB. This corresponds to the correction amount in the RGB individual equivalent model of FIG. On the other hand, FIG. 7B is a diagram in which the voltage drop amount is calculated for the two pixels (RGB total) of the present embodiment, and the correction amount is obtained. The correction amount is the same in the two RGB pixels. Even if the correction amount is the same in units of two pixels as shown in FIG. 7B, the color does not change after correction. This is because the correction amount for each RGB is small even when the voltage drop amount is calculated for each RGB as shown in FIG.

  However, when the unit of RGB total is 3 pixels or more, the change in the correction amount adjacent to the pixel gradually increases, so it is considered that the change in luminance and color can be visually observed at the change portion of the correction amount. Therefore, the unit of RGB total of the limit that can be visually observed is calculated as follows.

First, when the resolution of the panel is VGA, the number of pixels is 640, and the number of signal lines is 640 × 3 = 1920. As shown in FIG. 3, the change in the voltage drop amount is greatest at the left and right ends, and in the case of the left end, the voltage drop amount between R and G in the first pixel. Here, the luminance difference with which the luminance change can be visually confirmed is generally set to 1% or more. When the luminance is replaced with the applied voltage, for example, the applied voltage when displaying white is 3 Vpp, and if there is a voltage difference of 30 mVpp of 1%, the luminance difference can be visually observed. Therefore, if the voltage drop amount between R and G of the first pixel is ΔVm and the total number of RGB pixels is N,
ΔVm × 3 × N <30 mVpp
The maximum value of N that satisfies the above can be approximated to the unit of RGB summation that is visible. Therefore, N ′ = 30 mVpp / (ΔVm × 3) is calculated, and N ′ is rounded down to obtain N.

First, in order to obtain ΔVm, it is necessary to obtain the scanning line current Ir (1) between R and G of the first pixel. Ir (1) can calculate each signal line current (such as iro in FIG. 4) based on Kirchhoff's theorem, and if the nth signal line current is i (n),
Ir (1) = Σ ((1919−n) / 1919 × i (n)) (n: 1 to 1919)
It is represented by Here, if the video signal is all white display and i (n) at that time is 100 μA as a value in the case of general white, Ir (1) = 96 mA. Here, if the scanning line between R and G of the first pixel is R1, ΔVm = R1 × Ir (1), and if Rl is 9 mΩ as a general value,
ΔVm = 9mΩ × 96mA = 864μV
And
N ′ = 30 mVpp / (864 μV × 3) = 11.57
N = 11 is obtained.

  Thereby, if the total number of pixels of RGB is up to 11, the change in luminance cannot be visually observed. If the even and odd two pixels adjacent to each other are grouped as in this embodiment, since 11 ÷ 2 = 5.5, the change in luminance is not visible to five groups of adjacent even and odd pixels. .

  As described above, when the voltage drop amount is calculated by virtually adding a plurality of signal lines to one signal line, the error from the true correction data increases as the number of RGB combined pixels increases. For this reason, as calculated above, it is desirable that the total number of RGB pixels is such that the change in luminance is not visible.

  Note that the above calculation method is an example for obtaining the total number of RGB pixels in which changes in luminance and color are not visually recognized. Therefore, the voltage drop amount depends on the resolution of the panel and the scanning line voltage supply circuit, so that different values can be used. Further, the voltage drop amount between the leftmost R and G at which the voltage drop amount is maximum is used, but the voltage drop amount in the region where the voltage drop amount width is large may be used. Further, in the above example, a limit luminance change (detection limit) of 1% that is not visually recognized is used, but a limit luminance change (allowable limit) of 3% that can be allowed to be visually checked may be used.

  When the above correction is performed, when a video signal with a constant horizontal level is input as the input video signal, the drive voltage from the signal control circuit is as shown in FIG. A stepped output waveform is shown. At this time, in the case where the scanning line control circuit as in this embodiment is arranged at both ends of the scanning line, the voltage drop is maximized at the center of the scanning line, so the output waveform from the signal control circuit Has a staircase shape with a maximum at the center. On the other hand, in the case where the scanning line control circuit is provided at one end of the scanning line, the voltage drop is maximized at the other end side not provided with the scanning line control circuit, so that the output waveform from the signal control circuit Gradually rises from the scanning line control circuit side and has a staircase shape that becomes maximum at the other end side.

  With the configuration as described above, it is possible to provide a technique suitable for calculating the correction amount with a simpler configuration than before and improving the image quality.

  Next, a second embodiment of the FED type image display device according to the present invention will be described. FIG. 8 is a configuration example showing the second embodiment of the present invention. In FIG. 8, the same reference numerals as those in FIG. 2 of the first embodiment have the same functions. The second embodiment is different from the first embodiment shown in FIG. 2 in that the smoothing processing circuit 19 performs a smoothing process on the voltage drop amount ΔV (n). Thereby, it is possible to calculate the correction data with higher accuracy.

  The operation of the second embodiment will be described. Since the voltage drop calculation block 14 calculates the voltage drop amount ΔV (n) in units of two pixels, it is the same as that of the first embodiment, and thus the description thereof is omitted. The voltage drop amount ΔV (n) is input to the smoothing processing circuit 19 and smoothed so as to change gently. A specific processing example is shown in FIG. FIG. 9A shows the input voltage drop amount ΔV (n), where ΔV (n) changes in units of two pixels. FIG. 9B shows the output of the smoothing processing circuit 19. ΔV (n) is divided into six, and the amount of voltage drop is changed in each divided region. The calculation method of the change amount is as follows, for example. First, change points of the voltage drop amount ΔV (n) in FIG. Here, a straight line connecting points A and B is calculated as shown by a one-dot chain line in FIG. 9B, and the distance between points A and B is divided into six. The intersection of the alternate long and short dash line and 6 divisions is set as the voltage drop amount of the divided region, and is set as ΔVro, ΔVgo, ΔVbo, ΔVre, ΔVge, and ΔVbe, respectively. The smoothing processing circuit 19 performs such interpolation calculation processing. As shown in FIG. 8, the voltage drop amounts are input to the addition operation blocks 16Ro, 16Go, 16Bo, 16Re, 16Ge, and 16Be, respectively, and added to the video signal. As a result, it is possible to obtain the same effect as when correction data is calculated for each of RGB shown in FIG.

  Note that the calculation method of the amount of change is an example, and the voltage drop amount may be calculated by other interpolation methods, for example, non-linear such as spline interpolation or Lagrange interpolation. In the above calculation method, the number of divisions is 6. However, the number of divisions is not limited. For example, the number of divisions may be divided into two, and ΔV (n) may be changed in units of one pixel.

  If this embodiment is applied, ΔV (n) is roughly calculated by setting the calculation unit of the voltage drop amount ΔV (n) to a plurality of pixels of 3 pixels or more, and is passed through the smoothing processing circuit 19 to obtain ΔV (n ) Can be restored to one pixel unit or less, and the effect of reducing the scale of the arithmetic processing circuit can be obtained while maintaining the correction accuracy.

1 is a block diagram showing a first embodiment of an image display device according to the present invention. FIG. 2 is a block diagram illustrating a specific example of a correction circuit 10 illustrated in FIG. 1. It is a figure explaining the characteristic of the scanning voltage of the image display apparatus which concerns on this invention. It is a block diagram which shows the equivalent model of the electron source which concerns on this invention. It is a block diagram which shows the applied voltage-current characteristic of the electron source which concerns on this invention. FIG. 3 is a block diagram showing an operation of the correction circuit 10 shown in FIG. 2. It is a block diagram which shows the characteristic of the correction data based on this invention. It is a block diagram which shows 2nd Embodiment of the image display apparatus which concerns on this invention. FIG. 9 is a block diagram illustrating an operation of the smoothing processing circuit 19 illustrated in FIG. 8.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Horizontal / vertical synchronizing signal input terminal 2 Timing controller 3 Image signal input terminal 4 Signal line control circuit 6 Display panel 7 High voltage control circuit 8 Signal processing circuit
10 Correction circuit
11o, 11e Gradation current conversion block 12o, 12e Delay circuit 13 Scan line current value calculation block 14 Voltage drop calculation block 15o, 15e Current voltage conversion block 16Ro, 16Go, 16Bo, 16Re, 16Ge, 16Be, 17 Addition calculation block 18o , 18e Voltage gradation conversion block 19 Smoothing processing block 10 Signal processing circuit 20R, 20G, 20B, 21R, 21G, 21B Signal line 28 Scan line 22R, 22G, 22B, 23R, 23G, 23B Electron sources 24R, 24G, 24B, 25R, 25G, 25B, 26 Scanning line resistances 31o to 33o, 31e to 33e Video signal input terminals 41 to 45 Signal lines 51 to 55 Scanning lines 501 and 502 Scanning line control circuit

Claims (15)

In an image display device,
A plurality of scan lines;
A scanning line control circuit connected to at least one of the left and right ends of the plurality of scanning lines and sequentially applying a scanning voltage to the plurality of scanning lines;
Multiple signal lines,
A signal line control circuit that is connected to the plurality of signal lines and applies a driving voltage corresponding to the input video signal to the plurality of signal lines;
An electron source connected to intersections of the plurality of scanning lines and the plurality of signal lines, respectively, and emitting electrons in accordance with a potential difference between the scanning voltage and the driving voltage;
A correction circuit for correcting the video signal;
With
The correction circuit receives an RGB signal separated into two phases of an even pixel and an odd pixel, and a plurality of pixels including an even pixel and an odd pixel to which a driving voltage corresponding to the input video signal is applied at the same timing. An image display device characterized in that a correction amount is calculated in units of RGB electron sources as one group and N groups (N ≧ 1).   The image display apparatus according to claim 1, wherein the RGB electron sources of a plurality of pixels including the even pixels and the odd pixels are six RGB electron sources of adjacent even pixels and odd pixels. The correction circuit corrects the video signal so as to compensate for a voltage drop caused by a scanning line current flowing from the electron source to the scanning line or from the scanning line to the electron source and a wiring resistance included in the scanning line. Item 4. The image display device according to Item 1.   The image display apparatus according to claim 1, wherein the maximum value of N is determined based on 1% of the maximum applied voltage applied by the signal line control circuit.   The image display apparatus according to claim 1, wherein a range of the value of N is 1 ≦ N ≦ 5. In the correction circuit,
6 electron sources of RGB of adjacent even-numbered pixels and odd-numbered pixels are set as one group, and the unit in which the one group is grouped into N (N ≧ 1) is defined as one block, and each signal line current in the one block is added. 2. The image display apparatus according to claim 1, wherein the result is a signal line current of one block, and a correction amount for compensating for the voltage drop is calculated by performing a product-sum operation on the signal line current of each block. In the correction circuit,
2. The image according to claim 1, wherein the correction amount has the same value for each block, and the correction amount having the same value is added to RGB of adjacent even-numbered pixels and odd-numbered pixels of the input video signal. Display device. In the correction circuit,
2. The correction amount in one block unit is interpolated from two calculated correction amounts in adjacent block units, and a different correction amount is added to each electron source in one block unit. The image display device described. In the correction circuit,
The image display apparatus according to claim 1, wherein the correction amount in one block unit is interpolated by linear interpolation or nonlinear interpolation. A plurality of scan lines;
Multiple signal lines,
A display driving circuit for a display panel, comprising: an electron source that is connected to each of intersections of the plurality of scanning lines and the plurality of signal lines and emits electrons in accordance with a potential difference between the scanning voltage and the driving voltage. There,
A scanning line control circuit connected to at least one of the left and right ends of the plurality of scanning lines and sequentially applying a scanning voltage to the plurality of scanning lines;
A signal line control circuit that is connected to the plurality of signal lines and applies a driving voltage corresponding to the input video signal to the plurality of signal lines;
A correction circuit for correcting the video signal,
The correction circuit receives an RGB signal separated into two phases of an even pixel and an odd pixel, and a plurality of pixels including an even pixel and an odd pixel to which a driving voltage corresponding to the input video signal is applied at the same timing. A display driving circuit characterized in that a correction amount is calculated in a unit of RGB electron sources as one group and N (N ≧ 1) of the one group.   11. The display drive circuit according to claim 10, wherein the RGB electron sources of the plurality of pixels including the even pixels and the odd pixels are six RGB electron sources of the adjacent even pixels and odd pixels. .   The correction circuit corrects the video signal so as to compensate for a voltage drop caused by a scanning line current flowing from the electron source to the scanning line or from the scanning line to the electron source and a wiring resistance included in the scanning line. Item 11. A display drive circuit according to Item 10. A plurality of scan lines;
Multiple signal lines,
A display driving method for a display panel, comprising: an electron source that is connected to intersections of the plurality of scanning lines and the plurality of signal lines, and emits electrons in accordance with a potential difference between the scanning voltage and the driving voltage. There,
A scanning line control step connected to at least one of the left and right ends of the plurality of scanning lines and sequentially applying a scanning voltage to the plurality of scanning lines;
A signal line control step that is connected to the plurality of signal lines and applies a drive voltage corresponding to the input video signal to the plurality of signal lines;
A correction step for correcting the video signal,
In the correction step, RGB signals separated into two phases of an even pixel and an odd pixel are input, and a plurality of pixels including an even pixel and an odd pixel to which a driving voltage corresponding to the input video signal is applied at the same timing are input. A display driving method characterized in that a correction amount is calculated in units of RGB electron sources as one group and N (N ≧ 1) of the one group.   In the correction step, the RGB electron sources of the plurality of pixels including the even pixels and the odd pixels are grouped into six electron sources of RGB of the adjacent even pixels and odd pixels, and N groups ( 14. The display driving method according to claim 13, wherein the correction amount is calculated in a unit of N ≧ 1).   In the correction step, the video signal is corrected so as to compensate for a voltage drop caused by a scanning line current flowing from the electron source to the scanning line or from the scanning line to the electron source and a wiring resistance included in the scanning line. Item 14. The display driving method according to Item 13.

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