JP2003029694A - Picture display device and its display method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a picture display device capable of performing suitably and especially correction for luminance reduction caused by a voltage drop and its display method. SOLUTION: In this display device, a suitable current value corresponding to a true voltage drop is calculated by performing the calculation of a voltage drop with the current value of an initial set value first of all and by performing the calculation of a current value from a Vf-If characteristic and by comparing the current value obtained by this calculation with the current value of the previous time to obtain the difference and by converging the current value while repeating the calculation of the voltage drop by using the current value obtained again until the difference becomes equal to or smaller than a prescribed value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image of a television receiver or a display device for displaying an image by displaying an image using a plurality of display elements, for example, a television signal or a computer. The present invention relates to a display device and a display method thereof.

[0002]

2. Description of the Related Art A technique for performing correction in an image display device is disclosed in, for example, USP5659328, USP573436.
1 is disclosed.

[0003]

However, in the case of the prior art as described above, there is a problem of realizing suitable correction in an image display device in which a plurality of display elements are connected by using a common wiring. To do. Considering as a specific example the case where display elements are arranged in a matrix and an image is displayed by sequential scanning, for example, display brightness may be uneven due to the influence of a voltage drop generated on the scanning wiring.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide an image display device and an image display device thereof which particularly suitably perform correction for a decrease in luminance due to a voltage drop. To provide a display method.

[0005]

One of the inventions of the image display device according to the present application is configured as follows.

In the image display device, a plurality of scanning wirings, a plurality of modulation wirings that are non-parallel to the scanning wirings, and a plurality of scanning wirings and a plurality of modulation wirings are provided corresponding to respective intersections. A plurality of display elements respectively connected to the scanning wirings and the corresponding modulation wirings, and a modulation signal corresponding to an image signal input to each of the modulation wirings, which sequentially supplies selection signals to the scanning wirings. A correction data circuit for supplying a correction data to the modulation wiring, the correction data circuit generating a correction data based on the calculated value, and an image signal input with the correction data. And a correction circuit that generates the modulation signal based on the scanning signal, and the correction data circuit determines the scanning according to the image signal as a predetermined current flowing through the modulation wiring. A voltage drop calculation for calculating the voltage drop on the line, a current value calculation for calculating the current value flowing through the modulation wiring when the voltage drop calculated by the previous voltage drop calculation occurs, and a previous current value calculation Further voltage drop calculation for calculating a voltage drop on the scanning wiring determined according to the image signal as a current value flowing in the modulation wiring, and a voltage drop calculated by the further voltage drop calculation Is a circuit for performing a further current value calculation for calculating a current value flowing in the modulation wiring when occurs, and a current value obtained by the further voltage drop calculation and the further current value calculation. Alternatively, the method is characterized in that one of the voltage drop values is kept until the difference from the current value or the voltage drop value obtained by the previous calculation becomes equal to or less than a predetermined value.

In the image display device, a plurality of scanning wirings, a plurality of modulation wirings that are not parallel to the scanning wirings, and a plurality of scanning wirings and a plurality of modulation wirings are provided corresponding to respective intersections. A plurality of display elements respectively connected to the scanning wirings and the corresponding modulation wirings, and a modulation signal corresponding to an image signal input to each of the modulation wirings, which sequentially supplies selection signals to the scanning wirings. A correction data circuit for supplying a correction data to the modulation wiring, the correction data circuit generating a correction data based on the calculated value, and an image signal input with the correction data. And a correction circuit that generates the modulation signal based on the scanning signal, and the correction data circuit determines the scanning according to the image signal as a predetermined current flowing through the modulation wiring. A voltage drop calculation for calculating the voltage drop on the line, a current value calculation for calculating the current value flowing through the modulation wiring when the voltage drop calculated by the previous voltage drop calculation occurs, and a previous current value calculation Further voltage drop calculation for calculating a voltage drop on the scanning wiring determined according to the image signal as a current value flowing in the modulation wiring, and a voltage drop calculated by the further voltage drop calculation And a further current value calculation for calculating a current value flowing in the modulation wiring when occurs, and the further voltage drop calculation and the further current value calculation are repeated a plurality of times. To do.

In the voltage drop calculation and the further voltage drop calculation, the plurality of modulation wirings are divided into blocks each including the plurality of modulation wirings, and a current flowing through the modulation wirings belonging to each block according to the image signal. It is preferable to perform the operation by collecting the values.

It is preferable that the pulse width of the modulated signal is corrected by the value of the correction data.

It is preferable that the modulation signal has a pulse width that changes according to the image signal.

In the image display device, a plurality of scanning wirings, a plurality of modulation wirings that are not parallel to the scanning wirings, and a plurality of scanning wirings and a plurality of modulation wirings are provided corresponding to respective intersections. A plurality of display elements respectively connected to the scanning wirings and the corresponding modulation wirings, and a modulation signal corresponding to an image signal input to each of the modulation wirings, which sequentially supplies selection signals to the scanning wirings. And a drive circuit for giving the drive circuit, the drive circuit, the current value flowing in the modulation wiring in accordance with the value of the statistical image signal corresponding to each of the plurality of display elements connected to one scanning wiring A memory for outputting the indicated value; a correction data circuit for generating correction data based on the output from the memory and the image signal; and the modulation signal based on the correction data and the input image signal. Characterized in that it has a modulation circuit for generating.

The memory for outputting the value indicating the value of the current flowing through the modulation wiring is not limited to a memory for storing the value of the current flowing through the modulation wiring, but may be a value indirectly indicating the value of the current flowing through the modulation wiring or the modulation. A value obtained from the current value flowing through the wiring, for example, a voltage drop amount or an emission current amount may be stored and output.

In the memory, the plurality of modulation wirings are divided into blocks each including the plurality of modulation wirings, and the plurality of modulation wirings belong to each of the blocks, and the currents flowing according to the image signal are collected into the modulation wirings. It is preferable to output a value indicating a current value flowing through the modulation wiring.

It is preferable that the correction data is data for correcting a display defect due to a voltage drop in the scanning wiring.

It is preferable that the pulse width of the modulated signal is corrected by the value of the correction data.

It is preferable that the modulation signal has a pulse width that changes according to the image signal.

A method of displaying an image display device, comprising: a plurality of scanning wirings; a plurality of modulation wirings not parallel to the scanning wirings;
A plurality of display elements which are provided corresponding to the respective intersections of the plurality of scanning wirings and the plurality of modulation wirings and are respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and selection signals are sequentially supplied to the scanning wirings. The image display device has a drive circuit that gives a modulation signal according to an image signal input to each of the modulation wirings, and the drive circuit calculates a current flowing through the modulation wirings. A correction data circuit for generating correction data based on the calculated value, and a modulation circuit for generating the modulation signal based on the correction data and an input image signal. , A voltage drop calculation for calculating a voltage drop on the scanning wiring that is determined according to the image signal as a predetermined current flowing through the modulation wiring, and a previous voltage drop calculation A current value calculation for calculating a current value flowing through the modulation wiring when a generated voltage drop occurs, and the current value calculated by the previous current value calculation is determined according to the image signal as flowing through the modulation wiring. A further voltage drop calculation for calculating a voltage drop on the scanning wiring, and a further current value calculation for calculating a current value flowing through the modulation wiring when the voltage drop calculated by the further voltage drop calculation occurs. , And further performing the further voltage drop calculation and the further current value calculation by comparing either the current value or the voltage drop value obtained by the calculation with the current value or the voltage drop value obtained by the previous calculation. The feature is that the process is performed until the difference becomes a predetermined value or less.

A method of displaying an image display device, comprising: a plurality of scanning wirings; and a plurality of modulation wirings that are non-parallel to the scanning wirings.
A plurality of display elements which are provided corresponding to the respective intersections of the plurality of scanning wirings and the plurality of modulation wirings and are respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and selection signals are sequentially supplied to the scanning wirings. The image display device has a drive circuit that gives a modulation signal according to an image signal input to each of the modulation wirings, and the drive circuit calculates a current flowing through the modulation wirings. A correction data circuit for generating correction data based on the calculated value, and a modulation circuit for generating the modulation signal based on the correction data and an input image signal. , A voltage drop calculation for calculating a voltage drop on the scanning wiring that is determined according to the image signal as a predetermined current flowing through the modulation wiring, and a previous voltage drop calculation A current value calculation for calculating a current value flowing through the modulation wiring when a generated voltage drop occurs, and the current value calculated by the previous current value calculation is determined according to the image signal as flowing through the modulation wiring. A further voltage drop calculation for calculating a voltage drop on the scanning wiring, and a further current value calculation for calculating a current value flowing through the modulation wiring when the voltage drop calculated by the further voltage drop calculation occurs. , And further performing the further voltage drop calculation and the further current value calculation a plurality of times.

A display method for an image display device, comprising: a plurality of scanning wirings; and a plurality of modulation wirings that are non-parallel to the scanning wirings.
A plurality of display elements which are provided corresponding to the respective intersections of the plurality of scanning wirings and the plurality of modulation wirings and are respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and selection signals are sequentially supplied to the scanning wirings. A drive circuit for supplying a modulation signal according to an image signal input to each of the modulation wirings, wherein the drive circuit is connected to one scanning wiring in a memory. A value indicating a current value flowing in the modulation wiring is output according to a value obtained by statistically comparing image signals corresponding to each of the elements, and a correction data circuit generates correction data based on the output from the memory and the image signal. The modulation circuit generates the modulation signal based on the correction data and the input image signal.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Preferred embodiments of the present invention will be illustratively described in detail below with reference to the drawings. However, the dimensions of the components described in this embodiment,
Unless otherwise specified, the material, the shape, the relative arrangement, and the like are not intended to limit the scope of the present invention thereto.

As the display element that can be adopted in the structure to which the invention of the present application can be applied, a cold cathode element, an EL element and the like can be mentioned. In the following, a configuration using a cold cathode device, particularly a surface conduction electron-emitting device, as a display device will be described as an example.

(First Embodiment) In the following, an embodiment to which the invention of the present application is applied will be shown, and a specific embodiment will be simultaneously described.

In the display device in which the cold cathode elements are arranged in a simple matrix, the current flowing into the scanning wiring and the wiring resistance of the scanning wiring cause a voltage drop to deteriorate the display image. The present invention relates to an image display device provided with a processing circuit that corrects the influence of a voltage drop in a wiring on a display image, and in particular, it is realized with a relatively small circuit scale.

The correction circuit of the present invention calculates the deterioration of the display image caused by the voltage drop according to the input image data,
The correction data for correcting it is obtained, and the image data is corrected.

As an image display device having such a correction circuit built-in, the inventors have intensively studied an image display device of the type described below.

In describing the present invention below,
Overview of a display panel of an image display device according to an embodiment of the present invention, electrical connection of the display panel, characteristics of a surface conduction electron-emitting device, a method of driving the display panel, and when displaying an image by such a display panel. The mechanism of the reduction of the driving voltage due to the electric resistance of the scanning wiring will be described in order. Then, after that, a convergence calculation method at the time of correction for the influence of the voltage drop, which is a feature of the present invention, will be described.

(Overview of Image Display Device) FIG. 1 is a perspective view of a display panel used in the image display device according to the present embodiment, in which a part of the panel is cut away to show the internal structure. . In the figure, 1005 is a rear plate, 1006 is a side wall, 1007 is a face plate, and 1005-
1007 forms an airtight container for maintaining a vacuum inside the display panel.

The rear plate 1005 has a substrate 1001.
, But the cold cathode device 1002 is fixed on the substrate.
Are formed by N × M. Row wiring (scan wiring) 100
3, the column wiring (modulation wiring) 1004 and the cold cathode device are shown in FIG.
Are connected like.

Such a connection structure is called a simple matrix.

A fluorescent film 1008 is formed on the lower surface of the face plate 1007. Since the image display device according to the present embodiment is a color display device, the fluorescent film 1
Red, green, which is used in the field of CRT
Phosphors of three primary colors of blue are painted separately. The phosphor is formed in a matrix corresponding to each pixel (picture element) of the rear plate 1005, and forms a pixel at a position irradiated with an electron (emission current) emitted from the cold cathode element. Is configured.

A metal back 1 is formed on the lower surface of the fluorescent film 1008.
009 is formed.

Hv is a high voltage terminal and is a metal back 100.
9 is electrically connected. By applying a high voltage to the Hv terminal, a high voltage is applied between the rear plate 1005 and the face plate 1007.

In this embodiment, a surface conduction electron-emitting device was manufactured as a cold cathode device in the above display panel.

(Characteristics of Surface Conduction Type Emitting Element) In the surface conduction type emitting element, as shown in FIG. 3, (emission current Ie) vs. (element applied voltage Vf) characteristics, and (element current If) vs. (element applied voltage Vf). ) Has characteristics. Since the emission current Ie is significantly smaller than the device current If and it is difficult to draw the same current scale, the two graphs are shown on different scales.

That is, the emission current Ie has the following three characteristics.

First, a certain voltage (this is the threshold voltage Vth
When the above voltage is applied to the element, the emission current Ie rapidly increases, while the emission current Ie is hardly detected at a voltage lower than the threshold voltage Vth.

That is, it is a non-linear element having a clear threshold voltage Vth with respect to the emission current Ie.

Secondly, since the emission current Ie changes depending on the voltage Vf applied to the element, the magnitude of the emission current Ie can be controlled by changing the voltage Vf.

Thirdly, since the cold cathode element has a high-speed response, the emission current I depends on the application time of the voltage Vf.
The release time of e can be controlled.

The inventors have found that the surface conduction electron-emitting device having the above characteristics is preferably used for a display device. For example, in the image display device using the display panel shown in FIG. 1, if the first characteristic is used, it is possible to sequentially scan the display screen for display. That is, a voltage equal to or higher than the threshold voltage Vth is appropriately applied to the driven element according to the desired light emission luminance, and a voltage lower than the threshold voltage Vth is applied to the non-selected element. By sequentially switching the elements to be driven, it is possible to sequentially scan the display screen for display.

By utilizing the second characteristic,
By the voltage Vf applied to the element, the emission brightness of the phosphor can be controlled and an image can be displayed.

By utilizing the third characteristic,
The light emission time of the phosphor can be controlled by the time for which the voltage Vf is applied to the element, and an image can be displayed.

In the image display device of the present invention, the amount of the electron beam of the display panel is modulated by using the above third characteristic.

(Driving Method of Display Panel) A driving method of the display panel of the present invention will be specifically described with reference to FIG.

FIG. 4 shows an example of the potential applied to the voltage supply terminals of the scanning wiring and the modulation wiring when the display panel of the present invention is driven.

Now, the horizontal scanning period I is a period in which the pixels in the i-th row emit light. In order to cause the pixels in the i-th row to emit light, the scanning wiring in the i-th row is brought into a selected state, and the selection potential Vs is applied to its voltage supply terminal Dxi. In addition, the voltage supply terminals Dxk (k = 1,
2 ,. ． ． N, but k ≠ i) is in the non-selected state, and the non-selected potential Vns is applied.

In this example, the reference potential is the ground potential (GN
D), the selection potential is lower than the reference potential, and the potential difference between the selection potential Vs and the reference potential is half of the voltage VSEL shown in FIG. Therefore, Vs is -0.5VS
It is EL. The non-selection potential Vns is set to GND.

A pulse width modulation signal having a voltage amplitude | Vpwm | was supplied to the potential supply terminal of the modulation wiring. Here, the voltage amplitude applied to the modulation wiring is the potential difference between the modulation wiring potential and the modulation potential Vpwm at the time of off. Here, since the modulation wiring potential at the time of off is equal to the reference potential, the voltage amplitude is | Vpwm |. The pulse width of the pulse width modulation signal supplied to the j-th modulation wiring is determined according to the size of the image data of the pixel in the i-th row and the j-th column of the image to be displayed, and all the modulation wirings have the pixel width of each pixel. A pulse width modulation signal according to the size of the image data was supplied.

In this embodiment, the value of the potential Vpwm is +
It was set to 0.5 VSEL.

The surface conduction electron-emitting device emits electrons when the voltage VSEL is applied across the device as shown in FIG. 3, but does not emit electrons at all when the applied voltage is lower than Vth.

Note that VSEL has a value in which the voltage Vth becomes larger than 0.5 VSEL as shown in FIG.

Therefore, no electrons are emitted from the surface conduction electron-emitting device connected to the scanning wiring to which the non-selection potential Vns is applied.

Similarly, during a period in which the output of the pulse width modulation means is at the ground potential (hereinafter, referred to as a period in which the output is "L"), both ends of the surface conduction electron-emitting device on the selected scanning wiring are connected. Since the applied voltage is | Vs |, no electrons are emitted.

From the surface conduction electron-emitting device on the scanning wiring to which the selection potential Vs is applied, the output of the pulse width modulation means is V.
Pwm period (hereinafter referred to as "H" period of output)
The electrons are emitted according to the. When the electrons are emitted, the above-mentioned phosphor emits light in accordance with the amount of the emitted electron beam, so that it is possible to emit the brightness corresponding to the emitted time.

The image display device of the present embodiment displays images by such a line-sequential, pulse-width modulation method.

(Regarding Voltage Drop in Scan Wiring) The problem here is that the voltage drop in the scan wiring of the display panel raises the potential on the scan wiring (the output potential of the modulating means when the modulating means is H). The voltage applied to the surface-conduction type electron-emitting device decreases, so that the emission current from the surface-conduction type electron-emitting device decreases.

The device current for one device of the surface conduction electron-emitting device is about several hundred μA when the voltage VSEL is applied, although it depends on the design specifications and manufacturing method of the surface conduction electron-emitting device.

Therefore, when only one pixel on the selected scanning line is made to emit light and the other pixels are not made to emit light in a certain horizontal scanning period, the element current flowing from the modulation wiring to the scanning wiring of the selected row is 1. Since it is only the current for the pixel (that is, the above-mentioned several 100 μA), there is almost no voltage drop, and the emission brightness does not decrease.

However, in the case where all the pixels in the selected row are made to emit light in a certain horizontal scanning period, the current for all the pixels flows from all the modulation wirings to the scanning wirings in the selected state, so that the current The sum is several hundred mA
The number was several A, and a voltage drop occurred on the scanning wiring due to the wiring resistance of the scanning wiring.

If a voltage drop occurs on the scan wiring, the voltage applied across the surface conduction electron-emitting device will decrease. For this reason, the emission current emitted from the surface conduction electron-emitting device is reduced, and as a result, the emission brightness is reduced.

Specifically, consider a case where a white cross pattern is displayed on a black background as shown in FIG. 5A as a display image.

Then, when the row L in the same drawing is driven, since the number of lit pixels is small, almost no voltage drop occurs on the scanning wiring of that row. As a result, a desired amount of emission current is emitted from the surface conduction electron-emitting device of each pixel, and light can be emitted with a desired brightness.

On the other hand, when driving the row L'in the figure, since all the pixels are turned on at the same time, a voltage drop occurs on the scanning wiring, and the emission current from the surface conduction electron-emitting device of each pixel is generated. Decrease. As a result, the luminance of the line of row L'is reduced.

As described above, the influence of the voltage drop changes due to the difference in the image data for each horizontal line. Therefore, when displaying the cross pattern as shown in FIG. An image like this had been displayed.

It should be noted that this phenomenon is not limited to the cross pattern, but also occurs, for example, when a window pattern or a natural image is displayed.

Further, more complicatedly, the magnitude of the voltage drop has the property of changing within one horizontal scanning period by performing modulation by pulse width modulation.

When the pulse width modulation signal is a pulse width modulation signal whose rising edges are synchronized as shown in FIG. 4, it is generally turned on at the beginning of one horizontal scanning period although it depends on the input image data. Since the number of pixels that are turned on is large and the lights are turned off in order from a place with low brightness, the number of turned-on pixels decreases with time in one horizontal scanning period.

Therefore, the magnitude of the voltage drop generated on the scan wiring also tends to decrease gradually toward the beginning of one horizontal scanning period.

Since the output of the pulse width modulation signal changes at each time corresponding to one gradation of modulation, the temporal change of the voltage drop also changes at each time corresponding to one gradation of the pulse width modulation signal.

The voltage drop in the scan wiring has been described above.

(Calculation Method of Voltage Drop) In order to obtain the correction amount for reducing the influence of the voltage drop, the inventors first predict the magnitude of the voltage drop and its time change in real time as the first step. I thought it was necessary to develop hardware that would

However, the display panel of the image display device according to the present invention is generally provided with thousands of modulation wirings, and the voltage drop at the intersection of all the modulation wirings and the scanning wirings is calculated. It is very difficult to do so in the present embodiment.

Here, as a result of the examination of the voltage drop by the present inventors, it was found that the following characteristics are provided.

I) At a certain point in one horizontal scanning period, the voltage drop generated on the scan wiring is a spatially continuous amount on the scan wiring, which is a very smooth curve.

Ii) Although the magnitude of the voltage drop varies depending on the display image, it changes for each pulse width corresponding to one gradation of pulse width modulation. It either becomes smaller or maintains its size. That is, the driving method as shown in FIG. 4 does not increase the magnitude of the voltage drop in one horizontal scanning period.

Therefore, in consideration of the above-mentioned characteristics, the inventors examined whether the calculation amount can be reduced by performing simplification by the following approximate model.

First, from the characteristic of i), when calculating the magnitude of the voltage drop at a certain time, it is approximated by a degenerate model in which thousands of modulation wirings are concentrated into several to several tens of modulation wirings. We examined whether it could be simplified and calculated (this will be explained in detail in the calculation of the voltage drop by the following degenerate model).

Further, from the characteristics mentioned in ii), it is possible to roughly predict the time change of the voltage drop by providing a plurality of times in one horizontal scanning period and calculating the voltage drop at each time. did.

Specifically, the time change of the voltage drop was roughly predicted by calculating the voltage drop by the degeneration model described below for a plurality of times.

(Calculation of voltage drop by degenerate model) FIG. 6
(A) is a figure for demonstrating the block and node at the time of performing degeneration of this invention.

In the same figure, for simplification of the drawing, only the selected scanning wiring, each modulation wiring, and the surface conduction electron-emitting device connected to the intersection thereof are shown.

Now, at a certain time in one horizontal scanning period, the lighting state of each pixel on the selected scanning wiring (that is, whether the output of the modulating means is "H" or "L"). ) Is known.

In this lighting state, the element current flowing from each modulation wiring to the selected scanning wiring is set to Ifi (i =
1, 2 ,. ． ． N and i are defined as column numbers).

Further, as shown in the figure, a block is defined by grouping the n modulation wirings, the intersections of the selected scanning wirings and the surface conduction electron-emitting devices arranged at the intersections thereof. . In this example, the blocks are divided into four blocks.

A position called a node is set at the boundary position of each block. A node is a position for discretely calculating a voltage drop amount in a degenerate model.

In this example, node 0 is placed at the block boundary position.
~ 5 nodes of node 4 were set.

FIG. 6B is a diagram for explaining the degenerate model.

In the degenerate model, the n modulation wirings included in one block in FIG. 10A are degenerated into one, and the wirings are connected so that they are located at the center of the block of the scanning wirings.

A current source is connected to the centralized modulation wiring of each block, and the sum total IF0 to IF3 of the current in each block flows from each current source.

That is, IFj (j = 0, 1, ... 3)
Is

[Equation 1] Is the current expressed as

Further, the potentials at both ends of the scanning wiring are shown in FIG.
In the example of FIG. 5B, the GND potential is the potential difference between two points in the same figure (b), and in the degenerate model, it flows into the scanning wiring selected from the modulation wiring. This is because by modeling the current with the current source, the voltage drop amount of each portion on the scanning wiring can be calculated by calculating the potential of each portion with the feeding portion as the reference potential.

The surface-conduction type electron-emitting device is omitted regardless of the presence or absence of the surface-conduction type electron-emitting device as long as an equivalent current flows from the column line when viewed from the selected scanning line. This is because the generated voltage drop itself does not change. Therefore, here, the surface conduction electron-emitting device is omitted by setting the current value flowing from the current source of each block to the total current value of the device currents in each block (Equation 1).

Further, the wiring resistance of the scanning wiring of each block is set to n times the wiring resistance r of the scanning wiring of one section (here, one section is the intersection with the column wiring having the scanning wiring and the adjacent row). In this example, the wiring resistance of the scanning wiring in one section is assumed to be uniform.).

In such a degenerate model, the voltage drop amounts DV0 to DV generated at each node on the scanning wiring.
4 can be easily calculated by the following product-sum formula.

[0095]

[Equation 2] That is,

[Equation 3] Is.

However, aij is the potential of the feeding portion (here, GN) from the potential generated at the i-th node when a unit current is injected only into the j-th block in the degenerate model.
It is a potential difference obtained by subtracting D) (hereinafter, this is defined as aij).

The above aij can be easily derived as follows according to Kirchhoff's law.

That is, in FIG. 6B, the wiring resistance from the current source of the block i to the supply terminal on the left side of the scanning wiring is rli (i = 0,1,2,3), to the supply terminal on the right side. The wiring resistance is defined as rri (i = 0, 1, 2, 3), and the wiring resistance between the block 0 and the left supply terminal and the wiring resistance between the block 4 and the right supply terminal are both defined as rt. If

[Equation 4] further,

[Equation 5] far.

Then, aij is

[Equation 6] Can be derived easily.

Even if the number of blocks is not 4, (Equation 2) can be easily calculated according to Kirchhoff's law by considering the definition of aij. Further, even in the case where the power supply terminals are not provided on both sides of the scanning wiring as in this example and only one side is provided, the calculation can be easily performed by performing calculation according to the definition of aij.

The parameter aij defined by (Equation 3) does not need to be recalculated each time calculation is performed.
It should be calculated once and stored as a table.

In the above calculation, a predetermined value was used as the current flowing through the modulation wiring. Although the correction data can be obtained even under the condition, the predetermined current does not always flow due to the influence of the voltage drop. The present invention is
The convergence method is used in the calculation for obtaining the correction data that alleviates the influence of the voltage drop.

That is, calculation is performed based on the voltage drop obtained by the above calculation to calculate the value of the current flowing through the modulation wiring. Then, the voltage value is evaluated again by using the current value obtained there in (Equation 2). This voltage drop calculation and current value calculation are performed in the model shown in FIG.
As shown in FIG. 8, the value obtained by the calculation is repeatedly compared with the previously calculated value, and when the difference becomes equal to or less than a predetermined value, the repeated calculation is stopped.

Here, the voltage drop DV that occurs in each block
bi is

[Equation 7] And

That is, in FIG. 8, first, the current value of each block of the initial setting value is set to preIFi (i = 0, 1, 2, ...
.) As a voltage drop calculation, thereby calculating a current value from the Vf-If characteristics of the element as shown in FIG.
The current value IFi of each block obtained from the current value Ifi flowing in the modulation wiring of each block obtained by this calculation
And preIF, which is the current value flowing in each block last time
i is compared, and the current value IFi flowing in each block is again used as preIFi until the difference becomes equal to or less than a predetermined value, the voltage drop calculation is repeated, and the current value is converged.

For example, when the given IFi is larger than the true value, DVi is calculated from the equation (2), and the voltage drop DVbi generated in the block is calculated from the equation (4). That is, since the voltage applied to the elements in the block is calculated to be small, a current value smaller than IFi given previously is calculated from the Vf-If characteristics of the elements. Furthermore, when this current value is larger than the true value, a smaller current value is calculated. On the other hand, when the given current value is smaller than the true value, a current value larger than the given current value is calculated in the opposite process to the above.

That is, when the given current value is larger than the true value, a current value smaller than the current value is recalculated,
If it is smaller than the true value, a large current value is recalculated, so that the current value is converged by repeating it.

As a result, a suitable current value corresponding to the true voltage drop can be obtained by converging, and the correction for the decrease in luminance due to the voltage drop can be performed particularly preferably.

As the calculated values to be compared, the current value Ifi flowing in the modulation wiring in each block and the voltage drop amount DVb.
In this embodiment, the current values IFi of the blocks are compared with each other.

A specific example of this calculation is as follows.

Here, the number of modulation wirings is 120, and the resistance distributions in each section are substantially equal to each other, r = 0.042Ω, rt
= 2Ω. It was Also, pulse width modulation was adopted as the modulation method. The pulse width modulation method should be simple and ON
Only two potentials, the state potential and the OFF state potential, are switched, the pulse width is set according to the gradation value of the image signal, and the pulse width is corrected by the correction data. The value of If given first in the above calculation was set to 0.5 mA. The number of blocks is 4, and the number of wires in each block is 3
It was set to 0. At this time, the extracted values a00, a23, a31, a
The values of 43 are 1.412, 1.313, and 1.40, respectively.
0 and 1.417, and the values of IF0 to IF3 are all 15 mA. Under this condition, give a white solid image signal,
When the calculation in one time slot described later is performed, the voltage drops DV0 to DV4 are each 0.12.
1, 0.178, 0.196, 0.178, 0.121
v, the current values of the blocks obtained by the current value calculation are 11.47, 11.41, 11.41,
It was 11.47 mA. When IF0 to IF3 are updated with this value and further current value calculation based on further voltage drop calculation is performed to obtain values of IF0 to IF3, 11.3
It was 6, 11.27, 11.27, 11.36 mA. When the current value calculation and the voltage drop calculation were repeated eight times, all the values of IF0 to IF3 differed from the values of IF0 to IF3 obtained by the previous calculation by 0.1% or less. The iteration was stopped at this stage. In this example, it converged 8 times. In the present embodiment, the result obtained by the calculation and the previous calculation result are compared and it is determined whether or not the difference is equal to or less than a predetermined value. The determination step can be omitted. If it is set to repeat 10 times, a suitable result can be obtained.

FIG. 6C shows an example of the result of calculating the voltage drop amounts DV0 to DV4 of each node by the above method in a certain lighting state.

Since the voltage drop has a very smooth curve, it is assumed that the voltage drop between the nodes approximately takes the value shown by the dotted line in the figure.

As described above, by using this degenerate model, it is possible to calculate the voltage drop for each node at a desired time point with respect to arbitrary image data.

As described above, the amount of voltage drop in a certain lighting state was simply calculated using the degeneration model.

The voltage drop generated on the selected scanning wiring changes with time within one horizontal scanning period, which is as described above, for some times during one horizontal scanning period. The lighting state at that time was obtained, and the lighting state was predicted by calculating the voltage drop using a degenerate model.

The number of lights in each block at a certain point in one horizontal scanning period can be easily obtained by referring to the image data of each block.

As an example, assume that the number of bits of input data to the pulse width modulation circuit is 8 bits, and the pulse width modulation circuit outputs a linear pulse width with respect to the size of the input data. And

That is, when the input data is 0, the output is "L", when the input data is 255, "H" is output during one horizontal scanning period, and when the input data is 128, one horizontal scanning period. It is assumed that "H" is output in the first half period and "L" is output in the second half period.

In such a case, the number of lights at the time when the pulse rises can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than zero.

Similarly, the number of lights at the center time of one horizontal scanning period can be easily detected by counting the number of input data to the pulse width modulation circuit which is larger than 128.

By thus comparing the image data with a certain threshold value and counting the number of true outputs of the comparator, the number of lightings at any time can be easily calculated.

Here, in order to simplify the following description, a time amount called a time slot is defined.

That is, the time slot represents the time from the rise of the pulse width modulation signal in one horizontal scanning period, and the time slot = 0 represents the time immediately after the rise of the pulse width modulation signal. It is defined as

Time slot = 64 is defined as a time when 64 gradations have elapsed from the rise of the pulse width modulation signal.

Similarly, the time slot = 128 is defined to represent the time when 128 gradations have elapsed from the rise of the pulse width modulation signal.

(Calculation of Correction Data from Voltage Drop Amount) As described above, the time change of the voltage drop during one horizontal scanning period is approximately and discretely calculated by repeatedly performing the calculation using the degenerate model. I was able to.

FIG. 9 shows an example in which the voltage drop is repeatedly calculated for a certain image data, and the time change of the voltage drop in the scan wiring is calculated (the voltage drop shown here and its time change are , An example for one image data, and it is natural that the voltage drop for another image data has another change.

In the figure, time slots = 0, 64, 12
The degenerate model was applied to each of the four time points of 8 and 192 to perform the calculation, and the voltage drop at each time was calculated discretely.

In FIG. 9, the voltage drop amount at each node is connected by a dotted line, but the dotted line is shown to make the diagram easier to see, and the voltage drop calculated by this degenerate model is □, ○, ●. , Δ were calculated discretely at the positions of the nodes.

The inventors examined a method of calculating correction data for correcting image data from the amount of voltage drop as the next step after the magnitude of voltage drop and its change over time can be calculated.

FIG. 10 is a graph for estimating the emission current emitted from the surface conduction electron-emitting device in the lighting state when the voltage drop shown in FIG. 9 occurs on the selected scanning wiring.

The vertical axis represents the amount of the emission current when the magnitude of the emission current emitted when there is no voltage drop is 100%, and the horizontal axis represents the horizontal position.

As shown in FIG. 10, in node 2, The emission current when time slot = 0 is Ie0, The emission current at time slot = 64 is Ie1, The emission current at time slot = 128 is Ie2, The emission current when the time slot is 192 is Ie3, And

The figure is calculated from the graph of the voltage drop amount of FIG. 7 and the “driving voltage vs. emission current” of FIG. Specifically, it is a mechanical plot of the value of the emission current when a voltage obtained by subtracting the voltage drop amount from the voltage VSEL is applied.

Therefore, this figure only means the current emitted from the surface-conduction type emitting device in the lighting state, and the surface-conduction type emitting device in the extinguished state does not emit the current.

A method of calculating correction data for correcting image data from the amount of voltage drop will be described below.

(Calculation Method of Discrete Correction Data) FIG.
(A), (b), (c) is a figure for demonstrating the method of calculating the correction data of a voltage drop amount from the time change of the emission current of FIG. The figure shows an example of calculating correction data for image data of size 64.

Now, when there is no influence of the voltage drop, the emission current is IE, and the time corresponding to one gradation of pulse width modulation is Δt.
Then, when the image data is 64, the emission charge amount Q0 by the emission current pulse is the amplitude IE of the emission current pulse.
Multiplied by the pulse width (64 × Δt),

[Equation 8] Can be expressed as

However, in reality, a phenomenon occurs in which the emission current decreases due to the voltage drop on the scanning wiring.

The amount of charge emitted by the emission current pulse considering the influence of the voltage drop can be approximately calculated as follows. That is, if the emission currents of the time slots = 0 and 64 of the node 2 are Ie0 and Ie1, respectively, and if the emission current between 0 and 64 is approximated to change linearly between Ie0 and Ie1, the emission during this period can be approximated. The charge amount Q1 is shown in FIG.
The area of the trapezoid in (b), that is,

[Equation 9] Can be calculated as

Next, as shown in FIG. 11C, it is assumed that the influence of the voltage drop can be eliminated when the pulse width is extended by DC1 in order to correct the decrease in the emission current due to the voltage drop.

When the voltage drop is corrected and the pulse width is extended, the amount of emission current in each time slot is considered to change, but for simplification,
As shown in FIG. 11C, it is assumed that the emission current becomes Ie0 at time slot = 0 and the emission current becomes Ie1 at time slot = (64 + DC1).

Further, the emission current between the time slot 0 and the time slot (64 + DC1) is approximated to take a value on a line connecting the emission currents at two points with a straight line.

Then, the amount of charge Q2 emitted by the corrected emission current pulse is

[Equation 10] Can be calculated as

If this is equal to Q0, then

[Equation 11] Becomes

If this is solved for DC1,

[Equation 12] Becomes

In this way, the correction data when the image data is 64 was calculated.

That is, the size of the position of node 2 is 64
For the image data of, as described in (Equation 8), the CD
It is sufficient to add ata = DC1 as the correction amount.

FIG. 12 is an example in which correction data for image data of size 128 is calculated from the calculated voltage drop amount.

Now, when the image data is 128, the amount of emitted charge Q3 expected by the emission current pulse is

[Equation 13] Is.

On the other hand, the input charge amount due to the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 =
Emission current amounts of 0, 64, and 128 are Ie0 and Ie, respectively.
1 and Ie2. The emission current between 0 and 64 is I
If it is approximated to change linearly between e0 and Ie1 and change on a line connecting Ie1 and Ie2 with a straight line between 64 and 128, the emission charge during the time slot from 0 to 128 is approximated. The quantity Q4 is the sum of the areas of the two trapezoids in FIG.

[Equation 14] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to time slots 0 to 64 is defined as period 1, and the period corresponding to 64 to 128 is defined as period 2.

When the correction is applied, the portion of the period 1 is DC1.
Is extended to period 1'and the portion of period 2 is DC2
I think that it will be extended only in the period 2 '.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by performing the correction in each period.

Needless to say, the emission currents at the beginning and the end of each period change by correction, but it is assumed here that they do not change in order to simplify the calculation.

That is, the emission current at the beginning of the period 1'is I
e0, the emission current at the end of period 1'is Ie1, period 2 '
The emission current at the beginning of the period is Ie1 and the emission current at the end of the period 2'is Ie2. Then, DC1 can be calculated in the same manner as the equation.

DC2 uses the same concept as above.

[Equation 15] Can be calculated as

As a result, the size of the position of node 2 is 12
For the image data of 8,

[Equation 16] May be added as the correction amount.

FIG. 13 is an example in which correction data for image data of size 192 is calculated from the calculated voltage drop amount.

Now, when the image data is 192, the emission charge amount Q5 expected by the emission current pulse is

[Equation 17] Is.

On the other hand, the amount of electric charge emitted by the actual emission current pulse, which is affected by the voltage drop, can be approximately calculated as follows.

That is, the time slot of node 2 = 0
Let Ie0 be the emission current at the time of, Ie1 be the emission current at the time slot = 64, Ie2 be the emission current at the time slot = 128, and Ie3 be the emission current at the time slot = 192. Emission currents of Ie0 and Ie
It changes linearly between e1 and Ie1 between 64 and 128
And Ie2 change on a straight line connecting 128 to 1
If 92 is approximated to change on a line connecting Ie2 and Ie3 with a straight line, the input charge amount Q6 during the time slot from 0 to 192 is the area of the three trapezoids of FIG. 13B. , That is,

[Equation 18] Can be calculated as

On the other hand, the correction amount of the voltage drop was calculated as follows.

The period corresponding to the time slots 0 to 64 is the period 1, and the period corresponding to the time slots 64 to 128 is the period 2,128.
The period corresponding to 192 is defined as period 3.

Similarly to the above, after the correction, the portion of the period 1 is extended by DC1 and extended to the period 1 ', and the portion of period 2 is extended by DC2 and extended to the period 2',
It is considered that the portion of the period 3 is extended by DC3 and then extended to the period 3 ′.

At this time, it is assumed that the amount of emitted charges becomes the same as Q0 described above by being corrected in each period.

Further, it is assumed that the emission currents at the beginning and the end of each period do not change before and after the correction.

That is, the emission current at the beginning of the period 1'is
Ie0, the emission current at the end of the period 1'is Ie1, the emission current at the beginning of the period 2'is Ie1, the emission current at the end of the period 2'is Ie2, and the emission current at the beginning of the period 3'is Ie.
3, the emission current at the end of the period 3'is assumed to be Ie4.

Then, DC1 and DC2 are respectively expressed by equation 8,
It can be calculated in the same manner as 11.

For DC3,

[Formula 19] Can be calculated as

As a result, the size of the position of node 2 is 19
The correction data CData to be added to the image data of 2 is

[Equation 20] And it is sufficient.

As described above, the correction data DC of the image data 64, 128, 192 for the position of the node 2 was calculated.

When the pulse width is 0, of course, there is no influence of the voltage drop on the emission current, so the correction data is set to 0 and the correction data CData is added to the image data.
Is also 0. Note that 0, 64, 128, 19
The reason why correction data is calculated for discrete image data as in 2 is to reduce the amount of calculation.

That is, if the same calculation is performed for all arbitrary image data, the calculation amount becomes very large.
The amount of hardware for calculation becomes very large.

On the other hand, at a certain node position, the larger the image data, the larger the correction data tends to be. As a result, when calculating correction data for arbitrary image data, if the points near the image data for which correction data has already been calculated and the points are interpolated by linear approximation, the amount of calculation will be greatly reduced. This is because you can Note that this interpolation will be described in detail in the description of the discrete correction data interpolation means.

If the same idea is applied to the positions of all the nodes, the correction data of image data = 0, 64, 128, 192 at the positions of all the nodes can be calculated.

In this example, the time slots are 0, 64, 12
By applying the degenerate model to the four points of 8 and 192 and calculating the voltage drop amount at each time, the correction data can also be obtained for the four points of the image data of 0, 64, 128, and 192. did it.

However, it is preferable to set the time interval for calculating the voltage drop to be finer and more preferably by the degenerate model, so that the time change of the voltage drop can be handled more accurately and the error in the approximation calculation can be reduced. it can.

At that time, in a similar way,
Equations 5 to 15 may be modified to perform the calculation.

According to the above-mentioned method, image data = 0,6 at the position of each node with respect to certain input data.
When the correction data for 4,128,192 were calculated discretely, the results shown in FIG. 14 (a) were obtained.

FIG. 14A shows an example of the result of discretely calculating the correction data for image data = 0, 64, 128, 192 at the position of each node with respect to certain input data by the above method. Is.

Incidentally, in the same drawing, the discrete correction data for the same image data are shown by connecting them with a dotted curve in order to make the drawing easier to see.

(Interpolation Method of Discrete Correction Data) The correction data calculated discretely is discrete with respect to the position of each node, and correction data at an arbitrary horizontal position (column wiring number) is not given. Absent. At the same time, correction data for some modulated signals having predetermined pulse widths at each node position and not correction data for arbitrary pulse widths are not given.

Therefore, the inventors calculated the correction data adapted to the modulation signal having an arbitrary pulse width in each column wiring by interpolating the correction data calculated discretely.

FIG. 14B shows the pulse width Data at the position x between the node n and the node n + 1.
FIG. 6 is a diagram showing a method of calculating correction data of a pulse width modulation signal for.

As a premise, it is assumed that the correction data has already been discretely calculated at the positions Xn and Xn + 1 of the nodes n and n + 1.

Further, the pulse width Data is the pulse widths Dk and Dk + 1 for which the correction data has already been calculated discretely.
Shall take a value between.

If the correction data of the pulse width Dk of the node n is expressed as CData [k] [n], the position x
The correction data CA of the pulse width Dk at
By linear approximation using the values of [k] [n] and CData [k] [n + 1],

[Equation 21] Can be calculated.

Further, the correction data CB of the pulse width Dk + 1 at the position x is as follows.

[Equation 22] Can be calculated.

By linearly approximating the correction data of CA and CB, the correction data CD for the image data Data at the position x is as follows.

[Equation 23] Can be calculated.

As described above, in order to calculate the correction data suitable for the actual position and the size of the pulse width from the discrete correction data, the calculation is simply performed by the method described in (Expression 16) to (Expression 18). it can.

The method of calculating the correction data has been described above.

If the correction data calculated in this way is added to the image data to correct the image data and the pulse width modulation is performed according to the corrected image data, the image quality due to the voltage drop, which has been a problem in the past, can be obtained. Can be reduced and the image quality can be improved.

The hardware for correction, which has been a problem in the future, can be reduced on a very small scale by introducing an approximation such as degeneracy described above so that the calculation amount can be reduced. It had an excellent merit that it could be configured with various hardware.

The method of correcting image data in this embodiment has been described above.

(Explanation of Functions of Entire System and Each Part) Next, the hardware of the image display device incorporating the correction data calculating means in this embodiment will be explained.

FIG. 15 is a block diagram showing an outline of the circuit configuration. In the figure, 1 is the display panel of FIG. 1, Dx1
˜DxM and Dx1 ′ to DxM ′ are potential supply terminals of the scanning wiring of the display panel, Dy1 to DyN are potential supply terminals of the modulation wiring of the display panel, and Hv is for applying an acceleration voltage between the face plate and the rear plate. High voltage supply terminal,
Va is a high-voltage power supply, 2 is a scanning circuit, 3 is a synchronization signal separation circuit, 4 is a timing generation circuit, 7 is a conversion circuit for converting the YPbPr signal into RGB by the synchronization separation circuit 3,
Reference numeral 17 is an inverse γ processing unit, 5 is a shift register for one line of image data, 6 is a latch circuit for one line of image data, 8
Is a pulse width modulation means for outputting a modulation signal to the modulation wiring of the display panel, 12 is an adder, and 14 is a correction data calculation means.

Further, in the figure, R, G and B are RGB parallel input image data, Ra, Ga and Ba are RGB parallel image data subjected to an inverse γ conversion process which will be described later, and D.
ata is image data subjected to parallel / serial conversion by the data array conversion unit, CD is correction data calculated by the correction data calculating unit, and Dout is image data corrected by adding the correction data to the image data by the adder. Is.

(Synchronous Separation Circuit, Timing Generation Circuit) The image display device according to the present embodiment is NTSC, PAL, SE.
Television signals such as CAM and HDTV, and VGA output from a computer can be displayed together.

In FIG. 15, in order to simplify the drawing, HDTV
Only the method is described.

In the HDTV system video signal, the synchronization signals Vsync and Hsync are first separated by the synchronization separation circuit 3 and supplied to the timing generation circuit. The video signals separated by synchronization are supplied to the RGB conversion means. Inside the RGB conversion means, a YPbPr-to-RGB conversion circuit, a low-pass filter (not shown), an A / D converter, and the like are provided. The YPbPr is converted into a digital RGB signal, and the inverse γ processing is performed. Supply to the department.

(Timing Generation Circuit) The timing generation circuit is a circuit which has a built-in PLL circuit, generates timing signals synchronized with the synchronization signals of various video sources, and generates operation timing signals for each section.

The timing signal generated by the timing generation circuit 4 includes Tsft for controlling the operation timing of the shift register 5, the shift register, and the latch circuit 6.
Control signal Dataalo for latching data to
d, pulse width modulation start signal Pwmstar of the modulation means 8
t, a clock Pwmclk for pulse width modulation, Tscan for controlling the operation of the scanning circuit 2, and the like.

(Scanning Circuit) The scanning circuits 2 and 2'output the selection potential Vs or the non-selection potential Vns to the connection terminals Dx1 to DxM in order to sequentially scan the display panel row by row in one horizontal scanning period. Circuit (FIG. 16).

The scanning circuits 2 and 2 ′ are circuits that perform scanning by sequentially switching the selected scanning wiring in every horizontal period in synchronization with the timing signal Tscan from the timing generation circuit 4.

[0209] Note that Tscan is a timing signal group formed from a vertical synchronizing signal, a horizontal synchronizing signal, and the like.

The scanning circuits 2 and 2'are each composed of M switches and shift registers as shown in FIG. These switches are preferably composed of transistors or FETs.

In order to reduce the voltage drop in the scanning wiring, it is preferable that the scanning circuit is connected to both ends of the scanning wiring of the display panel and driven from both ends as shown in FIG.

On the other hand, the present invention is effective even when the scanning circuit is not connected to both ends of the scanning wiring, and can be applied only by changing the parameter of (Equation 3).

(Inverse γ Processing Unit) The CRT has a light emission characteristic of approximately 2.2 to the input (hereinafter referred to as an inverse γ characteristic).

Such characteristics of the CRT are taken into consideration, and the input video signal is generally converted according to the .gamma. Characteristic of 0.45 so as to have a linear emission characteristic when displayed on the CRT.

On the other hand, the display panel of the image display device of the present invention does not use the modulation by the peak value of the drive voltage applied to the electron-emitting device, but when the modulation is performed by the application time of the drive voltage, the length of the application time is reduced. On the other hand, since it has a substantially linear light emission characteristic, it is necessary to convert the input video signal based on the inverse γ characteristic (hereinafter referred to as inverse γ conversion).

The inverse γ processing section shown in FIG. 15 is a block for performing inverse γ conversion on the input video signal.

The inverse γ processing section of this embodiment is configured by a memory for the inverse γ conversion processing.

The inverse γ processing unit sets the number of bits of the video signals R, G, B to 8 bits, and the video signal R output from the inverse γ processing unit.
The number of bits of a, Ga, and Ba is also set to 8 bits, and a memory of 8 bits for address and 8 bits for data is used for each color (FIG. 17).

(Data Array Converter) Data Array Converter 9
Is a circuit for performing parallel / serial conversion of RGB parallel video signals Ra, Ga, Ba according to the pixel array of the display panel. The configuration of the data array converter 9 is shown in FIG.
As shown in, the FIFO (First
In First Out) memory 2021R, 20
21G, 2021B and a selector 2022.

Although not shown in the figure, the FIFO memory includes two horizontal pixel memory words for odd lines and even lines. When the video data of the odd line is input, the data is written in the FIFO for the odd line, while the image data accumulated in the previous horizontal scanning period is read from the FIFO memory for the even line. When the video data of the even-numbered lines is input, the data is written in the FIFO for the even-numbered lines, while the image data accumulated in the previous horizontal period is read from the FIFO memory for the odd-numbered lines.

The data read from the FIFO memory is parallel-serial converted by the selector according to the pixel array of the display panel and output as RGB serial image data SData. Although not described in detail, it operates based on the timing control signal from the timing generation circuit 4.

(Adder 12) The adder 12 is means for adding the correction data CD from the correction data calculating means and the image data Data. The image data Data is corrected by the addition, and transferred to the shift register as the image data Dout.

(Delay Circuit 19) The image data SData rearranged by the data array converter is input to the correction data calculator and the delay circuit 19. The correction data interpolation unit of the correction data calculation unit refers to the values of the horizontal position information x and the image data SData from the timing control circuit and calculates the correction data CD that matches them.

The delay circuit 19 is provided in order to absorb the time required for calculating the correction data. When the adder 12 adds the correction data to the image data, the correction data corresponding to the correction data is correctly added to the image data. It is a means for delaying the addition. The same means can be configured by using a flip-flop.

(Shift Register, Latch Circuit) The image data Dout, which is the output of the correction data interpolating section, is transferred from the serial data format by the shift register 5 to
The parallel image data ID1 to IDN for each modulation wiring are serial / parallel converted and output to the latch circuit. The latch circuit latches the data from the shift register by the timing signal Dataload immediately before the start of one horizontal period. The output of the latch circuit 6 is supplied to the modulation means as parallel image data D1 to DN.

In this embodiment, the image data ID1
-IDN and D1-DN are 8-bit image data. These operation timings are determined by the timing control signal TSFT from the timing generation circuit 4 (shown in FIG. 15).
And Dataload.

(Details of Modulating Means) The parallel image data D1 to DN output from the latch circuit 6 are supplied to the modulating means 8.

As shown in FIG. 19A, the modulation means is a pulse width modulation circuit (PWM circuit) including a PWM counter, a comparator and a switch (FET in the figure) for each modulation wiring.

The relationship between the image data D1 to DN and the output pulse width of the modulating means has a linear relationship as shown in FIG. 19 (b).

FIG. 3C shows an example of the output waveform of the modulator 3
Show one.

In the figure, the upper waveform is the waveform when the input data to the modulating means is 0, the center waveform is the waveform when the input data to the modulating means is 128, and the lower waveform is the modulating means. It is a waveform when the input data to is 255.

In this example, the input data D to the modulation means is
The number of bits of 1 to DN is 8 bits (note that in the above description, when the input data of the modulating means is 255, a modulation signal having a pulse width corresponding to one horizontal scanning period is output. However, in detail, as shown in (c) of the figure, although it is a very short time, a period in which the pulse is not driven and after the pulse is driven is provided to provide a timing margin.)

FIG. 20 is a timing chart showing the operation of the modulation means of the present invention.

In the figure, Hsync is a horizontal synchronizing signal indicating the beginning of one horizontal scanning period, Dataload is a load signal to the latch circuit 6, D1 to DN are input signals to the columns 1 to N of the above-mentioned modulator, and Pwmstart. Is PWM
A counter synchronization clear signal, Pwmclk, is a PWM counter clock. Further, XD1 to XDN represent outputs of the first to Nth columns of the modulation means.

When one horizontal scanning period starts as shown in the figure, the latch circuit 6 latches the image data and transfers the data to the modulating means.

The PWM counter, as shown in FIG.
Counting is started based on Pwmstart and Pwmclk, and when the count value reaches 255, the counter is stopped and the count value 255 is held.

The comparator provided for each column is
The count value of the PWM counter is compared with the image data of each column, and when the value of the PWM counter is greater than or equal to the image data, High
h is output, and Low is output during the other periods.

The output of the comparator is connected to the gates of the switches in each column, and the output of the comparator is Low.
During the period, the switch on the upper side (VPWM side) in the figure is ON,
The switch on the lower side (GND side) is turned off, and the modulation wiring is set to the potential VPWM.

On the contrary, while the output of the comparator is high, the upper switch in the figure is turned off and the lower switch is turned on, and the potential of the modulation wiring is set to the GND potential.

The pulse width modulation signal output from the modulating means is D1, D in FIG.
2, a waveform in which the rising edges of the pulses are synchronized as shown by DN.

(Correction Data Calculation Means) The correction data calculation means is a circuit for calculating the voltage drop correction data by the above-mentioned correction data calculation method. The correction data calculation means is composed of two blocks, a discrete correction data calculation unit and a correction data interpolation unit, as shown in FIG.

The discrete correction data calculation unit is means for calculating the amount of voltage drop from the input video signal and calculating the correction data discretely from the amount of voltage drop. In order to reduce the amount of calculation and the amount of hardware, the means introduces the concept of the above-mentioned degenerate model and calculates correction data discretely.

The correction data calculated discretely is interpolated by the correction data interpolating unit, and the correction data CD suitable for the size of the image data and its horizontal display position x is calculated.

(Discrete Correction Data Calculation Unit) FIG. 22 shows a discrete correction data calculation unit for calculating the discrete correction data of the present invention.

In the figure, 100a to 100d are lighting number counting means, 101a to 101d are register groups for storing the number of lighting of each block at each time, and 102 is C.
PU, 103 is the parameter ai described in Equation 2 and Equation 3.
j is a table memory for storing j, 104 is a temporary register for temporarily storing the calculation result, and 105 is C
A program memory in which the PU program is stored,
Reference numeral 110 denotes a table memory in which conversion data for converting a voltage drop amount into an emission current amount is described, and 111, conversion data for determining a current value flowing in the element from an applied voltage to the element as shown in FIG. Table memory, 106
Is a group of registers for storing the calculation result of the discrete correction data described above.

Lighting number counting means 100a to 100d
Is composed of a comparator and an adder as shown in FIG. The video signals Ra, Ga, and Ba are input to the comparators 107a to 107c, respectively, and sequentially C
It is compared with the value of val.

The comparators 107a to 107c compare Cval with the image data, and if the image data is larger, Hi.
gh is output, and Low is output if it is small.

The output of the comparator is the adders 108 and 1
09, and the addition is performed for each block by the adder 110, and the addition result for each block is set as the lighting number for each block in the register group 1
01a to d.

The lighting number counting means 100a to 100d respectively have 0, 64 and 1 as the comparison value Cval of the comparator.
28 and 192 are input.

As a result, the lighting number counting means 100a
Counts the number of image data larger than 0 among the image data, and totals each block by the register 101a.
To store.

Similarly, the lighting number counting means 100b counts the number of image data larger than 64 among the image data, and the total for each block is registered in the register 101b.
To store.

Similarly, the lighting number counting means 100c counts the number of image data larger than 128 among the image data, and the total for each block is registered in the register 101.
Store in c.

Similarly, the lighting number counting means 100d counts the number of image data larger than 192 among the image data, and the total for each block is registered in the register 101.
d Store.

When the number of lightings for each block and for each time is counted, the CPU performs the following operation according to the flowchart shown in FIG.

First, an IF initial value is calculated from a certain appropriate If initial value according to (Equation 1) according to the number of lightings stored in the register group 101, and the calculation result is stored in the temporary register 104.

Next, the IF stored in the temporary memory 104 and the parameter table aij stored in the table memory 103 are read out at any time, the voltage drop amount DV is calculated according to (Equation 2), and the DVb according to (Equation 1) is calculated. The voltage Vf applied to the element of each block is calculated.

Then, If is obtained from Vf-If stored in the table memory 111, IF is recalculated according to (Equation 1).

Next, the recalculated IF is compared with the IF (preIF) stored in the temporary register.

If the difference is not less than the predetermined value, the recalculated IF is stored in the temporary register and the recalculation is repeated.

When the difference becomes equal to or less than the predetermined value, the recalculated IF is stored in the temporary register and the convergence calculation is completed.

The end of the convergence calculation is determined by IF and preIF.
However, the calculation time can be shortened by using a certain number of calculations.

Further, since the image information is rarely changed line by line in one picture, the calculation time can be shortened by determining the initial value of the next line from the converged value of one line.

Further, the value to be stored in the temporary register and the judgment of the convergence calculation need not be IF, but If and D
It may be Vb.

In this example, the CPU is provided with a product-sum calculation function for smoothly performing the calculations of (formula 1) to (formula 3) and the convergence determination.

As a means for realizing the above calculation, a CPU
The multiply-accumulate operation may not be performed, and the calculation result may be stored in the memory, for example.

That is, the number of lighting of each block may be used as an input and the voltage drop amount at each node position may be stored in the memory for all possible input patterns.

When the convergence calculation is completed, the CPU reads the I of each block from the temporary register 104 at each time.
F reading was performed, the voltage drop was calculated according to (Equation 2), the amount of emission current was converted by referring to the table memory 2 (110), and the discrete correction data was calculated according to Equations 5 to 15.

The calculated discrete correction data was stored in the register group 106.

(Correction Data Interpolation Unit) The correction data interpolation unit is means for calculating the correction position data (horizontal position) at which the image data is displayed and the correction data suitable for the size of the image data. This means interpolates the correction data calculated discretely to display the image data (horizontal position).
Also, correction data that matches the size of the image data is calculated.

FIG. 23 is a diagram for explaining the correction data interpolation unit.

In the figure, 123 is a decoder for determining the node numbers n and n + 1 of the discrete correction data used for interpolation from the display position (horizontal position) x of the image data, and 124 is the size of the image data. (Equation 16) ~
It is a decoder for determining k and k + 1 in (Equation 18).

Further, the selectors 125 to 128 are selectors for selecting the discrete correction data and supplying it to the linear approximation means.

Further, 120 to 122 are (Equation 1
6) to (Equation 18) are linear approximation means for performing linear approximation.

FIG. 24 shows an example of the structure of the linear approximation means a120. Generally, the linear approximation means can be configured by a subtractor, an integrator, an adder, a divider, etc., as represented by the operators of (Expression 16) to (Expression 18).

However, preferably, the number of column wirings between the nodes for calculating the discrete correction data and the interval of the image data for calculating the discrete correction data (that is, the time interval for calculating the voltage drop) is a power of two. There is a merit that the hardware can be configured very easily if it is configured as follows. If you set them to a power of 2,
In the divider shown in (1), Xn + 1-Xn becomes a power of 2, and bit shift may be performed.

If the value of Xn + 1-Xn is always a constant value and a value represented by a power of 2, it is sufficient to shift the addition result of the adder by the multiplier of the power and output it. There is no need to make a divider.

Further, at other points, the intervals of the nodes for calculating the discrete correction data and the intervals of the image data are set to be a power of 2, for example, the decoders 123 to 12 can be used.
4 can be easily manufactured, and as shown in FIG.
There are many advantages, such as the fact that the operation performed by the subtractor can be replaced with a simple bit operation.

The image display device of the present invention including the voltage drop correction circuit, which the present inventors have intensively studied, has been described above. By adding the correction data calculated in this way to the image data by the adder 12, the influence of the voltage drop in the display image can be reduced, which is very preferable.

Further, the hardware has an excellent effect that it can be constituted by a small-scale hardware.

(Operation Timing of Each Part) FIG. 25 shows a timing chart of the operation timing of each part.

In the figure, Hsync is a horizontal synchronizing signal, and DotCLK is a PLL in the timing generation circuit.
A clock generated by the circuit from the horizontal synchronizing signal Hsync, R, G, B are digital image data from the input switching circuit, Data is image data after data array conversion,
Dout is image data that has been subjected to voltage drop correction, TSF
T is a shift clock for transferring the image data Dout to the shift register 5, Dataload is a load pulse for latching data in the latch circuit 6, and Pwms
start is the start signal of the above-mentioned pulse width modulation, the modulation signal X
D1 is an example of a pulse width modulation signal supplied to the modulation wiring 1.

With the start of one horizontal period, the digital image data RGB is transferred from the input switching circuit. In the figure, in the horizontal scanning period I, when the input image data is represented by R_I, G_I, and B_I, the image data is stored in the data array conversion circuit 9 for one horizontal period, and in the horizontal scanning period I + 1. , Is output as digital image data Data_I according to the pixel arrangement of the display panel.

R_I, G_I and B_I are input to the correction data calculating means in the horizontal scanning period I. With this means, the number of times of lighting described above is counted, and at the end of counting, the voltage drop amount is calculated.

Subsequent to the calculation of the voltage drop amount, the discrete correction data is calculated, and the calculation result is stored in the register.

In the scanning period I + 1, in synchronization with the output of the image data Data_I one horizontal scanning period before from the data array conversion unit, the correction data interpolating means interpolates the discrete correction data and outputs the correction data. It is calculated. The interpolated correction data is immediately subjected to gradation number conversion by the gradation number conversion unit 15 and supplied to the adder 12.

The adder 12 sequentially adds the image data Data and the correction data CD to obtain the corrected image data Do.
Transfer ut to the shift register. The shift register is T
Image data Dou for one horizontal period according to sft
t is stored, serial-parallel conversion is performed, and parallel image data ID1 to IDN are output to the latch circuit 6. The latch circuit 6 latches the parallel image data ID1 to IDN from the shift register according to the rising edge of Dataload, and transfers the latched image data D1 to DN to the pulse width modulation means 8.

The pulse width modulation means 8 outputs a pulse width modulation signal having a pulse width corresponding to the latched image data. In the image display device of the present embodiment, as a result, the pulse width output by the modulation means is displayed with a delay of two horizontal scanning periods with respect to the input image data.

When an image is displayed by such an image display device, it is possible to correct the amount of voltage drop in the scanning wiring, which has been a problem in the past, and it is possible to improve the deterioration of the displayed image due to it. It was possible to display a very good image.

Further, correction data can be calculated very easily by calculating correction data discretely and interpolating between discretely calculated points. It was very effective, as it could be achieved with simple hardware.

(Second Embodiment) In the first embodiment described above together with the embodiments, the sequential calculation is performed according to the image signal, the IF is determined, and the correction is performed. In this embodiment, in order to reduce the calculation load, a memory that outputs data indicating an IF value corresponding to the image signal pattern is used.

Specifically, a memory is used which inputs the number of lights of each block and outputs IFi.

By changing the number of lights in each block in advance, the first
The storage contents of the memory were determined by performing the same calculation as in the above embodiment. That is, as shown in FIG. 26, the number of modulation wirings included in block 0 is N0, and the number of modulation wirings included in block 1 is N.
1, the number of modulation wirings included in the block 2 is N2, the number of modulation wirings included in the block 3 is N3, and the number of lighting of the block 0 is X.
0 (X0 is an integer from 0 to N0), the number of lights in block 1 is X1 (X1 is an integer from 0 to N1), the number of lights in block 2 is X2 (X2 is an integer from 0 to N2), the number of lights in block 3 Is X3 (X3 is an integer from 0 to N3),
All the data of IF1, IF2, and IF3 are obtained and stored in the memory. As a result, IF0 and IF are input with X0, X1, X2, and X3, which are values corresponding to the image signal, as inputs.
Values indicating 1, IF2, IF3 can be output from the memory.

Generation of a modulation signal using this value is performed in the same manner as in the first embodiment.

In the present embodiment, the calculation in real time can be further reduced.

It should be noted that the voltage drop DV or the emission current amount Ie may be adopted as the information stored in the memory. In this case, there is an advantage that the conversion table from IF to Ie can be omitted.

[0296]

As described above, according to the present invention, it has been possible to improve the deterioration of the displayed image due to the voltage drop on the scanning wiring, which has been a conventional problem.

Further, by introducing some approximations, the correction amount of the image data for correcting the voltage drop can be easily calculated, and it can be realized by very simple hardware. It had a very good effect.

[Brief description of drawings]

FIG. 1 is a diagram showing an overview of an image display device.

FIG. 2 is a diagram showing an electrical connection of a display panel.

FIG. 3 is a diagram showing characteristics of a surface conduction electron-emitting device.

FIG. 4 is a diagram showing a driving method of a display panel.

FIG. 5 is a diagram illustrating an influence of a voltage drop.

FIG. 6 is a diagram illustrating a degenerate model.

FIG. 7 is a diagram illustrating a degenerate model.

FIG. 8 is a flowchart illustrating a convergence method by iterative calculation.

FIG. 9 is a graph showing a voltage drop amount calculated discretely.

FIG. 10 is a graph showing the amount of change in emission current calculated discretely.

FIG. 11 is a diagram illustrating an example of calculating correction data when the size of image data is 64.

FIG. 12 is a diagram showing an example of calculation of correction data when the size of image data is 128.

FIG. 13 is a diagram showing an example of calculation of correction data when the size of image data is 192.

FIG. 14 is a diagram for explaining an interpolation method of correction data.

FIG. 15 is a block diagram showing a schematic configuration of an image display device including a correction circuit.

FIG. 16 is a block diagram showing a configuration of a scanning circuit of the image display device.

FIG. 17 is a block diagram showing a configuration of an inverse γ processing unit of the image display device.

FIG. 18 is a block diagram showing a configuration of a data array conversion unit of the image display device.

FIG. 19 is a diagram illustrating the configuration and operation of the modulation means of the image display device.

FIG. 20 is a timing chart of the modulation means of the image display device.

FIG. 21 is a block diagram showing a configuration of a correction data calculation unit of the image display device.

FIG. 22 is a block diagram showing a configuration of a discrete correction data calculation unit of the image display device.

FIG. 23 is a block diagram showing a configuration of a correction data interpolation unit.

FIG. 24 is a block diagram showing a configuration of a linear approximation unit.

FIG. 25 is a timing chart of the image display device.

FIG. 26 is a block diagram showing a configuration of a memory according to the second embodiment.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 display panel 2 scanning circuit 8 pulse width modulation means 12 adder 14 correction data calculation means 17 inverse γ processing section 19 delay circuits 100a, 100b, 100c, 100d lighting number counting means 101a, 101b, 101c, 101d register group 103 table memory 110 table memories 107a, 107b, 107c comparators 123, 124 decoder 1001 substrate 1002 cold cathode device 1003 row wiring (scanning wiring) 1004 column wiring (modulation wiring) 1007 face plate 1008 fluorescent film

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 642 G09G 3/20 642A 642C 3/30 3/30 K (72) Inventor Osamu Sagano Tokyo 3-30-2 Shimomaruko, Ota-ku Canon Inc. F-term (reference) 5C080 AA06 AA18 BB05 DD05 EE28 JJ02 JJ04 JJ05

Claims (13)

[Claims] 1. An image display device, comprising: a plurality of scanning wirings; a plurality of modulation wirings that are not parallel to the scanning wirings; and a plurality of scanning wirings and a plurality of modulation wirings that correspond to respective intersections of the scanning wirings and the plurality of modulation wirings. A plurality of display elements respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and sequentially applying selection signals to the scanning wirings and modulating in accordance with image signals input to each of the modulation wirings. A drive circuit that gives a signal, and the drive circuit inputs a correction data circuit that calculates a current flowing through the modulation wiring and generates correction data based on the calculated value; and the correction data. A correction circuit that generates the modulation signal based on an image signal, and the correction data circuit is configured so that a predetermined current flows in the modulation wiring and is determined according to the image signal. Voltage drop calculation for calculating the voltage drop on the inspection wiring, current value calculation for calculating the current value flowing through the modulation wiring when the voltage drop calculated by the previous voltage drop calculation occurs, and previous current value calculation And a further voltage drop calculation for calculating a voltage drop on the scanning wiring, which is determined according to the image signal as the current value calculated in step S6 flows through the modulation wiring, and is calculated by the further voltage drop calculation. A circuit for performing a further current value calculation for calculating a current value flowing in the modulation wiring when a voltage drop occurs, and the further voltage drop calculation and the further current value calculation being obtained by the calculation. An image display device, characterized in that it is performed until a difference between the current value or the voltage drop value and the current value or the voltage drop value obtained by the previous calculation becomes a predetermined value or less. 2. An image display device, wherein a plurality of scanning wirings, a plurality of modulation wirings that are non-parallel to the scanning wirings, and a plurality of scanning wirings and a plurality of modulation wirings are provided corresponding to respective intersections. A plurality of display elements respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and sequentially applying selection signals to the scanning wirings and modulating in accordance with image signals input to each of the modulation wirings. A drive circuit that gives a signal, and the drive circuit inputs a correction data circuit that calculates a current flowing through the modulation wiring and generates correction data based on the calculated value; and the correction data. A correction circuit that generates the modulation signal based on an image signal, and the correction data circuit is configured so that a predetermined current flows in the modulation wiring and is determined according to the image signal. Voltage drop calculation for calculating the voltage drop on the inspection wiring, current value calculation for calculating the current value flowing through the modulation wiring when the voltage drop calculated by the previous voltage drop calculation occurs, and previous current value calculation And a further voltage drop calculation for calculating a voltage drop on the scanning wiring, which is determined according to the image signal as the current value calculated in step S6 flows through the modulation wiring, and is calculated by the further voltage drop calculation. A circuit for performing a further current value calculation for calculating a current value flowing in the modulation wiring when a voltage drop occurs, and repeating the further voltage drop calculation and the further current value calculation a plurality of times. Characteristic image display device. 3. The voltage drop calculation and the further voltage drop calculation divide the plurality of modulation wirings into blocks each including a plurality of the modulation wirings, and the modulation wirings belonging to each block are responsive to the image signal. The image display device according to claim 1, wherein the current values flowing are aggregated to perform a calculation. 4. The image display device according to claim 1, wherein the pulse width of the modulation signal is corrected by the value of the correction data. 5. The modulation signal has a pulse width that changes according to the image signal.
The image display device according to any one of 1. 6. An image display device, wherein a plurality of scanning wirings, a plurality of modulation wirings that are non-parallel to the scanning wirings, and a plurality of scanning wirings and a plurality of modulation wirings are provided corresponding to respective intersections. A plurality of display elements respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and sequentially applying selection signals to the scanning wirings and modulating in accordance with image signals input to each of the modulation wirings. And a drive circuit for giving a signal, wherein the drive circuit, the current flowing through the modulation wiring according to the statistical value of the image signal corresponding to each of the plurality of display elements connected to one scanning wiring A memory that outputs a value indicating a value, a correction data circuit that generates correction data based on the output from the memory and the image signal, and the modulation signal based on the correction data and the input image signal. The image display apparatus characterized by and a modulation circuit for generating. 7. The memory divides the plurality of modulation wirings into blocks each including the plurality of modulation wirings, and according to a value obtained by collecting current values flowing in the modulation wirings belonging to each block according to the image signal. 7. The image display device according to claim 6, wherein the image display device outputs a value indicating a current value flowing through the modulation wiring. 8. The image display device according to claim 6, wherein the correction data is data for correcting a display defect due to a voltage drop in the scanning wiring. 9. The image display device according to claim 5, wherein the pulse width of the modulation signal is corrected by the value of the correction data. 10. The image display device according to claim 5, wherein the modulation signal has a pulse width that changes according to the image signal. 11. A display method of an image display device, comprising: a plurality of scanning wirings, a plurality of modulation wirings that are not parallel to the scanning wirings, and a plurality of intersections of the plurality of scanning wirings and the plurality of modulation wirings. A plurality of display elements which are respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and which sequentially supply selection signals to the scanning wirings, and to apply image signals to the respective modulation wirings. The image display device has a drive circuit that provides a corresponding modulation signal, and the drive circuit calculates a current flowing through the modulation wiring and generates correction data based on the calculated value. A modulation circuit that generates the modulation signal based on the correction data and an input image signal, wherein a predetermined current flows in the modulation wiring in the correction data circuit. A voltage drop calculation for calculating a voltage drop on the scanning wiring determined according to the image signal, and a current for calculating a current value flowing through the modulation wiring when the voltage drop calculated by the previous voltage drop calculation occurs. A value calculation, and a further voltage drop calculation for calculating a voltage drop on the scanning wiring which is determined according to the image signal as a current value calculated by the current value calculation flowing through the modulation wiring, Further current value calculation for calculating a current value flowing through the modulation wiring when a voltage drop calculated by the further voltage drop calculation occurs, and the further voltage drop calculation and the further current value calculation The image is characterized in that the difference between the current value or the voltage drop value obtained by the calculation is less than a predetermined value from the current value or the voltage drop value obtained by the previous calculation. Display method of display device. 12. A display method for an image display device, comprising: a plurality of scanning wirings, a plurality of modulation wirings that are not parallel to the scanning wirings, and intersections of the plurality of scanning wirings and the plurality of modulation wirings. A plurality of display elements which are respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and which sequentially supply selection signals to the scanning wirings, and to apply image signals to the respective modulation wirings. The image display device has a drive circuit that provides a corresponding modulation signal, and the drive circuit calculates a current flowing through the modulation wiring and generates correction data based on the calculated value. A modulation circuit that generates the modulation signal based on the correction data and an input image signal, wherein a predetermined current flows in the modulation wiring in the correction data circuit. A voltage drop calculation for calculating a voltage drop on the scanning wiring determined according to the image signal, and a current for calculating a current value flowing through the modulation wiring when the voltage drop calculated by the previous voltage drop calculation occurs. A value calculation, and a further voltage drop calculation for calculating a voltage drop on the scanning wiring which is determined according to the image signal as a current value calculated by the current value calculation flowing through the modulation wiring, Further current value calculation for calculating a current value flowing through the modulation wiring when a voltage drop calculated by the further voltage drop calculation occurs, and the further voltage drop calculation and the further current value calculation A method of displaying an image display device, characterized in that the above is repeated a plurality of times. 13. A display method of an image display device, comprising: a plurality of scanning wirings, a plurality of modulation wirings that are not parallel to the scanning wirings, and a plurality of intersections of the plurality of scanning wirings and the plurality of modulation wirings. A plurality of display elements which are respectively connected to the corresponding scanning wirings and the corresponding modulation wirings, and which sequentially supply selection signals to the scanning wirings, and to apply image signals to the respective modulation wirings. And a drive circuit for giving a modulated signal according to the drive circuit, wherein the drive circuit according to a statistical value of the image signal corresponding to each of the plurality of display elements connected to one scanning wiring in the memory An image signal that outputs a value indicating a current value flowing in the modulation wiring, generates correction data based on the output from the memory and the image signal in the correction data circuit, and inputs the correction data in the modulation circuit. Display method of the image display apparatus, characterized in that to generate the modulated signal based on.