JP2007129030A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device having a stable wiring resistance as an integrated circuit wiring having a W plug by suppressing abnormal oxidation of a W plug surface and a method for manufacturing the same.
A lower conductive region and an upper wiring layer are separated by an interlayer insulating film. A tungsten plug 15 and a dummy tungsten plug 15D are provided through holes 14 and 14D penetrating the insulating film 12. The dummy tungsten plug 15D is provided adjacent to the tungsten plug 15 and is coupled to the lower conductive region 11 but is electrically open in the upper layer. Even if the surface of the tungsten plug 15 comes into contact with pure water during cleaning such as after CMP, a large amount of electron supply source is secured by the dummy tungsten plug 15D. Thereby, adhesion of the oxide on the surface of the tungsten plug 15 is suppressed, and an increase in resistance is also suppressed.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device having a wiring connection portion formed with a CMP process and a manufacturing method thereof.

  Multilayer wiring is common in the manufacture of semiconductor devices. In the multilayer wiring forming technology, blanket W and subsequent W etch-back processing or CMP (chemical mechanical polishing) processing for forming W (tungsten) plugs in contact holes and via holes are well known.

  In the integrated circuit wiring, the W etching rate varies between a dense part and a sparse part where the distribution of W plugs serving as contacts or vias varies. This is a phenomenon called a so-called loading effect, and the etching rate of W in a sparse part becomes relatively large. Accordingly, the upper portion of the W plug embedded in the relatively sparse contact hole or via hole is excessively etched, and the embedded state is not good. As a result, the W plug has a reduced contact area with the upper aluminum wiring layer, resulting in high resistance.

As a countermeasure, in the integrated circuit wiring, a dummy hole not connected to the wiring or the diffusion layer is formed in the vicinity of the W plug where the W plug distribution is sparse, and W is buried in the same manner as the W plug. This improves the non-uniformity of the W plug distribution exposed at the time of etch back and suppresses the loading effect (see, for example, Patent Document 1).
JP-A-6-85080 (paragraph numbers [0026], [0027], page 3, FIG. 1)

  Another cause different from the loading effect described above is that the wiring resistance of the sparse part, more specifically, the isolated W plug becomes higher than that of the dense part. At the time of forming the W plug, for example, the blanket of W is planarized and removed by CMP, but it contacts with pure water at the time of cleaning after CMP. At that time, abnormal oxidation may occur on the surface of the W plug, which causes an increase in wiring resistance.

At the time of cleaning after CMP, W usually reacts with H ₂ O + O ₂ (WO ₃ ), and OH ⁻ acts on WO ₃ by being mediated by electrons to become WO 4 ²⁻ and is detached from the surface of the W plug. However, if the W plug is isolated, the supply of electrons does not catch up and often remains on the surface of the W plug as WO ₃ . As a result, an abnormal oxide is formed on the surface of the W plug, and the contact area between the high-quality W and the upper aluminum wiring layer is reduced, resulting in high resistance.

  The present invention has been made in view of the above circumstances, and provides a semiconductor device having a stable wiring resistance as an integrated circuit wiring having a W plug by suppressing abnormal oxidation of the surface of the W plug and a method for manufacturing the same. It is what.

  A semiconductor device according to the present invention is formed so as to be adjacent to the tungsten plug, a tungsten plug that electrically connects a lower conductive region and an upper wiring through an insulating film between layers of a semiconductor integrated circuit, and the lower conductive region And one or more dummy tungsten plugs that are coupled to each other but are electrically open in the upper layer.

  According to the semiconductor device of the present invention, the dummy tungsten plug has no meaning as an electric circuit constituting the semiconductor integrated circuit, but is coupled to the lower conductive region. Thereby, even if the surface of the tungsten plug comes into contact with pure water during cleaning, a large amount of electron supply source is secured by the dummy tungsten plug. Thereby, the adhesion of oxide on the surface of the tungsten plug is suppressed, and the increase in resistance is also suppressed.

Note that the semiconductor device according to the present invention has any of the following characteristics, so that a tungsten plug that is less likely to have a high resistance and is highly reliable can be realized.
The distance between the tungsten plug and the dummy tungsten plug is 2 μm or less.
The dummy tungsten plug is either on the side opposite to the extension direction of the upper layer wiring, on the left side with respect to the extension direction of the upper layer wiring, or on the right side with respect to the extension direction of the upper layer wiring, with reference to the end of the upper layer wiring. It is arranged in.
An island member is formed on the dummy tungsten plug with the same conductive material as that of the upper wiring.
The lower conductive region is any one of a metal wiring related to the semiconductor integrated circuit, a diffusion layer constituting a semiconductor element, a polysilicon layer, and a silicide layer.

  The method for manufacturing a semiconductor device according to the present invention relates to the formation of a semiconductor integrated circuit in a semiconductor wafer, and includes a plurality of adjacent holes including wiring and dummy that penetrate through an interlayer insulating film and expose a lower conductive region at the bottom. A step of depositing tungsten that simultaneously fills the holes via a barrier metal coating in the holes, and polishing and removing the tungsten up to the level of the upper surface of the holes, for wiring, dummy A CMP process for forming each tungsten plug, a process for forming an upper wiring member so as to cover each tungsten plug, and a selective etching of the upper wiring member to connect with the tungsten plug for wiring And a patterning step for forming an upper layer wiring.

  According to the semiconductor device manufacturing method of the present invention, pure water cleaning is involved after the CMP process for forming the tungsten plug. At this time, a dummy tungsten plug connected to the lower conductive region is provided in the same manner as the tungsten plug for wiring. Therefore, even if the tungsten plug surface comes into contact with pure water, a large amount of electron supply source is secured by the dummy tungsten plug. Thereby, the ionization of the oxide is promoted on the tungsten plug surface by the supply of electrons, and the adhesion of the oxide is suppressed.

Note that the method for manufacturing a semiconductor device according to the present invention has one of the following characteristics, and thus can be a tungsten plug that is more effective and less likely to have a high resistance and can have high reliability.
With respect to the holes, one or more dummy holes are formed adjacent to the wiring holes at 2 μm or less.
In the patterning step, an island-shaped member connected to the dummy tungsten plug is formed simultaneously with the upper layer wiring.

BEST MODE FOR CARRYING OUT THE INVENTION

  FIG. 1 is a cross-sectional view showing the main part of the semiconductor device according to the first embodiment of the present invention. The lower conductive region 11 and the upper wiring layer 13 are separated by an interlayer insulating film 12. A tungsten plug 15 and a dummy tungsten plug 15D are provided through holes 14 and 14D penetrating the insulating film 12.

  The lower conductive region 11 is a metal wiring related to a semiconductor integrated circuit in a semiconductor wafer or IC chip (not shown). In addition, the lower conductive region 11 may be a diffusion layer constituting a semiconductor element, a polysilicon layer of a gate, or a silicide layer. The insulating film 12 is provided on the lower conductive region 11 and serves as an insulating film between layers separating the upper wiring layer 13 and the lower conductive region 11. The upper wiring layer 13 is a metal wiring whose main component is aluminum, for example. The tungsten plug 15 is made of W (tungsten) embedded in the hole 14 via a barrier metal (not shown), and is responsible for electrical connection between the lower conductive region 11 and the upper wiring 13.

  On the other hand, the dummy tungsten plug 15D is provided adjacent to the tungsten plug 15 and is coupled to the lower conductive region 11 but is electrically open in the upper layer. The island-shaped member 13I is formed of the same conductive material as that of the upper layer wiring 13, but has no meaning in terms of an electric circuit. The island-like member 13I is considered to be accompanied by a cap function such as a tungsten diffusion barrier, but may be omitted if there is no problem.

  The dummy tungsten plug 15D preferably has a smaller separation distance P1 from the tungsten plug 15 and is set so as not to be larger than 2 μm (P1 ≦ 2 μm). Here, the dummy tungsten plug 15D is provided on the side opposite to the extending direction of the upper layer wiring with reference to the end portion of the upper layer wiring 13, but a plurality of tungsten plugs 15D are further adjacent to the tungsten plug 15. You may make it provide in the location which fits.

  According to the configuration of the above embodiment, the dummy tungsten plug 15 </ b> D has no meaning as an electric circuit constituting the semiconductor integrated circuit, but is coupled to the lower conductive region 11. Thereby, even if the surface of the tungsten plug 15 comes into contact with pure water during cleaning such as after CMP, a large amount of electron supply source is secured by the dummy tungsten plug 15D. Thereby, adhesion of the oxide on the surface of the tungsten plug 15 is suppressed, and an increase in resistance is also suppressed. Hereinafter, the manufacturing method will be described.

2A to 2C are cross-sectional views showing, in the order of steps, the main parts of the method for manufacturing a semiconductor device according to the second embodiment of the present invention, and the steps for realizing the configuration of the first embodiment. It shows in order. The same parts as those in FIG. 1 are described with the same reference numerals.
As shown in FIG. 2A, an interlayer insulating film 12 is formed on the lower conductive region 11 by a CVD method. Next, using a photolithography technique and an anisotropic etching technique, a plurality of holes 14 and 14D that penetrate the insulating film 12 and expose the lower conductive region 11 at the bottom are formed. The holes 14 and 14D are formed adjacent to each other for normal wiring and dummy. Preferably, at least one dummy hole 14D is formed adjacent to the wiring hole 14 at 2 μm or less. Next, W (tungsten) that simultaneously fills the holes 14 and 14D is deposited through a barrier metal (not shown) coating in the holes 14 and 14D (W blanket). The W blanket can be achieved using sputtering or metal CVD.

Next, as shown in FIG. 2B, the W blanket is polished and removed using a CMP technique. That is, W is polished and removed to the level of the upper surfaces of the holes 14 and 14D, and tungsten plugs 15 and 15D for wiring and dummy are formed and planarized. During the CMP process or after the CMP process, there is pure water cleaning of the wafer, and W on the upper surfaces of the holes 14 and 14D comes into contact with pure water. W reacts with H ₂ O + O ₂ (WO ₃ ), and OH ⁻ acts on WO ₃ by being mediated by electrons to become WO 4 ²⁻ and is detached from the surface of the W plug. Since the W plug 15D electrically connected to the W plug 15 via the lower conductive region 11 is provided, supply of electrons can be supplemented. Therefore, the surface of the W plug is unlikely to be in a state of retaining WO ₃ and the adhesion of oxide is suppressed.

  Next, as shown in FIG. 2C, an upper wiring member is formed so as to cover the W plugs 15 and 15D, and the upper wiring layer 13 is formed through a photolithography process and an etching process. The upper wiring layer 13 is, for example, a metal wiring mainly composed of aluminum, and has a thin protective metal including TiN or the like on the main wiring member Al and Al on a thin barrier metal including TiN or the like (not shown). . The island-shaped member 13I is the same member formed in the same process as the upper layer wiring 13, but has no meaning in terms of an electric circuit. The island-like member 13I is considered to be accompanied by a cap function such as a tungsten diffusion barrier, but may be omitted if there is no problem.

  According to the method of the above embodiment, pure water cleaning is performed after the CMP process for forming the W plug. At this time, a dummy W plug 15D connected to the lower conductive region is provided in the same manner as the W plug 15 for wiring. Therefore, even if the surface of the W plug 15 comes into contact with pure water, a large amount of electron supply source is secured by the dummy W plug 15D. Thereby, the ionization of the oxide is promoted on the surface of the W plug 15 by the supply of electrons, and the adhesion of the oxide is suppressed. As a result, a multilayer wiring having a W plug that does not easily become high resistance and that provides high reliability is realized.

  3A and 3B are plan views showing modifications of FIG. The same code | symbol is attached | subjected to the same location. As shown in each figure, the dummy W plug 15D is connected to the lower conductive region 11 and is connected to the lower conductive region 11 according to the design of the tip shape of the lower conductive region 11 and according to the empty region on the upper wiring side. Can be deployed. The dummy W plug 15 </ b> D can be freely arranged either on the side opposite to the extending direction of the upper layer wiring 13 or on the left side or the right side with respect to the extending direction of the upper layer wiring 13.

  According to FIG. 3A, the dummy W plug 15 </ b> D has the end of the upper layer wiring 13 connected to the W plug 15 as a reference, and the side opposite to the extension direction of the upper layer wiring 13 and the extension of the upper layer wiring 13. It is arranged on the left and right sides with respect to the direction. The separation distance P2 between each of the W plug 15 and the W plug 15D is set so as not to be larger than 2 μm (P2 ≦ 2 μm). The island-shaped member 13I is the same member formed in the same process as the upper layer wiring 13, but may be omitted if there is no problem.

  According to FIG. 3B, the dummy W plug 15 </ b> D is based on the end of the upper layer wiring 13 connected to the W plug 15 on the left side with respect to the extension direction of the upper layer wiring 13 and in the extension direction of the upper layer wiring 13. Two pieces are arranged on the right side. The separation distance P3 between the W plug 15 and the W plug 15D is set so as not to be larger than 2 μm (P3 ≦ 2 μm).

  Even in the configuration as shown in FIGS. 3A and 3B, the same effects as those of the first embodiment can be obtained. That is, even if the surface of the W plug 15 comes into contact with pure water during cleaning such as after CMP, a large amount of electron supply source is secured by the dummy W plug 15D. Thereby, the adhesion of oxide on the surface of the W plug 15 is suppressed, and the increase in resistance is also suppressed.

  Further, the configuration as shown in FIGS. 3A and 3B has other advantages. For example, it is possible to cope with a small design change in the wiring path. In FIG. 3A, instead of the configuration in which the W plug 15 is connected to the upper layer wiring 13, the design can be changed so that the upper layer wiring 13 is connected to any one of the W plugs 15D.

FIG. 4 is a plan view showing an application example of FIG. The same code | symbol is attached | subjected to the same location. The MOS FET Q1 is assumed to be isolated in the integrated circuit. The MOS FET Q1 has a source / drain diffusion layer S / D and a gate electrode G. It is conceivable that the source / drain diffusion layer S / D is a silicide layer. The gate electrode G may be a polysilicon layer or a silicide layer. The source / drain diffusion layers S / D and the gate electrode G are connected to the upper layer wirings 131, 132, and 133 through the W plugs 15 as the lower conductive regions 11, respectively. Therefore, a W plug 15D is provided for each of the source / drain diffusion layer S / D and the gate electrode G. Each of the W plugs 15D is preferably arranged within 2 μm in the vicinity of the W plug 15.
Even in such a configuration, the effects described in the first embodiment and FIGS. 3A and 3B can be obtained. That is, the adhesion of oxide on the surface of the W plug is suppressed, and the resistance increase suppressing effect is obtained. Moreover, it can be expected to cope with a small design change in the wiring path.

  As described above, according to the present invention, the dummy tungsten plug has no meaning as an electric circuit constituting the semiconductor integrated circuit, but is coupled to the lower conductive region. Thereby, even if the surface of the tungsten plug comes into contact with pure water during cleaning, a large amount of electron supply source is secured by the dummy tungsten plug. Thereby, the adhesion of oxide on the surface of the tungsten plug is suppressed, and the increase in resistance is also suppressed. As a result, abnormal oxidation of the W plug surface can be suppressed, and a semiconductor device with stable wiring resistance as an integrated circuit wiring having the W plug and a method for manufacturing the same can be provided.

  The present invention is not limited to the above-described embodiments and methods, and various modifications and applications can be implemented without departing from the spirit of the present invention.

Sectional drawing which shows the principal part of the semiconductor device which concerns on 1st Embodiment. Sectional drawing which shows the principal part of the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Each plan view showing a modification of FIG. The top view which shows the application example of FIG.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Lower conductive area, 12 ... Interlayer insulating film, 13, 131, 132, 133 ... Upper wiring layer, 13I ... Island-like member, 14, 14D ... Hole, 15 ... Tungsten (W) plug, 15D ... Dummy tungsten (W) Plug, Q1... MOS FET.

Claims (8)

A tungsten plug that electrically connects the lower conductive region and the upper wiring through an insulating film between layers of the semiconductor integrated circuit;
One or more dummy tungsten plugs formed adjacent to the tungsten plug and coupled to the lower conductive region but electrically open in the upper layer;
A semiconductor device comprising: The semiconductor device according to claim 1, wherein a separation distance between the tungsten plug and the dummy tungsten plug is 2 μm or less. The dummy tungsten plug is either on the side opposite to the extending direction of the upper layer wiring, on the left side with respect to the extending direction of the upper layer wiring, or on the right side with respect to the extending direction of the upper layer wiring with respect to the end of the upper layer wiring. The semiconductor device according to claim 1, wherein the semiconductor device is disposed on the semiconductor device. 4. The semiconductor device according to claim 1, wherein an island member is formed of the same conductive material as that of the upper layer wiring on the dummy tungsten plug. 5. The semiconductor according to claim 1, wherein the lower conductive region is any one of a metal wiring related to the semiconductor integrated circuit, a diffusion layer constituting a semiconductor element, a polysilicon layer, and a silicide layer. apparatus. Regarding semiconductor integrated circuit formation in a semiconductor wafer, a step of forming a plurality of adjacent holes including a wiring and a dummy for exposing a lower conductive region at the bottom through an interlayer insulating film;
Depositing tungsten that simultaneously fills the holes via a barrier metal coating in the holes;
CMP process for polishing and removing the tungsten to the level of the upper surface of each hole to form tungsten plugs for wiring and dummy,
Forming an upper wiring member so as to cover each of the tungsten plugs;
A patterning step of forming an upper layer wiring connected to the tungsten plug for wiring by selectively etching the upper layer wiring member;
A method for manufacturing a semiconductor device comprising: The method for manufacturing a semiconductor device according to claim 6, wherein the one or more dummy holes are formed so as to be adjacent to the wiring hole at 2 μm or less. 8. The method of manufacturing a semiconductor device according to claim 6, wherein an island-like member connected to the dummy tungsten plug is formed simultaneously with the upper layer wiring in the patterning step.

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