JP2018056294A - Semiconductor device manufacturing method - Google Patents

Abstract

[Problem] To provide a technology for suitably removing abnormal growths of a metal layer. [Solution] An interlayer insulating film 28 is formed on a semiconductor substrate, and the interlayer insulating film 28 is etched from the front surface to form contact trenches 50 penetrating from the front surface to the back surface, and non-contact trenches 52 shallower than the contact trenches 50, thereby partitioning the surface of the interlayer insulating film 28 into a plurality of sections 28a. A first metal layer thinner than the depth of the non-contact trenches is formed on the surface of the interlayer insulating film 28, the inner surfaces of the contact trenches 50, and the inner surfaces of the non-contact trenches 52. A second metal layer is formed on the surface of the first metal layer so as to fill the contact trenches, and then the second metal layer is etched so that the second metal layer remains in the contact trenches. The maximum size of abnormal growth occurring in the second metal layer is specified, and the second metal layer can be etched without excess or deficiency. [Selected Figure] Figure 1

Description

  The present specification discloses a method for manufacturing a semiconductor device.

  There is known a semiconductor device in which a gate electrode is provided in a trench formed on the surface of a semiconductor substrate, and an interlayer insulating film is provided on the surface of the semiconductor substrate and on the gate electrode. Also, a technique for forming a contact groove penetrating from the front surface to the back surface of the interlayer insulating film is known in order to make electrical contact between the upper electrode provided on the interlayer insulating film and the semiconductor substrate. In this technique, the first metal layer is formed on the inner surface of the contact groove and the surface of the interlayer insulating film, and then the second metal layer is filled in the contact groove.

  When a defect exists in the first metal layer, the second metal layer formed at the position of the defect expands, and abnormal growth of the second metal layer occurs. The abnormally grown product proceeds while peeling off the first metal layer, and its size increases. If abnormal growth exists, the flatness of the upper electrode formed on the upper part is lowered. As a result, stress may be applied to the upper electrode, causing cracks. For this reason, the presence of abnormal growth affects the reliability of the semiconductor device.

  Patent Document 1 discloses a method for removing such abnormal growth. In Patent Document 1, a resist is formed on the second metal layer filled in the contact groove, and the abnormally grown product of the second metal layer abnormally grown on the interlayer insulating film is removed by etching.

JP-A-6-236874

  As abnormal growth continues, the size of abnormal growth increases accordingly. Current technology cannot accurately define the maximum size of abnormal growth. In particular, it is difficult to define the size of abnormally grown products in the thickness direction of the semiconductor substrate. For this reason, even if there exists a technique of patent document 1, it is difficult to set the etching amount without excess and deficiency. As described above, when the abnormal growth cannot be removed, the upper electrode cannot be formed flat, and the reliability of the semiconductor device is lowered. The present specification discloses a technique capable of managing the size of abnormally grown products and setting an etching amount without excess or deficiency.

  As a result of studying the abnormal growth phenomenon, the following was found. Abnormal growth of the second metal layer proceeds in the plane direction of the interlayer insulating film while peeling off the first metal layer. When the abnormally grown product reaches the periphery of the contact groove, the force in the surface direction acts on the boundary between the surface of the interlayer insulating film and the side surface of the contact groove, and the first metal film is broken. Thereby, the abnormal growth of the second metal layer stops. That is, the abnormal growth phenomenon continues until the abnormally grown product reaches the peripheral edge of the contact groove, and the abnormal growth stops when the abnormally grown product reaches the peripheral edge of the contact groove. From the above knowledge, the idea has been obtained that the size of the abnormally grown product can be managed, and the etching amount can be set without excess or deficiency in order to remove the abnormally grown product.

  A method of manufacturing a semiconductor device disclosed in this specification includes a step of forming an interlayer insulating film on a semiconductor substrate, a contact groove that etches the interlayer insulating film from the surface, and penetrates from the surface to the back surface of the interlayer insulating film, Forming a non-contact groove shallower than the contact groove and partitioning the surface of the interlayer insulating film into a plurality of layers, the surface of the interlayer insulating film, the inner surface of the contact groove, and the inner surface of the non-contact groove, Forming a first metal layer thinner than the first metal layer; forming a second metal layer on the surface of the first metal layer so as to fill the contact groove; and leaving the second metal layer in the contact groove. Thus, a step of etching the second metal layer is provided.

  In the above manufacturing method, in addition to the contact groove, a non-contact groove is formed on the surface of the interlayer insulating film. For this reason, even when the second metal layer grows abnormally, when the abnormally grown product reaches the periphery of the non-contact trench, the first metal layer is formed at the boundary between the surface of the interlayer insulating film and the side surface of the non-contact trench. Surface force acts. Since the thickness of the first metal layer is thinner than the depth of the non-contact groove, the first metal layer breaks at the boundary. Thereby, the abnormal growth of the second metal layer stops. Furthermore, the surface of the interlayer insulating film is partitioned into a plurality of parts by contact grooves and non-contact grooves. For this reason, by adjusting the area of each section, the growth size of the abnormally grown product can be managed to a desired size.

  Note that the step of forming the contact groove and the step of forming the non-contact groove may be performed separately or simultaneously.

The top view of MOSFET10 of an Example. Sectional drawing in the II-II line of FIG. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example. Explanatory drawing of the manufacturing method of MOSFET10 of an Example.

  One embodiment of a semiconductor device manufacturing method disclosed in this specification will be described with reference to the drawings. The semiconductor device manufactured by the manufacturing method according to the present embodiment is a kind of power semiconductor device, and is used, for example, in a power supply circuit that supplies current to a load such as a motor.

  First, the MOSFET 10 manufactured by the manufacturing method according to the present embodiment will be described. As shown in FIGS. 1 and 2, the MOSFET 10 includes a semiconductor substrate 12, an electrode, an insulating layer, and the like. In FIG. 1, the illustration of the configuration on the surface 12 a of the semiconductor substrate 12 (above the interlayer insulating film 28) is omitted for easy viewing. Hereinafter, a direction in which the trench 22 extends long when the surface 12a is viewed in plan is referred to as a y direction, and a direction parallel to the surface 12a and orthogonal to the y direction is referred to as an x direction. The thickness direction of the semiconductor substrate 12 is referred to as the z direction. The semiconductor substrate 12 is made of, for example, Si.

  A plurality of trenches 22 are provided on the surface 12 a of the semiconductor substrate 12. As indicated by broken lines in FIG. 1, each trench 22 extends linearly in the y direction. The trenches 22 are arranged at intervals in the x direction.

  As shown in FIG. 2, the inner surface of the trench 22 is covered with a gate insulating film 24. A gate electrode 26 is disposed in the trench 22. The gate electrode 26 is insulated from the semiconductor substrate 12 by the gate insulating film 24.

The surface 12 a of the semiconductor substrate 12 and the surface of the gate electrode 26 are covered with an interlayer insulating film 28. The interlayer insulating film 28 is made of, for example, silicon oxide (SiO ₂ ). Contact grooves 50 and non-contact grooves 52 are formed in the interlayer insulating film 28.

  The contact groove 50 penetrates from the front surface to the back surface of the interlayer insulating film 28. As shown in FIG. 1, the contact groove 50 is formed in a range sandwiched by the trenches 22 in plan view. The contact groove 50 is not formed in the upper part of the trench 22. The contact grooves 50 are formed in a lattice shape in a plan view by portions 50a extending in the y direction at equal intervals in the x direction and portions 50b extending in the x direction at equal intervals in the y direction.

  The non-contact groove 52 is shallower than the contact groove 50. That is, the non-contact trench 52 does not reach the back surface of the interlayer insulating film 28. The non-contact groove 52 is formed in the upper part of the trench 22 and in the vicinity thereof. Specifically, as shown in FIG. 1, the non-contact groove 52 includes a portion 52 a extending in the y direction along the upper portion of the trench and a plurality of portions 52 b extending in the x direction at equal intervals from the portion 52 a in the y direction. It is configured.

  As shown in FIG. 1, when viewed in plan, the contact grooves 50 and the non-contact grooves 52 are formed in a lattice shape. The contact groove 50 and the non-contact groove 52 are connected with a step at a point where they are adjacent to each other. The contact trench 50 and the non-contact trench 52 divide the surface of the interlayer insulating film 28 into a plurality of rectangular regions 28a.

  As shown in FIG. 2, the first metal layer 40 is coated on the surface of the interlayer insulating film 28, the inner surface of the contact groove 50, and the inner surface of the non-contact groove 52. The first metal layer 40 has a Ti layer made of titanium (Ti) and a TiN layer made of titanium nitride (TiN). The Ti layer is in contact with the surface of the interlayer insulating film 28, the inner surface of the contact groove 50, and the inner surface of the non-contact groove 52, and the TiN layer is laminated on the Ti layer. The thickness of the first metal layer 40 is thinner than the depth of the non-contact groove 52.

  The space above the first metal layer 40 in the contact groove 50 and the space above the first metal layer 40 in the non-contact groove 52 are filled with the second metal layer 42 without a gap. The second metal layer 42 is made of tungsten (W). The surface of the second metal layer 42 and the surface of the interlayer insulating film 28 have substantially the same height. Therefore, a substantially flat plane is formed by the surface of the second metal layer 42 and the surface of the interlayer insulating film 28.

  An upper electrode 70 is formed on the first metal layer 40 and the second metal layer 42. The upper electrode 70 is made of, for example, aluminum (Al). The upper electrode 70 covers almost the entire area on the first metal layer 40 and the second metal layer 42. The upper electrode 70 is insulated from the gate electrode 26 by the interlayer insulating film 28.

  Note that the space in the non-contact groove 52 may not be filled with the second metal layer 42. The space in the non-contact groove 52 may be filled with the upper electrode 70 instead of the second metal layer 42. Further, the first metal layer 40 may not be coated on the surface of the interlayer insulating film 28 and the inner surface of the non-contact groove 52.

  Next, the internal structure of the semiconductor substrate 12 will be described. As shown in FIG. 2, a source region 30, a body region 32, a drift region 33, and a drain region 34 are formed in the semiconductor substrate 12.

  The source region 30 is an n-type region and is exposed on the surface of the semiconductor substrate 12. The source region 30 is in contact with the gate insulating film 24.

  Body region 32 is a p-type region and is in contact with source region 30. The body region 32 is exposed on the surface of the semiconductor substrate 12 in a range between the source regions 30. The body region 32 is in contact with the gate insulating film 24 below the source region 30.

  The drift region 33 is an n-type region and is formed below the body region 32. The drift region 33 is separated from the source region 30 by the body region 32. The drift region 33 is in contact with the gate insulating film 24 below the body region 32. The drift region 33 has an n-type impurity concentration lower than that of the source region 30.

  The drain region 34 is an n-type region and is formed below the drift region 33. The drain region 34 is separated from the body region 32 by the drift region 33. The drain region 34 is exposed on the back surface 12 b of the semiconductor substrate 12. A lower electrode 80 is formed on the entire back surface 12 b of the semiconductor substrate 12.

  Next, an example of a method for manufacturing the MOSFET 10 of this embodiment will be described. In the following, only the process that is a feature of the present embodiment will be described. Therefore, an actual manufacturing method may include one or a plurality of steps that are not included in the following description as necessary.

  First, the semiconductor substrate 12 before the formation of the MOSFET 10 shown in FIG. 3 is prepared. The semiconductor substrate 12 has a drift region 33, a body region 32, and a source region 30. The body region 32 and the source region 30 can be formed by a conventionally known method such as ion implantation or epitaxial growth. Further, as shown in FIG. 4, a trench 22, a gate insulating film 24, and a gate electrode 26 are formed by a conventionally known method.

  Next, as shown in FIG. 5, an interlayer insulating film 28 is formed on the surface 12 a of the semiconductor substrate 12 and the surface of the gate electrode 26.

  Next, as shown in FIGS. 6 and 7, the non-contact trench 52 is formed by partially etching the interlayer insulating film 28. The non-contact groove 52 is formed in a region where the semiconductor substrate 12 and the upper electrode 70 formed in a later process are not in contact with each other. For example, the non-contact groove 52 is formed in the upper part of the trench 22. In the present embodiment, as shown in FIG. 7, the upper portion of the trench 22 includes a portion 52 a extending in the y direction and a plurality of portions 52 b extending in the x direction so as to be orthogonal thereto and arranged at equal intervals in the y direction. A non-contact groove 52 is formed. The depth of the non-contact trench 52 is a depth that does not penetrate the interlayer insulating film 28 and is deeper than the thickness of the first metal layer 40 described later.

  Next, as shown in FIGS. 8 and 9, the interlayer insulating film 28 is partially etched to form a contact groove 50 penetrating from the front surface to the back surface. The contact groove 50 is formed in a region where the semiconductor substrate 12 and the upper electrode 70 are in contact with each other. For example, the body region 32 is formed on the bottom surface of the contact groove 50 so as to be exposed. In the present embodiment, as shown in FIG. 9, a contact groove 50 constituted by a plurality of portions 50a extending in the y direction and a plurality of portions 50b extending in the x direction is formed.

  As is apparent from FIG. 9, when viewed in plan, the contact grooves 50 and the non-contact grooves 52 are formed in a lattice shape. In other words, the contact trench 50 and the non-contact trench 52 divide the surface of the interlayer insulating film 28 into a plurality of rectangular regions 28a. The contact groove 50 and the non-contact groove 52 are connected with a step at a point where they are adjacent to each other.

  Next, as shown in FIG. 10, the first metal layer 40 is formed on the surface of the interlayer insulating film 28, the inner surface of the contact groove 50, and the inner surface of the non-contact groove 52 by sputtering. A Ti layer and a TiN layer constituting the first metal layer 40 are grown in order. The thickness of the first metal layer 40 is thinner than the depth of the non-contact groove 52 (the distance from the surface of the interlayer insulating film to the bottom surface of the non-contact groove). Since the thickness of the first metal layer 40 is thin, the first metal layer 40 preferably grows also on the inner surfaces of the contact groove 50 and the non-contact groove 52.

  Next, as shown in FIG. 11, the second metal layer 42 is formed on the surface of the first metal layer 40 so as to fill the contact groove 50 by CVD (Chemical Vapor Deposition). Specifically, the second metal layer 42 grows in the contact trench 50, the non-contact trench 52, and the surface of the interlayer insulating film 28. When the second metal layer 42 is formed, the first metal layer 40 prevents the elements (that is, tungsten) constituting the second metal layer 42 from diffusing into the semiconductor substrate 12. This prevents defects and the like from being formed in the contact portion of the semiconductor substrate 12.

  Next, as shown in FIG. 12, the second metal layer 42 is etched so that the second metal layer 42 in the contact groove 50 remains. Here, the second metal layer 42 on the upper part of the interlayer insulating film 28 is removed, and the second metal layer 42 is left in the contact groove 50 and the non-contact groove 52. More specifically, the etching is performed so that the surface of the second metal layer 42 remaining in the contact groove 50 substantially matches the surface of the first metal layer 40.

  Next, the upper electrode 70 is formed on the surface of the first metal layer 40 on the interlayer insulating film 28 and on the surface of the second metal layer 42 in the contact groove 50 and the non-contact groove 52. Next, an n-type impurity is implanted into the back surface 12 b of the semiconductor substrate 12 to form the drain region 34. Next, the lower electrode 80 is formed on the back surface of the semiconductor substrate 12. Through the above steps, MOSFET 10 shown in FIG. 2 is completed.

  In a conventional semiconductor device (that is, a semiconductor device having no non-contact groove), the surface of the interlayer insulating film is wide in a region where the semiconductor substrate and the upper electrode are not in contact. For this reason, when the abnormal growth of the second metal layer occurs in the region, the abnormally grown product has a large size. Therefore, it becomes difficult to define the etching amount, and the reliability of the semiconductor device is affected when the abnormally grown product cannot be etched. However, the manufacturing method of this embodiment includes a step of forming a non-contact groove 52 in a region where the semiconductor substrate 12 and the upper electrode 70 do not contact each other. The surface of the interlayer insulating film 28 is partitioned into a plurality of rectangular regions 28 a by the contact grooves 50 and the non-contact grooves 52. Therefore, even when abnormal growth of the second metal layer 42 occurs during the subsequent formation of the second metal layer 42, the growth can be kept within the rectangular region 28a. By adjusting the area of the rectangular region 28a, the growth size of the abnormally grown product can be managed to a constant size. For this reason, the second metal layer 42 on the interlayer insulating film 28 is surely removed by adjusting the etching amount of the second metal layer 42 so that the maximum growth size of the abnormally grown material in the rectangular region 28a can be etched. can do. That is, it is possible to simplify the regulation of the etching amount of the second metal layer 42.

  In the above-described embodiment, the example in which the step of forming the non-contact groove 52 and the step of forming the contact groove 50 are described separately, but these may be simultaneously formed in one step. In order to form the non-contact groove 52 and the contact groove 50 at the same time, for example, by making the width of the non-contact groove 52 narrower than the width of the contact groove 50, the etching rate of the non-contact groove 52 is set to the etching rate of the contact groove 50. Make it slower. Thereby, the non-contact groove 52 shallower than the contact groove 50 can be formed simultaneously with the contact groove 50. Since the non-contact groove 52 does not contribute to the contact between the upper electrode 70 and the semiconductor substrate 12, even if the width of the non-contact groove 52 is narrowed, the performance of the semiconductor device is not affected.

  Further, in the step of etching the second metal layer 42, the second metal layer 42 in the non-contact groove 52 may be removed. In the same step, the first metal layer 40 other than in the contact trench 50 (the surface of the interlayer insulating film 28 and the inner surface of the non-contact trench 52) may be removed simultaneously.

  Further, the shape of the region 28a is not limited to a rectangle. The region 28a may be formed in a polygonal shape, a circular shape, or the like by appropriately changing the pattern of the contact groove 50 and the non-contact groove 52.

  Further, the maximum length in the plane of the region 28 a may be equal to or less than the thickness of the upper electrode 70. According to this configuration, the abnormally grown product of the second metal layer 42 can be covered with the upper electrode 70 even if it reaches the maximum size in the region 28a.

  In the above-described embodiments, the MOSFET has been described. However, the technology disclosed in this specification may be applied in the manufacturing process of the IGBT. In the embodiment described above, an IGBT can be obtained by forming a p-type collector region instead of the n-type drain region.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings achieves a plurality of objects at the same time, and has technical utility by achieving one of the objects.

10: MOSFET
12: semiconductor substrate 12a: front surface 12b: back surface 22: trench 24: gate insulating film 26: gate electrode 28: interlayer insulating film 28a: rectangular region 30: source region 32: body region 33: drift region 34: drain region 40: first 1 metal layer 42: second metal layer 50: contact groove 52: non-contact groove 70: upper electrode 80: lower electrode

Claims (1)

Forming an interlayer insulating film on the semiconductor substrate;
Etching the interlayer insulating film from the surface, forming a contact groove penetrating from the surface to the back surface of the interlayer insulating film and a non-contact groove shallower than the contact groove, and partitioning the surface of the interlayer insulating film into a plurality of layers; ,
Forming a first metal layer thinner than the depth of the non-contact groove on the surface of the interlayer insulating film, the inner surface of the contact groove, and the inner surface of the non-contact groove;
Forming a second metal layer on the surface of the first metal layer so as to fill the contact groove;
Etching the second metal layer such that the second metal layer in the contact groove remains;
A method for manufacturing a semiconductor device comprising:

Images