KR100387255B1 - Method of forming a metal wiring in a semiconductor device - Google Patents
Method of forming a metal wiring in a semiconductor device Download PDFInfo
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- KR100387255B1 KR100387255B1 KR10-2000-0033982A KR20000033982A KR100387255B1 KR 100387255 B1 KR100387255 B1 KR 100387255B1 KR 20000033982 A KR20000033982 A KR 20000033982A KR 100387255 B1 KR100387255 B1 KR 100387255B1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 229910052751 metal Inorganic materials 0.000 title claims abstract description 43
- 239000002184 metal Substances 0.000 title claims abstract description 43
- 239000004065 semiconductor Substances 0.000 title claims abstract description 22
- 230000004888 barrier function Effects 0.000 claims abstract description 19
- 238000009792 diffusion process Methods 0.000 claims abstract description 18
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 125000006850 spacer group Chemical group 0.000 claims abstract description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 14
- 229910052802 copper Inorganic materials 0.000 claims description 14
- 239000010949 copper Substances 0.000 claims description 14
- 238000005229 chemical vapour deposition Methods 0.000 claims description 13
- 238000009713 electroplating Methods 0.000 claims description 9
- 238000005240 physical vapour deposition Methods 0.000 claims description 9
- 238000007747 plating Methods 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 4
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 4
- 238000005530 etching Methods 0.000 claims description 4
- 229910004200 TaSiN Inorganic materials 0.000 claims description 2
- 229910008482 TiSiN Inorganic materials 0.000 claims description 2
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical group [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 2
- QRXWMOHMRWLFEY-UHFFFAOYSA-N isoniazide Chemical compound NNC(=O)C1=CC=NC=C1 QRXWMOHMRWLFEY-UHFFFAOYSA-N 0.000 claims description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 2
- 238000000059 patterning Methods 0.000 claims description 2
- 239000010936 titanium Substances 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 claims description 2
- 229910052721 tungsten Inorganic materials 0.000 claims description 2
- 239000010937 tungsten Substances 0.000 claims description 2
- 238000000231 atomic layer deposition Methods 0.000 description 4
- 230000007547 defect Effects 0.000 description 2
- 229910010037 TiAlN Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000593 degrading effect Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/7685—Barrier, adhesion or liner layers the layer covering a conductive structure
- H01L21/76852—Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 하부 배선을 포함한 소정의 구조가 형성된 반도체 기판 상부에 시드층을 형성한 후 상기 하부 배선 부분이 시드층이 노출되도록 감광막 패턴을 형성하고, 전기도금법으로 상기 감광막의 패턴 부분에 금속층을 매립한 후 감광막 패턴을 제거하며, 상기 금속층의 측벽에 확산 장벽층 스페이서를 형성한 후 전체 구조 상부에 절연막을 형성함으로써 고집적 반도체 소자의 상부 금속 배선 형성 공정에서 공정 마진의 부족으로 인한 하부 금속 배선과의 접촉 불량을 해결할 수 있는 반도체 소자의 금속 배선 형성 방법이 제시된다.The present invention relates to a method for forming a metal wiring of a semiconductor device, and after forming a seed layer on top of a semiconductor substrate having a predetermined structure including a lower wiring, the lower wiring portion to form a photosensitive film pattern to expose the seed layer, and In the upper metal wiring forming process of the highly integrated semiconductor device, a metal layer is buried in the pattern portion of the photoresist layer, the photoresist layer pattern is removed, a diffusion barrier layer spacer is formed on the sidewall of the metal layer, and an insulating film is formed over the entire structure. Provided is a method of forming a metal wiring of a semiconductor device that can solve a poor contact with a lower metal wiring due to a lack of process margin.
Description
본 발명은 반도체 소자의 금속 배선 형성 방법에 관한 것으로, 특히 고집적 반도체 소자의 상부 금속 배선 형성 공정에서 공정 마진의 부족으로 인한 하부 배선과의 접촉 불량을 해결할 수 있는 반도체 소자의 금속 배선 형성 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for forming metal wirings in semiconductor devices, and more particularly, to a method for forming metal wirings in semiconductor devices capable of solving poor contact with lower wirings due to a lack of process margins in the process of forming upper metal wirings of highly integrated semiconductor devices. will be.
종래의 반도체 소자의 금속 배선 형성 방법을 도 1(a) 내지 도 1(c)를 참조하여 설명하면 다음과 같다.A method of forming a metal wiring of a conventional semiconductor device will be described below with reference to FIGS. 1A to 1C.
도 1(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(11) 상부에 제 1 절연막(12)을 형성한다. 제 1 절연막(12)의 소정 영역을 식각하고, 식각된 영역에 금속층을 형성한 후 패터닝하여 하부 금속 배선(13)을 형성한다. 전체 구조 상부에 제 2 절연막(14)을 형성한 후 소정 영역을 식각하여 하부 금속 배선(13)을 노출시키는 비아홀을 형성한다.Referring to FIG. 1A, a first insulating layer 12 is formed on a semiconductor substrate 11 on which a predetermined structure is formed. A predetermined region of the first insulating layer 12 is etched, a metal layer is formed on the etched region, and then patterned to form a lower metal wiring 13. After forming the second insulating layer 14 over the entire structure, a predetermined region is etched to form a via hole exposing the lower metal wiring 13.
도 1(b)를 참조하면, 비아홀을 포함한 전체 구조 상부에 확산 장벽층(15) 및 시드층(16)을 순차적으로 형성한다. 비아홀이 매립되도록 전체 구조 상부에 전기도금법으로 구리층(17)을 형성한다.Referring to FIG. 1B, the diffusion barrier layer 15 and the seed layer 16 are sequentially formed on the entire structure including the via holes. The copper layer 17 is formed on the entire structure by the electroplating method so that the via holes are buried.
도 1(c)는 CMP 공정을 실시하여 제 2 절연막(14)을 노출시켜 상부 금속 배선을 형성한다.FIG. 1C illustrates the upper metal wiring by exposing the second insulating film 14 by performing a CMP process.
그런데, 상기와 같은 공정으로 금속 배선을 형성할 경우 다음과 같은 문제가발생하게 된다.However, when the metal wiring is formed by the above process, the following problem occurs.
첫째, 반도체 소자가 고집적화됨에 따라 비아홀을 형성하기 위한 리소그라피 공정시 하부 배선과 상부 배선의 정렬 문제가 필연적으로 발생한다. 따라서, 비아홀과 배선간의 접촉 면적이 감소하며, 접촉 저항을 증가시켜 소자의 동작 속도를 감소시킬 수 있다.First, as semiconductor devices are highly integrated, a problem of alignment between the lower wiring and the upper wiring inevitably occurs during the lithography process for forming the via holes. Therefore, the contact area between the via hole and the wiring is reduced, and the contact resistance can be increased to reduce the operating speed of the device.
둘째, 제 2 절연막을 식각하여 비아홀을 형성하기 때문에 제 2 절연막이 비아홀내에 조금이라도 잔류하게 되면 하부 배선과 전기적으로 연결되지 않는다. 이를 방지하기 위하여 과도하게 제 2 절연막을 식각하게 됨으로써 하부 배선이 손상된다.Second, since the second insulating film is etched to form the via hole, if the second insulating film remains at least in the via hole, it is not electrically connected to the lower wiring. To prevent this, the lower wiring is damaged by excessively etching the second insulating film.
세째, 확산 장벽층 및 시드층을 형성하기 때문에 초미세 구조의 배선 구조에서는 제 2 절연막 패턴내에 구리층을 매립할 공간이 극소화되어 매립이 불가능해지거나 결함이 발생되어 소자의 신뢰성을 저하시킨다.Third, because the diffusion barrier layer and the seed layer are formed, in the ultra-fine wiring structure, the space for embedding the copper layer in the second insulating film pattern is minimized, so that embedding is impossible or defects are generated, thereby degrading the reliability of the device.
상기와 같은 문제점들은 구리 배선을 형성하기 위하여 사용하는 다마신 공정의 경우 더욱 심각하고, 이를 극복하기 위해 많은 기술이 개발되었지만 여전히 많은 문제를 가지고 있다.The above problems are more serious in the damascene process used to form copper wiring, and many techniques have been developed to overcome them, but still have many problems.
따라서, 본 발명은 고집적 반도체 소자의 상부 금속 배선 형성 공정에서 공정 마진의 부족으로 인한 하부 금속 배선과의 접촉 불량으로 인한 문제점을 해결할수 있는 반도체 소자의 금속 배선 형성 방법을 제공하는데 그 목적이 있다.Accordingly, an object of the present invention is to provide a method for forming a metal wiring of a semiconductor device, which can solve a problem caused by a poor contact with a lower metal wiring due to a lack of process margin in an upper metal wiring forming process of a highly integrated semiconductor device.
상술한 목적을 달성하기 위한 본 발명은 하부 금속 배선을 포함한 소정의 구조가 형성된 반도체 기판 상부에 시드층을 형성하는 단계와, 전체 구조 상부에 감광막을 형성한 후 상기 하부 금속 배선이 형성된 부분의 상기 시드층이 노출되도록 패터닝하는 단계와, 상기 시드층이 노출된 부분의 상기 감광막 패턴이 매립되도록 전기도금법으로 금속층을 형성하는 단계와, 상기 감광막 패턴을 제거하여 금속층만을 잔류시킨 후 전체 구조 상부에 확산 장벽층을 형성하는 단계와, 상기 확산 장벽층 및 상기 시드층을 전면 식각하여 상기 금속층의 하부에 시드층이 잔류되고, 그 측벽에 확산 장벽층 스페이서가 형성된 상부 금속 배선을 형성하는 단계와, 전체 구조 상부에 절연막을 형성한 후 상기 상부 금속 배선의 상부가 노출되도록 평탄화하는 단계를 포함하여 이루어진 것을 특징으로 한다.According to an aspect of the present invention, there is provided a method of forming a seed layer on an upper portion of a semiconductor substrate on which a predetermined structure including a lower metal wiring is formed, and after forming a photosensitive film on the entire structure, the portion of the lower metal wiring is formed. Patterning the seed layer to be exposed; forming a metal layer by electroplating so that the photoresist pattern of the exposed part of the seed layer is embedded; and removing only the metal layer by removing the photoresist pattern to diffuse the upper part of the entire structure. Forming a barrier layer, and totally etching the diffusion barrier layer and the seed layer to form an upper metal interconnection having a seed layer remaining under the metal layer and a diffusion barrier layer spacer formed on a sidewall thereof; Forming an insulating film on the structure, and then planarizing the upper portion of the upper metal wiring to be exposed. Characterized in that made.
도 1(a) 내지 도 1(c)는 종래의 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.1 (a) to 1 (c) are cross-sectional views of devices sequentially shown in order to explain a metal wiring formation method of a conventional semiconductor device.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
<도면의 주요 부분에 대한 부호의 설명><Explanation of symbols for the main parts of the drawings>
11 및 21 : 반도체 기판 12 및 22 : 제 1 절연막11 and 21: semiconductor substrate 12 and 22: first insulating film
13 및 23 : 하부 금속 배선 14 및 28 : 제 2 절연막13 and 23: lower metal wiring 14 and 28: second insulating film
15 및 27 : 확산 장벽층 16 및 24 : 시드층15 and 27: diffusion barrier layer 16 and 24: seed layer
17 및 26 : 구리층 25 : 감광막17 and 26: copper layer 25: photosensitive film
첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.The present invention will be described in detail with reference to the accompanying drawings.
도 2(a) 내지 도 2(c)는 본 발명에 따른 반도체 소자의 금속 배선 형성 방법을 설명하기 위해 순서적으로 도시한 소자의 단면도이다.2 (a) to 2 (c) are cross-sectional views of devices sequentially shown to explain a method for forming metal wirings of a semiconductor device according to the present invention.
도 2(a)를 참조하면, 소정의 구조가 형성된 반도체 기판(21) 상부에 제 1 절연막(22)을 형성한다. 제 1 절연막(22)의 소정 영역을 식각하고, 식각된 영역에 금속층을 형성한 후 패터닝하여 하부 금속 배선(23)을 형성한다. 전체 구조 상부에 시드층(24)을 형성한다. 시드층(24)은 알루미늄, 티타늄, 텅스텐 및 구리중 어느하나를 PVD 방법, CVD 방법 또는 ALD(Atomic Layer Deposition) 방법을 사용하여 5∼1000Å의 두께로 형성한다. 전체 구조 상부에 원하는 배선 높이만큼 감광막(25)을 형성한 후 상부 전극이 형성되는 부분을 패터닝하여 하부 배선(23) 부분을 노출시킨다. 패터닝된 감광막(25) 부분에 전기도금법으로 구리층(26)을 형성한다. 구리층(26) 대신에 알루미늄층을 형성할 수 있다. 구리층(26)을 형성하기 위한 전기도금법으로는 순방향 DC 도금, 펄스-역펄스 도금등을 이용한 다단계 도금 방법을 사용한다.Referring to FIG. 2A, a first insulating layer 22 is formed on the semiconductor substrate 21 on which a predetermined structure is formed. A predetermined region of the first insulating layer 22 is etched, a metal layer is formed on the etched region, and then patterned to form a lower metal wiring 23. The seed layer 24 is formed on the entire structure. The seed layer 24 is formed of any one of aluminum, titanium, tungsten, and copper to a thickness of 5 to 1000 mm by using a PVD method, a CVD method, or an ALD (Atomic Layer Deposition) method. After the photoresist film 25 is formed on the entire structure by a desired wiring height, the portion where the upper electrode is formed is patterned to expose the lower wiring 23 portion. The copper layer 26 is formed on the patterned photoresist 25 by electroplating. An aluminum layer may be formed instead of the copper layer 26. As the electroplating method for forming the copper layer 26, a multi-step plating method using forward DC plating, pulse-reverse pulse plating, or the like is used.
도 2(b)를 참조하면, 감광막(25)을 제거하여 구리층(26)만을 잔류시킨 후 전체 구조 상부에 확산 장벽층(27)을 형성한다. 전면 식각 공정을 실시하여 확산 장벽층(27) 및 시드층(24)을 식각한다. 이에 의해 구리층(26) 측벽에 스페이서 형태로 확산 장벽층(27)이 형성되고, 그 하부에 시드층(24)이 형성된 상부 배선이 형성된다. 확산 장벽층(27)은 5∼1000Å의 두께로 형성하며, 이온화된(ionized) PVD 방법, CVD 방법 또는 MOCVD 방법에 의해 형성된 TiN막, 이온화된 PVD 방법에 의해 형성된 Ta막 또는 TaN막, CVD 방법에 의해 형성된 Ta막 또는 TaN막, CVD 방법에 의해 형성된 WN막, PVD 방법 또는 CVD 방법에 의해 형성된 TiAlN막, TiSiN막 또는 TaSiN막중 어느 하나를 적용할 수 있다.Referring to FIG. 2B, the photoresist 25 is removed to leave only the copper layer 26, and then the diffusion barrier layer 27 is formed on the entire structure. The entire surface etching process is performed to etch the diffusion barrier layer 27 and the seed layer 24. As a result, a diffusion barrier layer 27 is formed on the sidewalls of the copper layer 26 in the form of a spacer, and an upper wiring on which the seed layer 24 is formed is formed. The diffusion barrier layer 27 is formed to a thickness of 5 to 1000 GPa, and a TiN film formed by an ionized PVD method, a CVD method or a MOCVD method, a Ta film or a TaN film formed by an ionized PVD method, or a CVD method. Can be applied to any one of a Ta film or a TaN film, a WN film formed by a CVD method, a TiAlN film, a TiSiN film, or a TaSiN film formed by a PVD method or a CVD method.
도 2(c)를 참조하면, 상부 배선 사이가 매립되도록 전체 구조 상부에 제 2 절연막(28)을 형성하여 금속 배선의 형성 공정을 완료한다. 제 2 절연막(28)은 산화막 또는 낮은 유전 상수를 갖는 막으로 형성한다.Referring to FIG. 2C, the second insulating film 28 is formed on the entire structure to fill the gaps between the upper wires, thereby completing the process of forming the metal wires. The second insulating film 28 is formed of an oxide film or a film having a low dielectric constant.
상술한 바와 같이 본 발명에 의하면 전기도금법으로 증착되는 구리층은 시드층의 노출 부분이 감광막의 패터닝된 부분에 한정되기 때문에 전기도금시 시드층이 노출된 부분에만 증착된다. 따라서, 자기 정렬된 전기도금법으로 구리층이 증착된다. 또한, 초미세 구조에서 확산 장벽층이나 시드층 도포로 인한 패턴 내부의 매립 공간이 줄어들게 되는 문제가 없어 배선 매립을 결함없이 용이하게 할 수 있다.As described above, according to the present invention, the copper layer deposited by the electroplating method is deposited only on the exposed portion of the seed layer during electroplating because the exposed portion of the seed layer is limited to the patterned portion of the photosensitive film. Thus, a copper layer is deposited by self-aligned electroplating. In addition, in the ultra-fine structure, there is no problem that the buried space inside the pattern is reduced due to the diffusion barrier layer or seed layer application, thereby making it possible to easily fill the wiring without defects.
그리고, 본 발명에서 제시한 방법을 0.10㎛ 이하의 디자인 룰을 갖는 초미세 반도체 소자의 제조 공정에 적용할 경우 기술적인 장점이 많아 결함없는 배선 형성에 유리하다.In addition, when the method proposed in the present invention is applied to a manufacturing process of an ultrafine semiconductor device having a design rule of 0.10 μm or less, there are many technical advantages, which is advantageous in forming a defect-free wiring.
한편, 현재 다마신을 이용한 초미세 구조에 적용되는 확산 장벽층은 CVD 방법 또는 ALD 방법을 이용하는 등 그 방법이 매우 어려우나 본 발명을 적용하면 CVD 방법 또는 ALD 방법을 적용하지 않고 PVD 방법을 적용할 수 있어 공정의 난이성이 대폭 개선될 수 있으며, 별도의 CVD 방법을 이용한 시드층 형성 공정이 필요없는 장점이 있다.On the other hand, the diffusion barrier layer currently applied to ultrafine structures using damascene is very difficult, such as using the CVD method or ALD method, but if the present invention is applied, the PVD method can be applied without applying the CVD method or the ALD method. Therefore, the difficulty of the process can be greatly improved, and there is an advantage of not requiring a seed layer forming process using a separate CVD method.
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| KR10-2000-0033982A KR100387255B1 (en) | 2000-06-20 | 2000-06-20 | Method of forming a metal wiring in a semiconductor device |
| US09/883,964 US6627523B2 (en) | 2000-06-20 | 2001-06-20 | Method of forming a metal wiring in a semiconductor device |
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| KR10-2000-0033982A KR100387255B1 (en) | 2000-06-20 | 2000-06-20 | Method of forming a metal wiring in a semiconductor device |
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