JP2007103654A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To permit obtaining of a high carrier mobility in a surface layer by applying a stress on a channel region. <P>SOLUTION: The forming region of source/drain region 4 on a silicon substrate 2 is removed by etching to form an SiGe layer selectively. Compression strain is generated in the channel region 3 by receiving the stress due to SiGe. A dummy gate 11, previously formed on the channel region 3, is removed to release the stress and generate a big strain in the surface layer of the channel region 3. Thereafter, a silicon nitride film 7, a gate insulating film 5, and a gate electrode 6 are formed. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device including a MOS transistor configured to give stress strain to a channel region and a method for manufacturing the same.

  Some semiconductor substrates have characteristics in which carrier mobility changes when subjected to stress strain. By utilizing such characteristics, it is considered that MOS transistors are configured in such a manner that stress is applied to the channel portion to improve carrier mobility and thereby increase the response speed. .

As such a thing, there exists a thing as shown in a nonpatent literature 1, for example. In this structure, after a gate insulating film and a gate electrode are formed on a semiconductor substrate, a layer that applies stress to the channel is formed on the channel end and the gate electrode, and the channel is stressed to be distorted. .
Gannavaram, S Pesovic, N Ozturk, C, "Low Temperature (800 ° C) Recessed Junction Selective Silicon-Germanium Source / Drain Technology for sub-70nm CMOS", Electron Devices Meeting, 2000. IEDM Technical Digest. International, 2000, p. 437-440

  By adopting the above-described non-patent document 1, stress can be applied to the channel region portion of the semiconductor substrate from the source / drain regions on both sides, thereby applying stress strain in the lateral direction to the channel region. Carrier mobility can be increased.

  However, the non-patent document 1 has a structure in which distortion is not easily generated even when stress is applied because the gate electrode is formed in the surface layer portion of the channel region, that is, the region immediately below the gate electrode. ing. As the device characteristics, the improvement of the carrier mobility at the surface layer portion of the channel region is the most effective characteristic improvement. Therefore, the source / drain is subjected to a larger stress to generate a desired strain. When the thickness of the region is increased, a part where the strain becomes too large is generated, which causes a problem such as a crack, or a problem that makes it difficult to manufacture a device with a minute structure. .

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor device having a configuration capable of increasing carrier mobility even in a surface layer portion of a channel region.

  The semiconductor device of the present invention includes a semiconductor substrate, a channel region formed in the semiconductor substrate, and a source / drain region formed on the semiconductor substrate with the channel region interposed therebetween, and the lattice constant of the semiconductor substrate is A source / drain region formed of a different semiconductor material; and a gate insulating film and a gate electrode formed on an upper surface of the channel region, wherein the channel region has a strain generated by a stress received from the source / drain region. The semiconductor substrate is characterized in that it is distributed so as to be large on the surface side of the semiconductor substrate and to be smaller in the depth direction from the surface.

  According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising: removing a source / drain region portion formed on both sides of a channel formation region of a semiconductor substrate; and removing the source / drain region portion of the semiconductor substrate from the portion. It is characterized in that it comprises a step of embedding a semiconductor material having a lattice constant different from that of the semiconductor substrate and a step of forming a gate insulating film and a gate electrode on the surface of the channel formation region of the semiconductor substrate.

  Since the strain applied to the channel region by the stress is distributed so as to be large on the surface side and small in the depth direction from the surface, the carrier mobility is large in the surface layer when functioning as a transistor. As a result, the operation speed can be improved and the structure can be configured not to be adversely affected by stress.

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
FIG. 1 shows a schematic cross section of a p-channel MOS transistor 1. In FIG. 1, a silicon substrate 2 as a semiconductor substrate is provided with a channel region 3, and on both sides of the channel region 3. A source / drain region 4 formed so as to sandwich this is provided.

  The source / drain regions 4 are formed by selective epitaxial growth of SiGe (silicon germanium) instead of silicon, and the lattice constant of SiGe has a value larger than that of silicon. Due to the difference in lattice constant, the channel region 3 which is a part of the silicon substrate 2 is formed in a distorted state by receiving stress from the source / drain region 4.

  A gate insulating film 5 made of a silicon oxide film is formed on the channel region 3 with a predetermined thickness, and a gate electrode 6 made of polycrystalline silicon is formed thereon. The shape of the gate electrode 6 is such that the overall width dimension is wider than the width dimension of the channel region 3 and both sides protrude to the source / drain region 4 side. Further, the gate electrode 6 is formed so that the upper portion is smaller than the width dimension on the side in contact with the gate insulating film 5 due to the manufacturing process described later. A silicon nitride film 7 is formed with a predetermined film thickness on the side wall of the gate electrode 6 to form an electrically insulated state between the gate electrode 6 and the source / drain region 4.

  As described later, the gate insulating film 5, the gate electrode 6, and the silicon nitride film 7 are formed in such a state that the upper portion of the channel region 3 is once exposed after the SiGe crystal serving as the source / drain region 4 is formed. It was formed later. Therefore, the channel region 3 is distorted by receiving the compressive stress from the source / drain region 4 made of SiGe crystal, but the distortion is the largest in the surface layer portion.

  As a result, the mobility of carriers in the silicon substrate 2, that is, the channel region 3 made of silicon single crystal is increased as compared with the case where no stress strain is applied, and the operation speed is improved. In this case, the stress applied to the channel region 3 has a distribution as shown in FIG. 5, for example, according to measurement by the inventors. In FIG. 5, the vertical axis indicates the depth dimension (nm) from the surface of the channel region 3, and the horizontal axis indicates the magnitude of stress applied to the channel region 3 in units of pressure (MPa).

  As can be seen from FIG. 5, the stress is highest at 1.3 GPa in the surface layer portion. Further, the middle part of the channel region 3 receives stress of about the same level as 1.1 GPa, and as the depth increases, stress relaxation occurs by the silicon substrate 2 on the bottom side, and the magnitude of the stress decreases. Go.

  This result shows that the most remarkable effect is obtained in the surface layer portion of the channel region, from another measurement by the inventors regarding the structure of the conventional equivalent. That is, in the configuration in which the gate electrode is formed first, even if the portion corresponding to the source / drain region is formed later by SiGe, the gate electrode formed earlier is formed in the surface layer portion of the channel region. The presence of stress relieves the stress from the source / drain region, and the stress distribution state is smaller than the internal stress.

  Therefore, by forming the MOS transistor 1 having the above-described configuration, the distribution of stress applied to the channel region 3 in the depth direction is suppressed, and the channel functions as a channel in the surface layer where the amount of carriers (here, holes) flows most. It is possible to increase the amount of strain at the portion as compared with the conventional case. Therefore, even with the same Ge concentration / structure, the mobility of carriers (holes) can be improved.

Next, the manufacturing process of the said structure is demonstrated with reference to FIGS.
First, as shown in FIG. 2A, a silicon oxide film 8 is formed with a film thickness of about 5 to 50 nm on the upper surface of a silicon substrate 2 as a semiconductor substrate, and a polycrystalline silicon film 9 and a silicon nitride film are further formed on the upper surface. 10 are stacked.

  Next, a resist is applied by photolithography and patterning is performed. Etching is performed so as to leave the silicon oxide film 8, the polycrystalline silicon film 9, and the silicon nitride film 10 corresponding to the gate electrode formation portion, and the dummy gate. 11 is formed. As shown in FIG. 2B, a silicon nitride film 12 is formed on the side surface of the dummy gate 11 as a protective film. Here, the silicon nitride film 12 is formed on the entire surface and then etched by anisotropic etching so that the silicon nitride film 12 is left on the side surface of the dummy gate 11. In place of the silicon nitride film 12, a silicon oxide film can be formed.

  Subsequently, as shown in FIG. 2C, the portion of the silicon substrate 2 where the source / drain regions 4 are to be formed is removed by etching. In this etching process, a method such as an etching process using ions, an etching process using a solution, or an etching process using hydrochloric acid gas can be employed. At this time, in the silicon etching, the dummy gate 11 functions as a mask for leaving the channel region 3.

  Next, as shown in FIG. 3D, SiGe crystals are selectively formed on the silicon substrate 2 where the source / drain regions 4 are to be formed. In this case, the Ge concentration is 10 to 30%, and the lifted film thickness from the surface portion of the silicon substrate 2 is 0 to 50 nm. At this time, the stress applied to the channel region 3 is distributed as shown in FIG. As can be seen from the figure, there is a stress distribution in the depth direction, which is about 400 MPa in the portion immediately below the silicon oxide film 8, but has a maximum value of 1.1 GPa at a depth of about 20 nm from the silicon oxide film 8. .

  Thereafter, a TEOS film 13 is formed on the entire surface with a film thickness of about 100 nm, and subsequently polished by CMP (Chemical Mechanical Polishing) until the silicon nitride film 10 is exposed, as shown in FIG. To form. Subsequently, the silicon nitride film 10 on the gate electrode 9 is removed with a phosphoric acid solution, and the polycrystalline silicon film 9 constituting the dummy gate 11 is further removed.

  Subsequently, the silicon nitride film 12 remaining on the side wall and the silicon oxide film 8 remaining on the bottom surface are removed to form a recess 14 for forming the gate electrode 6 to obtain a state as shown in FIG. . In this case, the recess 14 has a shape in which the width of the opening is narrow and the width becomes wider toward the bottom surface. In this state, the stress applied to the channel region 3 is distributed as shown in FIG. That is, there is a difference in stress in the depth direction, 1.3 GPa on the surface of the silicon substrate 2, and the stress monotonously decreases as the depth increases.

  Next, a silicon nitride film 7 is formed on the entire surface, and this is etched by RIE (Reactive Ion Etching). As shown in FIG. 4G, the SiGe layer forming the source / drain regions 4 is formed. The side wall is covered.

  Thereafter, the oxide film on the surface of the silicon substrate 2 is removed with a solution containing dilute HF (hydrofluoric acid), and an oxidation process is performed again to form a gate insulating film 5 on the surface of the channel region 3 of the silicon substrate 2. Subsequently, a polycrystalline silicon film 6 is formed, and then the polycrystalline silicon film 6 other than the gate forming portion is removed by CMP processing to obtain a state as shown in FIG. Next, the TEOS film 14 is removed by etching using a solution to obtain a configuration as shown in FIG.

Since the manufacturing process as described above is employed, the following effects can be obtained.
That is, the source / drain regions 4 on both sides of the channel region 3 are configured to apply stress to the channel region 3 by selectively forming SiGe, and the dummy gate 11 formed above the channel region 3 is temporarily removed. By releasing the stress, the surface layer of the channel region 3 can be distorted most.

  In addition, since it is formed as described above, even when it is configured to give the largest strain to the surface layer portion of the channel region 3, it is only necessary to form a SiGe layer that gives a stress equivalent to that of the conventional method. As a result, it is possible to manufacture the device without causing trouble by applying unnecessary stress to other portions.

(Other embodiments)
The present invention is not limited to the above embodiment, and can be modified or expanded as follows.
In the above embodiment, the case where the mobility of holes as carriers is increased as a configuration in which compressive stress is applied to the channel region 3, but conversely, the source / drain region 4 is made to have tensile stress such as SiC (silicon carbide). It is also possible to configure by selecting a material that gives In this case, the largest strain can be applied to the surface layer portion of the channel region 3, whereby the mobility of electrons as carriers can be improved and applied to an n-channel MOSFET. Can do.

Although the side walls of the dummy gate 11 are covered with the silicon nitride film 12, other insulating films may be used, or a process that does not need to be provided may be employed.
Not only the silicon substrate 2 but also any material that can maintain the relationship of generating stress in the channel region 3 can be employed.

Schematic sectional view showing an embodiment of the present invention Schematic cross-sectional view shown at each stage of the manufacturing process (Part 1) Schematic cross-sectional view shown at each stage of the manufacturing process (Part 2) Schematic cross-sectional view shown at each stage of the manufacturing process (Part 3) Diagram showing stress distribution in the depth direction of the channel region Equivalent to FIG. 5 with the dummy gate remaining

Explanation of symbols

  In the drawings, 1 is a MOS transistor (semiconductor device), 2 is a silicon substrate (semiconductor substrate), 3 is a channel region, 4 is a source / drain region, 5 is a gate insulating film, 6 is a gate electrode, 7 is a silicon nitride film, Reference numeral 11 denotes a dummy gate.

Claims (5)

A semiconductor substrate;
A channel region formed in the semiconductor substrate;
A source / drain region formed on the semiconductor substrate with the channel region sandwiched between the source / drain region and a semiconductor material having a lattice constant different from that of the semiconductor substrate;
A gate insulating film and a gate electrode formed on the upper surface of the channel region;
The semiconductor is characterized in that the channel region has a distribution in which a strain generated by a stress received from the source / drain region is distributed on the surface side of the semiconductor substrate so as to decrease in the depth direction from the surface. apparatus. The semiconductor device according to claim 1,
The semiconductor substrate is a silicon (Si) substrate, and the source / drain regions are formed of silicon germanium (SiGe),
The semiconductor device, wherein the channel region is configured to receive a compressive stress from the source / drain region. The semiconductor device according to claim 1,
The semiconductor substrate is a silicon (Si) substrate, and the source / drain regions are formed of silicon carbide (SiC);
The semiconductor device, wherein the channel region is configured to receive a tensile stress from the source / drain region. Removing source / drain region portions formed on both sides of a channel formation region of a semiconductor substrate;
Embedding and forming a semiconductor material having a lattice constant different from that of the semiconductor substrate in a portion where the source / drain region portion of the semiconductor substrate is removed;
And a step of forming a gate insulating film and a gate electrode on a surface of a channel formation region of the semiconductor substrate. In the manufacturing method of the semiconductor device according to claim 4,
A method of manufacturing a semiconductor device, wherein selective epitaxial growth is performed in the step of embedding a semiconductor material in the source / drain regions.

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