JP2006179782A - 半導体基板の製造方法 - Google Patents
半導体基板の製造方法 Download PDFInfo
- Publication number
- JP2006179782A JP2006179782A JP2004373282A JP2004373282A JP2006179782A JP 2006179782 A JP2006179782 A JP 2006179782A JP 2004373282 A JP2004373282 A JP 2004373282A JP 2004373282 A JP2004373282 A JP 2004373282A JP 2006179782 A JP2006179782 A JP 2006179782A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- solder
- hole
- copper foil
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0302—Properties and characteristics in general
- H05K2201/0305—Solder used for other purposes than connections between PCB or components, e.g. for filling vias or for programmable patterns
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09572—Solder filled plated through-hole in the final product
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/02—Details related to mechanical or acoustic processing, e.g. drilling, punching, cutting, using ultrasound
- H05K2203/0278—Flat pressure, e.g. for connecting terminals with anisotropic conductive adhesive
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/08—Treatments involving gases
- H05K2203/082—Suction, e.g. for holding solder balls or components
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Ceramic Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
【解決手段】 基板(10)に貫通孔(14)を形成する工程と、該基板の一方の面にはんだ(42)を配置する工程と、該はんだをプレス(40)により前記基板の側に押圧すると共に、該はんだを加熱溶融させて、前記基板の貫通孔(14)に埋め込む工程と、からなることを特徴とすることを特徴とする。
【選択図】 図3
Description
14 貫通孔
14a はんだ濡れ性を向上する膜
40 プレス
42 はんだ
42a 溶融はんだ
Claims (5)
- 基板に貫通孔を形成する工程と、
該基板の一方の面にはんだを配置する工程と、
該はんだをプレスにより前記基板の側に押圧すると共に、該はんだを加熱溶融させて、前記基板の貫通孔に埋め込む工程と、
からなることを特徴とする半導体基板の製造方法。 - 基板の貫通孔には、孔壁とはんだとの濡れ性を向上させるために、予め濡れ性向上膜を塗布しておくことを特徴とする請求項1に記載の半導体基板の製造方法。
- 濡れ性向上膜として、粘度の比較的低いフラックス膜を使用することを特徴とする請求項2に記載の半導体基板の製造方法。
- はんだをプレスにより基板の側へ押圧する際、該基板の反対側から吸引することを特徴とする請求項2に記載の半導体基板の製造方法。
- はんだをプレスにより基板の側に押圧する操作を、減圧環境下にて行うことを特徴とする請求項1に記載の半導体基板の製造方法。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004373282A JP4508859B2 (ja) | 2004-12-24 | 2004-12-24 | 半導体基板の製造方法 |
KR1020050120398A KR20060073452A (ko) | 2004-12-24 | 2005-12-09 | 반도체 기판의 제조 방법 |
EP05027678A EP1675445B1 (en) | 2004-12-24 | 2005-12-16 | Method for producing semiconductor substrate |
DE602005003318T DE602005003318T2 (de) | 2004-12-24 | 2005-12-16 | Verfahren zur Herstellung eines Halbleitersubstrats |
US11/317,179 US20060141676A1 (en) | 2004-12-24 | 2005-12-22 | Method for producing semiconductor substrate |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2004373282A JP4508859B2 (ja) | 2004-12-24 | 2004-12-24 | 半導体基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2006179782A true JP2006179782A (ja) | 2006-07-06 |
JP4508859B2 JP4508859B2 (ja) | 2010-07-21 |
Family
ID=36032141
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004373282A Expired - Fee Related JP4508859B2 (ja) | 2004-12-24 | 2004-12-24 | 半導体基板の製造方法 |
Country Status (5)
Country | Link |
---|---|
US (1) | US20060141676A1 (ja) |
EP (1) | EP1675445B1 (ja) |
JP (1) | JP4508859B2 (ja) |
KR (1) | KR20060073452A (ja) |
DE (1) | DE602005003318T2 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009177011A (ja) * | 2008-01-25 | 2009-08-06 | Ferrotec Ceramics Corp | 導電性部材ならびにそれを用いた部品および装置 |
JP2011108858A (ja) * | 2009-11-18 | 2011-06-02 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20110079632A1 (en) * | 2009-10-01 | 2011-04-07 | International Business Machines Corporation | Multistack solder wafer filling |
US20130267089A1 (en) * | 2012-04-04 | 2013-10-10 | Henkel Corpration | Film for filling through hole interconnects and post processing for interconnect substrates |
PL3337528T3 (pl) | 2015-08-17 | 2023-08-21 | Musc Foundation For Research Development | System i sposób odtykania odsysania |
DE102017128630A1 (de) * | 2017-12-01 | 2019-06-19 | Wen Yao Chang | Leiterplatte mit einem siliziumsubstrat und fertigungsverfahren dafür |
Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01308038A (ja) * | 1988-06-06 | 1989-12-12 | Hitachi Cable Ltd | 半田供給方法 |
JPH0575253A (ja) * | 1991-08-27 | 1993-03-26 | Hitachi Constr Mach Co Ltd | レーザ光による回路パターンの形成方法及びスルーホール内の導体形成方法 |
JPH05267849A (ja) * | 1992-03-19 | 1993-10-15 | Fujitsu Ltd | セラミックス多層回路基板の製造方法 |
JP2000294591A (ja) * | 1999-04-07 | 2000-10-20 | Mitsubishi Electric Corp | バンプ形成装置、半導体製造装置、及びバンプ形成方法 |
JP2002050867A (ja) * | 2000-08-02 | 2002-02-15 | Casio Comput Co Ltd | ビルドアップ回路基板およびその製造方法 |
JP2002158191A (ja) * | 2000-11-22 | 2002-05-31 | Fujikura Ltd | 微細空間への金属充填装置および金属充填方法 |
JP2002219793A (ja) * | 2001-01-26 | 2002-08-06 | Matsushita Electric Ind Co Ltd | スクリーン印刷装置およびスクリーン印刷方法 |
JP2003115658A (ja) * | 2001-10-05 | 2003-04-18 | Advantest Corp | 配線基板の製造方法、充填物挿入方法、配線基板、及び素子パッケージ |
JP2003229659A (ja) * | 2002-02-05 | 2003-08-15 | Murata Mfg Co Ltd | 電子部品の製造方法 |
JP2004228135A (ja) * | 2003-01-20 | 2004-08-12 | Mitsubishi Electric Corp | 微細孔への金属埋め込み方法 |
JP2005183481A (ja) * | 2003-12-16 | 2005-07-07 | Matsushita Electric Ind Co Ltd | 回路基板とその製造方法 |
JP2005217055A (ja) * | 2004-01-28 | 2005-08-11 | Kyocera Corp | 熱電モジュールの製造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3318993A (en) * | 1963-07-11 | 1967-05-09 | Rca Corp | Interconnection of multi-layer circuits and method |
JPS55162451A (en) * | 1979-05-31 | 1980-12-17 | Sekisui Chem Co Ltd | Interlayer composition for safety laminated glass |
JP2788755B2 (ja) * | 1989-06-05 | 1998-08-20 | 古河電気工業株式会社 | 電子部品実装用パッドの製造方法 |
US6098283A (en) * | 1996-12-19 | 2000-08-08 | Intel Corporation | Method for filling vias in organic, multi-layer packages |
JP2000332369A (ja) * | 1999-05-25 | 2000-11-30 | Mitsui Mining & Smelting Co Ltd | プリント回路板及びその製造方法 |
US6426241B1 (en) * | 1999-11-12 | 2002-07-30 | International Business Machines Corporation | Method for forming three-dimensional circuitization and circuits formed |
US6380060B1 (en) * | 2000-03-08 | 2002-04-30 | Tessera, Inc. | Off-center solder ball attach and methods therefor |
JP3836375B2 (ja) * | 2002-01-11 | 2006-10-25 | シャープ株式会社 | 半導体装置の製造方法 |
-
2004
- 2004-12-24 JP JP2004373282A patent/JP4508859B2/ja not_active Expired - Fee Related
-
2005
- 2005-12-09 KR KR1020050120398A patent/KR20060073452A/ko not_active Application Discontinuation
- 2005-12-16 DE DE602005003318T patent/DE602005003318T2/de active Active
- 2005-12-16 EP EP05027678A patent/EP1675445B1/en not_active Ceased
- 2005-12-22 US US11/317,179 patent/US20060141676A1/en not_active Abandoned
Patent Citations (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH01308038A (ja) * | 1988-06-06 | 1989-12-12 | Hitachi Cable Ltd | 半田供給方法 |
JPH0575253A (ja) * | 1991-08-27 | 1993-03-26 | Hitachi Constr Mach Co Ltd | レーザ光による回路パターンの形成方法及びスルーホール内の導体形成方法 |
JPH05267849A (ja) * | 1992-03-19 | 1993-10-15 | Fujitsu Ltd | セラミックス多層回路基板の製造方法 |
JP2000294591A (ja) * | 1999-04-07 | 2000-10-20 | Mitsubishi Electric Corp | バンプ形成装置、半導体製造装置、及びバンプ形成方法 |
JP2002050867A (ja) * | 2000-08-02 | 2002-02-15 | Casio Comput Co Ltd | ビルドアップ回路基板およびその製造方法 |
JP2002158191A (ja) * | 2000-11-22 | 2002-05-31 | Fujikura Ltd | 微細空間への金属充填装置および金属充填方法 |
JP2002219793A (ja) * | 2001-01-26 | 2002-08-06 | Matsushita Electric Ind Co Ltd | スクリーン印刷装置およびスクリーン印刷方法 |
JP2003115658A (ja) * | 2001-10-05 | 2003-04-18 | Advantest Corp | 配線基板の製造方法、充填物挿入方法、配線基板、及び素子パッケージ |
JP2003229659A (ja) * | 2002-02-05 | 2003-08-15 | Murata Mfg Co Ltd | 電子部品の製造方法 |
JP2004228135A (ja) * | 2003-01-20 | 2004-08-12 | Mitsubishi Electric Corp | 微細孔への金属埋め込み方法 |
JP2005183481A (ja) * | 2003-12-16 | 2005-07-07 | Matsushita Electric Ind Co Ltd | 回路基板とその製造方法 |
JP2005217055A (ja) * | 2004-01-28 | 2005-08-11 | Kyocera Corp | 熱電モジュールの製造方法 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2009177011A (ja) * | 2008-01-25 | 2009-08-06 | Ferrotec Ceramics Corp | 導電性部材ならびにそれを用いた部品および装置 |
JP2011108858A (ja) * | 2009-11-18 | 2011-06-02 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
EP1675445A1 (en) | 2006-06-28 |
EP1675445B1 (en) | 2007-11-14 |
DE602005003318D1 (de) | 2007-12-27 |
KR20060073452A (ko) | 2006-06-28 |
JP4508859B2 (ja) | 2010-07-21 |
US20060141676A1 (en) | 2006-06-29 |
DE602005003318T2 (de) | 2008-09-11 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4434315B2 (ja) | 多層配線基板の製造方法 | |
JP4208631B2 (ja) | 半導体装置の製造方法 | |
JP5160895B2 (ja) | 電子モジュールの製造方法 | |
US8152953B2 (en) | Method of making printed wiring board and method of making printed circuit board unit | |
JP2008277750A (ja) | 電子素子内蔵印刷回路基板の製造方法 | |
JPWO2008143099A1 (ja) | 積層配線基板及びその製造方法 | |
JP5163806B2 (ja) | 部品内蔵モジュールの製造方法及び部品内蔵モジュール | |
TW201531189A (zh) | 導電膏的充塡方法及多層印刷配線板的製造方法 | |
US20030196833A1 (en) | Multilayer printed circuit board and method of manufacturing multilayer printed circuit board | |
EP1909322A1 (en) | Stacked electronic component, electronic device and method for manufacturing stacked electronic component | |
JP2003017859A (ja) | プリント基板の製造方法およびその製造方法によって形成されるプリント基板 | |
TW200425241A (en) | Process for producing electronic component and electronic component | |
US9596765B2 (en) | Manufacturing method for component incorporated substrate and component incorporated substrate manufactured using the method | |
JP2008263188A (ja) | 回路基板の製造方法 | |
JP4508859B2 (ja) | 半導体基板の製造方法 | |
WO2001060136A1 (fr) | Carte imprimee, carte imprimee multicouche et procede de fabrication | |
JP2007305636A (ja) | 部品実装モジュール | |
JP2010021369A (ja) | 部品内蔵配線基板及びその製造方法 | |
JP3933822B2 (ja) | プリント配線基板及びその製造方法 | |
JP2006049536A (ja) | 多層回路基板 | |
JP4720767B2 (ja) | フレキシブル基板およびその製造方法 | |
JP2003332705A (ja) | 配線基板およびその製造方法 | |
JP4127377B2 (ja) | 配線基板およびその製造方法 | |
JP2005129727A (ja) | 多層配線基板及びその製造方法 | |
CN103796418A (zh) | 一种电路板及电路板的制作方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20070829 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20091109 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20100105 |
|
A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20100224 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20100330 |
|
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20100427 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 4508859 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20130514 Year of fee payment: 3 |
|
FPAY | Renewal fee payment (event date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20140514 Year of fee payment: 4 |
|
LAPS | Cancellation because of no payment of annual fees |