JP2006162844A - Display apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display apparatus capable of displaying an image with a stable high quality by driving a display panel without invoking wrong discharging, in which each pixel cell is composed of two discharge cells performing address discharge and sustain discharge individually. <P>SOLUTION: When driving the display panel in which each pixel cell is composed of two discharge cells performing the address discharge and the sustain discharge individually, just before an addressing period in a headmost subfield in a unit display period, by sequentially applying a first voltage, a second voltage whose polarity is different from that of the first voltage and a third voltage whose polarity is the same and whose voltage is lower than the first voltage between one row electrode in a pair of electrodes and a column electrode in the display panel, a first reset discharge, a second reset discharge and a third reset discharge are sequentially invoked between the row electrode and the column electrode in the discharge cell which invokes the address discharge. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a display device equipped with a display panel.

  In recent years, a plasma display device equipped with a surface discharge type AC plasma display panel as a large and thin color display panel has attracted attention. As such a plasma display panel (hereinafter referred to as a PDP), one pixel cell is known which is composed of two cells including a display discharge cell and an address discharge cell in which discharge spaces communicate with each other. (For example, refer to Patent Document 1). In order to drive the PDP having such a structure, first, the address discharge is performed by selectively applying a drive pulse between the column electrode and the row electrode in the address discharge cell of each pixel cell in accordance with the input video signal. An address discharge is generated in the cell. This address discharge is drawn into the display discharge cells to form a desired amount of wall charges in the display discharge cells. At this time, the pixel cell in which the wall charges are formed is set in the lighting mode, and the pixel cell in which the wall charge is not formed is set in the extinguishing mode (address period). Next, only the pixel cell set to the lighting mode is repeatedly caused to generate a sustain discharge in the display discharge cell of the pixel cell, and the light emission state associated with the discharge is maintained.

Here, in the address period, a relatively high voltage pulse is applied between the column electrode and the row electrode in order to draw the address discharge generated in the address discharge cell into the display discharge cell. However, when a high-voltage pulse is applied, depending on the wall charge distribution state in the display discharge cell immediately before the address period, a discharge may be erroneously generated in the display discharge cell of the pixel cell that should be set to the extinguishing mode. was there.
JP 2003-31130 A

  The present invention provides a display device in which a stable image quality can be obtained by driving a display panel having a structure of two discharge cells in which each pixel cell individually performs address discharge and sustain discharge without causing erroneous discharge. It is intended to provide.

  According to a first aspect of the present invention, there is provided a display device comprising: a front substrate and a rear substrate disposed opposite to each other across a discharge space; a plurality of row electrode pairs provided on an inner surface of the front substrate; A plurality of column electrodes arranged crossing the row electrode pairs, and a display cell and a light absorption layer on the front substrate side are provided at each intersection of the row electrode pairs and the column electrodes. A display panel in which a pixel cell including a selected cell is formed is displayed in a unit display period composed of a plurality of subfields each including an address period and a sustain period in accordance with pixel data for each pixel based on an input video signal. The display device is driven every time, and in the address period of each of the subfields, the pixel data is synchronized with the scan pulse while sequentially applying a scan pulse to one row electrode of each of the row electrode pairs. Addressing means for generating an address discharge between the one row electrode and the column electrode in the selected cell by sequentially applying corresponding pixel data pulses to the column electrode one display line at a time, and each subfield In the sustain period, a sustain means for generating a sustain discharge between the row electrodes in the row electrode pair in the display cell by applying a sustain pulse to each of the row electrode pairs, and a head of the unit display period Immediately before the address period in the subfield, a first voltage, a second voltage having a polarity different from the first voltage, and the first voltage between one row electrode and the column electrode of the row electrode pair, By sequentially applying a third voltage having the same polarity and lower than the first voltage, the one voltage in the selected cell is set. Having row electrodes and the first reset discharge between the row electrodes, and reset means for sequentially to rise to second reset discharge and the third reset discharge, a.

  When each pixel cell drives a display panel having a structure composed of two discharge cells that individually perform address discharge and sustain discharge, immediately before the address period in the first subfield of the unit display period, Between one row electrode and column electrode of the row electrode pair, a first voltage, a second voltage having a polarity different from the first voltage, and a third voltage having the same polarity as the first voltage and lower than the first voltage Are sequentially applied to sequentially generate a first reset discharge, a second reset discharge, and a third reset discharge between the row electrode and the column electrode in the discharge cell in which the address discharge is generated.

  FIG. 1 is a diagram showing a configuration of a plasma display device as a display device according to the present invention.

  As shown in FIG. 1, the plasma display device includes a PDP 50 as a plasma display panel, and a drive control circuit 56 that drives and controls the PDP 50 according to an input video signal.

  The PDP 50 includes an address driver 55, an even X electrode driver 510, an odd X electrode driver 520, an odd Y electrode driver 530, an even Y electrode driver 540, and a display electrode formation portion DPE.

In the display electrode forming portion DPE, strip-like column electrodes (address electrodes) D _{1 to} D _m extending in the column direction (vertical direction) of the display screen are formed. Further, in the display electrode forming portion DE, strip-like row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n respectively extending in the row direction (left and right direction) of the display screen are respectively shown in FIG. , XY are arranged alternately and in numerical order. At this time, each pair of adjacent row electrodes, ie, each of the row electrode pair (X ₁ , Y ₁ ) to the row electrode pair (X _n , Y _n ) is a first display line in the PDP 50. This corresponds to the nth display line. A pixel cell PC serving as a pixel is formed in each intersection of each display line and the column electrodes D _{1 to} D _m , that is, in a unit light emitting region surrounded by a one-dot chain line in FIG.

Incidentally, the row electrodes X ₁ to X _n odd rows of the respective electrodes _{X 1, X 3, X 5} , ····, X n-3, and X _n-1 each of the display electrode forming portion DPE _Are commonly connected to a connection terminal T _XO provided at the right end of each. On the other hand, each of the even-numbered row electrodes X ₂ , X ₄ , X ₆ ..., X _n-2 , and X _n is common to the connection terminal T _XE provided at the left end of the display electrode formation portion DPE. It is connected. Further, the row electrodes Y ₁ to Y _n odd rows of the respective electrodes _{Y 1, Y 3, Y 5} , ····, Y n-3 and Y _n-1 each of the display electrodes forming part of the DPE Connection terminals T _Y1 , T _Y3 , T _Y5 ,..., T _{Y (n−3)} and T _{Y (n−1)} provided at the left end are individually connected. On the other hand, each of the even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n−2 , and Y _n is connected to the connection terminals T _Y2 , T _Y4,. ..., T _{Y (n-2)} and T _{Y (n)} are individually connected.

  2 to 5 are diagrams showing a part of the internal structure of the display electrode forming portion DPE.

  FIG. 2 is a plan view of the display electrode formation portion DPE viewed from the display surface side of the PDP 50. FIG. 3 is a cross-sectional view taken along line V1-V1 shown in FIG. 4 is a cross-sectional view taken along line V2-V2 shown in FIG. FIG. 5 is a cross-sectional view seen from the line W1-W1 shown in FIG.

  As shown in FIG. 2, the row electrode Y includes a strip-shaped bus electrode Yb (a main body of the row electrode Y) extending in the row direction (left-right direction) of the display screen, and a plurality of transparent electrodes connected to the bus electrode Yb. Ya. The bus electrode Yb is made of, for example, a black metal film. The transparent electrode Ya is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Yb. The transparent electrode Ya extends in a direction perpendicular to the bus electrode Yb, and has one end and the other end that are wide as shown in FIG. That is, the transparent electrode Ya can be regarded as a protruding electrode protruding from the main body of the row electrode Y. The row electrode X is composed of a strip-shaped bus electrode Xb (a main body portion of the row electrode X) extending in the row direction (left-right direction) of the display screen and a plurality of transparent electrodes Xa connected to the bus electrode Xb. The The bus electrode Xb is made of, for example, a black metal film. The transparent electrode Xa is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Xb. The transparent electrode Xa extends in a direction orthogonal to the bus electrode Xb, and one end thereof has a wide shape as shown in FIG. That is, the transparent electrode Xa can be regarded as a protruding electrode protruding from the main body of the row electrode X. As shown in FIG. 2, the wide portions of the transparent electrodes Xa and Ya are arranged to face each other with a discharge gap g having a predetermined width. That is, the transparent electrodes Xa and Ya as protruding electrodes protruding from the main body portions of the paired row electrodes X and Y are arranged to face each other via the discharge gap g.

  The row electrode Y composed of the transparent electrode Ya and the bus electrode Yb and the row electrode X composed of the transparent electrode Xa and the bus electrode Xb are arranged on the inner surface of the front transparent substrate 10 that serves as the display surface of the PDP 50 as shown in FIG. Is formed. Further, a dielectric layer 11 is formed on the back surface of the front transparent substrate 10 so as to cover the row electrodes X and Y. A raised dielectric layer 12 protruding from the dielectric layer 11 toward the back side is formed at a position corresponding to each selected cell C2 (described later) on the surface of the dielectric layer 11. The raised dielectric layer 12 is composed of a band-shaped light absorption layer containing a black or dark pigment, and is formed to extend in the row direction (left-right direction) of the display surface as shown in FIG. The surface of the raised dielectric layer 12 and the surface of the dielectric layer 11 where the raised dielectric layer 12 is not formed are covered with a protective layer (not shown) made of MgO (magnesium oxide). A plurality of column electrodes D extending in a direction perpendicular to the bus electrodes Xb and Yb are arranged in parallel with a predetermined gap on the back substrate 13 arranged in parallel to the front transparent substrate 10. ing. A white column electrode protective layer (dielectric layer) 14 that covers the column electrode D is formed on the rear substrate 13. On the column electrode protective layer 14, a partition wall 15 including a first horizontal wall 15A, a second horizontal wall 15B, and a vertical wall 15C is formed. The first horizontal wall 15A is formed to extend in the row direction (left-right direction) of the display surface at a position on the column electrode protective layer 14 facing the bus electrode Yb. The second horizontal wall 15B is formed to extend in the row direction (left-right direction) of the display surface at a position on the column electrode protective layer 14 facing the bus electrode Xb. The vertical wall 15C is formed to extend in a direction orthogonal to the bus electrode Xb (Yb) at each position between the transparent electrodes Xa (Ya) arranged at equal intervals on the bus electrode Xb (Yb). ing.

In addition, as shown in FIG. 3, secondary electrons are included in the region (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B) facing the raised dielectric layer 12 on the column electrode protective layer 14. A release material layer 30 is formed. The secondary electron emission material layer 30 is a layer made of a high γ material having a low work function (for example, 4.2 eV or less) and a high so-called secondary electron emission coefficient. Examples of materials used as the secondary electron emission material layer 30 include alkaline earth metal oxides such as MgO, CaO, SrO, and BaO, alkali metal oxides such as Cs ₂ O, fluorides such as CaF ₂ and MgF _{2, and the} like. There are TiO ₂ , Y ₂ O ₃ , or materials whose secondary electron emission coefficient is increased by crystal defects or impurity doping, diamond-like thin films, carbon nanotubes, and the like. On the other hand, in regions other than the region facing the raised dielectric layer 12 on the column electrode protective layer 14 (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B), as shown in FIG. A body layer 16 is formed. There are three types of phosphor layers 16: a red phosphor layer that emits red light, a green phosphor layer that emits green light, and a blue phosphor layer that emits blue light, and the assignment is determined for each pixel cell PC. A discharge space filled with a discharge gas exists between the secondary electron emission material layer 30 and the phosphor layer 16 and the dielectric layer 11. The height of each of the first horizontal wall 15A, the second horizontal wall 15B, and the vertical wall 15C is not so high as to reach the surface of the raised dielectric layer 12 or the dielectric layer 11, as shown in FIGS. Therefore, as shown in FIG. 3, there is a gap r between the second horizontal wall 15B and the raised dielectric layer 12 through which the discharge gas can flow. Between the first lateral wall 15A and the raised dielectric layer 12, a dielectric layer 17 extending in the direction along the first lateral wall 15A is formed to prevent discharge interference. Also, between the vertical wall 15C and the raised dielectric layer 12, a dielectric layer 18 is intermittently formed in the direction along the vertical wall 15C as shown in FIG.

  Here, a region surrounded by the first horizontal wall 15A and the vertical wall 15C (a region surrounded by an alternate long and short dash line in FIG. 2) is a pixel cell PC that carries a pixel. Further, as shown in FIGS. 2 and 3, the pixel cell PC is divided into a display cell C1 and a selection cell C2 by the second horizontal wall 15B. As shown in FIGS. 2 and 3, the display cell C <b> 1 includes a pair of row electrodes X and Y that bear a display line, and a phosphor layer 16. On the other hand, the selected cell C2 includes a row electrode Y of the pair of row electrodes that bears the display line, a row electrode X of the pair of row electrodes that bears a display line adjacent to the display surface above the display line, A raised dielectric layer 12 and a secondary electron emission material layer 30 are included. In the display cell C1, as shown in FIG. 2, a wide portion formed at one end of the transparent electrode Xa of the row electrode X, and a wide portion formed at one end of the transparent electrode Ya of the row electrode Y Are arranged opposite to each other via the discharge gap g. On the other hand, in the selected cell C2, the wide portion formed at the other end of the transparent electrode Ya is included, but the transparent electrode X is not included.

  As shown in FIG. 3, the discharge spaces of the pixel cells PC adjacent to each other in the vertical direction of the display surface (the horizontal direction in FIG. 3) are blocked by the first horizontal wall 15 </ b> A and the dielectric layer 17. On the other hand, the discharge spaces of the display cell C1 and the selected cell C2 belonging to the same pixel cell PC communicate with each other through a gap r as shown in FIG. The discharge spaces of the selected cells C2 adjacent to each other in the left-right direction of the display surface are blocked by the raised dielectric layer 12 and the dielectric layer 18 as shown in FIG. The discharge spaces of the display cells C1 to be communicated with each other. As described above, each of the pixel cells PC formed in the PDP 50 includes the display cell C1 and the selection cell C2 whose discharge spaces communicate with each other.

The display electrode forming portion DPE having such a structure is fixed on the chassis (not shown) of the PDP 50. An address driver 55 is mounted near the upper end of the display electrode formation portion DPE on the chassis. An even-numbered X electrode driver 510 and an odd-numbered Y electrode driver 530 are mounted in the vicinity of the left end of the display electrode forming portion DPE on the chassis. Further, an odd-numbered X electrode driver 520 and an even-numbered Y electrode driver 540 are mounted in the vicinity of the right end of the display electrode forming portion DPE on the chassis. The output terminal A1 of the even-numbered X electrode driver 510 is electrically connected to the odd-numbered Y electrode driver 530 and the connection terminal T _XE of the display electrode formation portion DPE. The output terminals B1 to B (n / 2) of the odd-numbered Y electrode driver 530 are connected to the connection terminals T _Y1 , T _Y3 ,..., T _{Y (n−} ) of the display electrode formation part DPE through a single connection line. _{1) It} is electrically connected to each. The output terminal A1 of the odd-numbered X electrode driver 520 is electrically connected to the even-numbered Y electrode driver 540 and the connection terminal T _XO of the display electrode formation portion DPE. Each of the output terminals B1 to B (n / 2) of the even-numbered Y electrode driver 540 is connected to the connection terminals T _Y2 , T _Y4 ,..., T _{Y (n} ) of the display electrode formation portion DPE through a single connection line. ₎ Electrically connected with each other.

The even X electrode driver 510 generates reset pulses RP _X1 , RP _X2 , RP _X3 , and a sustain pulse IP _X as will be described later, and generates the odd Y electrode driver 530 and the even-numbered row electrode X of the display electrode forming portion DPE. ₂ , X ₄ ,..., X _n are applied respectively. When the reset pulse RP _X1 , RP _X2 , RP _X3 is supplied from the even X electrode driver 510, the odd-numbered Y electrode driver 530 uses these series of reset pulses as they are as the reset pulses RP _Y1 , RP _Y2 , RP _Y3. It is applied to the odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n−1 of the display electrode formation portion DPE. Further, when the sustain pulse IP _X is supplied from the even X electrode driver 510, the odd Y electrode driver 530 is used as it is as the sustain pulse IP _Y , and the odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,. • Apply to Y _n-1 respectively. Furthermore, the odd Y electrode driver 530 generates a later-described but such scanning pulse SP, which odd-numbered row electrodes Y _1, Y _3, Y _5, · · ·, sequentially applied to the Y _n-1. The odd-numbered X electrode driver 520 generates reset pulses RP _X1 , RP _X2 , RP _X3 , and a sustain pulse IP _X as will be described later, and the even-numbered Y electrode driver 540 and the odd-numbered row electrodes X of the display electrode forming portion DPE. ₁ , X ₃ , X ₅ ,..., X _n−1 , respectively. When the reset pulse RP _X1 , RP _X2 , RP _X3 is supplied from the odd X electrode driver 520, the even-numbered Y electrode driver 540 displays these series of reset pulses as they are as the reset pulses RP _Y1 , RP _Y2 , RP _Y3. Apply to the even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n of the electrode forming portion DPE. Further, an even Y electrode driver 540, odd X from the electrode driver 520 when the sustain pulse IP _X is supplied, which as sustain pulse IP _Y as it is, the display electrode forming portions even-numbered row electrodes Y ₂ of DPE, Applied to Y ₄ ,..., Y _n . Further, the even Y electrode driver 540 generates a scan pulse SP as will be described later, and sequentially applies it to the even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n of the display electrode formation portion DPE.
..., Y _n-2 and Y _n are relayed to each. The address driver 55 applies pixel data pulses as will be described later to the column electrodes D _{1 to} D _m of the display electrode formation portion DPE according to the timing signal supplied from the drive control circuit 56.

The drive control circuit 56 first converts the input video signal into, for example, 8-bit pixel data representing the luminance level for each pixel, and performs error diffusion processing and dither processing on the pixel data. For example, in the error diffusion process, first, the upper 6 bits of pixel data are used as display data, and the remaining lower 2 bits are used as error data. Then, the weighted addition of each error data of the pixel data corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the drive control circuit 56, the upper 4 bits of the dither added pixel data as multi-gradation pixel data PD _S, 15 bits formed which from the first to 15th bits in accordance with data conversion table as shown in FIG. 6 To pixel drive data GD. Accordingly, pixel data that can represent 256 gradations in 8 bits is converted into 15-bit pixel drive data GD consisting of a total of 16 patterns, as shown in FIG. Next, the drive control circuit 56, the pixel drive data GD ₁ of one screen, 1～GD _n, for each _m, separates these pixel driving data GD1, ₁ to GD _{n, m} each at the same bit digit with each other By
DB1: pixel drive data GD1, ₁ to GD _n, the first bit of the _m each
DB2: the pixel drive data GD1, ₁ ~GD _n, the second bit of the _m each
DB3: pixel drive data GD1, ₁ ~GD _n, third bit of _m each
DB4: pixel drive data GD1, ₁ ~GD _n, fourth bit of the _m each
DB 5: pixel drive data GD1, ₁ ~GD _n, the fifth bit of the _m each
DB 6: pixel drive data GD1, ₁ ~GD _n, sixth bit of the _m each
DB7: pixel drive data GD1, ₁ ~GD _n, seventh bit of _m each
DB8: pixel drive data GD1, ₁ ~GD _n, eighth bit of the _m each
DB9: pixel drive data GD1, ₁ ~GD _n, 9th bit of _m each
DB 10: pixel drive data GD1, ₁ ~GD _n, 10th bit of _m each
DB 11: pixel drive data GD1, ₁ ~GD _n, 11th bit of _m each
DB 12: pixel drive data GD1, ₁ ~GD _n, 12th bit of _m each
DB 13: pixel drive data GD1, ₁ ~GD _n, the 13th bit of _m each
DB 14: pixel drive data GD1, ₁ ~GD _n, 14th bit of _m each
DB 15: obtaining pixel drive data GD1, ₁ ~GD _n, the 15th bit such pixel drive data bit groups of _m each DB1～DB15.

  Each of the pixel drive data bit groups DB1 to DB15 corresponds to each of subfields SF1 to SF15 described later. For each of the subfields SF1 to SF15, the drive control circuit 56 supplies the pixel driver data bit group DB corresponding to the subfield to the address driver 55 by one display line (m).

  Further, the drive control circuit 56 generates various timing signals for driving and controlling the PDP 50 in accordance with the light emission drive sequence as shown in FIG. 7, and the even X electrode driver 510, the odd Y electrode driver 530, the odd X electrode driver 520, and the even number. The Y electrode driver 540 is supplied.

  In the light emission drive sequence shown in FIG. 7, driving by 15 subfields SF1 to SF15 is performed for each unit display period (one field or one frame display period) in the video signal. In the first subfield SF1, the reset process R, the selective write address process W, and the sustain process I are executed in that order. In each of the subfields SF2 to SF15, the reset process Ro, the selective erase address process Wo, the reset process Re, the selective erase address process We, and the sustain process I are executed in that order. Only in the last subfield SF15, the erasing process E is executed immediately after the sustaining process I.

  8 shows that the address driver 55, the odd-numbered X electrode driver 520, the even-numbered X electrode driver 510, the odd-numbered Y electrode driver 530, and the even-numbered Y electrode driver 540 are each column electrodes of the display electrode forming portion DPE according to the light emission driving sequence shown in FIG. 4 is a diagram illustrating various drive pulses applied to D and row electrodes X and Y. FIG.

  In FIG. 8, only the operations in the first subfields SF1 and SF2 in the subfields SF1 to SF15 shown in FIG. 7 are extracted and shown.

First, in the reset process R of the subfield SF1, the odd-numbered X electrode driver 520 and the even-numbered X electrode driver 510 have a positive first reset pulse as shown in FIG. RP _X1 , a negative second reset pulse RP _X2 , and a positive third reset pulse RP _X3 having substantially the same pulse voltage as RP _X1 are sequentially generated and applied to each of the row electrodes X _{1 to} X _n . Apply. Meanwhile, the odd-numbered Y electrode driver 530 and the even-numbered Y electrode driver 540 have the first reset pulse RP _Y1 , the second reset pulse RP _Y2 , and the first reset pulse RP _Y2 having the same waveform as the reset pulses RP _X1 , RP _X2 , RP _X3 . Each of the three reset pulses RP _Y3 is sequentially applied to the row electrodes Y _{1 to} Y _n . Furthermore, while in the reset stage R, the address driver 55, first reset pulse RP _X1 to (RP _Y1) is applied to the row electrodes X ₁ to X _n and Y ₁ to Y _n, respectively, as shown in FIG. 8 Each of the column electrodes D _{1 to} D _m is set to 0 volts. Further, the address driver 55 applies a positive voltage adjustment pulse CP to each of the column electrodes D _{1 to} D _m while the second and third reset pulses RP _X2 and RP _X3 (RP _Y2 and RP _Y3 ) are applied. Apply. By applying the positive first reset pulse RP _Y1 as described above, the first voltage is applied between the column electrode D and the row electrode Y in the selected cell C2 of each of the pixel cells PC of the PDP 50. Become. Accordingly, a first reset discharge is generated between the column electrode D and the row electrode Y in the selected cell C2. After the end of the first reset discharge, a positive wall charge is formed on the column electrode D in the selected cell C2, and a negative wall charge is formed on the row electrode Y. Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. Next, the application of the negative second reset pulse RP _Y2 and the positive voltage adjustment pulse CP causes the above-described gap between the column electrode D and the row electrode Y in the selected cell C2 of all the pixel cells PC of the PDP 50. A second voltage having a polarity different from that of the first voltage is applied. As a result, a second reset discharge is generated between the column electrode D and the row electrode Y in the selected cell C2. Then, the application of the positive third reset pulse RP _Y3 and the positive voltage adjustment pulse CP causes the above-described first gap between the column electrode D and the row electrode Y in the selected cell C2 of each of the pixel cells PC of the PDP 50. A third voltage lower than 1 voltage is applied. In other words, while the third reset pulse RP _Y3 of positive polarity is applied, the voltage adjustment pulse CP having the same polarity as the third reset pulse RP _Y3 is applied to the column electrodes D, the column electrodes and row The voltage applied between the electrodes is lower than the first voltage. By applying the third voltage between the column electrode D and the row electrode Y in the selected cell C2, the second reset discharge is continued between the column electrode D and the row electrode Y in the selected cell C2. A third reset discharge is generated. Therefore, the third reset discharge is weaker than the first reset discharge. After the end of the third reset discharge, a positive wall charge is formed on the column electrode D in the selected cell C2, and a negative wall charge is formed on the row electrode Y. Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. Note that the amount of wall charges formed on each electrode by the third reset discharge is larger than the amount of wall charges formed immediately after the end of the first reset discharge.

Next, in selective write address step W of the subfield SF1, the odd Y electrode driver 530 and the even-Y electrode driver 540, at the same time a scan base pulse SBP having a voltage V1 of positive polarity to the row electrodes Y ₁ to Y _n applied while it is sequentially applies the scanning pulse SP having a positive voltage having a waveform projecting from the scan base pulse SBP V2 (V2> V1) to the row electrodes Y ₁ to Y _n, respectively. During this time, the odd X electrode driver 520 and the even X electrode driver 510 applies a scan base pulse SBP having row electrodes X ₁ to X _n respectively to the positive polarity voltage V1. The address driver 55 converts each data bit in the pixel drive data bit group DB1 corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, the address driver 55 converts a pixel drive data bit having a logic level 0 that should cause the pixel cell PC to be set to the light-off mode into a positive high-voltage pixel data pulse DP, while causing the pixel cell PC to be set to the light-on mode. A pixel drive data bit having a logic level 1 is converted into a pixel data pulse DP having a low voltage (0 volts). Then, the pixel data pulse DP is applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronization with the application timing of the scanning pulse SP. In other words, the address driver 55 first applies a pixel data pulse group DP ₁ composed of m pixel data pulses DP corresponding to the first display line to the column electrodes D _{1 to} D _m , and then the second display line. is the pixel data pulse group DP ₂ comprised of m pixel data pulses DP corresponding to the column electrodes D ₁ to D _m in. At this time, between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. Selective write address discharge is generated. In response to the selective write address discharge, a positive wall charge is formed on the column electrode D in the selected cell C2 of the pixel cell PC, and a negative wall charge is formed on the row electrode Y. . Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. On the other hand, since the pixel data pulse DP of low voltage (0 volt) is not applied to the pixel cell PC to be set in the extinguishing mode, the selective write address discharge as described above does not occur. Therefore, the wall charge distribution state in the pixel cell PC maintains the state immediately after the end of the reset discharge.

Next, in the sustain process I of each subfield, the odd Y electrode driver 530 odd row electrodes Y ₁ negative polarity sustain pulse IP _{Y of, Y 3, Y 5, ····} , Y n-3 and Repeatedly applied to each of Y _n-1 . Further, in the sustain process I, the even-Y electrode driver 540, even-numbered row electrodes sustain pulses IP _Y of negative polarity at a timing different from the applied sustain pulse IP _Y to the odd-numbered row electrodes Y as described above Applied to Y ₂ , Y ₄ ,..., Y _n-2 , and Y _n . In the sustain process I, the odd-numbered X electrode driver 520 applies the negative sustain pulse IPx to the odd-numbered row electrodes X ₁ , X ₃ at the same timing as the sustain pulse IP _Y applied to the even-numbered row electrodes Y. , X ₅ ,..., X _n-3 , and X _n-1 are repeatedly applied. In the sustain process I, the even-numbered X electrode driver 510 applies the negative sustain pulse IPx to the even-numbered row electrodes Y ₂ , Y at the same timing as the sustain pulse IP _Y applied to the odd-numbered row electrodes Y. ₄ ,..., Y _n-2 and Y _n are applied to each. In each sustain process I, the sustain pulses IP _Y and IP _X are applied only the number of times assigned to the subfield to which the sustain process I belongs. The address driver 55 applies a positive address pulse AP to the column electrodes D _{1 to} D _m in synchronization with the application of the first sustain pulse IP _Y applied first in the sustain process of each subfield. Depending on the application of the first sustain pulse IP _Y and the address pulse, discharge is produced between the column electrode D and the row electrode Y within the select cell C2 of the pixel cell PC to be set to the lighting mode. By this discharge, negative wall charges are formed on the column electrode D in the selected cell C2, and positive wall charges are formed on the row electrode Y in the selected cell C2. That is, the polarity of the wall charges on the row electrode Y in the selected cell C2 is reversed. Further, the discharge expands into the display cell C1 through the gap r in the pixel cell PC, and positive wall charges are formed on the row electrode Y in the display cell C1. At this time, negative wall charges remain on the row electrode X in the display cell C1. Therefore, the pixel cell PC including the display cell C1 is set to the lighting mode by the discharge. Accordingly, thereafter, every time sustain pulses IP _X and IP _Y are alternately applied by the number corresponding to each subfield, a sustain discharge (display discharge) is generated between the row electrodes Y and X in the display cell C1. Occurred and maintains the light emission state accompanying the discharge. On the other hand, in the pixel cell PC to be set to the extinguishing mode, negative wall charges are formed on the row electrode Y in the selected cell C2, and positive wall charges are formed on the column electrode D. . Therefore, even when the first sustain pulse IP _Y and the address pulse synchronized therewith are applied, no discharge occurs between the column electrode D and the row electrode Y in the selected cell C2, and the polarity of the wall charges is not reversed. Therefore, this pixel cell PC is set to the extinguishing mode, and even if the sustain pulses IP _X and IP _Y are applied, the sustain discharge occurs between the row electrode Y and the row electrode X in the display cell C1. It remains unlit. Here, at the same timing as the last sustain pulse IP _Y applied to the odd-numbered row electrodes Y in each sustain step I, the address driver 55 again returns the positive address to each of the column electrodes D _{1 to} D _m. A pulse AP is applied. As a result, a discharge is generated between the column electrode D and the row electrode Y in the selected cell C2. With this discharge, a negative electrode wall charge is formed on the column electrode D in the selected cell C2, and a positive electrode wall charge is formed on the row electrode Y in the selected cell C2. At this time, in the display cell C1, a positive wall charge is formed on the row electrode Y and a negative wall charge is formed on the row electrode X due to the sustain discharge generated between the row electrodes X and Y. The

Next, in reset step Ro of each sub-field, the odd Y electrode driver 530, row electrodes Y ₁ of the odd-numbered and generates a reset pulse RP _Y of moderate positive rising transition as shown in FIG. 8, Y ₃ ~ Y _n-1 applied to each. During this time, the even-numbered X electrode driver 510 generates a positive-polarity reset pulse RP _X with a gradual rising change in synchronization with the reset pulse RP _Y and applies it to each of the even-numbered row electrodes X ₂ , X _{4 to} X _n . Apply. Here, among all the pixel cells PC, in the pixel cell PC belonging to the odd display line in which the sustain discharge is generated in the immediately preceding sustain process I, between the column electrode D and the row electrode Y in the selected cell C2. A reset discharge occurs. A positive wall charge is formed on the column electrode D in the selected cell C2 where the reset discharge is generated, and a negative wall charge is formed on the row electrode Y. Further, positive wall charges are maintained on the row electrodes Y in the display cells C1 of the pixel cells PC belonging to the odd display lines, and negative wall charges are maintained on the row electrodes X.

Next, in selective erase address step Wo of each subfield, and applying a scan base pulse SBP odd Y electrode driver 530 has a voltage V1 of positive polarity to the row electrodes _{Y 1, Y 3 ~Y n-} 1 of the odd-numbered Meanwhile, a scan pulse SP having a positive voltage V2 having a waveform protruding from the scan base pulse SBP is sequentially applied to each of the odd-numbered row electrodes Y ₁ , Y _{3 to} Y _n−1 . During this time, the even X electrode driver 510 applies a scan base pulse SBP having row electrodes X _2, X ₄ to X _n each positive polarity voltage V1 of the even-numbered simultaneously. The application of the scan base pulse SBP by the odd-numbered Y electrode driver 530 and the application of the scan base pulse SBP by the even-numbered X electrode driver 510 are performed simultaneously. Further, during this time, the address driver 55 converts each data bit in the pixel drive data bit group DB corresponding to the odd display line into a pixel data pulse DP having a pulse voltage corresponding to the logic level for each subfield. For example, the address driver 55 converts a pixel drive data bit having a logic level 0 that should cause the pixel cell PC to be set to the light-off mode into a pixel data pulse DP having a low voltage (0 volts), while setting the pixel cell PC to the light-on mode. A logic level 1 pixel drive data bit to be converted is converted into a positive high voltage pixel data pulse DP. The logic of this conversion is opposite to that of the first subfield. Then, the pixel data pulse DP is applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronization with the application timing of the scanning pulse SP. In other words, the address driver 55 first applies the pixel data pulse group DP ₁ composed of m pixel data pulses DP corresponding to the first display line to the column electrodes D _{1 to} D _m , and then the third display line. is the pixel data pulse groups DP ₃ of m pixel data pulses DP corresponding to the column electrodes D ₁ to D _m in. At this time, a selective erase address discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the scanning pulse SP and the low-voltage (0 volt) pixel data pulse DP are simultaneously applied. . After the selective erasure address discharge, positive wall charges are formed on the column electrodes D in the selected cells C2, and negative wall charges are formed on the row electrodes Y. Further, negative wall charges are formed on the row electrodes Y in the display cells C1 of the pixel cells PC, and negative wall charges are also formed on the row electrodes X. As a result, the pixel cell PC is set to the extinguishing mode. On the other hand, since the pixel data pulse DP is not applied to the pixel cells PC on the odd-numbered rows to be set to the lighting mode, the selective erasure address discharge does not occur. Therefore, the wall charge distribution state in the pixel cell PC remains as it is immediately after the end of the reset discharge in the reset process Ro. That is, a mode in which positive wall charges are maintained on the row electrodes Y in the display cells C1 and negative wall charges are maintained on the row electrodes X, that is, a lighting mode is set.

  As described above, by executing the selective erasure address process Wo, each of the pixel cells PC belonging to the odd display lines in the PDP 50 is set to either the lighting mode or the extinguishing mode according to the pixel data.

Next, in reset step Re of each sub-field, the even Y electrode driver 540, simultaneously applies a negative polarity sustain pulse IP _Y of the even-numbered each of the row electrodes Y _2, Y ₄ to Y _n of the PDP 50. At the same time, the odd-numbered X electrode driver 520 applies a negative sustain pulse IP _X to each of the odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,..., X _n-3 and X _n−1. Apply simultaneously. In synchronization with the sustain pulses IP _Y and IP _X , the address driver 55 applies a positive address pulse AP to the column electrodes D _{1 to} D _m . As a result, no discharge occurs in the pixel cell PC set in the extinguishing mode, and the extinguishing mode is maintained. On the other hand, in the pixel cell PC set in the lighting mode, discharge is generated in each of the display cell C1 and the selected cell C2 of the pixel cell PC belonging to the even display line. By this discharge, positive wall charges are formed on the row electrode Y in the selected cell C2, and negative wall charges are formed on the column electrode D in the selected cell C2. Furthermore, positive wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are formed on the row electrodes X in the display cells C1. Thereafter, the even-Y electrode driver 540 applies to each of the moderate positive polarity of the reset pulse RP row electrodes _Y generate and the even-numbered Y _2, Y ₄ to Y _n of the rising change as shown in FIG. During this time, the odd-numbered X electrode driver 520 generates a positive polarity reset pulse RP _X having a gradual rising change in synchronization with the reset pulse RP _Y to generate odd-numbered row electrodes X ₁ , X _{3 to} X _n−1. To each of the above. In response to the application of the reset pulses RP _Y and RP _X , the weakness is generated between the column electrode D and the row electrode Y in the selected cell C2 in the pixel cell PC belonging to the even display line in which discharge is generated in the immediately preceding sustain process I. A reset discharge occurs. After the reset discharge is completed, positive wall charges are formed on the column electrode D in the selected cell C2 where the reset discharge is generated, and negative wall charges are formed on the row electrode Y. . Further, positive wall charges are maintained on the row electrodes Y in the display cells C1 in the pixel cells PC belonging to the even display lines, and negative wall charges are maintained on the row electrodes X.

Next, in the selective erase address step We of each subfield, while applying a scan base pulse SBP to the even Y electrode driver 540 has a voltage V1 of positive polarity to the row electrodes Y _2, Y ₄ to Y _n of the even-numbered , are sequentially applied to the scanning pulse SP having a voltage V2 of positive polarity having a waveform projecting from the scan base pulse SBP to the row electrodes Y _2, Y ₄ ~Y _n each even-numbered. The odd-numbered X electrode driver 520 simultaneously applies the scan base pulse SBP having the positive voltage V1 to each of the odd-numbered row electrodes X ₁ , X _{3 to} X _n−1 . The address driver 55 converts each data bit in the pixel drive data bit group DB corresponding to the even display line into a pixel data pulse DP having a pulse voltage corresponding to the logic level for each subfield. Then, the pixel data pulse DP is applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronization with the application timing of the scanning pulse SP. In other words, the address driver 55 first applies a pixel data pulse group DP ₂ composed of m pixel data pulses DP corresponding to the second display line to the column electrodes D _{1 to} D _m , and then the fourth display line. is the pixel data pulse group DP ₄ of m pixel data pulses DP corresponding to the column electrodes D ₁ to D _m in. At this time, a selective erase address discharge is generated between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the scanning pulse SP and the low-voltage (0 volt) pixel data pulse DP are simultaneously applied. . After such selective erasure address discharge, positive wall charges are formed on the column electrode D in the selected cell C2 of the pixel cell PC belonging to the even display line to be set in the extinction mode, and the negative electrode is formed on the row electrode Y. Sexual wall charges are formed. Further, negative wall charges are formed on the row electrodes Y in the display cells C1 in the pixel cells PC belonging to the even display lines, and negative wall charges are also formed on the row electrodes X. Thereby, the pixel cell PC is set to the extinguishing mode. On the other hand, the pixel cell PC belonging to the even display line to be set to the lighting mode is not applied with the low voltage (0 volt) pixel data pulse DP, so that the selective erase address discharge does not occur. Therefore, the wall charge distribution state in the pixel cell PC remains as it is immediately after the end of the reset discharge in the reset process Re. That is, a mode in which positive wall charges are maintained on the row electrodes Y in the display cells C1 and negative wall charges are maintained on the row electrodes X, that is, a lighting mode is set.

  As described above, by executing the selective erasure address process We, each pixel cell PC belonging to the even display line is set to either the lighting mode or the non-lighting mode according to the pixel data.

  After the execution of the selective erasing address process We, the sustain process I as described above is performed, and only the pixel cells PC set in the lighting mode are repeatedly subjected to the sustain discharge for the number of times assigned to each subfield. The accompanying light emission state is maintained.

  Then, the drive shown in FIGS. 7 and 11 as described above is executed based on the 16 types of pixel drive data GD as shown in FIG. According to such driving, as shown in FIG. 6, the write address in each pixel cell PC in the selective write address process W of the first subfield SF <b> 1 except when the luminance level 0 is expressed (first gradation). Discharge occurs (indicated by a double circle), and the pixel cell PC is set to the lighting mode. Thereafter, selective erasure address discharge is generated only in the selective erasure address steps Wo and We of one subfield in each of the subfields SF2 to SF15 (indicated by black circles), and the pixel cell PC is set to the extinguishing mode. In other words, each pixel cell PC is set to the lighting mode in each of the continuous subfields corresponding to the intermediate luminance to be expressed, and the light emission associated with the sustain discharge is repeated for the number of times assigned to each of these subfields. Occur (indicated by white circles). At this time, the luminance corresponding to the total number of light emission associated with the sustain discharge generated in one field is visually recognized. Therefore, according to the 16 types of light emission patterns by the 1st to 16th gradation driving as shown in FIG. 6, the intermediate for 16 gradations corresponding to the total number of sustain discharges generated in each of the subfields indicated by white circles. Luminance is expressed.

  Here, in the plasma display device shown in FIG. 1, the pixel cell PC which carries each pixel of the PDP 50 is constructed by the display cell C1 and the selection cell C2 as shown in FIGS. The sustain discharge related to the display image is generated in the display cell C1, while the reset discharge and the address discharge accompanied by the light emission not related to the display image are mainly generated in the selected cell C2. . In the selected cell C2, a raised dielectric layer composed of a light absorbing layer containing a black or dark pigment is used to prevent light accompanying the reset discharge and address discharge from passing through the front transparent substrate 10 and leaking to the outside. 12 is formed. Therefore, since the discharge light accompanying the reset discharge and the address discharge is blocked by the raised dielectric layer 12, it is possible to increase the contrast of the display image, particularly the dark contrast. Further, in the selected cell C2, a secondary electron emission material layer 30 is provided on the back substrate 13 side as shown in FIG. The secondary electron emission material layer 30 has good γ characteristics for emitting secondary electrons during discharge in which the formation surface becomes a cathode. Therefore, in the address process (W, Wo, We) shown in FIG. 8, a scan pulse SP having a positive voltage V2 is applied to the row electrode Y, and a pixel data pulse DP having a low voltage (0 volts) is applied to the column electrode D. Is applied to the address discharge. That is, when generating the address discharge, the column electrode D is relatively on the cathode side, so that the secondary electron emission material layer 30 formed in the selected cell C2 is also on the cathode side. As a result, secondary electrons are effectively emitted from the secondary electron emission material layer 30, and an address discharge is reliably generated in the selected cell C2.

  Further, in the driving shown in FIG. 8, in order to prevent erroneous address discharge between the row electrode Y and the column electrode D other than the row electrode Y to which the scan pulse SP is applied, Similarly, a reset discharge is generated between the row electrode and the column electrode. When a reset discharge is generated between the row electrode Y and the column electrode D, a positive wall charge is formed on the column electrode D and a negative wall charge is formed on the row electrode Y in the selected cell C2. . In such a state where wall charges are formed, in order to cause an address discharge in the selected cell C2 by applying a positive scan pulse SP, it is necessary to set the scan pulse SP to a high voltage (V2). In other words, when a positive wall charge is formed on the column electrode D and a negative wall charge is formed on the row electrode Y in the selected cell C2, a relatively high voltage is not applied between the column electrode D and the row electrode Y. As long as no discharge occurs, erroneous discharge is prevented.

  However, when a positive scan base pulse SBP as shown in FIG. 8 is applied to all the row electrodes X and Y in order to increase the voltage of the scan pulse SP, the pixel cell is not applied although the scan pulse SP itself is not applied. There is a problem that erroneous discharge occurs between the row electrode and the column electrode in the display cell C1 of the PC.

  Therefore, in the driving shown in FIG. 8, the amount of wall charges formed in the display cell C1 is increased by sequentially generating at least three reset discharges in the reset process R of the first subfield SF1. I am doing so. That is, first, a first reset voltage is generated between the one row electrode and the column electrode in the selected cell by applying a positive first voltage between the row electrode and the column electrode, and then, A second reset discharge is generated by applying a negative second voltage between the row electrode and the column electrode. A third reset discharge is caused between the one row electrode and the column electrode in the selected cell by applying a positive third voltage between the row electrode and the column electrode. At this time, a first voltage that is applied between the row electrode and the column electrode to cause the final third reset discharge is applied, and a first voltage that is applied between the row electrode and the column electrode to generate the first first reset discharge. By making the voltage lower than the voltage, the final third reset discharge is weaker than the first reset discharge at the head. Along with the first reset discharge, a relatively large amount of negative wall charge having a polarity opposite to that of the scan base pulse SBP is formed on the row electrode Y in the display cell C1, so that the scan base pulse SBP is applied. As a result, no discharge occurs between the row electrode and the column electrode in the display cell C1. That is, erroneous discharge in the display cell C1 during the address process W is prevented. Note that an excessive amount of wall charges is formed in the selected cell C2 due to the first reset discharge, but by generating a third reset discharge weaker than the first reset discharge, The amount of wall charge is reduced and adjusted to an appropriate amount.

Here, in the above embodiment, the third voltage applied between the row electrode and the column electrode to cause the third reset discharge is set to be higher than the first voltage applied to cause the first reset discharge. In order to lower the voltage, a third reset pulse RP _Y3 having the same pulse voltage as the first reset pulse RP _Y1 is applied to the row electrode, and a voltage adjustment pulse CP having the same polarity as the third reset pulse RP _Y3 is applied to the column electrode. Applied.

However, as shown in FIG. 9, while the third reset pulse RP _Y3 is being applied, the voltage adjustment pulse CP is not applied to the column electrodes, and the pulse voltage value of the third reset pulse RP _Y3 itself. _May be made lower than the first reset pulse RP _Y1 . Further, as shown in FIG. 10, the odd-numbered Y electrode driver 530 and the even-numbered Y electrode driver 540 respectively stop the voltage application in the middle of the rise of the voltage in the third reset pulse RP _Y3 to make a so-called high impedance state. The pulse voltage value of the third reset pulse RP _Y3 may be set lower than that of the first reset pulse RP _Y1 .

It is a figure which shows the structure of the plasma display apparatus as a display apparatus by this invention. It is the top view which looked at a part of structure of the display electrode formation part DPE shown by FIG. 1 from the display surface side. It is a figure which shows the cross section on the V1-V1 line | wire shown by FIG. It is a figure which shows the cross section on the V2-V2 line | wire shown by FIG. It is a figure which shows the cross section on the W1-W1 line | wire shown by FIG. It is a figure which shows the light emission drive pattern based on the conversion table of pixel data, and the pixel drive data GD obtained by this pixel data conversion table. It is a figure which shows an example of the light emission drive sequence in the plasma display apparatus shown by FIG. It is a figure which shows the various drive pulses applied to PDP50 according to the light emission drive sequence shown in FIG. 7, and its application timing. It is a figure which shows the other example of the 1st-3rd reset pulse applied in a reset process. It is a figure which shows the other example of the 1st-3rd reset pulse applied in a reset process.

Explanation of symbols

50 PDP
520 Odd X electrode driver
510 Even X Electrode Driver
530 Odd Y electrode driver
540 Even Y electrode driver 55 Address driver 56 Drive control circuit C1 Display cell C2 Selected cell
DPE display electrode formation part PC pixel cell

Claims (13)

A front substrate and a rear substrate arranged opposite to each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on the inner surface of the front substrate, and a plurality of rows arranged on the inner surface of the rear substrate so as to cross the row electrode pairs A pixel cell including a display cell and a selection cell provided with a light absorption layer on the front substrate side is formed at each intersection of the row electrode pair and the column electrode. A display device that drives each unit display period composed of a plurality of subfields each including an address period and a sustain period, in accordance with pixel data for each pixel based on an input video signal,
Within the address period of each of the subfields, a pixel data pulse corresponding to the pixel data is applied to the column electrode in synchronization with the scan pulse while sequentially applying a scan pulse to one row electrode of each of the row electrode pairs. Address means for generating an address discharge between the one row electrode and the column electrode in the selected cell by sequentially applying one display line at a time;
Sustain means for generating a sustain discharge between the row electrodes in the row electrode pair in the display cell by applying a sustain pulse to each of the row electrode pairs in the sustain period of each of the subfields;
Immediately before the address period in the first subfield of the unit display period, a first voltage, a second voltage having a polarity different from the first voltage, is applied between one row electrode and the column electrode of the row electrode pair. And a first reset discharge between the one row electrode and the column electrode in the selected cell by sequentially applying a third voltage having the same polarity as the first voltage and lower than the first voltage, And a reset means for sequentially generating a second reset discharge and a third reset discharge.   The addressing means applies the scan pulse to the one row electrode while applying the base pulse having the same polarity as the scan pulse to the one row electrode in the address period so as to be superimposed on the base pulse. The display device according to claim 1, characterized in that: A secondary electron emission layer is provided on the back substrate side of the selected cell,
The base pulse and the scan pulse are both positive pulses, and the pixel data pulse has a polarity that makes the column electrode side relatively negative when the address discharge occurs. The display device described.   The display device according to claim 1, wherein the sustain unit applies the negative sustain pulse during the sustain period.   The addressing means extends the address discharge generated in the selected cell into the display cell and sets the display cell to one of a lighting mode state and a light-off mode state. The display device according to claim 1. The address means selectively causes a write address discharge in an address period of a first subfield of the unit display period to set the display cell in a lighting mode state;
2. The extinguishing address discharge is selectively generated only in the address period of any one of the subfields subsequent to the first subfield to set the extinguishing mode state. Display device.   The reset means generates a first reset discharge by applying a positive first reset pulse to the one row electrode, and applies a negative second reset pulse to the one row electrode. The second reset discharge is generated, and a positive third reset pulse having substantially the same pulse voltage as the first reset pulse is applied to the one row electrode, and a voltage composed of a constant positive voltage is applied to the column electrode. The display device according to claim 1, wherein the third reset discharge is generated by applying an adjustment pulse.   The reset means generates a first reset discharge by applying a positive first reset pulse to the one row electrode, and applies a negative second reset pulse to the one row electrode. The second reset discharge is generated, and the third reset discharge is generated by applying a positive third reset pulse having a pulse voltage lower than that of the first reset pulse to the one row electrode. The display device according to claim 1.   9. The display device according to claim 7, wherein the first reset pulse and the third reset pulse have a waveform in which a level transition in a rising or falling period is gentler than that of the sustain pulse.   The display cell includes a portion in which the one row electrode and the other row electrode constituting the row electrode pair face each other through a first discharge gap in a discharge space, and the selected cell includes the column electrode. 2. The display device according to claim 1, further comprising a portion facing the one electrode constituting the row electrode pair through a second discharge gap in the discharge space. The one row electrode and the other row electrode constituting the row electrode pair protrude from the main body portion in the column direction via a main body portion extending in the row direction and a first discharge gap for each unit light emitting region. With protrusions,
The display cell includes a portion in which the protruding portion faces in the discharge space via a first discharge gap, and the selected cell includes a main body portion of the one electrode constituting the column electrode and the row electrode pair, and The display device according to claim 1, further comprising a portion facing each other through the second discharge gap in the discharge space. The display panel includes a partition wall including a vertical wall portion that divides a discharge space of the adjacent pixel cell in a row direction and a horizontal wall portion that divides the discharge space in a column direction, the discharge space of the display cell in the pixel cell, and the selection. A partition wall that partitions the discharge space of the cell,
The discharge spaces of the selected cells of the pixel cells are closed to each other by the partition walls,
The discharge spaces of the display cells of the pixel cells adjacent to each other in the row direction communicate with each other, and the discharge spaces of the display cells and the selected cells in each pixel cell communicate with each other. The display device according to claim 1.   The display device according to claim 1, wherein a phosphor layer that emits light by discharge is formed only in the display cell.

Images