JP2007316296A - Display apparatus and method for driving display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To surely set each pixel cell to a state according to a pixel data. <P>SOLUTION: In an address period WW of a head sub-field SF1 in one field display period, while alternately applying a scanning base potential BP+ of positive polarity to one row electrode and the other row electrode in all the row electrode pairs, a predetermined potential SP of positive polarity is sequentially superimposed on the respective electrode, and also after such write address discharge is ended, erase discharge is made to occur by applying thereto a wall charge conditioning pulse CP of negative polarity in which first a front edge part has a gradual potential transit section. After that, write-in discharge to form the wall charge is made to occur by applying thereto simultaneous write-in pulse AP of negative polarity. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a display device including a display panel and a display panel driving method.

In recent years, a plasma display device equipped with a surface discharge type AC plasma display panel as a large and thin color display panel has attracted attention. Further, as such a surface discharge type AC plasma display panel, a display panel is known in which a pixel cell carrying each pixel is composed of a selected cell and a display cell (see, for example, Patent Document 1). Such a display panel includes a front substrate and a rear substrate that are arranged to face each other with a discharge space interposed therebetween, a plurality of row electrode pairs provided on the inner surface of the front substrate, and a row electrode pair on the inner surface of the rear substrate. And a plurality of arranged column electrodes. A pixel cell PC including a display cell C1 and a selection cell C2 is formed at each intersection of the row electrode pair and the column electrode (see FIGS. 2 and 3 of Patent Document 1). When driving such a display panel, for each field display period, in each of the plurality of subfields SF, an address process W for determining the state of each pixel cell as one of the lit cell state and the unlit cell state; A sustain process I is performed in which only the discharge cells in the lighted cell state are repeatedly discharged (see FIGS. 7 and 8 of Patent Document 1). For example, in the address process W of the first subfield SF1, a positive scan pulse SP is applied to the pixel cell PC to be set in the lighted cell state while applying a potential of 0 volt to the column electrode D to which the pixel cell PC belongs. Is applied to the row electrode Y to cause an address discharge between the column electrode D and the row electrode Y in the selected cell C2. Then, in the sustain process I that is executed subsequent to the address process W, the negative sustain pulse IP is alternately applied to all the row electrodes Y and X while applying the positive address pulse AP to all the column electrodes D. Apply to. At this time, in response to the negative sustain pulse IP _Y first applied to the row electrode Y, the selected cell C2 of the pixel cell PC is targeted for the pixel cell PC in which the address discharge is generated in the address process W. The write discharge is generated simultaneously between the column electrode D and the row electrode Y. The write discharge is expanded to the display cell C1 through the gap r, so that the pixel cell PC has a positive charge on the row electrode Y and a negative charge on the row electrode X in the display cell C1. Is formed, that is, a lighted cell state is set. In the pixel cell PC set in the lighted cell state, a sustain discharge is generated between the row electrodes X and Y in the display cell C1 every time the sustain pulse IP is applied.

However, due to the variation of each pixel cell PC in manufacturing, even if the first negative pulse (sustain pulse) is applied after the occurrence of the address discharge as described above, the write discharge is surely performed. There was a problem that it could not be born.
JP-A-2005-107428

  The present invention has been made to solve such a problem, and a display device and a display capable of reliably setting each pixel cell in a state (lit cell state or unlit cell state) according to pixel data. An object of the present invention is to provide a panel driving method.

  The display device according to claim 1, wherein an address period for setting each of the pixels to one of a lighting mode and a lighting mode according to pixel data for each pixel based on an input video signal, and the state of the lighting mode A display device for displaying an image by a plurality of subfields including a sustain period for causing the pixels to emit light, wherein a front substrate and a rear substrate facing each other with a discharge space interposed therebetween, and a display line on the inner surface of the front substrate A plurality of row electrode pairs, a dielectric layer covering the row electrode pairs, and a plurality of column electrodes arranged on the inner surface of the back substrate so as to cross the row electrode pairs. And a display panel in which a pixel cell composed of a first discharge cell and a second discharge cell provided with a light shielding layer is formed at each intersection of the column electrode and the first support in the first field display period. In the address period of the field, a scanning base potential having a positive potential is applied to one row electrode of all the row electrode pairs, and a predetermined positive potential is sequentially superimposed on each of the one row electrode. Addressing means for generating a write address discharge that should form a wall charge in the second discharge cell by applying a potential corresponding to the pixel data to the column electrode while applying, and After completion, a part of the wall charge formed in the second discharge cell is erased by applying a negative wall charge adjustment pulse having a gradual potential transition section to the one row electrode. Wall charge adjusting means for generating an erasing discharge.

  According to another aspect of the display panel driving method of the present invention, a first discharge is generated at each intersection of a plurality of row electrode pairs constituting a display line and a plurality of column electrodes arranged to cross the row electrode pairs. A display panel in which a pixel cell composed of a cell and a second discharge cell provided with a light shielding layer is formed, and each of the pixels is turned on and off according to pixel data for each pixel based on an input video signal. A display panel driving method which is driven by a plurality of subfields including an address period set in one of modes and a sustain period in which the pixel in the lighting mode emits light. Generating a write address discharge in the second discharge cell in accordance with the pixel data in the address period of the head subfield of the pixel cell The erase address discharge is generated in the second discharge cell in accordance with the pixel data in the address period of each of the write address process set to the lighting mode and the subfield subsequent to the first subfield. An erase address process for setting the pixel cell to the extinguishing mode, and the write address process has a positive polarity while applying a positive scan base potential to one row electrode of all the row electrode pairs. A predetermined potential is sequentially applied to each of the one row electrode, and a write address discharge is generated in the second discharge cell by applying a potential corresponding to the pixel data to the column electrode. After the end of the write address discharge, a negative wall charge adjustment pulse having a gradual potential transition interval at the leading edge of each of the one row electrode. To rise to erase discharge for erasing a portion of the wall charges formed in the second discharge cell by pressure.

  In the present invention, a display in which a pixel cell composed of a first discharge cell and a second discharge cell provided with a light shielding layer is formed at the intersection of a plurality of row electrode pairs that bear display lines and column electrodes. The panel is driven as follows. In the address period of the first subfield of one field display period, a predetermined positive polarity potential is sequentially superimposed on each row electrode while applying a positive scan base potential to one row electrode of all row electrode pairs. In addition, a write address discharge is caused in the second discharge cell by applying a potential corresponding to the pixel data to the column electrode. Here, after the end of the write address discharge, a negative wall charge adjustment pulse having a gradual potential transition section at the leading edge is applied to each one of the row electrodes to be formed in the second discharge cell. This causes an erasing discharge that erases a part of the wall charge. Immediately after the application of the wall charge adjustment pulse, a negative simultaneous write pulse is applied to each of the row electrodes, thereby generating a write discharge that forms wall charges in the second discharge cells. In other words, a relatively large amount of wall charges formed in response to the write address discharge are erased by a part of the wall charges by erasing discharge in response to the application of the wall charge adjustment pulse, immediately before the application of the simultaneous write pulse. This prevents erroneous discharges from occurring. This ensures that each pixel cell is in a state corresponding to the pixel data (a lighting mode state in which wall charges remain, a light-off mode state in which wall charges do not remain), even if manufacturing variations occur in each pixel cell. It becomes possible to set.

  FIG. 1 is a diagram showing a configuration of a plasma display device as a display device according to the present invention.

  As shown in FIG. 1, the plasma display apparatus includes a PDP 50 as a plasma display panel and a drive control circuit 54 that drives and controls the PDP 50 according to an input video signal.

  The PDP 50 includes a column electrode driver 55, a first row electrode driver 510, a second row electrode driver 520, and a display electrode formation unit DPE.

In the display electrode forming portion DPE, strip-like column electrodes (address electrodes) D _{1 to} D _m extending in the column direction (vertical direction) of the display screen are formed. Further, in the display electrode forming portion DE, strip-like row electrodes X _{1 to} X _n and row electrodes Y _{1 to} Y _n respectively extending in the row direction (left and right direction) of the display screen are respectively shown in FIG. , XY are arranged alternately and in numerical order. At this time, each pair of adjacent row electrodes, ie, each of the row electrode pair (X ₁ , Y ₁ ) to the row electrode pair (X _n , Y _n ) is a first display line in the PDP 50. This corresponds to the nth display line. A pixel cell PC serving as a pixel is formed in each intersection of each display line and the column electrodes D _{1 to} D _m , that is, in a unit light emitting region surrounded by a one-dot chain line in FIG.

  2 to 4 are diagrams showing a part of the structure of the display electrode forming portion DPE.

  2 is a plan view viewed from the display surface side of the PDP 50. FIG. 3 is a cross-sectional view seen from the VV line shown in FIG. 2, and FIG. 4 is a cross-sectional view seen from the WW line shown in FIG.

  As shown in FIG. 2, the row electrode Y includes a bus electrode Yb (a main body portion of the row electrode Y) extending in the row direction (left-right direction) of the display screen, and a plurality of transparent electrodes Ya connected to the bus electrode Yb. Consists of The transparent electrode Ya is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Yb. The transparent electrode Ya extends in a direction orthogonal to the bus electrode Yb, and has one end and the other end that are wide as shown in FIG. That is, the transparent electrode Ya can be regarded as a protruding electrode protruding from the main body of the row electrode Y. The row electrode X includes a bus electrode Xb (a main body portion of the row electrode X) extending in the row direction (left-right direction) of the display screen and a plurality of transparent electrodes Xa connected to the bus electrode Xb. The bus electrode Xb is made of, for example, a black metal film. The transparent electrode Xa is made of a transparent conductive film such as ITO, and is disposed at a position corresponding to each column electrode D on the bus electrode Xb. The transparent electrode Xa extends in a direction perpendicular to the bus electrode Xb, and one end thereof has a wide shape as shown in FIG. That is, the transparent electrode Xa can be regarded as a protruding electrode protruding from the main body of the row electrode X. As shown in FIG. 2, the wide portions of the transparent electrodes Xa and Ya are arranged opposite to each other with a discharge gap g having a predetermined length. That is, the transparent electrodes Xa and Ya as protruding electrodes protruding from the main body portions of the paired row electrodes X and Y are arranged to face each other via the discharge gap g. The bus electrodes Yb and Xb are each composed of a black light-shielding conductive layer BE and a main conductive layer ME as shown in FIG.

  The row electrode Y composed of the transparent electrode Ya and the bus electrode Yb and the row electrode X composed of the transparent electrode Xa and the bus electrode Xb are arranged on the inner surface of the front transparent substrate 10 that serves as the display surface of the PDP 50 as shown in FIG. Is formed. Further, a dielectric layer 11 is formed on the back surface of the front transparent substrate 10 so as to cover the row electrodes X and Y. Dielectric layer raised portions 12 projecting from the dielectric layer 11 toward the back side are formed at positions corresponding to the selected cells C2 (described later) on the surface of the dielectric layer 11. The dielectric layer raised portion 12 is composed of a light absorbing layer containing a black or dark pigment, and is formed in a region indicated by a two-dot chain line in FIG. 2 when viewed from the display surface side of the PDP 50. Yes. The surface of the dielectric layer raised portion 12 and the surface of the dielectric layer 11 where the dielectric layer raised portion 12 is not formed are covered with a protective layer MG made of MgO (magnesium oxide). A plurality of column electrodes D extending in a direction perpendicular to the bus electrodes Xb and Yb are arranged in parallel with a predetermined gap on the back substrate 13 arranged in parallel to the front transparent substrate 10. ing. A white column electrode protective layer (dielectric layer) 14 that covers the column electrode D is formed on the back substrate 13. On the column electrode protective layer 14, a partition wall 15 including a first horizontal wall 15A, a second horizontal wall 15B, and a vertical wall 15C is formed. The first horizontal wall 15A is formed to extend in the row direction (left-right direction) of the display surface at a position on the column electrode protective layer 14 facing the bus electrode Yb. The second horizontal wall 15B is formed to extend in the row direction (left-right direction) of the display surface at a position on the column electrode protective layer 14 facing the bus electrode Xb. The vertical wall 15C is formed to extend in a direction orthogonal to the bus electrode Xb (Yb) at each position between the transparent electrodes Xa (Ya) arranged at equal intervals on the bus electrode Xb (Yb). ing.

  The heights of the first horizontal wall 15A, the second horizontal wall 15B, and the vertical wall 15C are not so high as to reach the surface of the dielectric layer 11, as shown in FIGS. Therefore, as shown in FIG. 3, there is a gap r between the second lateral wall 15B and the dielectric layer raised portion 12 in which the discharge gas can flow. However, the dielectric layer raised portion 12 is provided on the surface of the dielectric layer 11 at a portion facing the first horizontal wall 15A as shown in FIG. The flow of the discharge gas is blocked by the first lateral wall 15A and the dielectric layer raised portion 12.

  A region surrounded by the first horizontal wall 15A and the vertical wall 15C (a region surrounded by an alternate long and short dash line in FIG. 2) is a pixel cell PC serving as a pixel. As shown in FIGS. 2 and 3, the pixel cell PC is divided into a display cell C1 and a selection cell C2 by the second horizontal wall 15B.

A secondary electron emission material layer 30 is formed in a region (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B) corresponding to the selected cell C2 on the column electrode protective layer 14. The secondary electron emission material layer 30 is a layer made of a high γ material having a low work function (for example, 4.2 eV or less) and a high so-called secondary electron emission coefficient. Examples of materials used as the secondary electron emission material layer 30 include alkaline earth metal oxides such as MgO, CaO, SrO, and BaO, alkali metal oxides such as Cs ₂ O, fluorides such as CaF ₂ and MgF _{2, and the} like. There are TiO ₂ , Y ₂ O ₃ , or materials whose secondary electron emission coefficient is increased by crystal defects or impurity doping, diamond-like thin films, carbon nanotubes, and the like.

  On the other hand, in the region corresponding to the display cell C1 on the column electrode protective layer 14 (including the side surfaces of the vertical wall 15C, the first horizontal wall 15A, and the second horizontal wall 15B), the phosphor layer 16 is formed as shown in FIG. Has been. There are three types of phosphor layers 16: a red phosphor layer that emits red light, a green phosphor layer that emits green light, and a blue phosphor layer that emits blue light, and the assignment is determined for each pixel cell PC.

  A discharge space filled with a discharge gas exists between the secondary electron emission material layer 30 and the phosphor layer 16 and the dielectric layer 11.

  Thus, the display cell C1 includes the pair of row electrodes X and Y that bear the display line, and the phosphor layer 16. On the other hand, the selected cell C2 includes a row electrode Y of the pair of row electrodes that bears the display line, a row electrode X of the pair of row electrodes that bears a display line adjacent to the display surface above the display line, A secondary electron emission material layer 30. In the display cell C1, as shown in FIG. 2, a wide portion formed at one end of the transparent electrode Xa of the row electrode X, and a wide portion formed at one end of the transparent electrode Ya of the row electrode Y Are arranged opposite to each other via the discharge gap g. On the other hand, in the selected cell C2, the wide portion formed at the other end of the transparent electrode Ya is included, but the transparent electrode X is not included. Further, as shown in FIG. 3, the discharge spaces of the pixel cells PC adjacent to each other in the vertical direction of the display surface (the horizontal direction in FIG. 3) are formed by the first horizontal wall 15A, the dielectric layer raised portion 12 and the protective layer MG. Blocked. On the other hand, the discharge spaces of the display cell C1 and the selected cell C2 belonging to the same pixel cell PC communicate with each other through a gap r as shown in FIG. Further, the discharge spaces of the selected cells C2 adjacent to each other in the left-right direction of the display surface are blocked by the dielectric layer raised portion 12 and the first horizontal wall 15A, but the display cells C1 adjacent to each other in the left-right direction of the display surface. Each discharge space communicates with each other. Thus, each of the pixel cells PC is composed of the display cell C1 and the selection cell C2 whose discharge spaces communicate with each other.

First, the drive control circuit 54 converts the input video signal into, for example, 8-bit pixel data representing the luminance level for each pixel, and performs error diffusion processing and dither processing on the pixel data. For example, in the error diffusion process, first, the upper 6 bits of pixel data are used as display data, and the remaining lower 2 bits are used as error data. Then, the weighted addition of each error data of the pixel data corresponding to each peripheral pixel is reflected in the display data. With this operation, the luminance for the lower 2 bits in the original pixel is expressed in a pseudo manner by the peripheral pixels, and therefore, the display data for 6 bits smaller than 8 bits is equivalent to the pixel data for 8 bits. Brightness gradation expression is possible. Then, dither processing is performed on the 6-bit error diffusion processing pixel data obtained by the error diffusion processing. In the dither processing, a plurality of adjacent pixels are set as one pixel unit, and dither coefficients each having a different coefficient value are allocated and added to the error diffusion processing pixel data corresponding to each pixel in the one pixel unit. To obtain dither-added pixel data. According to the addition of the dither coefficients, when viewed in units of one pixel, it is possible to express a luminance corresponding to 8 bits even with only the upper 4 bits of the dither addition pixel data. Therefore, the drive control circuit 54, the upper 4 bits of the dither added pixel data as multi-gradation pixel data PD _S, 15 bits formed which from the first to 15th bits in accordance with data conversion table as shown in FIG. 5 To pixel drive data GD. Accordingly, pixel data that can represent 256 gradations in 8 bits is converted into 15-bit pixel drive data GD consisting of 16 patterns in total, as shown in FIG. Next, the drive control circuit 54, the pixel drive data GD ₁ of one screen, 1～GD _n, for each _m, separates these pixel driving data GD1, ₁ to GD _{n, m} each at the same bit digit with each other By
DB1: pixel drive data GD1, ₁ to GD _n, the first bit of the _m each
DB2: the pixel drive data GD1, ₁ ~GD _n, the second bit of the _m each
DB3: pixel drive data GD1, ₁ ~GD _n, third bit of _m each
DB4: pixel drive data GD1, ₁ ~GD _n, fourth bit of the _m each
DB 5: pixel drive data GD1, ₁ ~GD _n, the fifth bit of the _m each
DB 6: pixel drive data GD1, ₁ ~GD _n, sixth bit of the _m each
DB7: pixel drive data GD1, ₁ ~GD _n, seventh bit of _m each
DB8: pixel drive data GD1, ₁ ~GD _n, eighth bit of the _m each
DB9: pixel drive data GD1, ₁ ~GD _n, 9th bit of _m each
DB 10: pixel drive data GD1, ₁ ~GD _n, 10th bit of _m each
DB 11: pixel drive data GD1, ₁ ~GD _n, 11th bit of _m each
DB 12: pixel drive data GD1, ₁ ~GD _n, 12th bit of _m each
DB 13: pixel drive data GD1, ₁ ~GD _n, the 13th bit of _m each
DB 14: pixel drive data GD1, ₁ ~GD _n, 14th bit of _m each
DB 15: obtaining pixel drive data GD1, ₁ ~GD _n, the 15th bit such pixel drive data bit groups of _m each DB1～DB15.

  Each of the pixel drive data bit groups DB1 to DB15 corresponds to each of subfields SF1 to SF15 described later. The drive control circuit 54 supplies the pixel drive data bit group DB corresponding to each subfield to the column electrode driver 55 by one display line (m) for each subfield SF1 to SF15.

  Further, the drive control circuit 54 supplies various drive control signals for driving and controlling the PDP 50 according to the light emission drive sequence as shown in FIG. 6 to the column electrode driver 55, the first row electrode driver 510, and the second row electrode driver 520, respectively. To do.

  Here, the light emission driving sequence shown in FIG. 6 causes the following driving to be performed for each of the 15 subfields SF1 to SF15 within each unit display period (one field or one frame display period) in the video signal. is there.

In FIG. 6, in the first subfield SF1, a reset process R, a selective write address process _WW, and a sustain process I are executed in order. In the subfield SF2~SF15 each run odd row selective erase addressing step W _OR, sustain process I, the even row selective erase addressing step W _ER and sustain stage I in this order.

  7 shows various drive pulses applied to the column electrode D, the row electrodes X and Y by the column electrode driver 55, the first row electrode driver 510, and the second row electrode driver 520, respectively, according to the light emission drive sequence shown in FIG. FIG. FIG. 7 shows only the operations in the first subfield SF1 and the subsequent subfields SF2 and SF3 in the subfields SF1 to SF15 shown in FIG.

First, in the reset step R of the subfield SF1, the first row electrode driver 510 generates a positive reset pulse RP having a pulse waveform whose rising change is gentle compared to a sustain pulse described later, and this is even-numbered. the row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n-3 and Y _{n- 1} Apply to each. Further, in the reset process R of the subfield SF1, the second row electrode driver 520 generates the reset pulse RP as described above, and outputs the reset pulse RP to the odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,. X _n-3 and X _n-1 , and even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n-2 and Y _n are applied.

  As described above, in the reset process R, the positive reset pulse RP having a waveform with a gradual voltage transition at the time of rising as shown in FIG. 7 is simultaneously applied to all the row electrodes X and Y of the PDP 50. In response to the application of the reset pulse RP, a weak reset discharge is generated in the row electrode Y and the column electrode D in the selected cell C2 of all the pixel cells PC. After the end of the reset discharge, a positive charge is formed on the column electrode D in the selected cell C2, and a negative charge is formed on the row electrode Y. Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. That is, by executing the reset process R, all the pixel cells PC are initialized to the extinguishing mode in which charges having the same polarity are formed on the row electrodes X and Y in the display cell C1.

Next, in the selective write address process W _W of the subfield SF1, the first row electrode driver 510, as shown in FIG. 7, and its falling transition has a peak potential V1 of positive polarity having a gentle waveform A scan base pulse BP ⁺ (scan base potential) is generated, which is generated by even-numbered row electrodes X ₂ , X ₄ ,..., X _n-2 and X _n , and odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n-3 and Y _n-1 . Further, during this time, the first row electrode driver 510 generates a scan pulse SP (scanning potential) as shown in FIG. 7 in which a predetermined positive potential is superimposed on the peak potential V1 of the scanning base pulse BP ⁺ , and the odd-numbered , Y _n−3 and Y _n−1 are sequentially applied to the row electrodes Y ₁ , Y ₃ , Y ₅ ,.

Further, in the selective write address process W _W of the sub-field SF1, a second row electrode driver 520, scan and having a its falling transition is gradual waveform has a positive peak potential V1 as shown in FIG. 7 base A pulse BP ⁺ is generated, which is divided into odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,..., X _n-3 and X _n-1 , and even-numbered row electrodes Y ₂ , Y ₄ , ..., applied to each of Y _n-2 and Y _n . Further, during this period, the second row electrode driver 520 generates the scan pulse SP as shown in FIG. 7 in which the positive potential is superimposed on the peak potential V1 of the scan base pulse BP ⁺ , and the even-numbered row electrode Y ₂ , Y ₄ ,..., Y _n−2 and Y _n are sequentially applied alternatively.

During this time, the column electrode driver 55 converts each data bit in the pixel drive data bit group DB1 corresponding to the subfield SF1 into a pixel data pulse DP having a pulse voltage corresponding to the logic level. For example, the column electrode driver 55 converts the pixel drive data bit of the logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode, into a positive high voltage pixel data pulse DP, while the pixel cell PC For the logic level 1 pixel drive data bit to be set to the lighting mode, this is converted into a low voltage (0 volt) pixel data pulse DP. Then, the pixel data pulse DP is applied to the column electrodes D _{1 to} D _m by one display line (m) in synchronization with the application timing of the scanning pulse SP. At this time, a selection is made between the column electrode D and the row electrode Y in the selection cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. Write address discharge occurs. In response to the selective write address discharge, a positive wall charge is formed on the column electrode D in the selected cell C2 of the pixel cell PC, and a negative wall charge is formed on the row electrode Y. . Further, negative wall charges are formed on the row electrodes Y in the display cells C1, and negative wall charges are also formed on the row electrodes X. On the other hand, since the pixel data pulse DP of low voltage (0 volt) is not applied to the pixel cell PC to be set in the extinguishing mode, the selective write address discharge as described above does not occur.

In the selective write address stage W _W, the row Once electrodes Y ₁ application of the scan pulse SP for to Y _n is completed, the scanning base pulse is applied to the row electrodes X and Y BP ⁺ gradually from the peak potential V1 It drops to 0 volts. Here, as shown in FIG. 7, the first row electrode driver 510 generates a wall charge adjustment pulse CP having a waveform that gradually reaches the negative peak potential −Ve from the 0 volt state, and generates this even-numbered pulse CP. the row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n-3 and Y _{n- 1} Apply to each. During this time, the second row electrode driver 520 also generates the wall charge adjustment pulse CP, which is output from the odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,..., X _n-3 and X _{n−. 1} and even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n−2 and Y _n .

That is, immediately after the application of the scan base pulse BP ^+, the wall charge adjustment pulse CP having the negative peak potential −Ve is applied to all the row electrodes X and Y. In response to the application of the wall charge adjusting pulse CP, a weak erasing discharge for reducing the amount of wall charge is generated in the selected cell C2 of each pixel cell PC. By this erasing discharge, surplus charges among the charges formed in the selected cell C2 by the selective write address discharge are erased. That is, in order to surely cause a write discharge in response to the application of a simultaneous write pulse AP, which will be described later, a part (by a predetermined amount) of wall charges remaining in the selected cell C2 at the immediately preceding stage is erased. That is, the wall charge amount is adjusted. Note that the column electrode driver 55 applies a constant positive potential as shown in FIG. 7 to all the column electrodes D during the falling period of the scan base pulse BP ⁺ and the wall charge adjustment pulse CP. Apply to.

After the application of the wall charge adjustment pulse CP, the first row electrode driver 510 generates a simultaneous write pulse AP having a negative peak potential (−Vs) as shown in FIG. the row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n-3 and Y _n- Apply simultaneously to each _one . In response to the application of the simultaneous write pulse AP, the row electrode Y and the column in the selected cell C2 of the pixel cell PC in which the selective write address discharge is generated in each of the pixel cells PC belonging to the odd-numbered display lines. Write discharge is generated between the electrodes D. Then, the write discharge expands into the display cell C1 through the gap r in the pixel cell PC, and a positive charge is formed on the row electrode Y in the display cell C1. Therefore, at this time, in the display cells C1 of the pixel cells PC belonging to the odd-numbered display lines, the row electrode X is in a negative charge and the row electrode Y is in a positive charge. That is, the pixel cell PC is set to a lighting mode in which charges having different polarities are formed on the row electrodes X and Y in the display cell C1. On the other hand, in the display cell C1 of the pixel cell PC in which the selective write address discharge has not occurred, the same polarity (negative polarity) charge is formed in each of the row electrodes X and Y. The state of is maintained.

Here, when the application of the simultaneous write pulse AP to each of the odd-numbered row electrodes Y ₁ , Y ₃ , Y ₅ ,..., Y _n−3 and Y _n−1 is finished, the second row electrode driver 520. It is to generate a simultaneous write pulse AP having a negative peak potential as shown in FIG. 7, this odd-numbered row electrodes _{X 1, X 3, X 5} , ····, X n-3 and X _n-1, and even-numbered row electrodes Y _2, Y _4, ····, is applied to each Y _n-2 and Y _n. In response to the application of the simultaneous write pulse AP, the row electrode Y and the column in the selected cell C2 of the pixel cell PC in which the selective write address discharge is generated in each of the pixel cells PC belonging to the even-numbered display line. Write discharge is generated between the electrodes D. Then, the write discharge expands into the display cell C1 through the gap r in the pixel cell PC, and a positive charge is formed on the row electrode Y in the display cell C1. Therefore, at this time, in the display cell C1 of the pixel cell PC belonging to the even-numbered display line, the row electrode X is in a negative charge and the row electrode Y is in a positive charge. That is, the pixel cell PC is set to a lighting mode in which charges having different polarities are formed on the row electrodes X and Y in the display cell C1. On the other hand, in the display cell C1 of the pixel cell PC in which the selective write address discharge has not occurred, the same polarity (negative polarity) charge is formed in each of the row electrodes X and Y. The state of is maintained.

Thus, according to the selective write address stage W _W, the reset stage pixel cells PC are initialized to off-mode in R is to transition to selectively lighting mode depending on the pixel data.

Next, in the sustain step I of the first subfield SF1, the first row electrode driver 510 generates a sustain pulse IP having a negative polarity peak potential (-Vs) as shown in FIG. the row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n-3 and Y _{n- 1} Apply to each. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the display cell C1 in the pixel cell PC in the lighting mode, and the phosphor layer 16 irradiates with the sustain discharge. The irradiated light is irradiated to the outside through the front transparent substrate 10. As shown in FIG. 7, the pulse voltage of the sustain pulse IP is the same voltage (−Vs) as the pulse voltage of the simultaneous write pulse AP.

Then, the odd row selective erase addressing step W _OR subfield SF2 (or SF3～SF15), the first row electrode driver 510, as shown in FIG. 7, the scan base pulse BP having a peak potential -V2 of negative ^- it generates, which even-numbered row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ···· , Y _n-3 and Y _n-1 . Further, during this time, the first row electrode driver 510 generates a scan pulse SP as shown in FIG. 7 in which a predetermined positive potential is superimposed on the peak potential (−V2) of the scan base pulse BP ⁻ , and the odd-numbered , Y _n−3 and Y _n−1 are sequentially applied to the row electrodes Y ₁ , Y ₃ , Y ₅ ,. During this time, the column electrode driver 55 converts each data bit in the pixel drive data bit group DB2 (or DB3 to DB15) corresponding to the subfield SF2 (or SF3 to SF15) to a pixel data pulse having a pulse voltage corresponding to the logic level. Convert to DP. For example, the column electrode driver 55 converts the pixel drive data bit of the logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode, into a positive high voltage pixel data pulse DP, while the pixel cell PC For the logic level 1 pixel drive data bit to be set to the lighting mode, this is converted into a low voltage (0 volt) pixel data pulse DP. Then, the pixel data pulses DP corresponding to the pixel cell PC belonging to the odd display lines among all the display lines, display line in synchronization with the application timing of the scanning pulse SP (m the number) per time to the column electrodes D ₁ ~ _Apply to D _m . At this time, between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. A selective erase address discharge is generated. In response to the selective erase address discharge, positive charges are formed on the column electrodes D in the selected cells C2, and negative charges are formed on the row electrodes Y. Then, the discharge expands into the display cell C1 through the gap r in the pixel cell PC, and negative charges are formed on the row electrodes Y and X in the display cell C1. Therefore, at this time, the pixel cells PC belonging to the odd-numbered display lines shift from the extinguishing mode to the lighting mode. On the other hand, in each of the pixel cells PC belonging to the odd display line, the selective erase address discharge as described above is not generated in the selected cell C2 of the pixel cell PC to which the positive pixel voltage pulse DP is applied. Therefore, the pixel cell PC to which the positive high-voltage pixel data pulse DP is applied maintains the state (lighting mode or light-off mode) up to that point.

As described above, by executing the selective erase address process _WOR , each of the pixel cells PC belonging to the odd display line is set to one of the lighting mode and the non-lighting mode according to the pixel data.

In the sustain process I are carried out immediately after completion of the selective erase address step W _OR in the subfield SF2, the second row electrode driver 520, the sustain pulse IP odd-numbered row electrodes X having a negative peak potential ₁ , X ₃ , X ₅ ,..., X _n-3 and X _n-1 , and even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n-2 and Y _n respectively Apply to. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the display cell C1 of the pixel cell PC in the lighting mode, and the phosphor layer 16 irradiates with the sustain discharge. The irradiated light is irradiated to the outside through the front transparent substrate 10.

In the even-numbered row selective erasing address process W _ER performed immediately after the end of the sustain process I, the second row electrode driver 520 has a scan base having a negative peak potential (−V2) as shown in FIG. pulse BP ^- to generate, this odd-numbered row electrodes _{X 1, X 3, X 5} , ····, X n-3, and X _n-1, and even-numbered row electrodes Y _2, Y ₄ ,..., Y _n-2 , and Y _n are applied to each. Further, during this period, the second row electrode driver 520 generates the scan pulse SP as shown in FIG. 7 in which the positive potential is superimposed on the peak potential (−V2) of the scan base pulse BP ⁻ , The row electrodes Y ₂ , Y ₄ ,..., Y _n−2 and Y _n are sequentially applied alternatively. During this time, the column electrode driver 55 converts each data bit in the pixel drive data bit group DB2 (or DB3 to DB15) corresponding to the subfield SF2 (or SF3 to SF15) to a pixel data pulse having a pulse voltage corresponding to the logic level. Convert to DP. For example, the column electrode driver 55 converts the pixel drive data bit of the logic level 0 that should cause the pixel cell PC to be set to the extinguishing mode, into a positive high voltage pixel data pulse DP, while the pixel cell PC For the logic level 1 pixel drive data bit to be set to the lighting mode, this is converted into a low voltage (0 volt) pixel data pulse DP. Then, the pixel data pulses DP corresponding to the pixel cell PC belonging to the even display lines among all the display lines, display line in synchronization with the application timing of the scanning pulse SP (m the number) per time to the column electrodes D ₁ ~ _Apply to D _m . At this time, between the column electrode D and the row electrode Y in the selected cell C2 of the pixel cell PC to which the low-voltage (0 volt) pixel data pulse DP to be set to the lighting mode is applied simultaneously with the scanning pulse SP. A selective erase address discharge is generated. In response to the selective erase address discharge, positive charges are formed on the column electrodes D in the selected cells C2, and negative charges are formed on the row electrodes Y. Then, the discharge expands into the display cell C1 through the gap r in the pixel cell PC, and negative charges are formed on the row electrodes Y and X in the display cell C1. Therefore, at this time, the pixel cells PC belonging to the even-numbered display lines transition from the extinguishing mode to the lighting mode. On the other hand, in each of the pixel cells PC belonging to the even display line, the selective erasure address discharge as described above is not generated in the selected cell C2 of the pixel cell PC to which the positive pixel voltage pulse DP is applied. Therefore, the pixel cell PC to which the positive high-voltage pixel data pulse DP is applied maintains the state (lighting mode or light-off mode) up to that point.

As described above, by executing the selective erasure address process W _ER , each of the pixel cells PC belonging to the even display line is set to one of the lighting mode and the non-lighting mode according to the pixel data.

In the sustain process I performed immediately after the selection erase address process W _{ER in} the subfield SF2, the first row electrode driver 510 generates a sustain pulse IP having a negative peak potential as shown in FIG. This even-numbered row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ····, Y n- Applied to ₃ and Y _n-1 respectively. In response to the application of the sustain pulse IP, a sustain discharge is generated between the row electrodes X and Y in the display cell C1 in the pixel cell PC in the lighting mode, and the phosphor layer 16 irradiates with the sustain discharge. The irradiated light is irradiated to the outside through the front transparent substrate 10.

In the sustain process I of each of the subfields SF3 to SF15, the second row electrode driver 520 generates a sustain pulse IP having a negative peak potential intermittently and repeatedly generates odd-numbered row electrodes X ₁ , X ₃ , X ₅ ,..., X _n-3 and X _n-1 , and even-numbered row electrodes Y ₂ , Y ₄ ,..., Y _n-2 , and Y _n . Further, in the sustain process I of each of the subfields SF3 to SF15, the first row electrode driver 510 has a timing different from the sustain pulse IP applied to the even-numbered row electrode Y and the odd-numbered row electrode X as described above. but negative sustain pulse IP even-numbered row electrodes _{X 2, X 4, ····,} X n-2, and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , · ..., applied to Y _n-3 and Y _n-1 respectively. In the sustain process I of each of the subfields SF3 to SF15, the sustain pulse IP is repeatedly applied as many times as the number corresponding to the luminance weight assigned to the subfield. Therefore, in the sustain process I of each of the subfields SF3 to SF15, a sustain discharge is repeatedly generated between the row electrodes X and Y in the display cell C1 of the pixel cell PC set in the lighting mode, and the number of the sustain discharges is determined. The corresponding brightness will be visible.

Then, the driving shown in FIGS. 6 and 7 is executed based on 16 kinds of pixel driving data GD as shown in FIG. According to such driving, as shown in FIG. 5, a write address discharge is first generated in each pixel cell PC in the first subfield SF1 except when the luminance level 0 is expressed (first gradation) ( This pixel cell PC is set to the lighting mode. Then, (indicated by black circles) subfield SF2~SF15 each selective erase address step W _OR or W _ER of one of sub-fields only in selective erase address discharge is occurring, then the pixel cell PC to off-mode Is set. In other words, each pixel cell PC is set to the lighting mode in each of the continuous subfields corresponding to the intermediate luminance to be expressed, and the light emission associated with the sustain discharge is repeated for the number of times assigned to each of these subfields. Occur (indicated by white circles). At this time, the luminance corresponding to the total number of light emission associated with the sustain discharge generated in one field is visually recognized. Therefore, according to the 16 types of light emission patterns by the 1st to 16th gradation driving as shown in FIG. 5, the intermediate for 16 gradations corresponding to the total number of sustain discharges generated in each of the subfields indicated by white circles. Luminance is expressed.

  Here, in the plasma display device shown in FIG. 1, the pixel cell PC which carries each pixel of the PDP 50 is constructed by the display cell C1 and the selection cell C2 as shown in FIGS. The sustain discharge related to the display image is generated in the display cell C1, while the reset discharge and the address discharge accompanied by the light emission not related to the display image are mainly generated in the selected cell C2. . At this time, the selected cell C2 is shielded from light as shown in FIG. 3 in order to reduce the amount of light emitted from the phosphor layer 16 through the front transparent substrate 10 due to reset discharge and address discharge and leaking outside. A conductive layer BE is provided on each bus electrode Xb and Yb. That is, part of the light emitted from the phosphor layer 16 due to the reset discharge and the address discharge is blocked by the light-shielding conductive layer BE, so that the contrast of the display image, particularly the dark contrast can be increased. Further, in the selected cell C2, a secondary electron emission material layer 30 is provided on the back substrate 13 side as shown in FIG. The secondary electron emission material layer 30 has good γ characteristics for emitting secondary electrons during discharge in which the formation surface becomes a cathode.

Therefore, in the selective write address process W _W of the first subfield SF1, and at the same time applying a scan pulse SP having a positive polarity as shown in FIG. 7 to the row electrodes Y, applying a pixel data pulse DP of 0 volt to the column electrodes D By doing so, the column electrode D is set relatively on the cathode side to generate an address discharge. As a result, the secondary electron emission material layer 30 formed in the selected cell C2 becomes the cathode side, so that secondary electrons can be effectively emitted from the secondary electron emission material layer 30 and the selection is made. The address discharge is surely generated in the cell C2.

  Further, in the drive shown in FIG. 7, in order to prevent an erroneous address discharge between the row electrode Y and the column electrode D other than the row electrode Y to which the scan pulse SP is applied, the address discharge is performed in the reset process R. Similarly, a reset discharge is caused between the row electrode and the column electrode. When a reset discharge is generated between the row electrode Y and the column electrode D, a positive wall charge is formed on the column electrode D and a negative wall charge is formed on the row electrode Y in the selected cell C2. . In such a state of wall charge formation, in order to cause an address discharge in the selected cell C2 by applying a positive scan pulse SP, it is necessary to set the scan pulse SP to a high voltage. In other words, when a positive wall charge is formed on the column electrode D and a negative wall charge is formed on the row electrode Y in the selected cell C2, a relatively high voltage is not applied between the column electrode D and the row electrode Y. As long as no discharge occurs, erroneous discharge is prevented.

However, in the selective write address process W _W of the first subfield SF1, since by rise to selective write address discharge in accordance with the scanning pulse SP having the highest voltage as shown in FIG. 7, this time, the selected cell Many wall charges are formed in C2. Therefore, after such selective write address discharge occurs, erroneous discharge occurs only by changing the potential applied on the row electrode Y from the positive potential V1 based on the scan base pulse BP ⁺ to the ground potential (0 volt). As a result, the wall charge amount is reduced.

Therefore, the head in the sub-field SF1 of the selective write address stage W _W, is the scanning base pulse BP ⁺ than was to reduce gradually the potential V1 applied to the row electrodes X and Y. As a result, it is possible to weaken the erroneous discharge that occurs in the falling period of the potential of the scan base pulse BP ⁺ , so that the reduction of the wall charge amount in the selected cell C2 is suppressed.

Further, in the driving shown in FIG. 7, after the application of the scan base pulse BP ⁺ in the selective write address stage W _W, by applying a wall charge adjusting pulse CP to all the row electrodes X and Y, a weak erase discharge It occurs in each selected cell C2. That is, by erasing only a part of the relatively large wall charges formed in response to the selective write address discharge by the erasure discharge, before the write discharge in response to the application of the simultaneous write pulse AP is generated. This prevents erroneous discharges from occurring. As a result, it is possible to reliably generate the write discharge in each selected cell C2 in accordance with the application of the simultaneous write pulse AP.

  Therefore, according to the wall charge adjustment as described above, the erroneous discharge as described above is prevented even if there is a manufacturing variation or the like, so that each pixel cell is reliably in a state corresponding to the pixel data (lighted cell state). Or a non-lighted cell state).

  Here, it is necessary to adjust the peak potential (−Ve) of the wall charge adjustment pulse CP to an appropriate value in order to surely generate the write discharge in response to the application of the simultaneous write pulse AP.

  FIG. 8A schematically shows the state of the write discharge generated in response to the simultaneous write pulse AP when the peak potential (−Ve) of the wall charge adjustment pulse CP is an appropriate potential. FIG. Thus, if the peak potential (−Ve) of the wall charge adjustment pulse CP is an appropriate potential, as shown in FIG. 8A, a discharge occurs in the peak potential section of the simultaneous write pulse AP. This is a write discharge that forms wall charges.

  However, when the peak potential (−Ve) of the wall charge adjustment pulse CP is lower than an appropriate potential, the erasure discharge caused by the wall charge adjustment pulse CP becomes weak, and a predetermined amount of wall charge can be erased. Disappear. Then, the amount of wall charges remaining in the selected cell C2 becomes excessive, and a discharge is generated at a stage immediately before the peak potential of the simultaneous write pulse AP as shown in FIG. 8B. At this time, the discharge becomes an erasing discharge for erasing the wall charges, and correct writing cannot be performed.

  On the other hand, when the peak potential (−Ve) of the wall charge adjustment pulse CP is higher than an appropriate potential, the erasure discharge generated by the wall charge adjustment pulse CP becomes strong, and the wall charge of a predetermined amount or more is erased. Will be. As a result, the amount of wall charge remaining in the selected cell C2 becomes insufficient, and even if a write discharge occurs at the timing of the peak potential of the simultaneous write pulse AP as shown in FIG. Because of the weakness, a sufficient amount of wall charges cannot be formed.

  Therefore, the peak potential (−Ve) of the wall charge adjustment pulse CP is adjusted within a range that does not reach the state as shown in FIGS. 8B and 8C. In adjusting the peak potential (−Ve) of the wall charge adjustment pulse CP so as to fall within this range, the wall charge is applied to the first row power driver 510 and the second row electrode driver 520 shown in FIG. The peak potential of each of the adjustment pulse CP and the simultaneous writing pulse AP can be adjusted in conjunction with each other.

  FIG. 9 is a diagram illustrating only a pulse generation unit that generates the wall charge adjustment pulse CP and the simultaneous write pulse AP from each of the first row power driver 510 and the second row electrode driver 520. FIG.

In FIG. 9, the voltage adjustment circuit 511 adjusts the power supply potential V _DD to the potential V _CC corresponding to the adjustment signal and supplies it to the wall charge adjustment pulse generation circuit 512 and the simultaneous write pulse generation circuit 513, respectively. The wall charge adjustment pulse generation circuit 512 generates a wall charge adjustment pulse CP having a negative polarity peak potential (−Ve) as shown in FIG. 7 based on the potential V _CC and is supplied from the drive control circuit 54. depending on the drive control signal, the even-numbered row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ··· Apply to Y _n-3 and Y _n-1 respectively. The simultaneous write pulse generation circuit 513 generates a simultaneous write pulse AP having a negative peak potential (−Vs) as shown in FIG. 7 based on the potential V _CC , and this is supplied from the drive control circuit 54. depending on the drive control signal, the even-numbered row electrodes _{X 2, X 4, ····,} X n-2 and X _n, and the odd-numbered row electrodes _{Y 1, Y 3, Y 5} , ··· Apply simultaneously to each of Y _n-3 and Y _n-1 . The voltage adjustment circuit 521 adjusts the power supply potential V _DD to the potential V _CC corresponding to the adjustment signal and supplies it to the wall charge adjustment pulse generation circuit 522 and the simultaneous write pulse generation circuit 523, respectively. The wall charge adjustment pulse generation circuit 522 generates a wall charge adjustment pulse CP having a negative peak potential (−Ve) as shown in FIG. 7 based on the potential V _CC and is supplied from the drive control circuit 54. depending on the drive control signal, the odd-numbered row electrodes _{X 1, X 3, X 5} , ····, X n-3 and X _n-1, and even-numbered row electrodes Y _2, Y _4, · ..., applied to each of Y _n-2 and Y _n . The simultaneous write pulse generation circuit 523 generates a simultaneous write pulse AP having a negative peak potential (−Vs) as shown in FIG. 7 based on the potential V _CC , and this is supplied from the drive control circuit 54. depending on the drive control signal, the odd-numbered row electrodes _{X 1, X 3, X 5} , ····, X n-3 and X _n-1, and even-numbered row electrodes Y _2, Y _4, · ..., applied to each of Y _n-2 and Y _n .

That is, when adjustment is performed to increase the peak potential of the wall charge adjustment pulse CP by the adjustment signal, the potential V _CC supplied to each of the wall charge adjustment pulse generation circuit 512 (522) and the simultaneous write pulse generation circuit 513 (523). And the peak potentials of the wall charge adjustment pulse CP and the simultaneous writing pulse AP are increased in conjunction with each other. On the other hand, when adjustment is performed to reduce the peak potential of the wall charge adjustment pulse CP, the potential V _CC supplied to each of the wall charge adjustment pulse generation circuit 512 (522) and the simultaneous write pulse generation circuit 513 (523) is low. Therefore, the peak potentials of the wall charge adjusting pulse CP and the simultaneous writing pulse AP are lowered in conjunction with each other.

  At this time, when the peak potential (−Ve) of the wall charge adjustment pulse CP is set relatively high within the range that does not reach the state as shown in FIG. 8B and FIG. When the amplitude is small, the erase discharge generated in response to the application of the wall charge adjustment pulse CP becomes relatively weak, and the amount of wall charges to be erased is also reduced. Therefore, the amount of wall charges remaining in the selected cell C2 is also relatively large. At this time, even if the peak potential (−Vs) of the simultaneous writing pulse AP is high, that is, the amplitude of the simultaneous writing pulse AP is small. Even in such a case, it is possible to surely cause the write discharge.

  Therefore, the voltage adjustment circuit 511 (522) shown in FIG. 9 can adjust the wall voltage adjustment pulse CP and the pulse voltage of the simultaneous writing pulse AP in conjunction with each other, thereby adjusting the wall charge adjustment pulse CP. If the pulse voltage is set to the optimum value, the pulse voltage of the simultaneous write pulse AP is automatically set to the optimum value.

It is a figure which shows the structure of the plasma display apparatus as a display apparatus by this invention. It is the top view which looked at a part of structure of the display electrode formation part DPE in PDP50 shown by FIG. 1 from the display surface side. It is a figure which shows the cross section on the VV line | wire shown by FIG. It is a figure which shows the cross section on the WW line shown by FIG. It is a figure which shows the light emission drive pattern based on the conversion table of pixel data, and the pixel drive data GD obtained by this pixel data conversion table. It is a figure which shows an example of the light emission drive sequence in the plasma display apparatus shown by FIG. It is a figure which shows the various drive pulses applied to PDP50 according to the light emission drive sequence shown in FIG. 6, and its application timing. It is a figure which represents typically the write discharge generated according to the application of simultaneous write pulse AP. FIG. 5 is a diagram illustrating only a pulse generation unit that generates a wall charge adjustment pulse CP and a simultaneous writing pulse AP from each of a first row power driver 510 and a second row electrode driver 520. FIG.

Explanation of symbols

50 PDP
54 Drive control circuit 55 Address driver
510 1st row electrode driver
511,521 Voltage adjustment circuit
512,522 Wall charge control pulse generator
513,523 Simultaneous write pulse generator
520 Second row electrode driver C1 Display cell C2 Selected cell
DPE display electrode formation part PC pixel cell

Claims (17)

An address period for setting each of the pixels to one of a lighting mode and a non-lighting mode according to pixel data for each pixel based on an input video signal, and a sustaining period for causing the pixels in the lighting mode to emit light A display device that displays an image by a plurality of subfields including:
A front substrate and a rear substrate facing each other with a discharge space interposed therebetween, a plurality of row electrode pairs constituting display lines on the inner surface of the front substrate, a dielectric layer covering the row electrode pairs, and an inner surface of the rear substrate on the inner surface A second discharge cell having a plurality of column electrodes arranged to intersect with the row electrode pair, wherein a first discharge cell and a light shielding layer are provided at each intersection of the row electrode pair and the column electrode A display panel in which a pixel cell comprising:
In the address period of the first subfield of one field display period, a positive scan base potential is applied to one row electrode of all the row electrode pairs, and a predetermined positive potential is applied to the one row electrode. Addressing means for generating a write address discharge that should form a wall charge in the second discharge cell by applying a potential corresponding to the pixel data to the column electrode while sequentially superimposing each on the column electrode;
A wall formed in the second discharge cell by applying a negative wall charge adjustment pulse whose front edge has a gradual potential transition section to each of the one row electrode after the end of the write address discharge. And a wall charge adjusting means for generating an erasing discharge for erasing a part of the electric charge.   Simultaneous writing means for generating a writing discharge for forming a wall charge in the second discharge cell by applying a negative simultaneous writing pulse to each of the one row electrodes immediately after the application of the wall charge adjusting pulse. The display device according to claim 1, further comprising:   3. The display device according to claim 2, further comprising adjusting means for adjusting the pulse voltage of each of the simultaneous writing pulse and the wall charge adjusting pulse in conjunction with each other.   2. The display device according to claim 1, further comprising sustain means for applying a negative sustain pulse to each of one row electrode and the other row electrode in the row electrode pair in the sustain period.   The apparatus further comprises reset means for generating a reset discharge in the same discharge current direction as the address discharge in the second discharge cell immediately before the address period of at least the first subfield of the display period of the one field. The display device according to claim 1.   The reset means generates a reset discharge in the second discharge cell by applying a reset pulse between the one row electrode and the column electrode so that the column electrode is relatively negative. The display device according to claim 1.   The addressing means applies the scanning potential to the one row electrode so that the column electrode is relatively negative in the address period of the first subfield of the display period of the one field, while applying the scanning potential to the column electrode. The display device according to claim 1, wherein a potential corresponding to pixel data is applied.   The address means sequentially applies a scanning potential obtained by superimposing a predetermined positive potential on a positive scanning base potential to each of the one row electrodes in the address period of the first subfield of the display period of the one field. The display device according to claim 1.   The display device according to claim 1, wherein the light shielding layer is formed on a front substrate side in the second discharge cell.   The display device according to claim 1, wherein a secondary electron emission layer is formed on a back substrate side in the second discharge cell.   2. The display device according to claim 1, wherein a phosphor layer is formed only in the first discharge cell of the first discharge cell and the second discharge cell.   The first discharge cell includes a portion where one row electrode and the other row electrode of the row electrode pair face each other with a first discharge gap in a discharge space, and the second discharge cell includes the column electrode The display device according to claim 1, further comprising a portion where the first row electrode and the one row electrode are opposed to each other with a second discharge gap in the discharge space. One row electrode and the other row electrode in the row electrode pair each have a main body portion extending in the row direction and a protrusion portion protruding in the column direction from the main body portion via the first discharge gap for each pixel cell. Prepared,
The first discharge cell includes a portion where the protruding portion is opposed to the first discharge gap in the discharge space,
2. The display device according to claim 1, wherein the second discharge cell includes a portion where the column electrode and the main body portion of the one row electrode are opposed to each other through a second discharge gap in the discharge space. The display panel includes a partition wall including a vertical wall section that divides a discharge space of the adjacent pixel cell in a row direction and a horizontal wall section that divides the discharge space in a column direction, and a discharge space of the first discharge cell in the pixel cell. A partition wall that partitions the discharge space of the second discharge cell,
The discharge space of the second discharge cell is closed by the discharge space of the adjacent pixel cell and the partition, and the discharge space of the first discharge cell and the discharge space of the second discharge cell in the pixel cell The display device according to claim 1, wherein the display devices communicate with each other.   The display device according to claim 1, wherein discharge spaces of the first discharge cells of the pixel cells adjacent in the row direction communicate with each other. A first discharge cell and a second discharge cell provided with a light shielding layer at each intersection of a plurality of row electrode pairs constituting a display line and a plurality of column electrodes arranged to cross the row electrode pair An address period in which each of the pixels is set to one of a lighting mode and a non-lighting mode in accordance with pixel data for each pixel based on an input video signal. A driving method of a display panel that is driven by a plurality of subfields including a sustain period in which the pixel in a lighting mode state emits light,
Write address for setting the pixel cell to the lighting mode by causing a write address discharge in the second discharge cell in accordance with the pixel data in the address period of the first subfield of one field display period The process,
An erase address process for setting the pixel cell to the extinguishing mode by causing an erase address discharge in the second discharge cell in accordance with the pixel data in the address period of each subfield subsequent to the first subfield. And comprising
In the write address process, while applying a positive scanning base potential to one row electrode of all the row electrode pairs, a positive potential is sequentially superimposed on each of the one row electrode, and applied. The write address discharge is generated in the second discharge cell by applying a potential according to the pixel data to the column electrode, and a front edge portion is formed on each of the one row electrode after the end of the write address discharge. An erasing discharge for erasing a part of the wall charge formed in the second discharge cell is generated by applying a negative wall charge adjustment pulse having a gradual potential transition section. Panel drive method.   The write address process includes a write discharge for forming a wall charge in the second discharge cell by applying a negative simultaneous write pulse to each of the one row electrode immediately after the application of the wall charge adjustment pulse. The display panel driving method according to claim 16, wherein the display panel is caused to occur.

Images