JP2006156658A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is capable of reducing the ON-state resistance, while keeping its substrate high in strength. <P>SOLUTION: The semiconductor device is equipped with a support 21, which has two or more recesses formed through reticulate projections provided on its rear side and is formed of semiconductor having first impurity concentration, a semiconductor layer 3 which is formed on the surface of the support 21 opposite to its rear side and has a second impurity concentration lower than the first impurity concentration, and a semiconductor element formed on the semiconductor layer 3. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device that can reduce substrate resistance structurally and realize low on-resistance.

  As a semiconductor device, a vertical semiconductor device in which a current path in an element flows from a first main surface to a second main surface of the element is known. The performance of this type of semiconductor device is mainly determined by the element structure formed in the epitaxial layer formed on the substrate surface, and the substrate holds the epitaxial layer and plays the role of maintaining the strength.

  The resistance of the current path of the vertical semiconductor device is roughly divided into the contact resistance between the epitaxial surface and the electrode, the epitaxial layer resistance, the substrate resistance, and the series resistance that combines the contact resistance between the substrate surface and the electrode. The resistance of the substrate for imparting strength is very large, and in order to reduce the overall resistance, the substrate resistance must be lowered.

  In the vertical semiconductor device of silicon, in order to reduce the substrate resistance as much as possible, after forming the element structure on the surface of the epitaxial layer, the substrate is ground to about several tens to 100 μm to reduce the contact resistance with the back electrode. After ion implantation on the back surface, the ions implanted by laser annealing are activated to lower the contact resistance.

  Here, the reason why the element structure is formed on the surface of the epitaxial layer before grinding the back surface of the substrate is that after the substrate is ground to about several tens to 100 μm, the element structure forming process (thermal process, metal film formation, oxide film) This is because the substrate is cracked due to differences in strain and thermal expansion coefficient.

  When the same technique is applied to an element using a silicon carbide (SiC) substrate, the activation annealing temperature of SiC is about 1600 ° C., so that the oxide film, electrode, etc. formed on the surface are damaged. was there.

  Further, even when a means for heating only the uppermost surface of the substrate, such as laser annealing or pulse annealing, is used, the thermal conductivity coefficient of SiC is 4.9 W / cmK, which is similar to copper (Cu), and the opposite surface (annealing) When the surface was the back surface, thermal damage to the “front surface”) was an inevitable problem. Also, in SiC, there is a problem that if the substrate back surface grinding is performed before the element structure is formed on the surface of the epitaxial layer, the substrate is cracked.

  In order to solve the above problem, in Patent Document 1, in a semiconductor device in which a vertical MOSFET and a bipolar transistor are mixed on a silicon substrate, a recess is provided on the back surface of the semiconductor substrate in the vertical MOSFET forming portion, and the bottom surface of the recess is formed. A drain electrode is provided to lower the on-resistance. In this example, since the concave portion is provided locally on the mixed substrate of the vertical MOSFET and the bipolar transistor, it seems that the strength of the entire substrate is ensured, but the substrate strength is lowered when forming the semiconductor device of the vertical MOSFET alone. There was a fear.

Further, in Patent Document 2, in a vertical MOSFET using a silicon carbide substrate, a concave portion is provided on the back surface of the substrate below the element forming portion, and a drain electrode is formed on the bottom surface of the concave portion to reduce the on-resistance. In this example, in the semiconductor device having a single vertical MOSFET, the substrate is provided with a recess, but the substrate strength is ensured by providing a recess having a depth of about 200 μm with respect to the thickness of the substrate of 400 μm. If the depth of the recess is further increased in order to sufficiently reduce the on-resistance, a problem that the strength of the substrate is lowered is expected.
JP-A-9-102604 JP 2003-303966 A

  The present invention has been made in view of the above circumstances, and provides a configuration of a semiconductor device capable of reducing the resistance of an electrode lead portion while ensuring the substrate strength even when a substrate having a high substrate resistance is used. Objective.

  In order to solve the above-described problems, a semiconductor device according to the present invention includes a support made of a semiconductor having a plurality of recesses formed on a back surface and having a first impurity concentration, and the support. And a semiconductor layer having a second impurity concentration lower than the first impurity concentration, and a semiconductor element formed in the semiconductor layer.

  In the present invention, a plurality of concave portions formed by mesh-like convex portions are provided on the back surface of the substrate and processed into a continuous waffle shape, and at least a part of the back surface electrode is formed in the waffle concave portion. Since the wall surfaces of the mesh-shaped convex portions are connected to each other, even if an oxide film or a metal film is formed on the surface of the substrate (epitaxial layer) through a thermal process, the warpage of the substrate can be greatly suppressed. . At the same time, the waffle recess can be made thinner or zero in thickness up to the epitaxial layer than the inter-waffle protrusion, so that the substrate resistance can be greatly reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
1 is a schematic cross-sectional view of a semiconductor device (Schottky barrier diode) according to a first embodiment of the present invention, FIG. 2 is a bottom view thereof, and a cross-sectional view along the line AA in FIG. Corresponds to FIG. That is, a continuous waffle substrate having a plurality of (in this case, four) concave portions (waffle portions) on the back surface is used. Note that the top view is omitted because only a rectangular electrode is formed at the center of the rectangular substrate.

  More specifically, as shown in FIG. 1, a SiC epitaxial layer (low concentration layer) 3 is formed by homoepitaxial growth on a support 21 made of bulk SiC. In this SiC epitaxial layer 3, a Schottky barrier diode (SBD) element structure is formed. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a plane portion of the SiC support 21 having a plurality of recesses, and the substrate 1 composed of the bulk SiC support and the epitaxial layer 3 is formed in a continuous waffle shape as a whole. A surface electrode 19 that makes a Schottky contact with the epitaxial layer 3 is formed on the upper surface of the epitaxial layer 3, and a back electrode 17 is formed on the rear surface via an ohmic contact layer 13. In this embodiment, the ohmic contact layer 13 is n-type, and a Schottky barrier diode is formed between the front surface electrode 19 and the back surface electrode 17.

  On the upper surface of the epitaxial layer 3, a resurf region 12 and a guard ring 14, which are termination structures, are formed so as to surround a contact portion with the surface electrode 19, and each of them is formed in a p-type in this embodiment. The upper surface of the epitaxial layer 3 is covered with the Si oxide layer 15, the surface electrode 19 formation region is selectively opened, and the surface electrode (first electrode) 19 is formed here. On the back surface of the epitaxial layer 3, a back electrode (second electrode) 17 is formed on the ohmic contact layer 13. The back surface electrode 17 is also formed on the bottom surface of the leg portion of the SiC support 21.

  The Schottky barrier diode of the first embodiment is given strength by a bulk SiC support 21 having a U-shaped projection on the back surface, and the diode element formed in the epitaxial layer 3 is connected to the back electrode. Since the distance is short, low on-resistance is realized.

Next, a method for manufacturing the semiconductor device according to the first embodiment will be described. First, as shown in FIG. 3, a substrate obtained by growing 10 μm of an epitaxial layer 3 having an n-type impurity concentration of 3.5 × 10 ¹⁵ cm ⁻³ on an SiC substrate 2 (n-type) having a substrate resistance of 0.02 Ωcm (hereinafter referred to as “the substrate”). (Referred to as substrate 1). The substrate 1 is removed of organic stains adhering to the substrate 1 with a mixed acid of sulfuric acid and hydrogen peroxide solution, and rinsed with pure water. Next, metal impurities adhering to the substrate 1 are removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the natural oxide film on the surface of the substrate 1 is removed with dilute hydrofluoric acid and rinsed with pure water.

  The substrate 1 is heated in an oxygen atmosphere at 1100 ° C. for 2 hours to oxidize the surface of the substrate 1 to form a sacrificial oxide film 5. After a Ti film 7 having a thickness of 50 nm is formed on the back surface of the substrate 1, an Al film 9 having a thickness of 2 μm is formed. Here, the Ti film 7 serves as an adhesion layer for bringing the SiC substrate 2 and the Al film 9 into close contact, and the Al film 9 serves as an etching mask for later SiC etching.

  As shown in FIG. 4, a resist 11 having a thickness of about 2 μm is spin-coated on the surface of the Al film 9, and a pattern for forming a waffle recess is formed by exposure and development, followed by hard baking at a high temperature. 11 is baked and hardened. The substrate 1 on which the resist 11 is patterned is introduced into an RIE chamber using a chlorine-based gas, and the Al film 9 and the Ti film 7 are dry-etched using the patterned resist 11 as an etching mask as shown in FIG.

Next, the SiC substrate 2 is dry-etched with a mixed gas of CF ₄ and O _{2 using} the patterned Al film 9 as an etching mask. By repeating this process, the resist opening becomes a waffle-shaped recess, and the SiC substrate 2 is entirely etched, and the epitaxial layer 3 appears on the back surface as shown in FIG.

  The Al film 9 can be formed by electron gun vapor deposition, sputtering, hot dipping, or the like, and hot dipping can obtain thicker Al than vacuum evaporation such as electron gun vapor deposition or sputtering. it can. In the case of hot dip plating, iron or the like is formed on the back surface of the SiC substrate protected by the sacrificial oxide film, and the hot dip plating film of aluminum is obtained on the back surface of the SiC substrate by immersing the substrate in a molten aluminum bath. In this step, an oxide film by chemical vapor deposition is further formed on the sacrificial oxide film by thermal oxidation to about 1 μm, and oxide film sintering is performed at 1000 ° C. for 30 minutes in an Ar atmosphere to increase the density of the deposited oxide film. And the function as a protective film can be improved.

  The substrate 1 is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution, the resist and metal adhering to the substrate 1 are removed, rinsed with pure water, and the Al layer 9 formed on the back surface of the SiC support 21. The Ti layer 7 is also removed and rinsed with pure water.

Next, multistage implantation of P (phosphorus) ions is performed on the back surface of the substrate 1 with a total dose of 7 × 10 ¹⁵ cm ⁻² and a maximum acceleration energy of 200 keV, and an ohmic contact region 13 for the back electrode is formed as shown in FIG. Form.

Next, a mask layer for ion implantation (not shown) is formed on the upper surface of the epitaxial layer 3 via the sacrificial oxide film 5, and a resist film (not shown) is formed thereon, so that a RESURF region serving as a termination structure is formed. The guard ring region is patterned. Based on this resist pattern, the ion implantation mask layer is patterned. Using this ion implantation mask, aluminum ions are subjected to multi-stage implantation with a total dose of 1.5 × 10 ¹³ cm ⁻² and a maximum acceleration energy of 300 keV to form a resurf region 12 and a guard ring 14 as shown in FIG. To do.

  The substrate 1 is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution to remove the resist and metal adhering to the substrate 1 and then rinsed with pure water. Next, a trace amount of metal impurities adhering to the substrate is removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the sacrificial oxide film 5 on the surface of the substrate 1 is removed with dilute hydrofluoric acid and rinsed with pure water.

The cleaned substrate 1 is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 ⁻⁴ Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. An annealing process is performed to obtain the structure shown in FIG.

Next, after thermally oxidizing the surface of the substrate 1 again, as shown in FIG. 10, a 1 μm Si oxide film (SiO ₂ ) film 15 is formed on the surface of the substrate 1 by CVD, and an Si oxide film is formed at 1000 ° C. in an Ar atmosphere. Sinter. Further, as shown in FIG. 11, a Ni film to be the back electrode 17 is formed on the back surface of the substrate 1 by electron gun vapor deposition, and sintering is performed in an Ar atmosphere at 1000 ° C. for 1 minute, so that the ohmic contact region 13 and the back electrode 17 is in ohmic contact.

Next, after protecting the back surface of the substrate 1 with a resist, a resist (not shown) is applied to the surface of the Si oxide film 15 on the surface of the substrate, and an opening is formed on the surface electrode formation region by patterning. Next, the Si oxide film 15 is etched by RIE of CF ₄ and O ₂ , the natural oxide film on the outermost surface of the substrate is removed by dilute hydrofluoric acid, a Ti film to be the surface electrode 19 is formed, and unnecessary portions are resisted. It is removed by patterning and RIE. Through this process, a SiC Schottky barrier diode (SBD) is formed in which the back surface of the substrate is processed into a continuous waffle shape as shown in FIG.

The on-resistance of the SBD element of this embodiment was 1.2 Ωcm ² and the withstand voltage was 1000V. When the back substrate is a normal substrate that is not waffle-shaped, the withstand voltage is similarly 1000 V, but the on-resistance is ² mΩcm ^2. Compared with this, the on-resistance of the element processed into a waffle is reduced by 40%. I understood.

  Furthermore, as shown in FIG. 12, if one element has one waffle concave portion (that is, only the waffle convex portion 21 is formed along the dicing line 23), the convex portion is formed during dicing. There is a risk that the part 21 is missing and the entire device is broken. Thus, as in this embodiment, if two or more waffle recesses are provided for one element as shown in FIG. 13, the element can be prevented from being destroyed. In the present embodiment, the convex portion on the back surface of the substrate has a square shape, but the present invention is not limited to this, and the shape of the convex portion on the back surface is such as “day letter”, “field letter”, “enclosed letter”. It is further preferable to form a large number of waffle projections 21 inside the dicing line 23 and reinforce them. FIG. 14 shows a schematic perspective view when a large number of waffle convex portions 21 are formed. Moreover, as shown in FIG. 13, the relationship between the element area (A) defined by the area inside the dicing line and the total of the concave area of the waffle (B) is as follows. A). These items are also applied to the second and subsequent embodiments. In addition, although the shape of the convex part 21 was made into the taper shape in FIG. 12, 13, this is demonstrated in 2nd Embodiment.

  Further, in this embodiment, the waffle concave portion is formed by removing all of the SiC substrate 2 by etching, but a part of the SiC substrate 2 may remain as shown in FIG. FIG. 15A is a modification of the first embodiment, and FIG. 15B is a modification in the case where a taper is provided in the concave portion of the SiC support 21 in the second embodiment described later. 1 is basically the same as that of FIG. 1 except that the contact layer 13 on the bottom surface of the recess is provided on the SiC substrate 2. In this case, the remaining amount of the substrate and the substrate resistance are in a linear relationship, and as the remaining amount increases, the substrate resistance increases, but there is an advantage that the substrate strength increases accordingly. Depending on the design of the element and the required performance, the user can consider the remaining amount of the recess. This is also applied to the second to sixth embodiments.

In the first embodiment, aluminum is used as an example of a mask material for SiC etching. However, it is sufficient that there is a sufficient difference in etching rate with SiC, and it does not depend on the material and the film forming method. Other than aluminum, for example, Ni or Cu is formed by electroless plating on the back side of a SiC substrate patterned with a thick film resist, and waffles are formed by lifting off the resist portion and Ni (Cu) thereon using acetone. An etching mask to be formed may be formed, and RIE may be performed with an etching gas such as CF ₄ .

(Second Embodiment)
FIG. 16 is a cross-sectional view of a Schottky barrier diode (SBD) according to the second embodiment of the present invention. The second embodiment is different from the first embodiment in that the side surface of the concave portion of the SiC support 21 is formed with a taper. By forming in this way, the strength of the SiC support 21 can be increased and the back contact area can be increased.

Next, a method for manufacturing the SBD of the second embodiment will be described. The same parts as those in the first embodiment are denoted by the same reference numerals, and redundant description is omitted. First, the steps from FIG. 3 to FIG. 5 of the first embodiment are performed under the same conditions. Next, as shown in FIG. 17, the SiC substrate 2 is dry-etched with a mixed gas of CF ₄ and O _{2 using} the patterned Al film 9 as an etching mask. By this process, a portion opened by resist patterning becomes a waffle-shaped recess, and the SiC substrate 2 is entirely etched, and an epitaxial layer appears on the surface. In the present embodiment, the tapered waffle recess is formed. However, when the gas pressure of the etchant gas is increased, the tapered shape can be formed in the waffle recess by utilizing the property that the etching amount in the lateral direction increases. The substrate 1 is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution, the resist and metal adhering to the substrate 1 are removed, rinsed with pure water, and the Al layer 9 formed on the back surface of the SiC support 21. The Ti layer 7 is also removed and rinsed with pure water.

Next, as shown in FIG. 18, multistage implantation of P (phosphorus) ions is performed on the back surface of the substrate 1 with a total dose of 7 × 10 ¹⁵ cm ⁻² and a maximum acceleration energy of 200 keV, and the ohmic contact layer 13 of the back electrode is formed. Form. At this time, since the waffle recess has a tapered shape, the ohmic contact layer 13 is also formed on the side wall of the waffle, and the ohmic contact layer 13 is continuously formed to the bottom of the substrate (back surface). It will be.

  Next, as in the first embodiment, the RESURF region 12 and the guard ring 14 are formed on the upper surface of the epitaxial layer 3 as shown in FIG. Next, the substrate 1 is subjected to the same surface treatment / cleaning process as in the first embodiment, and the substrate 1 that has been cleaned is subjected to activation annealing in an induction heating type activation annealing furnace, and the structure shown in FIG. Get the body.

Next, as shown in FIG. 21, an Si oxide film (SiO ₂ ) film 15 is again formed on the surface of the substrate 1, and this Si oxide film is sintered. Further, as shown in FIG. 22, a Ni film to be the back electrode 17 is formed on the back surface of the substrate 1 by electron gun vapor deposition, and the ohmic contact region 13 and the back electrode 17 are brought into ohmic contact by sintering. At this time, since the waffle recess has a tapered shape, the Ni film in contact with the back ohmic contact layer 13 is also formed on the side wall of the waffle, and the back electrode 17 continues to the bottom of the substrate (back surface top surface). The film is formed. By adopting this shape, connection to the back electrode 17 can be performed at the bottom of the substrate.

  Next, after protecting the back surface with a resist, the surface of the Si oxide film 15 on the front surface is selectively opened, the natural oxide film on the outermost surface of the substrate is removed, Ti that is a Schottky electrode is formed, and unnecessary portions are patterned. And removed by RIE. By this process, a SiC Schottky barrier diode in which the back surface of the substrate is processed into a continuous waffle shape as shown in FIG. 16 is formed.

The on-resistance of this element was 1.2 mΩcm ² and the withstand voltage was 1000V. For reference, in the case of a normal substrate where the back substrate is not waffle, the withstand voltage is similarly 1000 V, but the on-resistance is ² mΩcm ^2. On the other hand, the on-resistance of the element processed into a waffle is reduced by 40%. I found out.

(Third embodiment)
FIG. 23 is a cross-sectional view of the electrostatic induction transistor (SIT) according to the third embodiment of the present invention, and is a cross-sectional view taken along line BB of the top view shown in FIG. Note that the bottom view is the same as FIG. Further, the present embodiment can be applied almost directly to a junction field effect transistor (JFET).

  More specifically, in FIG. 23, a plurality of SIT or JFET unit elements are formed in parallel on a SiC epitaxial layer (low concentration layer) 3 formed on a support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and a plurality of waffles are continuously formed on the substrate 1 composed of the bulk SiC support 21 and the epitaxial layer 3. A source region 25 and a gate region 27 are formed on the upper surface of the epitaxial layer 3, and a back electrode 17 serving as a drain electrode is formed on the back surface via an ohmic contact layer 13. In the present embodiment, the source region 25 is n-type and the gate region 27 is p-type.

  On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the gate region 27, and in this embodiment, each is formed of a p-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and a source electrode 19 s and a gate electrode 19 g as surface electrodes are provided in openings selectively formed in the Si oxide film 15, respectively. A back electrode (drain electrode) 17 is formed on the ohmic contact layer 13 on the back surface of the epitaxial layer 3. The back electrode 17 is also formed on the inner side inclined portion and the bottom surface of the SiC support 21.

  In the SIT or JFET of the third embodiment, the strength is given by the bulk SiC support 21, the active region is formed in the epitaxial layer 3, and the distance from the back electrode 17 is short, so low on-resistance is realized. Has been.

Next, a method for manufacturing the SIT (JFET) of the third embodiment will be described. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The process up to the process of FIG. 19 of the second embodiment is similarly performed. Next, as shown in FIG. 25, in order to form the source region 25 on the surface by ion implantation, an ion implantation mask (not shown) is formed and ion implantation is performed. The source region 25 is given a box profile by multistage implantation of P (phosphorus) with a total dose of 7 × 10 ¹⁵ cm ⁻² and a maximum acceleration energy of 200 keV. Similarly, Al ions are implanted into the gate region 27, but ions are implanted with higher energy than the source region to form a gate region deeper than the source region. Here, an oxide film is used as an ion implantation mask, and this oxide film is etched by RIE.

  After the ion implantation of the termination regions 12 and 14 on the surface, the source region 25, and the gate region 27 is completed, as shown in FIG. 26, the Al film 9 and the Ti film 7 on the back surface of the SiC support 21 are removed, After removing the ion implantation mask attached to the substrate surface with a mixed acid of hydrogen oxide water, the sacrificial oxide film 5 and the like on the substrate surface are removed with diluted hydrofluoric acid and washed with water.

The substrate after cleaning is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 ⁻⁴ Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. Annealing is performed.

  After the substrate surface is thermally oxidized again, as shown in FIG. 27, a 1 μm Si oxide film 15 is formed on the substrate surface by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere.

  The Si oxide film 15 corresponding to the source contact portion and the gate contact portion on the surface of the substrate is removed by etching as shown in FIG. 28, and a Ni film is selectively formed on the source contact portion by electron gun evaporation to form a source electrode. 19s is formed, and a Ni film is formed on the gate contact portion to form a gate electrode 19g. Further, a Ni film is formed on the back surface by electron gun vapor deposition to form a back electrode (drain electrode) 17, and sintering is performed at 1000 ° C. for 1 minute in an Ar atmosphere. The source electrode 19s, the gate electrode 19g, and the back electrode 17 Are brought into ohmic contact with the respective contact regions. By this process, an SIT (or JFET) of SiC in which the back surface of the substrate is processed into a continuous waffle shape as shown in FIG. 23 is formed. Here, Ni is formed on the source electrode, the gate electrode, and the drain electrode. However, when Al is used for the gate electrode, the gate contact resistance is further lowered and the switching speed is improved.

The on-resistance of this element was 5 mΩcm ² and the withstand voltage was 1000V. For reference, in the case of a normal substrate in which the back substrate is not waffle, the withstand voltage is similarly 1000 V, but the on-resistance is 5.8 mΩcm ² , and the on-resistance of the element processed into the waffle is 0.8 mΩcm ^2. It can be seen that there is a reduction.

(Fourth embodiment)
FIG. 29 is a cross-sectional view of the MOSFET according to the fourth embodiment of the present invention, and is a cross-sectional view taken along line CC in the top view shown in FIG. Since the bottom view is the same as FIG. 2 of the first embodiment except for the tapered portion, it is omitted.

  In the MOSFET of this embodiment, a plurality of unit elements of the MOSFET are formed in parallel on a SiC epitaxial layer (low concentration layer) 3 formed on a support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and a plurality of waffles are continuously formed on the substrate 1 composed of the bulk SiC support 21 and the epitaxial layer 3. . An n-type source region 25 formed in a p-type well 29 and a gate electrode 19g formed through a gate insulating film 31 are formed on the upper surface of the epitaxial layer 3, and an ohmic contact layer 13 is formed on the rear surface. A back electrode 17 serving as a drain electrode is formed therebetween.

  On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the p-type well 29, and in this embodiment, each is formed of p-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and the source electrode 19s and gate electrode 19g forming regions which are surface electrodes are selectively opened, and the respective electrodes are formed therein. On the back surface of the epitaxial layer 3, a back electrode (drain electrode) 17 is formed on the ohmic contact layer 13. The back electrode 17 is also formed on the inner side surface and the bottom surface of the SiC support 21.

  In the MOSFET of the fourth embodiment, the strength is given by the bulk SiC support 21, the active region is formed in the low-resistance epitaxial layer 3, and the distance from the back electrode 17 is short, so that the low on-resistance is low. It has been realized.

  Next, a method for manufacturing the MOSFET of the fourth embodiment will be described. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The process up to the process of FIG. 19 of the second embodiment is similarly performed.

  Next, in order to form the p-type well region 29 on the surface by ion implantation, an ion implantation mask (not shown) is formed, and a resist is applied to the surface and patterned. The ion implantation mask is etched using the resist to which this pattern is transferred as an etching mask for the ion implantation mask. Next, as shown in FIG. 31, Al ions are implanted to make the well region 29 have p-type conductivity.

  Further, in order to form the p-type contact region 30 on the surface by ion implantation, an ion implantation mask is formed, and a resist is applied to the surface and patterned. Using the resist to which this pattern is transferred as an etching mask for the ion implantation mask, an ion implantation mask is formed by etching. This contact region 30 is formed at a higher concentration than the well region by implanting Al ions to provide p-type conductivity.

Similarly, P (phosphorus) ions are implanted into the source region 25. The source region 25 is formed in a region shallower than the p-type well region 29. Here, an oxide film is used as an ion implantation mask, and RIE using a mixed gas of CF ₄ and O ₂ is used to etch the oxide film.

  After ion implantation of the surface termination region, p-type well region 29, and source region 25 is completed, the Al film 9 and Ti film 7 formed on the back surface of the SiC support 21 are removed, and sulfuric acid and hydrogen peroxide solution are removed. After removing the ion implantation mask (Mo) adhering to the substrate surface by the mixed acid, the sacrificial oxide film 5 and the like are removed by dilute hydrofluoric acid and washed with water.

The substrate after cleaning is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 ⁻⁴ Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. Annealing is performed to obtain the structure shown in FIG.

  After thermally oxidizing the substrate surface again, as shown in FIG. 33, a 1 μm Si oxide film 15 is formed on the substrate surface by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere. Next, as shown in FIG. 34, the source contact portion on the surface of the substrate and the Si oxide film 15 corresponding to the gate region are removed by etching.

  Next, as shown in FIG. 35, the substrate is thermally oxidized again, a CVD oxide film is formed, and a gate insulating film 31 is formed by patterning. Next, the Si oxide film 15 in the source region is removed, a Ni film is selectively formed in the source region and the insulated gate region, and a source electrode 19s and a gate electrode 19g are formed. Further, a Ni film is formed on the back surface by electron gun vapor deposition to form a back electrode (drain electrode) 17, and sintering is performed at 1000 ° C. for 1 minute in an Ar atmosphere so that the source electrode 19s, the gate electrode 19g, and the back electrode 17 are Make ohmic contact with each contact area. By this process, a SiC MOSFET in which the back surface of the substrate is processed into a waffle shape as shown in FIG. 29 is completed.

The on-resistance of this device was 10 mΩcm ² and the withstand voltage was 1000V. For reference, in the case of a normal substrate in which the back surface of the substrate is not waffle, the withstand voltage is similarly 1000 V, but the on-resistance is 10.8 mΩcm ² , and the on-resistance of the element processed into a waffle is 0 It can be seen that it is reduced by .8 mΩcm ² .

(Fifth embodiment)
FIG. 36 is a cross-sectional view of a pin diode according to the fifth embodiment of the present invention. The top view is omitted because the rectangular electrode is only formed at the center of the rectangular substrate. The bottom view is the same as FIG. 2 except that a taper is formed.

  A diode element structure is formed in SiC epitaxial layer 3 formed on SiC support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are p-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and the substrate 1 is formed in a continuous waffle shape. A first contact layer 33 and a second contact layer 13 are formed on the upper surface and the back surface of the epitaxial layer 3, respectively. In the present embodiment, when the first contact layer 33 is n-type, the second contact layer 13 is p-type, and the low-concentration p-type epitaxial layer 3 is considered i-type, a pin diode is formed sandwiching this. ing.

  On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the first contact layer 33, and in this embodiment, each is formed in an n-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and the upper portion of the first contact layer 33 is selectively opened, and a surface electrode (first electrode) 19 is formed there. On the back surface of the epitaxial layer 3, a back surface electrode (second electrode) 35 is formed on the second contact layer 13. The back electrode (second electrode) 17 is formed to extend from the bottom surface of the recess to the tapered inner side surface of the SiC support 21 and the bottom surface of the leg portion of the SiC support 21.

  The pin diode of the fifth embodiment is given strength by the SiC support 21, and the diode element is formed in the epitaxial layer 3, and since the distance from the back electrode 17 is short, a low on-resistance is realized. .

  Next, a manufacturing method of the pin diode of the fifth embodiment will be described. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. The drawings showing the same shape refer to the drawings of the first or second embodiment.

One of the differences of the fifth embodiment from the first embodiment is that the p-conductivity type impurity concentration is 3.5 × 10 ¹⁵ cm ⁻³ on the SiC substrate 2 (p-type) having a substrate resistivity of 5 Ωcm. The substrate 1 is prepared by growing the epitaxial layer 3 of 10 μm. The cross-sectional structure is the same as that in FIG. 2 of the first embodiment. The substrate 1 is subjected to a cleaning process under the same conditions as in the first embodiment, a sacrificial oxide film 5 is formed on the upper surface of the substrate, and a Ti layer 7, an Al layer 9, and a resist layer 11 are formed on the rear surface of the substrate, as in FIG. Are sequentially formed.

  Subsequently, a resist pattern for forming a waffle recess is formed in the resist layer 11 and introduced into an RIE chamber using a chlorine-based gas. Using the resist pattern as an etching mask, an Al layer 9 and a Ti layer 7 are formed as in FIG. Is dry-etched.

Next, using the patterned Al layer 9 as an etching mask, the SiC substrate 2 is dry-etched with a mixed gas of CF ₄ and O ₂ as in FIG. 17 of the second embodiment. Also in this embodiment, a tapered waffle recess is formed. This substrate is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution, the resist and metal adhering to the substrate are removed, rinsed with pure water, and the Al layer 9 and Ti layer 7 formed on the back surface of the SiC support 21. Also rinse with pure water.

Next, similarly to FIG. 18 of the second embodiment, Al ion multi-stage implantation is performed on the back surface of the substrate with a total dose of 7 × 10 ¹⁵ cm ⁻² and a maximum acceleration energy of 200 keV, and an ohmic contact region for the back electrode 13 is formed.

Next, an ion implantation mask for forming the RESURF region 12 and the guard ring region 14 serving as termination structures is formed on the upper surface of the epitaxial layer 3. A multi-stage implantation of P (phosphorus) ions is performed on the mask formation surface with a total dose of 1.5 × 10 ¹³ cm ⁻² and a maximum acceleration energy of 300 keV to form a resurf region 12 and a guard ring 14 as shown in FIG. To do.

Subsequently, as shown in FIG. 37, in order to selectively form the ohmic contact region 33 for the surface electrode in the inner portion of the RESURF layer 12, the total dose amount is 7 × 10 ¹⁵ cm ⁻² and the maximum acceleration is formed on the upper surface of the substrate. Multistage implantation of P (phosphorus) ions is performed at an energy of 200 keV.

  The substrate is washed with a mixed acid of sulfuric acid and hydrogen peroxide solution to remove the resist and metal adhering to the substrate, and then rinsed with pure water. Next, a trace amount of metal impurities adhering to the substrate is removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the sacrificial oxide film 5 and the like on the substrate surface are removed with dilute hydrofluoric acid, and rinsed with pure water.

The substrate after cleaning is introduced into an induction heating type activation annealing furnace, evacuated to an ultimate vacuum of 1 × 10 ⁻⁴ Pa, filled with Ar as an inert gas, and activated at 1600 ° C. for 5 minutes. Annealing is performed to obtain the structure shown in FIG.

  Next, after the surface of the substrate is thermally oxidized again, as shown in FIG. 39, a Si oxide film 15 having a substrate surface of 1 μm is formed by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere.

A resist is applied and patterned on the Si oxide film 15 on the surface of the substrate 1 to selectively open a region on the ohmic contact region 33. Next, the Si oxide film 15 is etched by RIE of CF ₄ and O ₂ , the natural oxide film on the outermost surface of the substrate is removed by dilute hydrofluoric acid, and a Ni layer is formed by electron gun evaporation. Next, as shown in FIG. 40, Ni is selectively left in the opening portion, and the remaining portion is removed to form the surface electrode 19. Thereafter, sintering is performed in an Ar atmosphere at 1000 ° C. for 1 minute to realize ohmic contact between the surface electrode 19 and the ohmic contact region 33.

  Next, an Al film 17 which is an ohmic electrode on the back surface is formed and sintered in an Ar atmosphere. This process completes a SiC pin diode as shown in FIG. 36 in which the back surface of the substrate is processed into a continuous waffle shape.

In this embodiment, a device is formed by growing a p-type epitaxial layer having a low impurity concentration on a p-type SiC substrate. However, it is difficult to obtain a p-type SiC substrate having a low substrate resistance comparable to that of an n-type SiC substrate. The current substrate resistivity is approximately 5 Ωcm or more. In this case, a large substrate resistance of ² Ωcm ² or more remains as a series resistance, but this large substrate resistance can be eliminated by using this embodiment.

(Sixth embodiment)
Although the fifth embodiment is a pin diode formed using a substrate obtained by growing a p-type epitaxial layer on a p-type SiC substrate, in the sixth embodiment, an n-type epitaxial layer is formed on an n-type SiC substrate. An embodiment will be described in which a pin diode is formed using a substrate on which is grown. Although the conductivity type and the material used are different from those of the fifth embodiment, the structure is the same as that of the fifth embodiment. Therefore, description will be made with reference to FIGS. 36 to 40 referred to in the fifth embodiment. Further, the same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted.

  A cross-sectional view of the pin diode according to the sixth embodiment is as shown in FIG. However, in the present embodiment, the SiC support 21 and the epitaxial layer 3 are n-type. The first ohmic contact layer 33 is p-type, and the second ohmic contact layer 13 is n-type. An n-type low impurity concentration epitaxial layer is provided between the first ohmic contact layer 33 and the second ohmic contact layer 13. A pin diode sandwiching the layer 3 is formed.

  On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the first contact layer 33, and each is p-type in this embodiment.

  The pin diode of the sixth embodiment is also given strength by the bulk SiC support 21, and the diode element is formed in the epitaxial layer 3, so that a low on-resistance is realized.

  Next, a manufacturing method of the pin type diode according to the sixth embodiment will be described. For the drawings showing the same form, reference is made to the drawings of the first or second embodiment. The process up to the process of FIG. 19 of the second embodiment is similarly performed.

Next, in order to selectively form the ohmic contact region 33 of the surface electrode in the inner portion of the RESURF region 12, as shown in FIG. 37, the total dose amount is 7 × 10 ¹⁵ cm ⁻² and the maximum acceleration energy is 200 keV on the substrate surface. Multi-stage implantation of Al ions is performed. This substrate is subjected to cleaning and activation annealing under the same conditions as in the first embodiment to obtain a structure as shown in FIG.

  Next, as shown in FIG. 39, after thermally oxidizing the upper surface of the substrate again, a 1 μm Si oxide film 15 is formed on the upper surface of the substrate by CVD, and the Si oxide film 15 is sintered at 1000 ° C. in an Ar atmosphere.

  Thereafter, in the same manner as in the fifth embodiment, a region on the ohmic contact region 33 of the Si oxide film 15 is selectively opened, and after Al is formed, Al in the opening is selectively left, and the remaining The portion is selectively removed to form the upper electrode 19. Thereafter, sintering is performed in an Ar atmosphere at 1000 ° C. for 1 minute to realize ohmic contact between the surface electrode 19 and the ohmic contact region 33.

  Next, as in the fifth embodiment, a back electrode 35 is formed of Ni and sintered to form an ohmic contact. As shown in FIG. 36, an SiC pin diode whose back surface is processed into a waffle shape is formed. Is completed.

  In general, an n-type epitaxial layer having a low impurity concentration is grown on a p-type conductive substrate, and a pin diode is formed by ion implantation of Al on the back surface and P (phosphorus) on the front surface. In this embodiment, an n-type epitaxial layer with a low impurity concentration is grown on an n-type substrate of 0.02 Ωcm, the back substrate is processed into a waffle shape, and then p-type conductive impurity ions (Al) are implanted into the surface. Then, after contacting the ohmic electrode on the surface, impurity ions (P) that become n-type conductivity are ion-implanted on the back surface to form a pin diode.

The substrate specific resistance of the p-type substrate is approximately 5 Ωcm or more, and a large substrate resistance of ² Ωcm ² or more remains as a series resistance when a normal pin diode manufacturing method is used. Substrate resistance can be eliminated.

  In addition, n-type epitaxial growth on a p-type substrate is difficult to grow a high-quality film, and degradation of device performance due to crystal defects has been a problem. According to this embodiment, n-type epitaxial growth is n Since it can be formed on a mold substrate, crystal defects in the epitaxial film can be greatly suppressed.

(Seventh embodiment)
FIG. 41 is a cross-sectional view of an insulated gate bipolar transistor (IGBT) according to the seventh embodiment of the present invention. The top view is the same as that of the MOSFET of the fourth embodiment shown in FIG. 30, and the bottom view is the same as that of the first embodiment except for the taper portion, and is omitted.

  In the IGBT of this embodiment, a plurality of IGBT unit elements are formed in parallel on a SiC epitaxial layer (low concentration layer) 3 formed on a support 21 made of bulk SiC. In this embodiment, the bulk SiC and the epitaxial layer 3 are n-type. The back surface of the epitaxial layer 3 is supported by a SiC support 21 having a plurality of recesses, and a plurality of waffles are continuously formed on the substrate 1 composed of the bulk SiC support 21 and the epitaxial layer 3. An n-type source region 25 formed in a p-type well 29 and a gate electrode 19g formed through a gate insulating film 31 are formed on the upper surface of the epitaxial layer 3, and a p-type ohmic contact layer is formed on the rear surface. A back electrode 17 serving as a drain electrode is formed via 13. Since the SiC support 21 is n-type, an insulating film 35 is formed between the SiC support 21 and the back electrode 17 to insulate the back electrode 17 connected to the p-type ohmic contact layer 13.

  On the upper surface of the epitaxial layer 3, the RESURF layer 12 and the guard ring 14, which are termination structures, are formed so as to surround the p-type well 29, and in this embodiment, each is formed of p-type. The upper surface of the epitaxial layer 3 is covered with a Si oxide layer 15, and the source electrode 19s and gate electrode 19g forming regions which are surface electrodes are selectively opened, and the respective electrodes are formed therein.

  The strength of the IGBT according to the seventh embodiment is given by the bulk SiC support 21, the active region is formed in the low-resistance epitaxial layer 3, and the distance from the back electrode 17 is short. It has been realized.

  Next, the manufacturing method of IGBT of 7th Embodiment is demonstrated. The same parts as those in the first and second embodiments are denoted by the same reference numerals, and redundant description is omitted. For the drawings showing the same form, refer to the drawings of the first or second embodiment. The steps up to the process of FIG. 17 of the second embodiment are similarly performed. Next, as shown in FIG. 18, a back contact region 13 is formed. In this embodiment, Al ions are multi-stage implanted into the back surface of the substrate at a total dose of 7 × 10 17 cm −3 and a maximum acceleration energy of 200 keV. A p-type region that also serves as an ohmic contact region 13 of the electrode is formed. Next, the process of FIG. 19 is performed similarly to the second embodiment, and the processes of FIGS. 31 and 32 of the fourth embodiment (MOSFET) are performed similarly.

  Next, after the substrate surface is thermally oxidized again, as shown in FIG. 42, a 1 μm Si oxide film 15 is formed on the substrate surface by CVD and a 1 μm Si oxide film 35 is formed on the back surface of the substrate, and is 1000 ° C. in Ar atmosphere. Then, the SiO2 film is sintered.

  Subsequently, as shown in FIG. 43, the source contact portion on the surface of the substrate and the oxide film corresponding to the gate region are removed by etching. Next, as shown in FIG. 44, the substrate is thermally oxidized again, a CVD oxide film is formed, and a gate insulating film 31 is formed by patterning.

  Next, the natural oxide film formed in the source region 25 is removed, and Ni is selectively formed on the source region 25 and the gate insulating film 31. Sintering is performed at 1000 ° C. for 1 minute in an Ar atmosphere to make ohmic contact with the surface electrode.

Next, after protecting the surface with a resist, a resist is applied to the surface of the Si oxide film 35 on the back surface, and the back electrode portion (directly under the p-type contact region 13) is opened by patterning by patterning with a thick film resist. Next, the Si oxide film 35 is etched by RIE of CF ₄ and O ₂ , the oxide film on the outermost surface of the substrate is removed by dilute hydrofluoric acid, and an Al film that is an ohmic electrode on the back surface is formed, and sintered in an Ar atmosphere. To do. By this process, as shown in FIG. 41, a SiC IGBT whose back surface is processed into a waffle shape is formed.

  In this embodiment, an n-type epitaxial layer 3 having a low impurity concentration is grown on an n-type SiC substrate 2 of 0.02 Ωcm, the back surface of the substrate is processed into a waffle shape, and then p-type conductive impurity ions ( After forming the ohmic region 13 on the back surface by ion implantation of Al), the termination structures 12, 14, the p-type well region 29, the source region 25, and the p-type contact region 30 are formed on the front surface to make an IGBT. After growing an n-type epitaxial layer on a p-type substrate, the back surface of the substrate may be processed into a waffle to make an IGBT.

When a p-type substrate is used, the current substrate specific resistance is approximately 5 Ωcm or more. In this case, a large substrate resistance of ² Ωcm ² or more remains as a series resistance, but this large substrate resistance can be eliminated by using the present invention.

  Further, in this embodiment, when an n-type epitaxial film is grown on an n-type substrate and the substrate is processed into a waffle shape, the waffle recess is removed by etching all the substrate, and impurity ions that become p-type conductivity are formed on the back surface. (Al) is ion-implanted, but when making an IGBT by growing an n-type epitaxial film on a p-type substrate, a part of the substrate may be left. In this case, the remaining amount of the substrate and the substrate resistance are in a linear relationship, and as the remaining amount increases, the substrate resistance increases, but there is an advantage that the substrate strength increases accordingly. Depending on the design of the element and the required performance, the user can consider the remaining amount of the recess.

  On the other hand, n-type epitaxial growth on a p-type substrate makes it difficult to grow a high-quality film, and degradation of device performance due to crystal defects is a problem. After growing on the substrate, the back surface of the n-type substrate is processed into a waffle shape, and thus an IGBT can be created, so that crystal defects in the epitaxial film can be greatly suppressed.

(Eighth embodiment)
Similar to SiC, attention is focused on the application of GaN, which is a wide bandgap semiconductor, to power devices. In the case of GaN, it is known that when an AlGaN / GaN heterostructure is formed in combination with AlGaN, a two-dimensional electron gas channel is obtained, the channel mobility is very high, and low on-resistance is realized. In this HEMT using AlGaN / GaN, a horizontal element in which a source, a gate, and a drain are formed laterally on the uppermost AlGaN layer is generally used. However, for the purpose of reducing the chip area and circuit wiring, etc. In some cases, a structure in which the drain electrode is taken out from the lower surface of the substrate is desirable. In the eighth embodiment, an example in which the present invention is applied to such a vertical GaN HEMT will be described.

  FIG. 45 is a cross-sectional view of a GaN switching element (MEMT) according to the eighth embodiment. An AlN buffer layer 43 having a thickness of 100 nm is formed on an n-type SiC substrate 41 whose back surface is formed in a waffle shape. Further thereon, an undoped GaN layer 45 (3 μm), an undoped AlGaN layer 47 (3 nm), an n-type AlGaN layer 49 (10 nm), and an undoped AlGaN layer 51 (5 nm) are sequentially formed. A source region 53 is selectively formed on the n-type AlGaN layer 49 through the undoped AlGaN layer 51. A gate electrode 55 is selectively formed on the undoped AlGaN layer 51. A contact hole reaching the SiC substrate 41 from the undoped AlGaN layer 51 is formed, and a drain region 59 is formed so as to fill the contact hole. A Si oxide film 51 is formed on the upper surface of this structure via a SiN film 59, and a field plate 63 is selectively formed thereon. A back electrode 65 is formed on the back surface of the SiC substrate 41. With the above configuration, a GaN switching element in which the drain region 59 is extracted to the back electrode 65 is realized.

  Next, a method for forming the switching element of this embodiment will be described. First, an organic stain adhering to a substrate is removed from a n-type SiC substrate (substrate) having a substrate resistance of 0.02 Ωcm with a mixed acid of sulfuric acid and hydrogen peroxide, and rinsed with pure water. Next, metal impurities adhering to the substrate are removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the natural oxide film on the substrate surface is removed with dilute hydrofluoric acid and rinsed with pure water.

  Although not shown, this substrate is heated in an oxygen atmosphere at 1100 ° C. for 2 hours to oxidize the substrate surface and form a sacrificial oxide film, as in the first embodiment. After a Ti film having a thickness of 50 nm is formed on the back surface of the substrate, an Al film having a thickness of 2 μm is formed. Here, Ti serves as an adhesion layer for bringing SiC and Al into close contact, and Al serves as an etching mask for later SiC etching. A resist of about 2 μm is spin-coated on the Al surface, a pattern for forming a waffle recess is exposed and developed, and then hard-baked to harden the resist. The substrate on which the resist is patterned is introduced into an RIE chamber using a chlorine-based gas, and Al is dry etched using the patterned resist as an etching mask.

Then, SiC is dry-etched with a mixed gas of CF ₄ and O _{2 using} the patterned Al as an etching mask. By this process, the back surface of the SiC substrate 41 is selectively etched to form a waffle-shaped recess.

Next, multistage implantation of P (phosphorus) ions is performed on the back surface of the substrate with a total dose of 7 × 10 ¹⁵ cm ⁻² and a maximum acceleration energy of 200 keV, thereby forming an ohmic contact region (not shown) of the back electrode.

  This substrate is again washed with a mixed acid of sulfuric acid and hydrogen peroxide solution to remove Ti / Al and organic substances on the back surface and rinse with pure water. Next, metal impurities adhering to the substrate are further removed with a mixed acid of dilute hydrochloric acid and hydrogen peroxide, and rinsed with pure water. Finally, the sacrificial oxide film on the substrate surface is removed with dilute hydrofluoric acid, and rinsed with pure water to form a waffle substrate 41.

The substrate 41 is transferred to an MO-CVD (metal organic chemical vapor deposition) apparatus, and as shown in FIG. 46, the AlN buffer layer 43 is 100 nm, the undoped GaN layer 45 is 3 μm, the undoped AlGaN layer 47 is 3 nm, and the n-type. The AlGaN layer 49 is 10 nm and the undoped AlGaN layer 51 is sequentially heteroepitaxially grown. Here, the Al content of the AlGaN layers 49 and 51 is 30%, and the doping concentration of the n-type AlGaN layer 49 is 5 × 10 ¹⁸ cm ⁻³ . Also, the SiC substrate 41 is used because there is little lattice mismatch of the upper GaN layer and it is easy to perform epitaxial growth.

  Thereafter, as shown in FIG. 47, a source contact region 67 reaching the n-type AlGaN layer 49 from the substrate surface is provided by lithography or anisotropic etching. Next, as shown in FIG. 48, an internal contact hole 69 that reaches the SiC substrate 41 from the substrate surface is provided by lithography or anisotropic etching.

  Thereafter, the patterning mask and the etching mask are removed, and a resist is spin-coated on the substrate surface. Then, the source contact region and the contact hole region are opened again by patterning, and Ti is formed by MO-CVD, sputtering, electron evaporation, or the like. The front electrode is formed with / Al, and the back electrode 65 is also formed with Ti / Al. Thereafter, the electrode non-film forming portion on the surface is removed by lift-off simultaneously with the resist removal, and a source region (electrode) 53 and a drain region 59 are formed as shown in FIG. Thereafter, sintering is performed in an Ar atmosphere to make ohmic contact between the electrode portions.

  Next, resist patterning is performed to form the gate electrode 55, and Ni / Au is deposited by electron gun evaporation or the like. Also here, as shown in FIG. 50, the electrode non-film formation portion on the surface is removed by lift-off and sintered simultaneously with the resist removal.

  Next, as shown in FIG. 51, a SiN film 59 as an insulating film is formed on the substrate surface, and then a Si oxide film 61 is further deposited thereon as shown in FIG. Finally, a field plate 63 is formed to complete the high breakdown voltage GaN switching element shown in FIG.

  As described above, a semiconductor device in which a semiconductor element is formed in a semiconductor layer heteroepitaxially grown on a substrate having a waffle portion on the back surface can be obtained, and the resistance of the drain region taken out from the back surface can be reduced.

(Ninth embodiment)
When the semiconductor device (power device) described in the first to eighth embodiments is used by being attached to a heat sink, there is a case where the drain electrode on the back surface is taken out to the front surface and all wiring to the electrode is desired to be performed on the top surface. The waffle type semiconductor device of the present invention can be easily applied to such a demand. In the ninth embodiment, such an example will be described.

  FIG. 53 is a schematic perspective view showing a mounting form of the semiconductor device according to the ninth embodiment. The semiconductor element 71 is assumed to be the SBD described in the first or second embodiment, for example. Reference numeral 19 is a surface electrode (first electrode). The semiconductor device 71 is bonded to the heat sink 73 via an insulating film 75. The back electrode (17) of the SBD 71 is connected to the second electrode 77 by a method described later, and is configured so that connection to the first and second electrodes is possible on the upper surface of the semiconductor device.

  Next, a method for forming this semiconductor structure will be described. First, as shown in FIG. 54, a plurality of stripe-shaped steps 79 are provided so as to connect a plurality of waffle forming portions on the back surface of the substrate for forming the SBD 71. As shown in FIG. 55, the surface element region 81 is formed on the upper surface of the substrate by the same method as already described in the first or second embodiment, and the contact metal 17 is formed on the rear surface. Next, as shown in FIG. 56, after protecting the substrate surface with a thick film resist (not shown) or the like, the step 79 of the waffle recess on the back surface of the substrate is embedded with a conductor 83 of Al or Cu.

  Subsequently, as shown in FIG. 57, after removing the surface protective film (not shown), a resist (not shown) is applied to the surface again, and the outer peripheral portion is opened from the element region by patterning, and the back surface is formed by RIE or the like. Etching is performed until the embedded electrode 17 is visible. The back-surface embedded electrode 17 that appears on the front surface is connected by an Al strap or the like to serve as the second electrode 79.

  Finally, as shown in FIG. 53, the SBD 71 is mounted on the cooling fin 73 with the insulating film 75 on the surface, and the first electrode 19 and the second electrode 79 are connected to the required connection locations by the bonding wires 85. Bond.

  Through the above steps, the waffle type power device attached to the heat sink is completed, and the wiring of the first and second electrodes can be easily performed on the upper surface of the power device (semiconductor device).

(Modification)
In the first to eighth embodiments, the back electrode 17 is formed along the bottom surface of the waffle recess or the surface from the projection to the bottom of the recess. However, the recess may be embedded with a conductor 83 as shown in FIG. . In this case, the conductor 83 may be embedded with Al or Cu as in the ninth embodiment.

  In the first to eighth embodiments, the dicing line 23 is made to coincide with the waffle convex portion 21 as shown in FIG. 59. However, as shown in FIG. 60, the dicing line 23 passes through the waffle concave portion. Also good. That is, at least a part of the waffle recess may be disposed immediately below the element formation region. In FIGS. 59 and 60, only one element of the dicing line 23 is schematically displayed for easy understanding.

  Furthermore, the present invention is not limited to the above-described embodiments and modifications, and various modifications can be made without departing from the spirit of the invention.

1 is a cross-sectional view of a semiconductor device (SBD) according to a first embodiment of the present invention. The bottom view of the semiconductor device of a 1st embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing for demonstrating the manufacturing process of 1st Embodiment. Sectional drawing explaining the dicing for every recessed part. Sectional drawing explaining the dicing for every four recessed parts. The typical perspective view explaining the waffle board | substrate of this invention. Sectional drawing which shows the modification of recessed part formation. Sectional drawing of the semiconductor device (SBD) which concerns on the 2nd Embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. Sectional drawing for demonstrating the manufacturing process of 2nd Embodiment. Sectional drawing of the semiconductor device (SIT / JFET) concerning the 3rd Embodiment of this invention. The top view of the semiconductor device (SIT / JFET) concerning a 3rd embodiment. Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. Sectional drawing for demonstrating the manufacturing process of 3rd Embodiment. Sectional drawing of the semiconductor device (MOSFET) based on the 4th Embodiment of this invention. The top view of the semiconductor device (MOSFET) concerning a 4th embodiment. Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. Sectional drawing for demonstrating the manufacturing process of 4th Embodiment. Sectional drawing of the semiconductor device (pin diode) which concerns on 5th (6th) embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. Sectional drawing for demonstrating the manufacturing process of 5th (6th) embodiment. Sectional drawing of the semiconductor device (IGBT) which concerns on the 7th Embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of 7th Embodiment. Sectional drawing for demonstrating the manufacturing process of 7th Embodiment. Sectional drawing for demonstrating the manufacturing process of 7th Embodiment. Sectional drawing of the semiconductor device (HEMT) which concerns on the 8th Embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing for demonstrating the manufacturing process of 8th Embodiment. Sectional drawing of the semiconductor device which concerns on the 9th Embodiment of this invention. Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. Sectional drawing for demonstrating the manufacturing process of 9th Embodiment. Sectional drawing explaining the modification of this invention. The figure explaining an example of the relationship between the convex part of the waffle board | substrate of this invention, and a dancing line. The figure explaining the other example of the relationship between the convex part of the waffle board | substrate of this invention, and a dancing line.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate 2 ... SiC substrate 3 ... Epitaxial layer 5 ... Sacrificial oxide film 7 ... Ti layer 9 ... Al layer 11 ... Resist 12 ... RESURF region 13 ... (second) ohmic contact region 14 for back electrode ... Guard ring 15 ... Si oxide film 17 ... back surface (second) electrode 19 ... top surface (first) electrode 19g ... gate electrode 19s ... source electrode 21 ... SiC support 23 ... dicing line 25 ... source region 27 ... gate region 29 ... p-type Well 31 ... Gate insulating film 33 ... (first) ohmic contact region 35 for upper electrode ... Insulating film 41 ... SiC substrate 43 ... AlN buffer layer 45 ... Undoped GaN layer 47 ... Undoped AlGaN layer 49 ... n-type AlGaN layer 51 ... Undoped AlGaN layer 53 ... source region 55 ... gate electrode 57 ... drain region 59 ... silicon nitride film 61 ... silico Oxide film 63 ... field plate 65 ... back electrode 71 ... SBD device 73 ... heat sink 75 ... insulating film 77 ... second electrode (drain electrode)
79 ... Step 81 ... SBD element region 83 ... Conductor 85 ... Bonding wire

Claims (6)

A support made of a semiconductor having a plurality of recesses formed by mesh-like protrusions on the back surface and having a first impurity concentration;
A semiconductor layer formed on a surface facing the back surface of the support and having a second impurity concentration lower than the first impurity concentration;
A semiconductor element formed in the semiconductor layer;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein an area of the surface of the support is larger than a total area occupied by the plurality of recesses.   A first electrode is formed on the front surface, a second electrode is formed on at least the bottom surfaces of the plurality of recesses on the back surface, and at least a part of the second electrode is disposed directly below the first electrode. The semiconductor device according to claim 1, wherein:   4. The semiconductor device according to claim 1, wherein the semiconductor layer is made of the same element as the support and has the same crystal orientation.   The semiconductor device according to claim 4, wherein the same element includes Si and C.   The semiconductor device according to claim 1, wherein the semiconductor layer includes an element different from the support and has the same crystal orientation.

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