CN116314316A - A concave gate enhanced GaN HEMT with anti-reverse conduction current and its manufacturing method - Google Patents

Abstract

The invention provides a concave gate enhanced GaN HEMT structure resisting reverse conduction current, which comprises the following components: an anode, a cathode, a substrate, a buffer layer, a PN junction, a separation layer and a concave grid enhanced GaN HEMT device which are stacked in sequence; wherein: the PN junction comprises a P-type doped region and an N-type doped region, and the P-type doped region wraps the N-type doped region; the concave gate enhanced GaN HEMT device comprises a first nucleation layer, a channel layer and a barrier layer which are sequentially formed on a separation layer; the barrier layer is provided with a first groove, the first groove penetrates through the barrier layer, and the first groove is filled with a gate dielectric layer and gate metal to form a gate; a source electrode and a drain electrode are respectively formed on the barrier layers at two sides of the grid electrode; wherein; the anode is electrically connected with the P-type doped region and is electrically connected to the source electrode; the cathode is electrically connected with the N-type doped region and is electrically connected to the drain electrode; the N-type doped region covers the region below the drain electrode and extends to the region below the grid electrode; reverse on-current of the device can be suppressed by the PN junction.

Description

A concave gate enhanced GaN HEMT with anti-reverse conduction current and its manufacturing method

technical field

The invention relates to the field of concave grid enhanced GaN HEMT, in particular to a concave grid enhanced GaN HEMT capable of resisting reverse conduction current and a manufacturing method thereof.

Background technique

Recessed gate enhanced GaN HEMT has great potential to replace Si-based devices in the application of power devices due to its advantages of high breakdown voltage and low on-resistance. In addition to the advantages of high breakdown voltage and low on-resistance, the concave-gate enhanced GaNHEMT also makes passive devices more miniaturized and lightweight in power electronic devices. Among them, the concave gate technology refers to etching away the barrier layer under the gate during the device preparation process, so that the concentration of two-dimensional electron gas in the entire channel is reduced, and the bottom of the conduction band under the gate is raised to a low level. Above the meter energy level, so that the concave gate enhanced GaN HEMT realizes the enhanced application.

Due to the material properties and conduction mechanism, the concave-gate enhanced GaN HEMT does not have a body diode, so when the concave-gate enhanced GaN HEMT is turned off, its reverse conduction current will be larger, so the turn-off power consumption is also higher. high. There is an urgent need for a concave-gate enhanced GaN HEMT that can suppress the reverse conduction current.

Contents of the invention

The invention provides a concave grid enhanced GaN HEMT with anti-reverse conduction current and a manufacturing method, so as to suppress the reverse conduction current of the concave gate enhanced GaN HEMT when it is turned off.

According to the first aspect of the present invention, there is provided a concave gate enhanced GaN HEMT structure resistant to reverse conduction current, comprising:

Substrate;

a buffer layer formed on the substrate;

A PN junction is formed on the buffer layer, and the PN junction includes a P-type doped region and an N-type doped region, and the N-type doped region is formed on a part of the surface layer of the P-type doped region, and The P-type doped region wraps the N-type doped region;

a separation layer formed on the PN junction and covering the P-type doped region and the N-type doped region;

A concave-gate enhanced GaN HEMT device formed on the separation layer; and the concave-gate enhanced GaN HEMT device includes a first nucleation layer, a channel layer, and a barrier layer sequentially formed on the separation layer; A first groove is opened on the barrier layer, the first groove penetrates the barrier layer, and the first groove is filled with a gate dielectric layer and a gate metal to form a gate; and the A source and a drain are respectively formed on the barrier layers on both sides of the gate; and the gap between the source, the gate and the drain is filled with a passivation layer;

an anode and a cathode, the anode is electrically connected to the P-type doped region, and the anode is electrically connected to the source; the cathode is electrically connected to the N-type doped region, and the cathode is electrically connected to the drain;

Wherein, the N-type doped region covers the region below the drain and extends to the region below the gate.

Optionally, the concave gate enhanced GaN HEMT further includes a field plate structure formed on the top of the gate.

Optionally, the P-type doped region and the N-type doped region are doped with magnesium ions and silicon ions respectively.

Optionally, the doping concentration in the P-type doping region is 1*10 ¹⁷ ~2*10 ¹⁷ cm ^-3 ; the doping concentration in the N-type doping region is 2*10 ¹⁸ ~6*10 ¹⁸ cm ^-3 .

Optionally, magnesium ions and silicon ions doped in the P-type doped region and the N-type doped region are respectively activated after selective annealing.

Optionally, the substrate is a Si-based substrate.

Optionally, the material of the separation layer includes aluminum oxide, the material of the first nucleation layer includes AlN, so the material of the channel layer is GaN, and the material of the barrier layer is AlGaN.

Optionally, the material of the passivation layer is aluminum oxide.

According to the second aspect of the present invention, there is provided a method for fabricating a concave gate-enhanced GaN HEMT with anti-reverse conduction current, which is used to manufacture the concave anti-reverse conduction current provided in the first aspect of the present invention and alternative solutions. Gate-enhanced GaNHEMT, the preparation method includes:

Provide a substrate,

forming a buffer layer on top of the substrate;

forming a P-type doped region on the buffer layer, and forming an N-type doped region on the surface layer of a part of the P-type doped region to form a PN junction;

forming a separation layer on the PN junction, the separation layer covering the P-type doped region and the N-type doped region;

forming the concave gate enhanced GaN HEMT device on the top of the spacer layer;

Forming an anode and a cathode; wherein the anode is electrically connected to the P-type doped region, and the anode is also electrically connected to the source of the concave gate enhanced GaN HEMT device; the cathode is electrically connected to the N-type The doped region is electrically connected, and the cathode is electrically connected to the drain of the concave gate enhanced GaN HEMT device;

Wherein, the N-type doped region covers the region below the drain and extends to the region below the gate of the recessed gate enhanced GaN HEMT device.

Optionally, a P-type doped region is formed on the buffer layer, and an N-type doped region is formed on the surface layer of a part of the P-type doped region to form a PN junction; specifically including:

forming a GaN layer on the buffer layer;

A P-type doped region is formed in the GaN layer, and an N-type doped region is formed in the P-type doped region, and the P-type doped region is in contact with the N-type doped region to form a PN junction.

Optionally, the forming a P-type doped region in the GaN layer specifically includes:

performing P-type ion implantation on the first region of the GaN layer;

performing rapid thermal annealing activation or laser annealing activation on the implanted P-type ions to form the P-type doped region.

Optionally, an N-type doped region is formed on the surface layer of a part of the P-type doped region, including:

performing N-type ion implantation on the first region of the P-type doped region;

performing rapid thermal annealing activation or laser annealing activation on the implanted N-type ions to form the N-type doped region.

Optionally, forming the concave gate enhanced GaN HEMT device on the top of the spacer layer specifically includes;

sequentially forming a first nucleation layer, a channel layer and a barrier layer on the separation layer;

forming isolation steps, wherein the isolation steps include first isolation steps located at both ends of the buffer layer along a first direction and second isolation steps located at both ends of the isolation layer along the first direction;

forming a first groove in the barrier layer;

Depositing a source metal and a drain metal on the surface of the barrier layer on both sides of the first groove, respectively, to form a source and a drain;

Depositing a gate metal in the first groove after depositing a gate dielectric on the bottom and sidewalls of the first groove to form a gate;

A passivation layer is filled in the gaps among the source, the gate and the drain.

Optionally, the forming of the isolation step specifically includes:

Etching the isolation layer and the PN junction along both ends of the first direction to form a first isolation step at both ends of the buffer layer;

Etching the barrier layer, the channel layer and the first nucleation layer along both ends of the first direction to form a second isolation step at both ends of the isolation layer.

Optionally, making the anode and the cathode specifically includes:

Depositing a passivation layer on the surface of the first isolation step, the second isolation step, and the concave gate enhanced GaN HEMT device;

A plurality of openings are formed in the passivation layer, and the openings respectively penetrate to the P-type doped region, the source, the gate, the drain and the N-type doped region ;

Depositing an electrode metal layer, the electrode metal layer fills the plurality of through holes, wherein the electrode metal layer electrically connected to the P-type doped region constitutes the anode, and is electrically connected to the N-type doped region The electrode metal layer constitutes the cathode, and the anode is electrically connected to the source; the cathode is electrically connected to the drain.

Optionally, the method further includes: forming a field plate structure, wherein the field plate structure is the electrode metal layer deposited in the opening penetrating through the gate.

According to a third aspect of the present invention, a semiconductor device is provided, including the concave gate enhanced GaN HEMT anti-reverse conduction current provided in the first aspect of the present invention and alternative solutions.

According to a fourth aspect of the present invention, an electronic device is provided, including the semiconductor device provided in the third aspect of the present invention.

According to the fifth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, including the method for preparing a recessed gate-enhanced GaN HEMT with anti-reverse conduction current provided by the second aspect of the present invention and alternative solutions.

According to a sixth aspect of the present invention, there is provided a method for manufacturing an electronic device, including the method for manufacturing a semiconductor device provided in the fifth aspect of the present invention.

By forming the PN junction on the buffer layer as the body diode of the concave-gate enhanced GaN HEMT, the reverse conduction current of the concave-gate enhanced GaN HEMT is suppressed.

Description of drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings that need to be used in the description of the embodiments or the prior art. Obviously, the accompanying drawings in the following description are only These are some embodiments of the present invention. For those skilled in the art, other drawings can also be obtained according to these drawings without any creative effort.

FIG. 1 is a schematic diagram of a device structure of a concave gate enhanced GaN HEMT structure in the prior art;

2 is a schematic device structure diagram of a concave gate enhanced GaN HEMT structure anti-reverse conduction current provided by an embodiment of the present invention;

FIG. 3 is a schematic flow diagram of a method for preparing a concave-gate-enhanced GaN HEMT with anti-reverse conduction current provided by an embodiment of the present invention;

Fig. 4 is a schematic diagram of the device structure at different process stages produced according to the method of manufacturing the anti-reverse conduction current-enhanced GaN HEMT provided by the embodiment of the present invention;

FIG. 5 is a schematic flow diagram II of a method for preparing a concave-gate-enhanced GaN HEMT with anti-reverse conduction current provided by an embodiment of the present invention;

Fig. 6 is a schematic diagram of the device structure II in different process stages manufactured according to the method of manufacturing the anti-reverse conducting current-enhanced GaN HEMT provided by the embodiment of the present invention;

Fig. 7 is a schematic diagram of device structure III in different process stages manufactured according to the method of manufacturing a concave gate-enhanced GaN HEMT with anti-reverse conduction current provided by an embodiment of the present invention;

Fig. 8 is a schematic diagram 4 of the device structure at different process stages manufactured according to the preparation method of the anti-reverse conducting current-enhanced GaN HEMT provided by the embodiment of the present invention;

FIG. 9 is a schematic diagram of the device structure in different process stages according to the method of manufacturing the anti-reverse conduction current-enhanced GaN HEMT according to the embodiment of the present invention;

FIG. 10 is a schematic flow chart III of a method for preparing a concave-gate enhanced GaN HEMT with anti-reverse conduction current provided by an embodiment of the present invention;

FIG. 11 is a schematic diagram of the device structure at different process stages manufactured according to the method of manufacturing the anti-reverse conduction current-enhanced GaN HEMT according to the embodiment of the present invention;

Fig. 12 is a schematic diagram of the device structure at different process stages according to the preparation method of the anti-reverse conduction current-enhanced GaN HEMT according to the embodiment of the present invention;

Fig. 13 is a schematic diagram of the device structure eight in different process stages manufactured according to the method of manufacturing the anti-reverse conducting current-enhanced GaN HEMT provided by the embodiment of the present invention;

FIG. 14 is a schematic diagram of the device structure at different process stages manufactured according to the method of manufacturing the anti-reverse conducting current-enhanced GaN HEMT according to the embodiment of the present invention;

Fig. 15 is a schematic flow diagram 4 of a method for fabricating a concave gate-enhanced GaN HEMT with anti-reverse conduction current provided by an embodiment of the present invention;

Fig. 16 is a schematic diagram of the device structure at different process stages according to the method of manufacturing the anti-reverse conducting current-enhanced GaN HEMT according to the embodiment of the present invention;

FIG. 17 is a eleventh schematic view of the device structure at different process stages manufactured according to the method for fabricating the anti-reverse conducting current-enhanced GaN HEMT provided by the embodiment of the present invention.

Explanation of reference signs:

100-substrate;

101-buffer layer;

102-GaN layer;

103-P type doped region;

104-N-type doped region;

105-separation layer;

106 - the first nucleation layer;

107 - channel layer;

108 - barrier layer;

109-source;

110-drain;

111-gate dielectric layer;

112-grid;

113 - passivation layer;

114 - anode;

115 - cathode;

116 - field plate structure

117 - the first isolation step;

118 - Second isolation step.

Detailed ways

The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

The terms "first", "second", "third", "fourth", etc. (if any) in the description and claims of the present invention and the above drawings are used to distinguish similar objects, and not necessarily Used to describe a specific sequence or sequence. It is to be understood that the data so used are interchangeable under appropriate circumstances such that the embodiments of the invention described herein can be practiced in sequences other than those illustrated or described herein. Furthermore, the terms "comprising" and "having", as well as any variations thereof, are intended to cover a non-exclusive inclusion, for example, a process, method, system, product or device comprising a sequence of steps or elements is not necessarily limited to the expressly listed Those steps or elements may instead include other steps or elements not explicitly listed or inherent to the process, method, product or apparatus.

Before setting forth the embodiments of the present invention, the design idea of the present invention is briefly described:

Please refer to Figure 1. The existing recessed gate enhanced GaN HEMT consists of a substrate, a buffer layer and a recessed gate enhanced GaN HEMT device on the buffer layer. When a conduction voltage is applied to the drain of the recessed gate enhanced GaN HEMT device When the concave gate enhanced GaN HEMT is turned on, the conduction current easily flows out from the substrate through the concave gate enhanced GaN HEMT device from the drain, resulting in substrate leakage; at the same time, when applied to the drain When the turn-on voltage is withdrawn, a reverse conduction current flowing through the concave-gate enhanced GaN HEMT device from the source to the drain will be generated to increase device loss. In view of the above-mentioned defects of the existing concave-gate enhanced GaN HEMT, the applicant of the present invention specially fabricated a PN junction on the buffer layer to suppress substrate leakage and leakage when the concave-gate enhanced GaN HEMT is turned on. Reverse conduction current problem during shutdown.

Please refer to FIG. 2 , an embodiment of the present invention provides a concave gate enhanced GaN HEMT structure resistant to reverse conduction current, including:

substrate 100;

a buffer layer 101 formed on the substrate 100;

A PN junction is formed on the buffer layer, and the PN junction includes a P-type doped region 103 and an N-type doped region 104, and the N-type doped region 104 is formed in part of the P-type doped region 103 surface layer, and the P-type doped region 103 wraps the N-type doped region 104;

a separation layer 105 formed on the PN junction and covering the P-type doped region 103 and the N-type doped region 104;

A concave gate enhanced GaN HEMT device is formed on the separation layer 105; and the concave gate enhanced GaN HEMT device includes a first nucleation layer 106, a channel layer 107 and a first nucleation layer 107 formed sequentially on the separation layer 105. Barrier layer 108; a first groove is opened on the barrier layer 108, the first groove runs through the barrier layer 108, and the first groove is filled with gate dielectric 111 and gate 112 metal to form a gate 112; and a source 109 and a drain 110 are respectively formed on the barrier layer 108 on both sides of the gate 112; and the source 109, the gate 112 and the drain 110 Passivation layer 113 is filled in the gap between;

An anode 114 and a cathode 115, the anode 114 is electrically connected to the P-type doped region 103, and the anode 114 is electrically connected to the source 109; the cathode 115 is electrically connected to the N-type doped region 104 , and the cathode 115 is electrically connected to the drain 110;

Wherein, the N-type doped region 104 covers the region below the drain 110 and extends to the region below the gate 112 .

The principle of suppressing the leakage of the substrate 100 when the concave gate-enhanced GaN HEMT is turned on through the PN junction is: when the drain 110 is applied with a turn-on voltage, if the turn-on current wants to flow out of the substrate 100, the It will flow from the cathode 115 to the opposite end of the PN junction and be suppressed, so that the conduction current can only flow from the drain 110 on the concave gate enhanced GaN HEMT device to the source , so as to suppress the leakage problem of the recess gate enhanced GaN HEMT substrate 100 .

The principle of suppressing the reverse conduction current when the concave gate-enhanced GaN HEMT is turned off through the PN junction is: when the conduction voltage applied to the drain 110 is withdrawn, if the reverse conduction current wants to flow from the The source 109 flows through the concave gate enhanced GaN HEMT device to the drain 110, and will be guided by the anode 114 to the positive end of the PN junction, and flow through the PN junction from the cathode 115 flows out, so that the device loss will not be increased through the concave gate enhanced GaN HEMT device.

In addition, the PN junction also has the function of preventing the forward breakdown of the concave gate enhanced GaN HEMT. The specific principle is: when the conduction voltage applied to the drain 110 is too large, the conduction current is originally suppressed The PN junction will be reversely broken down, so that the conduction current flows out from the anode 114 through the PN junction, so as to avoid the forward breakdown of the concave gate enhanced GaN HEMT device.

Please refer to FIG. 2 , as a specific implementation manner, the recess gate enhanced GaN HEMT further includes a field plate structure 116 formed on the top of the gate 112 .

As a specific implementation manner, the P-type doped region 103 and the N-type doped region 104 are respectively doped with magnesium ions and silicon ions. The magnesium ions and the silicon ions are respectively selected as doping ions because these two ions are easier to activate. Of course, other P-type ions and other N-type ions can also be selected as doping ions. For example, P-type ions can also be Zn, Be, etc., which are not limited here; for example, N-type ions may also be V, C, etc., which are not limited here.

As a specific implementation manner, the doping concentration in the P-type doped region 103 is 1*10 ¹⁷ ~ 2*10 ¹⁷ cm ^-3 ; the doping concentration in the N-type doped region 104 is 2*10 ¹⁸ ~6*10 ¹⁸ cm ⁻³ . Of course, the doping concentration in the P-type doping region 103 is only an experimental preferred data, which can be adjusted according to actual needs, and is not limited here; similarly, the doping concentration in the N-type doping region 104 is also It is only the optimized data of the experiment, and it can also be adjusted according to actual needs, which is not limited here.

As a specific implementation manner, the magnesium ions and silicon ions doped in the P-type doped region 103 and the N-type doped region 104 are respectively activated after selective annealing.

As a specific implementation manner, the substrate 100 is a Si-based substrate.

As a specific embodiment, the material of the separation layer 105 includes aluminum oxide, the material of the first nucleation layer 106 includes AlN, so the material of the channel layer 107 is GaN, and the material of the barrier layer 108 is AlGaN, the material of the buffer layer 101 is AlGaN. Of course, the above-mentioned structural layers may also be made of other materials, and the present invention is not limited thereto, and any material realization form of the corresponding structural layers falls within the protection scope of the present invention. Wherein, the function of the spacer layer 105 is to insulate and isolate the recessed gate-enhanced GaN HEMT device from the PN junction below, and its material is not limited to aluminum oxide, and can also be other insulating materials, such as SiO2, etc. , is not limited here.

As a specific implementation manner, the material of the passivation layer 113 is aluminum oxide.

Please refer to FIG. 2 and FIG. 3 to FIG. 16. The embodiment of the present invention also provides a method for preparing a concave-gate enhanced GaN HEMT with anti-reverse conduction current, which is used to manufacture the anti-reverse conduction provided by the embodiment of the present invention. Current concave gate enhanced GaN HEMT, the preparation method includes:

S1: Referring to FIG. 4 , a substrate 100 is provided.

S2: Please refer to FIG. 4 , forming a buffer layer 101 on the top of the substrate 100 .

S3: forming a P-type doped region 103 on the buffer layer 101, and forming an N-type doped region 104 on a surface layer of a part of the P-type doped region 103 to form a PN junction.

S4: Please refer to FIG. 9 , forming a spacer layer 105 on the PN junction, and the spacer layer 105 covers the P-type doped region 103 and the N-type doped region 104 .

S5: forming the concave gate enhanced GaN HEMT device on the top of the spacer layer 105 .

S6: forming an anode 114 and a cathode 115; wherein the anode 114 is electrically connected to the P-type doped region 103, and the anode 114 is also electrically connected to the source 109 of the concave gate enhanced GaN HEMT device; The cathode 115 is electrically connected to the N-type doped region 104, and the cathode 115 is electrically connected to the drain 110 of the concave gate enhanced GaN HEMT device;

Wherein, the N-type doped region 104 covers the region below the drain 110 and extends to the region below the gate 112 of the recessed gate enhanced GaN HEMT device.

Please refer to FIGS. 5 to 8. As a specific implementation, in S3, a P-type doped region 103 is formed on the buffer layer 101, and an N-type doped region is formed on the surface layer of a part of the P-type doped region 103. The doped region 104 to form a PN junction specifically includes:

S31 : forming a GaN layer 102 on the buffer layer 101 .

S32: forming a P-type doped region 103 in the GaN layer 102 .

S33 : forming an N-type doped region 104 in the P-type doped region 103 .

Please refer to FIG. 6, as a specific implementation manner, in S31, a GaN layer 102 is formed on the buffer layer 101, specifically including:

The GaN layer 102 is epitaxially compositionally graded by MOCVD on the buffer.

Please refer to FIG. 7, as a specific implementation manner, in S32, the P-type doped region 103 is formed in the GaN layer 102, which specifically includes: first covering the GaN layer 102 with a patterned hard mask except for the first Other areas of the region; then perform P-type ion implantation on the first region, such as magnesium ions; then perform rapid thermal annealing activation or laser annealing activation on the implanted P-type ions to form the P-type doped region 103; Finally, the hard mask is removed with a hydrofluoric acid solution.

Please refer to FIG. 8 , as a specific implementation manner, forming the N-type doped region 104 in the P-type doped region 103 in S33 specifically includes: first covering the P-type doped region 104 with a patterned hard mask; Region 103 except the other regions of the first region; then perform N-type ion implantation on the first region, such as silicon ions; then perform rapid thermal annealing activation or laser annealing activation on the implanted N-type ions to form the N-type doping region 104; finally remove the hard mask with hydrofluoric acid solution. Wherein, the first region of the P-type doped region 103 covers the region below the drain 110 and extends to the region below the gate 112 of the recessed gate enhanced GaN HEMT device.

As a specific implementation manner, the material of the hard mask is specifically SiN.

Please refer to FIG. 10 to FIG. 14, as a specific implementation manner, in S5, the concave gate enhanced GaN HEMT device is formed on the top of the spacer layer 105, specifically including:

S51 : Please refer to FIG. 11 , forming a first nucleation layer 106 , a channel layer 107 and a barrier layer 108 on the separation layer 105 in sequence.

S52: Form isolation steps, wherein the isolation steps include first isolation steps 117 located at both ends of the buffer layer 101 along the first direction and second isolation steps 118 located at both ends of the isolation layer 105 along the first direction.

S53: forming a first groove in the barrier layer 108 .

S54: Deposit source 109 metal and drain 110 metal on the surface of the barrier layer 108 on both sides of the first groove, respectively, to form the source 109 and the drain 110 .

S55 : after depositing the gate dielectric 111 on the bottom and sidewalls of the first groove, deposit the gate 112 metal in the first groove to form the gate 112 .

S56: filling the passivation layer 113 in the gaps between the source 109 , the gate 112 and the drain 110 .

Please refer to FIG. 12, as a specific implementation manner, an isolation step is formed in S52, which specifically includes:

Etching the isolation layer and the PN junction along both ends of the first direction to form a first isolation step 117 at both ends of the buffer layer 101;

The barrier layer 108 , the channel layer 107 and the first nucleation layer 106 are etched at both ends along the first direction to form a second isolation step 118 at both ends of the isolation layer. Among them, the purpose of step isolation is to prevent a single device from being connected to the surrounding devices, so the electrical isolation is performed by means of isolation. Of course, in addition to the etching method proposed in the embodiment of the present invention, ion implantation can also be used. It is not limited here.

Please refer to FIG. 13 , as a specific implementation manner, forming a first groove in the barrier layer 108 in S53 specifically includes: using oxygen gas and boron trichloride gas to etch the gate of the barrier layer 108 cyclically; The barrier layer 108 at the trench position until the gate trench position is completely etched to form the first groove. Wherein, making the first groove will reduce the 2DEG concentration below the gate 112, and reduce the two-dimensional electron gas concentration of the entire channel, thereby raising the bottom of the conduction band below the gate 112 to a low level. Above the meter energy level, the enhanced application of the concave gate enhanced GaN HEMT is realized.

Please refer to FIG. 13. As a specific implementation, in S54, the source 109 metal and the drain 110 metal are respectively deposited on the surface of the barrier layer 108 on both sides of the first groove to form the source 109 and the drain. The electrode 110 also specifically includes: the source 109 metal and the drain 110 metal are respectively deposited on the surface of the barrier layer 108 on both sides of the first groove, and the source 109 metal and the drain 110 metal are respectively The ohmic contacts are thermally annealed to form source 109 and drain 110 .

Please refer to FIG. 14 , as a specific implementation manner, the metal material of the gate 112 in S55 and S56 is specifically TiN, the material of the gate dielectric 111 and the passivation layer 113 are both aluminum oxide, or Both are silicon nitride, and are not limited here.

Please refer to FIG. 15, FIG. 16, and FIG. 2. As a specific implementation, the anode 114 and the cathode 115 are formed in S6, specifically including:

S61 : Please refer to FIG. 15 , deposit a passivation layer 113 on the surface of the first isolation step 117 , the second isolation step 118 , and the concave gate-enhanced GaN HEMT device.

S62: Please refer to FIG. 16 , forming several openings in the passivation layer 113, and the several openings respectively penetrate to the P-type doped region 103, the source 109, the gate 112, the The drain 110 and the N-type doped region 104.

S63: Please refer to FIG. 1, deposit an electrode metal layer, the electrode metal layer fills the plurality of through holes, wherein the electrode metal layer electrically connected to the P-type doped region 103 constitutes the anode 114, and the electrode metal layer is connected to the anode 114 The electrode metal layer electrically connected to the N-type doped region 104 constitutes the cathode 115 , and the anode 114 is electrically connected to the source 109 ; the cathode 115 is electrically connected to the drain 110 .

The method for fabricating a concave-gate-enhanced GaN HEMT with anti-reverse conduction current provided by an embodiment of the present invention specifically includes forming a field plate structure 116, wherein the field plate structure 116 is deposited on the gate penetrating to the gate 112. The electrode metal layer inside the hole.

An embodiment of the present invention also provides a semiconductor device, including the concave gate enhanced GaN HEMT structure against reverse conduction current.

An embodiment of the present invention also provides an electronic device, including the electronic device.

The embodiment of the present invention also provides a method for manufacturing a semiconductor device, including the method for manufacturing a concave-gate enhanced GaN HEMT that resists reverse conduction current.

The embodiment of the present invention also provides a method for manufacturing an electronic device, the method for manufacturing a semiconductor device.

The concave gate-enhanced GaN HEMT structure against reverse conduction current provided by the embodiment of the present invention has the following beneficial effects: 1. By setting a PN junction on the top of the buffer layer 101 to suppress the off-time, the concave gate enhanced The reverse conduction current of GaN HEMT reduces the turn-off loss.

2. By setting a PN junction on the top of the buffer layer 101 to suppress the substrate 100 leakage when the concave gate enhanced GaN HEMT is turned on.

3. By setting a PN junction on the top of the buffer layer 101 to prevent the forward breakdown of the concave gate enhanced GaN HEMT device when the turn-on voltage is too large.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: It is still possible to modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the technical solutions of the various embodiments of the present invention. scope.

Claims (20)

1. The concave gate enhanced GaN HEMT structure for resisting reverse conduction current is characterized by comprising:

a substrate;

a buffer layer formed on the substrate;

the PN junction is formed on the buffer layer and comprises a P-type doped region and an N-type doped region, the N-type doped region is formed on the surface layer of part of the P-type doped region, and the P-type doped region wraps the N-type doped region;

the separation layer is formed on the PN junction and covers the P-type doped region and the N-type doped region;

the concave grid enhanced GaN HEMT device is formed on the separation layer; the concave gate enhanced GaN HEMT device comprises a first nucleation layer, a channel layer and a barrier layer which are sequentially formed on the separation layer; the barrier layer is provided with a first groove, the first groove penetrates through the barrier layer, and a gate dielectric layer and gate metal are filled in the first groove to form a gate; a source electrode and a drain electrode are respectively formed on the barrier layers at two sides of the grid electrode; and a passivation layer is filled in the gap among the source electrode, the grid electrode and the drain electrode;

the anode is electrically connected with the P-type doped region and is electrically connected to the source electrode; the cathode is electrically connected with the N-type doped region and is electrically connected to the drain electrode;

the N-type doped region covers the area under the drain electrode and extends to the area under the grid electrode.

2. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 1, further comprising a field plate structure formed on top of said gate.

3. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 1, wherein said P-type doped region and said N-type doped region are doped with magnesium ions and silicon ions, respectively.

4. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 3 wherein said P-type doped region has a doping concentration of 1 x 10 ¹⁷ ～2*10 ¹⁷ cm ^-3 The method comprises the steps of carrying out a first treatment on the surface of the Doping in N-type doped regionsThe impurity concentration is 2 x 10 ¹⁸ ～6*10 ¹⁸ cm ^-3 。

5. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 3, wherein said P-type doped region and said N-type doped region are doped with magnesium ions and silicon ions, respectively, that are activated after selective annealing.

6. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 1, wherein said substrate is a Si-based substrate.

7. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 1, wherein the material of said spacer layer comprises aluminum oxide, the material of said first nucleation layer comprises AlN, so the material of the channel layer is GaN, and the material of said barrier layer is AlGaN.

8. The reverse conduction current resistant concave gate enhanced GaN HEMT of claim 2, wherein the material of said passivation layer is aluminum oxide.

9. A method for preparing a concave gate enhanced GaN HEMT resistant to reverse conduction current, which is used for preparing the concave gate enhanced GaN HEMT structure resistant to reverse conduction current as described in any one of claims 1 to 8, and is characterized in that the method comprises the following steps:

a substrate is provided and a substrate is provided,

forming a buffer layer on top of the substrate;

forming a P-type doped region on the buffer layer, and forming an N-type doped region on the surface layer of a partial region of the P-type doped region to form a PN junction;

forming a separation layer on the PN junction, wherein the separation layer covers the P-type doped region and the N-type doped region;

forming the concave grid enhanced GaN HEMT device at the top end of the separation layer;

forming an anode and a cathode; the anode is electrically connected with the P-type doped region, and is also electrically connected with a source electrode of the concave gate enhanced GaN HEMT device; the cathode is electrically connected with the N-type doped region, and the cathode is electrically connected with the drain electrode of the concave gate enhanced GaN HEMT device;

the N-type doped region covers the area below the drain electrode and extends to the area below the grid electrode of the concave grid enhanced GaN HEMT device.

10. The method of manufacturing a reverse on-current resistant concave gate enhanced GaN HEMT of claim 9, wherein a P-type doped region is formed on said buffer layer and an N-type doped region is formed on a surface layer of a partial region of said P-type doped region to form a PN junction; the method specifically comprises the following steps:

forming a GaN layer on the buffer layer;

and forming a P-type doped region in the GaN layer, and forming an N-type doped region in the P-type doped region, wherein the P-type doped region is contacted with the N-type doped region to form a PN junction.

11. The method for preparing the concave gate enhanced GaN HEMT with reverse conduction current resistance according to claim 10, wherein forming the P-type doped region in the GaN layer comprises:

p-type ion implantation is carried out on the first area of the GaN layer;

and performing rapid thermal annealing activation or laser annealing activation on the implanted P-type ions to form the P-type doped region.

12. The method for manufacturing a reverse on-current resistant concave gate enhanced GaN HEMT of claim 11, wherein forming an N-type doped region on a surface layer of a partial region of said P-type doped region comprises:

performing N-type ion implantation on the first region of the P-type doped region;

and performing rapid thermal annealing activation or laser annealing activation on the implanted N-type ions to form the N-type doped region.

13. The method for preparing the concave gate enhanced GaN HEMT resistant to reverse on current according to claim 12, wherein the concave gate enhanced GaN HEMT device is formed at the top end of the separation layer, and specifically comprises;

sequentially forming a first nucleation layer, a channel layer and a barrier layer on the separation layer;

forming isolation steps, wherein the isolation steps comprise first isolation steps positioned at two ends of the buffer layer along a first direction and second isolation steps positioned at two ends of the separation layer along the first direction;

forming a first groove in the barrier layer;

respectively depositing source electrode metal and drain electrode metal on the surfaces of the barrier layers at two sides of the first groove to form a source electrode and a drain electrode;

depositing gate metal in the first groove after depositing gate dielectric at the bottom and the side wall of the first groove to form a gate;

and filling a passivation layer in a gap among the source electrode, the gate electrode and the drain electrode.

14. The method for preparing the concave gate enhanced GaN HEMT of reverse conduction current resistance according to claim 13, wherein said forming the isolation step comprises:

etching the isolation layer and the PN junction along two ends of the first direction to form first isolation steps at two ends of the buffer layer;

and etching the barrier layer, the channel layer and the first nucleation layer along the two ends of the first direction so as to form second isolation steps at the two ends of the isolation layer.

15. The method for manufacturing the reverse conduction current resistant concave gate enhanced GaN HEMT of claim 14, wherein the manufacturing of the anode and the cathode comprises:

depositing passivation layers on the surfaces of the first isolation step, the second isolation step and the concave gate enhanced GaN HEMT device;

forming a plurality of openings in the passivation layer, wherein the openings penetrate through the P-type doped region, the source electrode, the grid electrode, the drain electrode and the N-type doped region respectively;

depositing an electrode metal layer, wherein the electrode metal layer fills the through holes, the electrode metal layer electrically connected with the P-type doped region forms the anode, the electrode metal layer electrically connected with the N-type doped region forms the cathode, and the anode is electrically connected with the source electrode; the cathode is electrically connected with the drain electrode.

16. The method of manufacturing a reverse conduction current resistant concave gate enhanced GaN HEMT of claim 15, further comprising: a field plate structure is formed, wherein the field plate structure is the electrode metal layer deposited through into the gate opening.

17. A semiconductor device comprising the reverse conduction current resistant concave gate enhancement GaN HEMT structure of any of claims 1-8.

18. An electronic device comprising the semiconductor device of claim 17.

19. A method for manufacturing a semiconductor device, characterized in that the method for manufacturing a concave gate enhanced GaN HEMT against reverse on-current according to any one of claims 9 to 16 is used.

20. A method of manufacturing an electronic device comprising the method of manufacturing a semiconductor device according to claim 19.

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