JP2006079041A - Drive unit and display device having the same - Google Patents

Abstract

To prevent malfunction by eliminating or reducing the number of contact electrodes.
A gate driver 160 includes a circuit portion CS including a plurality of stages of subordinate connections and outputting a drive signal according to a control signal, and a wiring portion LS. The wiring portion connects the start signal wiring SL1, the first and second clock wirings SL2 and SL3, the off-voltage wiring SL4, the reset wiring SL5, the first and second clock wirings, and the off-voltage (earth voltage) wiring to a plurality of stages. A plurality of connection wirings CL1 to CL3 are included. The connection wiring that connects the first clock wiring and the first and second clock wirings to each stage is arranged in a different layer from the second clock wiring. Since the contact electrode between the first clock wiring and its connection line is not necessary, it is possible to prevent malfunction of the drive unit due to corrosion of the electrode.
[Selection] Figure 1

Description

  The present invention relates to a drive unit and a display device having the same, and more particularly to a drive unit capable of preventing malfunction and a display device having the drive unit.

Generally, a display device includes a display panel having a plurality of gate lines and a plurality of data lines, a gate driver that outputs gate signals to the plurality of gate lines, and a data driver that outputs data signals to the plurality of data lines. It comprises.
The gate driver and the data driver have a chip form and are mounted on the display panel. Recently, however, a structure in which a gate driver is built in a display panel has been developed in order to reduce the overall size of the display device and increase productivity.
The gate driver includes one shift register composed of a plurality of stages, a plurality of signal wirings for receiving input of various signals from the outside, and a plurality of connection wirings for connecting the plurality of signal wirings to the shift register. Since the plurality of signal wirings are arranged in different layers from the plurality of connection wirings, the plurality of signal wirings and the plurality of connection wirings are connected through contact electrodes.

Meanwhile, the display panel includes an array substrate having a plurality of gate lines and a plurality of data lines, a color filter substrate facing the array substrate, a liquid crystal layer interposed between the array substrate and the color filter substrate, and the array substrate. And a sealant for bonding the color filter substrate.
The gate driver is built in the array substrate of the display panel, and parasitic capacitance is generated between the gate driver and the common electrode formed on the color filter substrate. Such parasitic capacitance induces malfunction of the gate driver.
Recently, a structure in which a sealant is disposed between a gate driver and a common electrode has been proposed as a method for reducing parasitic capacitance.

However, since the sealant has hygroscopicity, moisture flows into the display panel through the sealant. The introduced moisture corrodes the contact electrode provided on the top of the gate driver. Particularly, among the plurality of signal wirings, the contact electrode that connects the signal wiring provided on the outermost surface of the array substrate and the corresponding connection wiring is most vulnerable to corrosion. As a result, the gate drive unit malfunctions due to corrosion.
Accordingly, an object of the present invention is to provide a drive unit for preventing malfunction.
Another object of the present invention is to provide a display device having the drive unit described above.

A driving unit according to one aspect of the present invention includes a circuit unit and a wiring unit. The circuit unit includes a plurality of stages connected in cascade, and outputs a drive signal in accordance with a plurality of control signals.
The wiring section includes first and second signal wirings that receive inputs of the plurality of control signals from the outside, a first connection wiring that connects the first signal wirings to the plurality of stages, and the second signal wirings, respectively. Second connection wiring connected to the plurality of stages is included. The first signal wiring, the first and second connection wirings are arranged in different layers from the second signal wiring.

According to another aspect of the present invention, a display device includes a display panel that displays an image according to a gate signal and a data signal, a data driver that generates the data signal and provides the data panel, and generates the gate signal. A gate driver provided on the display panel;
The gate driver includes a circuit unit and a wiring unit. The circuit unit includes a plurality of stages connected in cascade, and outputs a drive signal in accordance with a plurality of control signals.
The wiring unit includes first and second signal wirings that receive the plurality of control signals from outside, a first connection wiring that connects the first signal wirings to the plurality of stages, and the second signal wirings. Second connection wiring connected to the plurality of stages. The first signal wiring, the first and second connection wirings are provided in different layers from the second signal wiring.

  According to the driving unit and the display device having the driving unit, the first signal wiring farthest from the circuit unit is provided in the same layer as the first and second connection wirings, and is integrated with the corresponding first connection wiring. Formed. Therefore, a contact electrode for connecting the first signal wiring and the first connection wiring is unnecessary, and malfunction due to corrosion of the drive unit can be prevented.

Hereinafter, a preferred embodiment of the present invention will be described in more detail with reference to the drawings.
FIG. 1 is a block diagram illustrating a gate driver according to an embodiment of the present invention.
As shown in FIG. 1, the gate driver 160 according to an embodiment of the present invention includes a circuit unit CS and a wiring unit LS provided adjacent to the circuit unit CS.
The circuit unit CS includes first to n + 1th stages SRC1 to SRCn + 1 that are connected in a dependent manner, and sequentially outputs first to nth gate signals OUT1 to OUTn. Here, n is an even number.
Each of the first to n + 1th stages SRC1 to SRCn + 1 includes a first clock terminal CK1, a second clock terminal CK2, a first input terminal IN1, a second input terminal IN2, an off-voltage (usually ground potential) terminal V1, and a reset terminal. It includes RE, carry terminal CR and output terminal OUT.

  The first clock terminal CK1 of the odd-numbered stages SRC1, SRC3,..., SRCn + 1 among the first to n + 1 stages is provided with the first clock CKV, and the even-numbered stages SRC2,. A second clock CKVB having a phase different from that of the first clock CKV is provided to the first clock terminal CK1 of the SRCn. Meanwhile, the second clock terminal CK2 of the odd-numbered stages SRC1, SRC3,..., SRCn + 1 is provided with the second clock CKVB, and the second stages of the even-numbered stages SRC2,. The first clock CKV is provided to the clock terminal CK2.

A start signal STV or a gate signal from the previous stage is input to the first input terminal IN1 of each of the first to n + 1th stages SRC1 to SRCn + 1. The start signal STV for starting the operation of the circuit unit CS is provided to the first input terminal IN1 of the first driving stage SRC1.
Meanwhile, a carry signal from the next stage is input to the second input terminal IN1 of each of the first to (n + 1) th stages SRC1 to SRCn + 1. The n + 1th stage SRCn + 1 is a stage prepared as a dummy for providing a carry signal to the second input terminal IN2 of the nth stage SRCn. The start signal STV is provided to the second input terminal IN2 of the SRCn + 1 of the (n + 1) th stage instead of the carry signal from the next stage.

The off-voltage terminal V1 of the first to (n + 1) th stages SRC1 to SRCn + 1 is provided with the off-voltage (usually ground voltage) Voff, and the reset terminal RE of the first to (n + 1) th stages SRC1 to SRCn + 1 is the n + 1-th stage. The (n + 1) th gate signal output from the first stage SRCn + 1 is provided.
A gate pulse synchronized with the first clock CKV is output to the carry terminal CR and the output terminal OUT of the odd-numbered stages SRC1, SRC3,..., SRCn + 1, and the even-numbered stages SRC2,. A gate pulse synchronized with the second clock CKVB is output to the carry terminal CR and the output terminal OUT. The carry signals output from the carry terminals CR of the second to (n + 1) th stages SRC2 to SRCn + 1 are provided to the second input terminal IN2 of the previous stage. The first to nth gate signals OUT1 to OUTn output from the output terminals OUT of the first to nth stages SRC1 to SRCn are provided to the first input terminal IN1 of the next stage.

Meanwhile, the wiring part LS includes a start signal line SL1, a first clock line SL2, a second clock line SL3, an off-voltage line SL4, and a reset line SL5 that are extended in parallel to each other.
The start signal line SL1 provides the start signal STV provided from the outside to the first input terminal IN1 of the first stage SRC1 and the second input terminal IN2 of the (n + 1) th stage SRCn + 1.
The first clock line SL2 receives the input of the first clock CKV from the outside, and the second clock line SL3 receives the input of the second clock CKVB from the outside. The off-voltage line SL4 receives the off-voltage Voff from the outside, and the reset line SL5 resets the n + 1 gate signal output from the (n + 1) th stage SRCn + 1 to reset the first to (n + 1) th stages SRC1 to SRCn + 1. Provided to terminal RE.

  The reset line SL5 is closest to the circuit unit CS, and the start signal line SL1 is disposed between the reset line SL5 and the second clock line. The second clock line SL3 is disposed between the start signal line SL1 and the first clock line. The first clock line SL2 is disposed between the second clock line SL3 and the off-voltage line SL4. Accordingly, the off-voltage line SL4 is farthest away from the circuit part CS and is disposed at the outermost part of the wiring part DS.

The wiring part LS further includes first, second, and third connection wirings CL1, CL2, CL3.
The first connection line CL1 connects the off-voltage line SL4 to the off-voltage terminal V1 of the first to (n + 1) th stages SRC1 to SRCn + 1 of the circuit unit CS. The second connection wiring CL2 is connected to the first clock wiring SL2 through the odd-numbered stages SRC1, SRC3,..., SRCn + 1 of the first clock terminal CK1 and the even-numbered stages SRC2,. It is connected to the second clock terminal CK2 of SRCn. The third connection line CL3 connects the second clock line SL3 with the even-numbered stages SRC2,..., The first clock terminal CK1 and the odd-numbered stages SRC1, SRC3,. It is connected to the second clock terminal CK2 of SRCn + 1.

FIG. 2 is a layout diagram of a portion I shown in FIG. 1, and FIG. 3 is a cross-sectional view taken along the line II-II ′ of FIG.
As shown in FIG. 2, each of the first to nth stages SRC1 to SRCn of the circuit unit CS is directly connected to the output terminal OUT and controls the output of the first to nth gate signals OUT1 to OUTn. And a second circuit part CS2 for controlling driving of the first circuit part CS1.
On the other hand, the wiring portion LS includes a start signal wiring SL1, a first clock wiring SL2, a second clock wiring SL3, an off-voltage wiring SL4, and a reset wiring SL5. The wiring part LS further includes first, second, and third connection wirings CL1, CL2, CL3. As shown in FIG. 3, the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5 are made of a first metal film and disposed on the substrate 110.

The start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5 disposed on the substrate 110 are entirely covered with a gate insulating film 120.
The off-voltage line SL4 and the first to third connection lines CL1 to CL3 are made of a second metal film and disposed on the gate insulating film 120. The first to third connection wirings CL1 to CL3, the start signal wiring SL1, the first clock wiring SL2, the second clock wiring SL3, and the reset wiring SL5 are arranged in different layers, whereby the first to third wirings are arranged. The connection lines CL1 to CL3 are electrically insulated from the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5.
Meanwhile, the off-voltage line SL4 is disposed on the gate insulating film 120 together with the first connection line CL1. Accordingly, the off-voltage line SL4 and the first connection line CL1 are simultaneously patterned and formed integrally with each other. As a result, a contact electrode for electrically connecting the off-voltage line SL4 and the first connection line CL1 becomes unnecessary.

The off-voltage line SL4 and the first to third connection lines CL1 to CL3 formed on the gate insulating film 120 are entirely covered with a protective film 130. The protective layer 130 includes an inorganic insulating layer 131 and an organic insulating layer 132.
First and second contact holes C1 and C2 that expose the first clock line SL2 and the second connection line CL2 are formed in the protective layer 130 and the gate insulating layer 120. Accordingly, the first contact electrode CE1 electrically connects the first clock line SL2 exposed through the first and second contact holes C1 and C2 and the second connection line CL2. In addition, third and fourth contact holes C3 and C4 that expose the second clock wiring SL3 and the third connection wiring CL3 are further formed in the protective film 130 and the gate insulating film 120. Accordingly, the second contact electrode CE2 electrically connects the second clock line SL3 exposed through the third and fourth contact holes C3 and C4 and the third connection line CL3. For example, the first and second contact electrodes CE1 and CE2 include indium tin oxide (hereinafter referred to as ITO) or indium zinc oxide (hereinafter referred to as IZO).

As described above, the first clock line SL2 and the second connection line CL2 are arranged in different layers and are electrically connected by the first contact electrode CE1, and the second clock line SL3 and the third connection line are connected. It is arranged in a layer different from CL3 and is electrically connected by the second contact electrode CE2.
The first to third connection lines CL1 to CL3 are disposed in different layers from the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5. Each of the connection wirings CL1 to CL3 is electrically insulated from the signal wirings SL1, SL2, SL3, and SL5 that do not correspond to each other.

Here, the off-voltage line SL4 is disposed outside the substrate 110 with respect to the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5, and the second and third connection lines CL2. , Does not overlap with CL3.
Accordingly, the off-voltage line SL4 can be disposed in the same layer as the first to third connection lines CL1 to CL3. As a result, a contact electrode for electrically connecting the off-voltage line SL4 and the first connection line CL1 becomes unnecessary, and the number of contact electrodes formed in the gate driver 160 is reduced. Further, the wiring resistance increased by the contact electrode can be reduced, and the corrosion of the gate driver 160 due to the contact electrode can be reduced.

FIG. 4 is a circuit diagram of the first stage shown in FIG. Since the first stage SRC1 has the same configuration as the second to (n + 1) th stages SRC2 to SRCn + 1, the internal configuration of the first stage SRC1 will be described with reference to FIG. Instead of description of the internal configuration of each of the stages SRC2 to SRCn + 1.
As shown in FIG. 4, the first stage SRC1 includes a pull-up unit 161 and a second stage (SRC2) that pull up the first gate signal output from the output terminal OUT to the first clock (CKV, shown in FIG. 1). 1 includes a pull-down unit 162 that pulls down the first gate signal pulled up in response to a carry signal from FIG. 1 to an off voltage (ground potential).

The pull-up unit 161 includes a first transistor NT1 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the output terminal OUT. The pull-down unit 162 includes a second transistor NT2 having a gate electrode connected to the second input terminal IN2, a drain electrode connected to the output terminal OUT, and a source electrode provided with an off voltage Voff.
The first stage SRC1 further includes a pull-up driver that turns on the pull-up unit 161 in response to a start signal and turns off the pull-up unit 161 in response to a carry signal from the second stage SRC2. The pull-up driving unit includes a buffer unit 163, a charging unit 164, and a first discharging unit 165.

The buffer unit 163 includes a third transistor NT3 having a gate and a drain electrode commonly connected to the first input terminal IN1 and a source electrode connected to the first node N1. The charging unit 164 includes a first capacitor C1 having a first electrode connected to the first node N1 and a second electrode connected to the second node N2. The first capacitor C1 constitutes a bootstrap circuit together with the first transistor NT1. The first discharge unit 165 includes a fourth transistor NT4 having a gate electrode connected to the second input terminal IN2, a drain electrode connected to the first node N1, and a source electrode provided with the off voltage Voff. .
When the third transistor NT3 is turned on according to the start signal, the first capacitor C1 is charged. When the first capacitor C1 is charged with a charge equal to or higher than the threshold voltage of the first transistor NT1, the first transistor NT1 is turned on to output a high period of the first clock CKV to the output terminal OUT. Thereafter, when the fourth transistor NT4 is turned on in response to a carry signal from the subsequent stage, the charge charged in the first capacitor C1 is discharged to the off voltage (earth voltage) Voff.

The first stage SRC1 includes a holding unit 166 that holds the first gate signal in the state of the off voltage Voff, and a second discharge unit that discharges the first gate signal to the off voltage Voff according to a second clock CKVB. 167 and a switching unit 168 for controlling driving of the holding unit 166.
The holding unit 166 includes a fifth transistor NT5 having a gate electrode connected to the third node N3, a drain electrode connected to the second node N2, and a source electrode provided with the off voltage Voff. The second discharge part 167 includes a sixth transistor NT6 having a gate electrode connected to the second clock terminal CK2, a drain electrode connected to the second node N2, and a source electrode provided with the off voltage Voff.
The switching unit 168 includes seventh to tenth transistors NT7, NT8, NT9, NT10, and second and third capacitors C2, C3.

The gate electrode and the drain electrode of the seventh transistor NT7 are commonly connected to the first clock terminal CK1, and the source electrode is connected to the third node N3. The drain electrode of the eighth transistor NT8 is connected to the first clock terminal CK1, the gate electrode is connected to the first clock terminal CK1 through the second capacitor C2, and the source electrode is connected to the third node N3. . The third capacitor C3 is connected between the gate electrode and the source electrode of the eighth transistor NT8.
The gate electrode of the ninth transistor NT9 is connected to the second node N2, the drain electrode is connected to the source electrode of the seventh transistor NT7, and the off voltage Voff is provided to the source electrode. The gate electrode of the tenth transistor NT10 is connected to the second node, the drain electrode is connected to the third node N3, and the off voltage Voff is provided to the source electrode.

  When the first clock CKV is output to the output terminal OUT via the first transistor NT1 with the seventh and eighth transistors NT7 and NT8 turned on by the first clock CKV, the second node The potential of N2 is raised to a high state. As the potential at the second node N2 is increased, the ninth and tenth transistors NT9 and NT10 are turned on, and the voltages at the drain terminals of the seventh and eighth transistors NT7 and NT8 are the ninth and tenth transistors. The off voltage Voff is obtained through the transistors NT9 and NT10. Accordingly, the potential of the third node N3 is maintained in a low state, and the fifth transistor NT5 is turned off.

Thereafter, when the first gate signal is discharged to the off voltage Voff by a carry signal from the subsequent stage, the potential of the second node N2 gradually falls to a low state. Accordingly, the ninth and tenth transistors NT9 and NT10 are turned off, and the potential of the third node N3 is gradually increased by the voltages output from the seventh and eighth transistors NT7 and NT8. As the potential of the third node N3 is increased, the fifth transistor NT5 is turned on. The turned-on fifth transistor NT5 causes the potential of the second node N2 to be further lowered to the off voltage Voff. The
In this state, when the sixth transistor NT6 is turned on by the second clock CKVB provided to the second clock terminal CK2, the potential of the second node N2 is reliably discharged to the off voltage Voff. The

Meanwhile, the first stage SRC1 further includes a carry unit 169, a ripple prevention unit 170, and a reset unit 171.
The carry unit 169 includes an eleventh transistor NT11 having a gate electrode connected to the first node N1, a drain electrode connected to the first clock terminal CK1, and a source electrode connected to the carry terminal CR. The eleventh transistor NT11 is turned on when the potential of the first node N1 is increased, and outputs the first clock CKV input to the drain electrode as a carry signal to the carry terminal CR.

The ripple prevention unit 170 includes twelfth and thirteenth transistors NT12 and NT13. The gate electrode of the twelfth transistor NT12 is connected to the first clock terminal CK1, the drain electrode is connected to the source electrode of the thirteenth transistor NT13, and the source electrode is connected to the second node N2. The gate electrode of the thirteenth transistor NT13 is connected to the second clock terminal CK2, the drain electrode is connected to the first input terminal IN1, and the source electrode is connected to the drain electrode of the eleventh transistor NT11.
The ripple prevention unit 170 prevents the first gate signal from being rippled by the first and second clocks CK1 and CK2 after being discharged to the off voltage Voff.

  The reset unit 171 includes a fourteenth transistor NT14 having a gate electrode connected to the reset terminal RE, a drain electrode connected to the first input terminal IN1, and a source electrode provided with the off voltage Voff. When the (n + 1) th gate signal is provided to the reset terminal RE, the fourteenth transistor NT14 is turned on to discharge the signal provided through the first input terminal IN1 to the off voltage Voff. Accordingly, the third transistor NT3 can be prevented from being turned on by a signal provided through the first input terminal IN1.

FIG. 5 is a plan view of a display device according to another embodiment of the present invention, and FIG. 6 is a cross-sectional view taken along line III-III ′ of FIG.
Referring to FIGS. 5 and 6, a display device 400 according to another embodiment of the present invention includes a display panel 300 that displays an image according to first and second driving signals, and the display panel 300 includes the display panel 300. The display panel 300 includes a data driver 150 and a gate driver 160 for outputting the first and second driving signals, respectively.
The display panel 300 includes an array substrate 100, a color filter substrate 200 facing the array substrate 100, a liquid crystal layer 330 interposed between the array substrate 100 and the color filter substrate 200, and the array substrate 100 and the color. A sealant 350 that bonds the filter substrate 200 is included.

The display panel 300 includes a display area DA that displays the image, a seal line area SA that surrounds the display area DA, a first peripheral area PA1 that is disposed outside the seal line area SA, the display area DA, and the seal. A second peripheral area PA2 arranged between a part of the line area SA is included.
The first to nth gate lines GL1 to GLn and the first to mth data lines DL1 to DLm are formed on the first substrate 110 of the array substrate 100 corresponding to the display area DA. The first to nth gate lines GL1 to GLn intersect the first to mth data lines DL1 to DLm so as to be insulated from each other. In addition, a plurality of thin film transistors and a plurality of liquid crystal capacitors are further formed on the first substrate 110 corresponding to the display area DA.
For example, among the plurality of thin film transistors, the gate electrode of the first thin film transistor TR1 is electrically connected to the first gate line GL1, and the source electrode of the first thin film transistor TR1 is electrically connected to the first data line DL1. The drain electrode of the first thin film transistor TR1 is connected to the first liquid crystal capacitor Cl among the plurality of liquid crystal capacitors.

A color filter layer 220 including red, green, and blue pixels R, G, and B and the red, green, and blue pixels are disposed on the second substrate 210 of the color filter substrate 200 corresponding to the display area DA. A first light shielding layer 230 formed between two adjacent color pixels of R, G, and B is disposed. A second light shielding layer 240 is disposed on the second substrate corresponding to the seal line area SA. A common electrode 250 is formed on the entire surface of the second substrate 210 on which the color filter layer 220 and the first and second light shielding layers 230 and 240 are disposed.
Meanwhile, in the first peripheral area PA1, the first substrate 110 of the array substrate 100 extends longer than the second substrate 210 of the color filter substrate 200, and the first substrate 110 corresponds to the first peripheral area PA1. The data driver 150 in the form of a chip is mounted on the top. The data driver 150 is electrically connected to the first to mth data lines DL1 to DLm formed in the display area DA. The first driving signal output from the data driver 150 includes first to mth data signals, and the first to mth data signals are applied to the first to mth data lines DL1 to DLm.

Meanwhile, the gate driver 160 is formed at the same time through the same process as the plurality of thin film transistors in a part of the seal line area SA adjacent to the second peripheral area PA2 and the second peripheral area PA2. The gate driver 160 is electrically connected to the first to nth gate lines GL1 to GLn formed in the display area DA. The second driving signal output from the gate driver 160 includes first to nth gate signals (OUT1 to OUTn, illustrated in FIG. 1), and the first to nth gate signals are the first to nth gate signals. Applied to n gate lines GL to GLn.
The liquid crystal layer 330 is interposed between the color filter substrate 200 and the array substrate 100 corresponding to the display area DA and the second peripheral area PA2, and the array substrate 100 is disposed in the seal line area SA. And the color filter substrate 200 are formed.

The sealant 350 covers a part of the gate driver 160 formed in the seal line area SA. Accordingly, the sealant 350 prevents the common electrode 250 and the gate driver 160 from being electrically shorted by a conductive foreign material.
Further, the sealant 350 having a dielectric constant smaller than that of the liquid crystal layer 330 is interposed between the common electrode 250 and the gate driver 160, so that the sealant 350 is generated between the common electrode 250 and the gate driver 160. Parasitic capacitance is reduced. Accordingly, malfunction of the gate driver 160 can be prevented.

FIG. 7 is an enlarged cross-sectional view showing a region corresponding to II-II ′ of FIG. 2 and a part of a display region where gate lines are formed in the array substrate shown in FIG.
As shown in FIG. 7, the start signal line SL1, the first clock line SL2, the second clock line SL3, the reset line SL5, and the first gate line GL1 are disposed on the first substrate 110 made of the first metal film. . For example, the first metal film has a single film structure including aluminum Al series metal, silver Ag series metal, copper Cu series metal, molybdenum Mo series metal, chromium Cr, tantalum Ta or titanium Ti.
Meanwhile, the first metal film may have a double film structure including a lower film and an upper film provided on the lower film and having physical properties different from those of the lower film. The upper layer includes a low non-resistance metal such as an aluminum Al series metal, a silver Ag series metal, or a copper Cu series metal so that signal delay and voltage drop can be reduced. The lower film includes a material having excellent contact characteristics with ITO and IZO, for example, chromium Cr, molybdenum Mo, molybdenum Mo alloy, tantalum Ta, or titanium Ti.

As a preferred embodiment of the present invention, the first metal film having a double film structure may include an upper film made of aluminum neodymium AINd and a lower film made of molybdenum tungsten MoW.
The start signal line SL1, the first clock line SL2, the second clock line SL3, the reset line SL5, and the first gate line GL1 provided on the first substrate 110 are entirely covered with a gate insulating film 120. .
The off-voltage line SL4, the first to third connection lines CL1 to CL3, and the first data line DL1 are made of a second metal film and disposed on the gate insulating film 120. Here, the second metal film may have a single film structure made of chromium Cr or a triple film structure made of molybdenum tungsten MoW, aluminum neodymium AlNd, and molybdenum tungsten MoW, which are sequentially stacked.

The first to third connection lines CL1 to CL3 are arranged in different layers from the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5. Accordingly, the first to third connection lines CL1 to CL3 are electrically insulated from the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5.
The off-voltage line SL4 is disposed on the gate insulating film 120 together with the first connection line CL1. Accordingly, the off-voltage line SL4 and the first connection line CL1 are simultaneously patterned and formed integrally with each other. As a result, a contact electrode for electrically connecting the off-voltage line SL4 and the first connection line CL1 becomes unnecessary.

Thereafter, the off-voltage line SL4 and the first to third connection lines CL1 to CL3 formed on the gate insulating film 120 are entirely covered with a protective film 130. The protective layer 130 includes an inorganic insulating layer 131 and an organic insulating layer 132.
The first clock line SL2 and the second connection line CL2 arranged in different layers are electrically connected by the first contact electrode CE1, and the second clock line SL3 and the third connection line arranged in different layers. CL3 is connected to the second contact electrode CE2. On the other hand, the off-voltage line SL4 and the first connection line CL1 are integrally formed because they are arranged in the same layer.
The first to third connection lines CL1 to CL3 are disposed in different layers from the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5. Each of the connection wirings CL1 to CL3 is electrically insulated from the signal wirings SL1, SL2, SL3, and SL5 that do not correspond to each other.

Here, since the off-voltage line SL4 is disposed outside the substrate 110 with respect to the start signal line SL1, the first clock line SL2, the second clock line SL3, and the reset line SL5, the second and third connection lines Does not overlap with CL2 and CL3.
Therefore, the off-voltage line SL4 can be disposed in the same layer as the first to third connection lines CL1 to CL3. As a result, a contact electrode for electrically connecting the off-voltage line SL4 and the first connection line CL1 becomes unnecessary. Accordingly, the number of contact electrodes formed in the gate driver 160 is reduced, and the wiring resistance increased by the contact electrodes can be reduced.
Further, even if the off-voltage wiring SL4 is exposed to the outside due to misalignment of a sealant (350, shown in FIG. 6), the corrosion rate of the gate driver 160 due to contact electrodes can be reduced, and as a result, the gate driver 160 malfunctions can be prevented.

FIG. 8 is a cross-sectional view of an array substrate according to still another embodiment of the present invention.
As shown in FIG. 8, on the first substrate 110 of the array substrate according to another embodiment of the present invention, an off-voltage line SL5 made of a first metal film, first to third connection lines CL1 to CL3, and first One gate line GL1 is arranged.
The off-voltage line SL5, the first to third connection lines CL1 to CL3, and the first gate line GL1 disposed on the first substrate 110 are covered with a gate insulating film 120. A start signal line SL1, first and second clock lines SL2, SL3, a reset line SL5, and a first data line DL1 are disposed on the gate insulating layer 120.
The start signal line SL1, the first and second clock lines SL2 and SL3, the reset line SL5, and the first data line DL1 disposed on the gate insulating layer 120 are covered with a protective layer 130.

The first clock line SL2 and the second connection line CL2 arranged in different layers are electrically connected by the first contact electrode CE1, and the third clock line SL3 and the third connection line arranged in different layers are connected to each other. The wiring CL3 is connected to the second contact electrode CE2. On the other hand, the off-voltage line SL4 and the first connection line CL1 are integrally formed because they are arranged in the same layer.
Accordingly, a contact electrode for electrically connecting the off-voltage line SL4 and the first connection line CL1 becomes unnecessary, and the number of contact electrodes formed in the gate driver 160 is reduced. Thereby, the wiring resistance increased by the contact electrode can be reduced, and corrosion of the gate driver 160 by the contact electrode can be prevented.

1 to 8 show a structure in which the off-voltage line SL4 is arranged in the same layer as the first to third connection lines CL1 to CL3 as an embodiment of the present invention.
However, if any one of the first and second clock lines SL2 and SL3 other than the off-voltage line SL4 is disposed adjacent to the outline of the array substrate, the first or second clock lines SL2 and SL3 are 1 to 1. Arranged in the same layer as the third connection lines CL1 to CL3. In this case, the first or second clock lines SL2 and SL3 are formed integrally with the second or third connection lines CL2 and CL3, respectively. Accordingly, the first or second contact electrode CE1, CE2 can be eliminated, and as a result, the gate driver 160 can be prevented from being corroded by the first or second contact electrode CE1, CE2.

  As described above, the embodiments of the present invention have been described in detail. However, the present invention is not limited to these embodiments, and any technical knowledge to which the present invention belongs can be used without departing from the spirit and spirit of the present invention. The present invention can be modified or changed.

4 is a block diagram specifically illustrating a gate driver according to an exemplary embodiment of the present invention. FIG. It is a layout of I part shown by FIG. FIG. 3 is a cross-sectional view taken along the line II-II ′ in FIG. 2. FIG. 2 is a circuit diagram of a first stage shown in FIG. 1. It is a top view of the display device by other embodiments of the present invention. FIG. 6 is a cross-sectional view taken along line III-III ′ in FIG. 5. FIG. 7 is an enlarged cross-sectional view illustrating a region corresponding to II-II ′ in FIG. 2 and a part of a display region in which gate lines are formed in the array substrate illustrated in FIG. 6. FIG. 10 is a cross-sectional view of an array substrate according to still another embodiment of the present invention.

Explanation of symbols

100 array substrate 110 substrate 120 gate insulating film 130 protective film 150 data driver 160 gate driver 200 color filter substrate 300 display panel 330 liquid crystal layer 350 sealant 400 display device

Claims (19)

A circuit unit including a plurality of stages connected in a dependent manner and outputting a drive signal in response to a plurality of control signals;
First and second signal lines that receive the input of the plurality of control signals from the outside, a first connection line that connects the first signal lines to the plurality of stages, and the second signal line to the plurality of stages A second connecting wiring to be connected, wherein the first signal wiring, the first and second connecting wirings are arranged in layers different from the second signal wiring, and
A drive unit comprising: The drive unit according to claim 1, wherein the second signal line is interposed between the first signal line and the circuit unit. The drive unit according to claim 2, wherein the first signal wiring is formed integrally with the first connection wiring. The second signal wiring is
A start signal wiring for receiving an input of a start signal for starting the operation of the circuit unit from the outside;
A first clock wiring for receiving a first clock input from the outside;
A second clock wiring for receiving an input of a second clock having a phase different from that of the first clock from the outside;
The drive unit according to claim 1, comprising: The first signal wiring is an off-voltage wiring that receives an off-voltage input from the outside,
5. The drive unit according to claim 4, wherein the start signal wiring, the first and second clock wirings are interposed between the first signal wiring and the circuit unit. Each of the plurality of stages is
An input terminal for receiving a start signal or a drive signal from the previous stage;
A first clock terminal for receiving an input of a first or second clock;
A second clock terminal for receiving an input of the second or first clock;
An off-voltage terminal for receiving an off-voltage input;
A control terminal for receiving a carry signal from the next stage;
A carry terminal for outputting a carry signal;
An output terminal for outputting the drive signal;
The drive unit according to claim 1, comprising: The drive unit according to claim 6, wherein each of the plurality of stages includes a reset terminal that receives an input of a drive signal from the last stage. 8. The driving unit according to claim 7, wherein the second signal wiring further includes a reset wiring for providing the driving signal from the last stage to the plurality of stages. A display panel for displaying an image according to a gate signal and a data signal;
A data driver that generates and provides the data signal to the display panel;
A gate driver for generating the gate signal and providing it to the display panel;
Including
The gate driver is
A circuit unit including a plurality of stages connected in a dependent manner and outputting a drive signal in response to a plurality of control signals;
First and second signal lines that receive the plurality of control signals from outside, a first connection line that connects the first signal lines to the plurality of stages, and a second signal line that connects the plurality of stages. A second connection wiring to be connected to the first signal wiring, the first and second connection wirings are arranged in layers different from the second signal wiring, and
A display device comprising: The display device according to claim 9, wherein the gate driver is formed on the display panel. The display panel is
A first display substrate formed with the gate driver for outputting the gate signal, a plurality of gate lines for receiving the input of the gate signal, and a plurality of data lines for receiving the input of the data signal;
A second display substrate coupled to face the first display substrate;
The display device according to claim 9, comprising: The plurality of gate lines are disposed in a first layer, and the plurality of data lines are disposed in a second layer different from the first layer and intersect with each other so as to be insulated from the plurality of gate lines. Item 12. The display device according to Item 11. The second signal wiring is disposed on the first layer;
13. The display device according to claim 12, wherein the first signal wiring, the first and second connection wirings are arranged in the second layer. 14. The display device according to claim 13, wherein the first signal wiring, the first connection wiring, and the second connection wiring have a triple film structure in which molybdenum tungsten, aluminum, and molybdenum tungsten are sequentially stacked. The display device according to claim 13, wherein the first signal wiring and the first connection wiring are integrally formed. The first signal wiring, the first and second connection wirings are disposed on the first layer,
The display device according to claim 12, wherein the second signal wiring is disposed in the second layer. The display panel is
A liquid crystal layer formed between the first display substrate and the second display substrate;
The first display substrate and the second display substrate are coupled to each other between the first display substrate and the second display substrate, and partially overlap the gate driver formed on the first display substrate. A coupling member;
The display device according to claim 11, further comprising: The second signal wiring is
A start signal wiring for receiving an input of a start signal for starting the operation of the circuit unit from the outside;
A first clock wiring for receiving a first clock input from the outside;
A second clock wiring for receiving an input of a second clock having a phase different from that of the first clock from the outside;
The display device according to claim 9, comprising: The first signal wiring is an off-voltage wiring that receives an off-voltage input from the outside,
19. The display device according to claim 18, wherein the start signal line and the first and second clock lines are provided between the first signal line and the circuit unit.

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