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CN101727859B - Grid electrode driving device of liquid display crystal - Google Patents

Grid electrode driving device of liquid display crystal Download PDF

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Publication number
CN101727859B
CN101727859B CN 200810224096 CN200810224096A CN101727859B CN 101727859 B CN101727859 B CN 101727859B CN 200810224096 CN200810224096 CN 200810224096 CN 200810224096 A CN200810224096 A CN 200810224096A CN 101727859 B CN101727859 B CN 101727859B
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shift register
register cell
reset
film transistor
connects
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CN101727859A (en
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商广良
韩承佑
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BOE Technology Group Co Ltd
Beijing BOE Optoelectronics Technology Co Ltd
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Beijing BOE Optoelectronics Technology Co Ltd
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Abstract

The invention discloses a grid driving device of a liquid crystal display, which comprises n displacement register units, a clock signal line, a power signal line and a grid driving signal output end, and also comprises a reset unit. The reset unit is connected with the lock signal line, and the power signal line and the nth displacement register unit and used for generating a reset signal which lasts longer than or as long as the grid driving signal after the grid driving signal output end of the nth displacement register unit outputs the grid driving signal, so the grid driving signal output end of the nth displacement register unit can reset. The grid driving device of the liquid crystal display provided by the invention can generate the reset signal which lasts longer than or as long as the grid driving signal and can ensure the reliable reset of the nth displacement register; and the reset unit covers a small area in the liquid crystal display screen, without causing obvious increase of difficulty for designing the screen.

Description

LCD device grid drive device
Technical field
The present invention relates to the liquid crystal technology field, relate in particular to a kind of LCD device grid drive device.
Background technology
LCD device grid drive device is used to grid line drive signal is provided, and comprises a plurality of shift register cells.The typical reset mode of shift register cell has two kinds.Be depicted as liquid crystal display grate drive device structural representation in the prior art shift register cell reset mode one like Fig. 1 a, be depicted as the sequential chart of prior art shift register cell reset mode one like Fig. 1 b.Each shift register cell (Shift Register wherein; Abbreviation SR) includes power supply signal input end (POWERIN), clock signal input terminal (CLOCKIN), gate drive signal output terminal (OUT), signal input part (INPUT) and reset signal input end (RESETIN); Except that first shift register cell and last shift register cell; The signal input part of the reset signal input end of the upper level shift register cell that the gate drive signal output terminal of each shift register cell is equal and adjacent with self and the next stage shift register cell adjacent with self is connected; The signal input part of first shift register cell (INPUT) incoming frame start signal (STV), the reset signal output terminal (RESETOUT) of last shift register cell (SRn+1) and the reset signal input end (RESETIN) of the upper level shift register cell (SRn) that is adjacent and the reset signal input end (RESETIN) of self is connected.The gate drive signal output terminal of each shift register cell all connects a grid line (GL), is used to this grid line drive signal is provided.The power supply signal input end (POWERIN) of each shift register cell, clock signal input terminal (CLOCKIN) all receive the power supply signal and the clock signal of input through power supply signal line A and clock cable B.Clock signal can comprise first clock signal (CLK) and second clock signal (CLKB), also can comprise more clock signal.
Among Fig. 1 b, the gate drive signal output terminal of each shift register cell whenever at a distance from high level of frame time output, open by the thin film transistor (TFT) (TFT) of control corresponding line, thereby realize lining by line scan of LCD.The high level of last shift register cell (SRn+1) output is simultaneously as the reset signal of self and upper level shift register cell (SRn).Can see in last shift register cell (SRn+1) in the reset signal input end (RESETIN) that reset signal (RESETOUT) duration of input is shorter, can cause last shift register cell (SRn) like this and the upper level shift register cell (SRn) that is adjacent reset unreliable.
Be depicted as liquid crystal display grate drive device structural representation in the prior art shift register cell reset mode two like Fig. 2 a, be depicted as the sequential chart of prior art shift register cell reset mode two like Fig. 2 b.Fig. 2 a is with the difference of Fig. 1 a: the reset signal input end (RESETIN) of last shift register cell (SRn+1) provides the signal source (RESET) of reset signal to be connected with special being used to; Reseting signal line C the reset signal input end (RESETIN) from signal source (RESET) to a last shift register cell (SRn+1) need be provided separately; The time that the reset signal (RESETOUT) of signal source (RESET) output is kept is long; Can guarantee to reset reliably; But need to increase a reseting signal line C; Make the LCDs design difficulty increase, and need to generate special signal source (RESET), improved the difficulty of signal controlling.Even adopt the signal of frame start signal (STV) as signal source (RESET), existence needs to increase the problem of a reseting signal line too.
Summary of the invention
The objective of the invention is to the problem that exists in the prior art; A kind of LCD device grid drive device is provided; Can guarantee the reliable reset of each shift register cell in the LCD device grid drive device; And can too much not take the area of LCDs, can not cause the remarkable increase of screen design difficulty.
For realizing above-mentioned purpose, the invention provides a kind of LCD device grid drive device, comprise n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, also comprise reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number.
Above-mentioned reset unit can be in the following structure any one:
First kind: said reset unit comprises: the first film transistor and second thin film transistor (TFT);
The transistorized grid of said the first film connects first clock signal input terminal that links to each other with said clock cable; Drain electrode connects high voltage signal input end or said first clock signal input terminal that links to each other with said power supply signal line, and source electrode connects the drain electrode of said second thin film transistor (TFT) and the reset signal output terminal of said reset unit;
The grid of said second thin film transistor (TFT) connects the second clock signal input part that links to each other with said clock cable, and drain electrode connects the transistorized source electrode of said the first film, and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal that said reset unit produces.
Second kind: said reset unit also is connected with the gate drive signal output terminal of n-1 shift register cell;
Said reset unit comprises: the first film transistor and second thin film transistor (TFT);
The transistorized grid of said the first film connects first clock signal input terminal that links to each other with said clock cable; Drain electrode connects high voltage signal input end or said first clock signal input terminal that links to each other with said power supply signal line, and source electrode connects the drain electrode of said second thin film transistor (TFT) and the reset signal output terminal of said reset unit;
The grid of said second thin film transistor (TFT) connects first signal input part; Said first signal input part connects the gate drive signal output terminal of n-1 shift register cell; Drain electrode connects the transistorized source electrode of said the first film, and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said reset signal output terminal is used to export the reset signal that said reset unit produces.
The third: said reset unit also is connected with the gate drive signal output terminal of n shift register cell;
Said reset unit comprises: the first film transistor, second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);
Said the first film transistor drain connects the second clock signal input part that links to each other with said clock signal signal wire, and source electrode connects the reset signal output terminal of said reset unit;
The drain electrode of said second thin film transistor (TFT) connects the transistorized source electrode of said the first film, and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects first clock signal input terminal;
The grid of said the 3rd thin film transistor (TFT) connects the secondary signal input end; Said secondary signal input end connects the gate drive signal output terminal of n shift register cell; The high voltage signal input end that drain electrode connects said grid or links to each other with said power supply signal line, source electrode connects the transistorized grid of said the first film;
The drain electrode of said the 4th thin film transistor (TFT) connects the source electrode of said the 3rd thin film transistor (TFT), and source electrode connects said low voltage signal input end, and grid connects said first clock signal input terminal;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal that said reset unit produces.
Or, in this LCD device grid drive device, also comprising at least one Load Balance Unit, said Load Balance Unit is used to keep being input to all load clock signals equilibriums of said LCD device grid drive device; And the number of said Load Balance Unit is one, and the clock signal number of importing said LCD device grid drive device is 2 o'clock,
Above-mentioned reset unit can also be in the following structure any one:
The 4th kind: said reset unit comprises the one one thin film transistor (TFT) and the one or two thin film transistor (TFT), and said Load Balance Unit comprises the 21 thin film transistor (TFT) and the two or two thin film transistor (TFT);
The drain electrode of said the one one thin film transistor (TFT) connect grid or with the high voltage signal input end of said power supply signal line; Source electrode connects the drain electrode of said the one or two thin film transistor (TFT) and the reset signal output terminal of said reset unit, and grid connects first clock signal input terminal that links to each other with said clock cable;
The drain electrode of said the one or two thin film transistor (TFT) connects the source electrode of said the one one thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects the gate drive signal output terminal of n-1 shift register cell;
The drain electrode of said the 21 thin film transistor (TFT) connect grid or with the high voltage signal input end of said power supply signal line; Source electrode connects the drain electrode of said the two or two thin film transistor (TFT) and the reset signal output terminal of said Load Balance Unit, and grid connects the input end of the second clock signal that links to each other with said clock cable;
The drain electrode of said the two or two thin film transistor (TFT) connects the source electrode of said the 21 thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects z 1The gate drive signal output terminal of-1 shift register cell; z 1Be the number of the shift register cell that is in said Load Balance Unit higher level, z 1Be less than or equal to n-1, z 1Be natural number;
Reset signal output terminal in the said reset unit connects the reset signal input end of said n shift register cell, and the reset signal output terminal connects said z in the said Load Balance Unit 1The reset signal input end of individual shift register cell;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal of said reset unit or the generation of said Load Balance Unit.
The 5th kind: said reset unit comprises the one one thin film transistor (TFT) and the one or two thin film transistor (TFT), and said Load Balance Unit comprises the 21 thin film transistor (TFT) and the two or two thin film transistor (TFT);
The grid of said the one one thin film transistor (TFT) connects first clock signal input terminal that links to each other with said clock cable; Drain electrode connects high voltage signal input end or said first clock signal input terminal that links to each other with said power supply signal line, and source electrode connects the drain electrode of said the one or two thin film transistor (TFT) and the reset signal output terminal of said reset unit;
The grid of said the one or two thin film transistor (TFT) connects the second o'clock signal input part that links to each other with said clock cable, and drain electrode connects the source electrode of said the one one thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
The grid of said the 21 thin film transistor (TFT) connects the second clock signal input part that links to each other with said clock cable; Drain electrode connects high voltage signal input end or the said second clock signal input part that links to each other with said power supply signal line, and source electrode connects the drain electrode of said the two or two thin film transistor (TFT) and the reset signal output terminal of said Load Balance Unit;
The grid of said the two or two thin film transistor (TFT) connects the first o'clock signal input part that links to each other with said clock cable, and drain electrode connects the source electrode of said the 21 thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
Reset signal output terminal in the said reset unit connects the reset signal input end of said n shift register cell; Reset signal output terminal in the said Load Balance Unit connects said z 1The reset signal input end of individual shift register cell; z 1Be the number of the shift register cell that is in said Load Balance Unit higher level, z 1Be less than or equal to n-1, z 1Be natural number;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal of said reset unit or the generation of said Load Balance Unit.
The 6th kind: said reset unit comprises the one one thin film transistor (TFT), the one or two thin film transistor (TFT), the one or three thin film transistor (TFT) and the one or four thin film transistor (TFT), and said Load Balance Unit comprises the 21 thin film transistor (TFT), the two or two thin film transistor (TFT), the two or three thin film transistor (TFT) and the two or four thin film transistor (TFT);
The drain electrode of said the one one thin film transistor (TFT) connects the second clock signal input part that links to each other with said clock cable, and source electrode connects the reset signal output terminal of said reset unit;
The drain electrode of said the one or two thin film transistor (TFT) connects the source electrode of said the one one thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects first clock signal input terminal that links to each other with said clock cable;
The high voltage signal input end that the drain electrode of said the one or three thin film transistor (TFT) connects grid or links to each other with said power supply signal line, source electrode connects the grid of said the one one thin film transistor (TFT), and grid connects the gate drive signal output terminal of n shift register cell;
The drain electrode of said the one or four thin film transistor (TFT) connects the source electrode of said the one or three thin film transistor (TFT), and source electrode connects said low voltage signal input end, and grid connects said first clock signal input terminal;
The drain electrode of said the 21 thin film transistor (TFT) connects first clock signal input terminal that links to each other with said clock cable, and source electrode connects the reset signal output terminal of said Load Balance Unit;
The drain electrode of said the two or two thin film transistor (TFT) connects the source electrode of said the 21 thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects the second clock signal input part that links to each other with said clock cable;
The high voltage signal input end that the drain electrode of said the two or three thin film transistor (TFT) connects grid or links to each other with said power supply signal line, source electrode connects the grid of said the 21 thin film transistor (TFT), and grid connects z 1The gate drive signal output terminal of individual shift register cell; z 1Be the number of the shift register cell that is in said Load Balance Unit higher level, z 1Be less than or equal to n-1, z 1Be natural number;
The drain electrode of said the two or four thin film transistor (TFT) connects the source electrode of said the two or three thin film transistor (TFT), and source electrode connects said low voltage signal input end, and grid connects said second clock signal input part;
The reset signal output terminal connects said z in the said Load Balance Unit 1The reset signal input end of individual shift register cell, the reset signal output terminal in the said reset unit connects the reset signal input end of said n shift register cell;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal of said reset unit or Load Balance Unit generation.
The present invention is through increasing reset unit in LCD device grid drive device, can produce the duration more than or equal to the reset signal of gate drive signal duration, can guarantee that n shift register cell resets reliably; And this reset unit shared area in LCDs can be accomplished less; Can not cause the remarkable increase of screen design difficulty; The input signal of reset unit adopts the signal of available liquid crystal display apparatus grid drive unit; Need not import new signal, can not cause the raising of signal controlling difficulty, convenient resetting of realizing LCD device grid drive device reliably.
Through accompanying drawing and embodiment, technical scheme of the present invention is done further detailed description below.
Description of drawings
Fig. 1 a is depicted as liquid crystal display grate drive device structural representation in the prior art shift register cell reset mode one;
Fig. 1 b is depicted as the sequential chart of prior art shift register cell reset mode one;
Fig. 2 a is depicted as liquid crystal display grate drive device structural representation in the prior art shift register cell reset mode two;
Fig. 2 b is depicted as the sequential chart of prior art shift register cell reset mode two;
Shown in Figure 3 is LCD device grid drive device embodiment one structural representation of the present invention;
Fig. 4 a is depicted as reset unit (RU-1) structure one synoptic diagram among the LCD device grid drive device embodiment one of the present invention;
Fig. 4 b is depicted as LCD device grid drive device embodiment one sequential chart of the present invention;
Fig. 4 c is depicted as reset unit (RU-1) structure two synoptic diagram among the LCD device grid drive device embodiment one of the present invention;
Shown in Figure 5 is LCD device grid drive device embodiment two structural representations of the present invention;
Fig. 6 a is depicted as reset unit (RU-2) structure one synoptic diagram among the LCD device grid drive device embodiment two of the present invention;
Fig. 6 b is depicted as LCD device grid drive device embodiment two sequential charts of the present invention;
Fig. 6 c is depicted as reset unit (RU-2) structure two synoptic diagram among the LCD device grid drive device embodiment two of the present invention;
Shown in Figure 7 is LCD device grid drive device embodiment three structural representations of the present invention;
Fig. 8 a is depicted as reset unit (RU-3) structure one synoptic diagram among the LCD device grid drive device embodiment three of the present invention;
Fig. 8 b is depicted as LCD device grid drive device embodiment three sequential charts of the present invention;
Fig. 8 c is depicted as reset unit (RU-3) structure two synoptic diagram among the LCD device grid drive device embodiment three of the present invention
Shown in Figure 9 is LCD device grid drive device embodiment four structural representations of the present invention;
Shown in Figure 10 is LCD device grid drive device embodiment five structural representations of the present invention;
Shown in Figure 11 is LCD device grid drive device embodiment six structural representations of the present invention;
Shown in Figure 12 is LCD device grid drive device embodiment seven structural representations of the present invention;
Shown in Figure 13 is LCD device grid drive device embodiment eight structural representations of the present invention;
Shown in Figure 14 is LCD device grid drive device embodiment nine structural representations of the present invention.
Embodiment
LCD device grid drive device provided by the invention is except that comprising n shift register cell; Also comprise a reset unit; This reset unit is connected with clock cable, power supply signal line and n shift register cell respectively; Be used for after the gate drive signal output terminal output gate drive signal of n shift register cell; The generation duration makes the gate drive signal output terminal (OUTn) of n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration.
Be illustrated in figure 3 as LCD device grid drive device embodiment one structural representation of the present invention, the reset signal output terminal (RESETOUT) of the reset unit of this LCD device grid drive device (being called for short RU-1) is connected with the reset signal input end (RESETIN) of n shift register cell (SRn).
Among Fig. 3, through clock cable B, power supply signal line A can be to the clock signal input terminal (CLKIN) in the reset unit (RU-1) and power supply signal input end (POWERIN) input clock signal (CLOCK) and power supply signal (POWER).The clock signal input terminal (CLOCKIN) that links to each other with clock cable B can comprise first clock signal input terminal (CLKIN) and second clock signal input part (CLKBIN); Also can comprise more clock signal, be that example describes with two clock signals in the embodiment of the invention.Input first clock signal (CLK) in first clock signal input terminal (CLKIN), input second clock signal (CLKB) in the second clock signal input part (CLKBIN), second clock signal (CLKB) is the inversion signal of first clock signal (CLK).The power supply signal input end (POWERIN) that links to each other with the power supply signal line can comprise high voltage signal input end (VDDIN) and low voltage signal input end (VSSIN); Input high voltage signal (VDD) in the high voltage signal input end (VDDIN), input low voltage signal (VSS) in the low voltage signal input end (VSSIN).
Be depicted as reset unit (RU-1) structure one synoptic diagram among the LCD device grid drive device embodiment one of the present invention like Fig. 4 a; This reset unit (RU-1) comprising: the first film transistor T 1 and the second thin film transistor (TFT) T2; The grid of the first film transistor T 1 connects first clock signal input terminal (CLKIN); Drain electrode connects high voltage signal input end (VDDIN), and source electrode connects reset signal output terminal (RESETOUT); The grid of the second thin film transistor (TFT) T2 connects second clock signal input part (CLKBIN), and drain electrode connects the source electrode of the first film transistor T 1, and source electrode connects low-voltage input end (VSSIN).
Be depicted as LCD device grid drive device embodiment one sequential chart of the present invention like Fig. 4 b, below in conjunction with the generation of reset signal in the reset unit (RU-1) in Fig. 4 a and the 4b illustrative embodiment one.
Shown in Fig. 4 b, in the phase one, first clock signal (CLK) is a low level, and the first film transistor T 1 ends, and second clock signal (CLKB) is a high level, the second thin film transistor (TFT) conducting, then reset signal output terminal (RESETOUT) output low level.Subordinate phase, second clock signal (CLKB) is a low level, and second thin film transistor (TFT) ends, and first clock signal (CLK) is a high level, the first film transistor turns, then reset signal output terminal (RESETOUT) output high level.Reset signal output terminal (RESETOUT) output signal repeats the state of phase one and subordinate phase always.
Through at the reset unit (RU-1) that increases in the LCD device grid drive device shown in Fig. 4 a; Can produce the appearing reset signal that exchanges variation shown in Fig. 4 b; The duration of this reset signal is longer; Duration more than or equal to the gate drive signal of shift register cell output, can guarantee that n shift register cell resets reliably, and exchange variation because this reset signal appears; Be unlikely to make the thin film transistor (TFT) that is used to reset in n the shift register cell to receive bias always, can guarantee the operate as normal of the thin film transistor (TFT) that is used to reset in n the shift register cell.
Be depicted as reset unit (RU-1) structure two synoptic diagram among the LCD device grid drive device embodiment one of the present invention like Fig. 4 c; The structure of the reset unit among Fig. 4 c (RU-1) is with the difference of Fig. 4 a: the transistorized grid of the first film all is connected first clock signal input terminal (CLKIN) with drain electrode among Fig. 4 c, and the first film transistor drain connects high voltage signal input end (VDDIN) among Fig. 4 a.
Be illustrated in figure 5 as LCD device grid drive device embodiment two structural representations of the present invention; Be with the difference of LCD device grid drive device shown in Figure 3: the reset unit of LCD device grid drive device shown in Figure 5 also comprises one first signal input part (INPUT1) in (being called for short RU-2), and this first signal input part (INPUT1) is connected with gate drive signal output terminal (OUTn-1) in n-1 the shift register cell.
Be depicted as reset unit (RU-2) structure one synoptic diagram among the LCD device grid drive device embodiment two of the present invention like Fig. 6 a; This reset unit (RU-2) comprising: the first film transistor T 1 and the second thin film transistor (TFT) T2; The grid of the first film transistor T 1 connects first clock signal input terminal (CLKIN); Drain electrode connects high voltage signal input end (VDDIN), and source electrode connects reset signal output terminal (RESETOUT); The grid of the second thin film transistor (TFT) T2 connects first signal input part (INPUT1); Promptly with the gate drive signal output terminal (OUTn-1) of n-1 shift register cell; Drain electrode connects the source electrode of the first film transistor T 1, and source electrode connects low-voltage input end (VSSIN).
Be depicted as LCD device grid drive device embodiment two sequential charts of the present invention like Fig. 6 b, below in conjunction with the generation of reset signal in the reset unit (RU-2) in Fig. 6 a and the 6b illustrative embodiment two.In the phase one; First clock signal (CLK) is a high level; The gate drive signal output unit (OUTn-1) of n-1 shift register cell is a high level; The first film transistor T 1 and the equal conducting of the second thin film transistor (TFT) T2 through the size of the first film transistor T 1 and the second thin film transistor (TFT) T2 is set, can make reset signal output terminal (RESETOUT) output low level.Subordinate phase; First clock signal (CLK) is a low level; The gate drive signal output unit (OUTn-1) of n-1 shift register cell is a low level, and the first film transistor T 1 and the second thin film transistor (TFT) T2 all end, and reset signal output terminal (RESETOUT) keeps low level.Phase III; First clock signal (CLK) is a high level, the first film transistor turns, and the gate drive signal output terminal (OUTn-1) of n-1 shift register cell is a low level; Second thin film transistor (TFT) ends, reset signal output terminal (RESETOUT) output high level.Stage; First clock signal (CLK) is a low level, and the first film transistor T 1 ends, and the gate drive signal output terminal (OUTn-1) of n-1 shift register cell is a low level; Second thin film transistor (TFT) ends, and reset signal output terminal (RESETOUT) keeps high level output.After this, the output signal of reset signal output terminal (RESETOUT) repeats the state of phase III and stage, and is intact up to the capable picture element scan of next frame n-1.
Through at the reset unit (RU-2) that increases in the LCD device grid drive device shown in Fig. 6 a; Can produce the appearing reset signal that exchanges variation shown in Fig. 6 b; The duration of this reset signal is longer; Duration more than or equal to the gate drive signal of shift register cell output, can guarantee that n shift register cell resets reliably.
Be depicted as reset unit (RU-2) structure two synoptic diagram among the LCD device grid drive device embodiment two of the present invention like 6c; The structure of the reset unit among Fig. 6 c is with the difference of Fig. 6 a: the transistorized grid of the first film all is connected first clock signal input terminal (CLKIN) with drain electrode among Fig. 6 c, and the first film transistor drain connects high voltage signal input end (VDDIN) among Fig. 6 a.
Be illustrated in figure 7 as LCD device grid drive device embodiment three structural representations of the present invention; Be with the difference of LCD device grid drive device shown in Figure 3: the reset unit of LCD device grid drive device shown in Figure 7 also comprises a secondary signal input end (INPUT2) in (being called for short RU-3), and this secondary signal input end (INPUT2) is connected with gate drive signal output terminal (OUTn) in n the shift register cell.
Fig. 8 a is depicted as reset unit (RU-3) structure one synoptic diagram among the LCD device grid drive device embodiment three of the present invention, and this reset unit (RU-3) comprising: the first film transistor T 1, the second thin film transistor (TFT) T2, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4.The drain electrode of the first film transistor T 1 connects second clock signal input part (CLKBIN), and source electrode connects reset signal output terminal (RESETOUT); The drain electrode of the second thin film transistor (TFT) T2 connects the source electrode of the first film transistor T 1, and the source electrode of the second thin film transistor (TFT) T2 connects low voltage signal input end (VSSIN); The drain electrode of the 3rd thin film transistor (TFT) T3 connects high voltage signal input end (VDDIN), and source electrode connects the grid of the first film transistor T 1, and grid connects the gate drive signal output terminal (OUTn) of n shift register cell; The drain electrode of the 4th thin film transistor (TFT) T4 connects the source electrode of the 3rd thin film transistor (TFT), and grid connects the grid of first clock signal input terminal (CLKIN) and second thin film transistor (TFT), and source electrode connects low voltage signal input end (VSSIN).
Be depicted as LCD device grid drive device embodiment three sequential charts of the present invention like Fig. 8 b, below in conjunction with the generation of reset signal in the reset unit (RU-3) in Fig. 8 a and the 8b illustrative embodiment three.In the phase one; First clock signal (CLK) is a high level, and gate drive signal output terminal (OUTn) the output high level of n shift register cell is so the 3rd thin film transistor (TFT) T3 and the equal conducting of the 4th thin film transistor (TFT) T4; Can guarantee that through the size that the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4 are set Q node place is a high level; 1 conducting of the first film transistor T, second clock signal (CLKB) is a low level, and because first clock signal (CLK) is a high level; The second thin film transistor (TFT) T2 conducting, reset signal output terminal (RESETOUT) output low level.Subordinate phase, first clock signal (CLK) is a low level, gate drive signal output terminal (OUTn) output low level of n shift register cell; The 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4 end; The Q node is floating empty, because second clock signal (CLKB) is a high level, and the stray capacitance of the first film transistor T 1 can be coupled to the Q node; Make the current potential of Q node continue to raise; The first film transistor T 1 conducting simultaneously, the second thin film transistor (TFT) T2 ends, and reset signal output terminal (RESETOUT) is a high level.Phase III, first clock signal (CLK) is a high level, gate drive signal output terminal (OUTn) output low level of n shift register cell; The 4th thin film transistor (TFT) T4 conducting; The 3rd thin film transistor (TFT) T3 ends, and Q node place current potential is dragged down is low level, and the first film transistor T 1 ends; The second thin film transistor (TFT) T2 conducting, reset signal output terminal (RESETOUT) is a low level.Stage; First clock signal (CLK) is a low level; Gate drive signal output terminal (OUTn) output low level of n shift register cell, the 3rd thin film transistor (TFT) T3 and the 4th thin film transistor (TFT) T4 all end, and the Q node keeps low level; The first film transistor T 1 and the second thin film transistor (TFT) T2 end, and reset signal output terminal (RESETOUT) is a low level.After this, the signal of reset signal output terminal (RESETOUT) output repeats the state of phase III and stage, and is intact up to the capable picture element scan of next frame n.
Through at the reset unit (RU-3) that increases in the LCD device grid drive device shown in Fig. 8 a; Can produce the appearing reset signal that exchanges variation shown in Fig. 8 b; The duration of this reset signal is longer; Duration more than or equal to the gate drive signal of shift register cell output, can guarantee that n shift register resets reliably.
Be depicted as reset unit (RU-3) structure two synoptic diagram among the LCD device grid drive device embodiment three of the present invention like Fig. 8 c; The structure of the reset unit among Fig. 8 c (RU-3) is with the difference of Fig. 8 a: the grid of the 3rd thin film transistor (TFT) all is connected secondary signal input end (INPUT2) with drain electrode among Fig. 8 c, and the drain electrode of the 3rd thin film transistor (TFT) connects high voltage signal input end (VDDIN) among Fig. 8 a.
Can also combine redundant shift register cell and reset unit to realize to comprise m (m is a natural number) individual redundant shift register cell (being labeled as RSR) and n-m working shift register unit (being labeled as SR) in the n of the LCD device grid drive device shift register cell in the LCD device grid drive device that provides among the present invention to the resetting of last shift register cell; For the LCD that the capable pixel of n-m is arranged; Usually there be n-m shift register cell to be used to export gate drive signal and control lining by line scan of the capable pixel of n-m; Among the present invention; For the embodiment that contains redundant shift register cell; This n-m is used to export gate drive signal controls the shift register cell of lining by line scan of the capable pixel of n-m and be called the working shift register unit, all the other shift register cells except that this n-m working shift register unit are not used in the output gate drive signal, can be called redundant shift register cell; Redundant shift register cell can not be connected with grid line, and is promptly unloaded; Even be connected with grid line, the drain electrode of the TFT that is connected with this grid line is not connected with data line yet, and the load that promptly is equivalent to this redundancy shift register cell is the sky pixel.
M redundant shift register cell is arranged on the subordinate of n-m working shift register unit; Wherein the 2nd to m-1 redundant shift register cell all (redundant shift register cell is not used in the output gate drive signal with the gate drive signal output terminal of clock cable, power supply signal line, the upper level redundancy shift register cell adjacent with self; For ease of difference, the gate drive signal output terminal of redundant shift register cell ROUT is in the accompanying drawings represented), the signal input part of the reset signal input end of the redundant shift register cell of the upper level adjacent with self and the next stage redundancy shift register cell adjacent with self is connected; The 1st redundant shift register cell is connected with the gate drive signal output terminal of clock cable, power supply signal line, a n-m working shift register unit, the reset signal input end of a n-m working shift register unit and the reset signal input end of the 2nd redundant shift register cell; The gate drive signal output terminal of m redundant shift register cell and said clock cable, power supply signal line, a m-1 redundant shift register cell, the reset signal input end of a m-1 redundant shift register cell and the reset signal output terminal (RESETOUT) of reset unit (RU-1, RU-2 or RU-3) connect.
The structure of reset unit can adopt the structure of Fig. 4 a or 4c; Perhaps the structure of reset unit also can adopt the structure shown in Fig. 6 a or 6c; The grid of second thin film transistor (TFT) connects first signal input part (INPUT1) in the reset unit, and first signal input part (INPUT1) need be connected to the gate drive signal output terminal (ROUTm-1) of m-1 redundant shift register cell.Need to prove; Because the sum of shift register cell is n; The number of working shift register unit is n-m; The number of redundant shift register cell is m, and m redundant shift register cell is in the subordinate of n-m working shift register, so the individual redundant shift register cell of m-1 n-1 shift register cell just here.
Perhaps the structure of reset unit can also adopt the structure shown in Fig. 8 a or 8c; The grid of second thin film transistor (TFT) connects secondary signal input end (INPUT2) in the reset unit, and secondary signal input end (INPUT2) need be connected to the gate drive signal output terminal (ROUTm) of m redundant shift register cell.Need to prove; Because the sum of shift register cell is n; The number of working shift register unit is n-m; The number of redundant shift register cell is m, and m redundant shift register cell is in the subordinate of n-m working shift register, so the individual redundant shift register cell of m n shift register cell just here.。
Preferably, m can select 1 or 2 or 3.Be illustrated in figure 9 as LCD device grid drive device embodiment four structural representations of the present invention; Reset unit among this embodiment four can adopt the structure shown in Fig. 6 a; Comprise the individual redundant shift register cell of 2 (being m=2); First signal input part (INPUT1) of reset unit (RU-2) connects first (m=2, m-1=1) the gate drive signal output terminal (ROUT1) of individual redundant shift register cell.First redundant shift register cell can connect a grid line (GL2-1), and the drain electrode of the TFT that is connected with this grid line (GL2-1) is not connected with data line.If the signal output part of these 2 redundant shift register cells (ROUT1 and ROUT2) all is unloaded; Then the signal of the output of these 2 redundant shift register cells is easy to receive the interference of clock signal; If the signal output part (ROUT1) at first redundant shift register cell (RSR1) connects a grid line (GL2-1); Because the TFT that is connected with this grid line (GL2-1) can produce stray capacitance, thereby can reduce the interference of clock signal to the output signal.Based on same reason; For the LCD device grid drive device that includes m redundant shift register cell; In order to reduce the interference of clock signal to redundant shift register cell signal output part output signal; Can make the signal output part of part or all of redundant shift register cell connect a grid line respectively, the drain electrode of the TFT that is connected with each bar grid line is not connected with data line.
Shown in figure 10 is LCD device grid drive device embodiment five structural representations of the present invention; Reset unit among this embodiment five can adopt the structure shown in Fig. 8 a or 8c; Comprise the individual redundant shift register cell of 2 (being m=2), the secondary signal input end (INPUT2) of reset unit connects the signal output part (ROUT2) of the individual redundant shift register cell of second (m=2).
Shown in figure 11 is LCD device grid drive device embodiment six structural representations of the present invention, and the reset unit among this embodiment six can adopt the structure shown in Fig. 4 a, comprises the individual redundant shift register cell of 3 (being m=3).
Can also comprise two or more reset units in the LCD device grid drive device, as 4,6 etc., the number of reset unit can be confirmed according to the number that is input to the clock signal in the LCD device grid drive device.The number reset unit identical with the clock signal number is set guarantees that load clock signal is balanced.For example; If a reset unit only is set in gate drive apparatus; Because the TFT that different clock signals connects is different, the load of different clock signals difference just like this, and if the load of clock signal is unbalanced; May cause the voltage swing difference of the gate drive signal of adjacent lines shift register cell output, thereby influence the demonstration of adjacent lines of pixels.
Shown in figure 12 is LCD device grid drive device embodiment seven structural representations of the present invention.Two clock signal input terminals are arranged, so preferably, the number of reset unit can be two in the LCD device grid drive device like Figure 12.Comprise two reset units (RU-1) among this embodiment seven; These two reset units all can adopt the structure shown in Fig. 4 a or 4c; First reset unit (being labeled as RU-1-1 in the accompanying drawing) connects clock cable, power supply signal line; Reset signal output terminal (RESETOUT1) connects the reset signal input end (RESETIN) of n-1 shift register cell; Second reset unit (being labeled as RU-1-2 in the accompanying drawing) connects clock cable, power supply signal line, and reset signal output terminal (RESETOUT2) connects the reset signal input end (RESETIN) of n shift register cell.Through two reset units are set; The reset signal of n-1 shift register cell is no longer provided by n shift register cell; But provide by the reset signal of first reset unit (RU-1-1) output; Thereby can guarantee the reliable reset of n-1 and n shift register cell, and, preferably; It is opposite that the clock signal that first reset unit (being labeled as RU-1-1 in the accompanying drawing) connects and second reset unit (being labeled as RU-1-2 in the accompanying drawing) are connected clock signal; Because first reset unit (being labeled as RU-1-1 in the accompanying drawing) is positioned at the subordinate of n-1 shift register cell, second reset unit (being labeled as RU-1-2 in the accompanying drawing) is positioned at the subordinate of n shift register, can guarantee the load balancing of two clock signals like this.First reset unit (being labeled as RU-1-1 in the accompanying drawing) role in this embodiment is to make two load clock signal equilibriums that are input in the LCD device grid drive device, is equivalent to a Load Balance Unit.
As can be seen from Figure 12; More universal a kind of embodiment can be: the reset signal input end (RESETIN) of n shift register cell is connected with the reset signal output terminal of a reset unit (RU-1-2), and the reset signal input end (RESETIN) of the 1st any shift register cell in the n-1 is connected with another reset unit (RU-1-1).
Can also comprise a plurality of redundant shift register cells on the embodiment basis shown in Figure 12; For example comprise m redundant shift register cell and n-m working shift register unit in n shift register cell; An embodiment that possesses ubiquity so can be; The reset signal input end (RESETIN) of last shift register cell (shift register cell comprises the working shift register unit and redundant shift register cell that is used for driving grid here) is connected with the reset signal output terminal of a reset unit (RU-1-2), and the reset signal input end (RESETIN) of another reset unit (RU-1-1) can be connected with the gate drive signal output terminal of the 1st any shift register cell in n-1 the shift register cell.
Shown in figure 13 is LCD device grid drive device embodiment eight structural representations of the present invention.Comprise two reset units among this embodiment eight; These two reset units all can adopt the structure shown in Fig. 8 a or 8c; First reset unit (being labeled as RU-3-1 in the accompanying drawing) connects the gate drive signal output terminal (OUTn-1) of clock cable, power supply signal line, a n-1 shift register cell; Reset signal output terminal (RESETOUT1) connects the reset signal input end (RESETIN) of n-1 shift register cell; Second reset unit (RU-3-2) connects the gate drive signal output terminal (OUTn) of clock cable, power supply signal line, a n shift register cell, and reset signal output terminal (RESETOUT2) connects the reset signal input end (RESETIN) of n shift register cell.The gate drive signal output terminal of n and n-1 shift register cell is connected common grid line (GLn-1 and GLn), and the source electrode of the TFT that is connected with GLn-1 with GLn need connect data line.Through two reset units are set; The reset signal of n-1 shift register cell is no longer provided by n shift register cell; But provide, thereby can guarantee the reliable reset of n-1 and n shift register cell by first reset unit (RU-3-1).First reset unit (being labeled as RU-3-1 in the accompanying drawing) role in this embodiment is to make two load clock signal equilibriums that are input in the LCD device grid drive device, is equivalent to a Load Balance Unit.
As can be seen from Figure 13; More universal a kind of embodiment can be: the reset signal input end (RESETIN) of n shift register cell is connected with the reset signal output terminal of a reset unit (RU-3-2); The secondary signal input end (INPUT2) of this reset unit (RU-3-2) is connected with the signal output part (OUTn) of n shift register cell; The reset signal input end (RESETIN) of any shift register cell in the 1st to n-1 is connected with another reset unit (RU-3-1), secondary signal input end (INPUT2) of this reset unit (RU-3-1) and z 1The gate drive signal output terminal of individual register cell connects, z 1Be the number of the shift register cell that is in this reset unit (RU-3-1) higher level, z 1Be less than or equal to n-1, z 1Be natural number.
If comprise m redundant shift register cell in the embodiment shown in fig. 13; For example comprise m redundant shift register cell and n-m working shift register unit in n shift register cell, then the secondary signal input end (INPUT2) of reset unit (RU-3-1) need with z 1The gate drive signal output terminal of individual shift register cell connects, z 1Be the number of the shift register cell that is in this reset unit (RU-3-1) higher level, z 1Be less than or equal to n-1, z 1Be natural number; The reset signal output terminal (RESETOUT) of reset unit (RU-3-1) need with z 1The reset signal input end (RESETIN) of individual shift register cell connects.The secondary signal input end (INPUT2) of another reset unit (RU-3-2) need be connected with the gate drive signal output terminal of n shift register cell (m redundant shift register cell just), and the reset signal output terminal (RESETOUT) of reset unit (RU-3-2) need be connected with the reset signal input end (RESETIN) of n shift register cell.Two reset units in the LCD device grid drive device shown in figure 13 also can adopt the structure shown in Fig. 6 a or 6c, and shown in figure 14 is LCD device grid drive device embodiment nine structural representations of the present invention.RU-2-1 representes first reset unit (RU-2) among the figure; RU-2-2 representes second reset unit (RU-2); First reset unit (being labeled as RU-2-1 in the accompanying drawing) connects the gate drive signal output terminal (OUTn-2) of clock cable, power supply signal line, a n-2 shift register cell; Reset signal output terminal (RESETOUT1) connects the reset signal input end (RESETIN) of n-1 shift register cell; Second reset unit (RU-2-2) connects the gate drive signal output terminal (OUTn-1) of clock cable, power supply signal line, a n-1 shift register cell, and reset signal output terminal (RESETOUT2) connects the reset signal input end (RESETIN) of n shift register cell.The gate drive signal output terminal of n and n-1 shift register cell is connected common grid line (GLn-1 and GLn), and the source electrode of the TFT that is connected with GLn-1 with GLn need connect data line.Through two reset units are set; The reset signal of n-1 shift register cell is no longer provided by n shift register cell; But provide, thereby can guarantee the reliable reset of n-1 and n shift register cell by first reset unit (RU-2-1).
As can be seen from Figure 14; More universal a kind of embodiment can be: the reset signal input end (RESETIN) of n shift register cell is connected with the reset signal output terminal of a reset unit (RU-2-2); First signal input part (INPUT1) of this reset unit (RU-2-2) is connected with the signal output part (OUTn-1) of n-1 shift register cell; The reset signal input end (RESETIN) of any shift register cell in the 1st to n-1 is connected with another reset unit (RU-2-1), first signal input part (INPUT1) of this reset unit (RU-2-1) and z 1The signal output part of-1 register cell connects, z 1Be the number of the shift register cell that is in this reset unit (RU-2-1) higher level, z 1Be less than or equal to n-1, z 1Be natural number.First reset unit (being labeled as RU-2-1 in the accompanying drawing) role in this embodiment is to make two load clock signal equilibriums that are input in the LCD device grid drive device, is equivalent to a Load Balance Unit.
If comprise m redundant shift register cell in the embodiment shown in fig. 14; For example comprise a n-m working shift register unit and m redundant shift register cell in n shift register cell, then first signal input part (INPUT1) of reset unit (RU-2-1) need with z 1The gate drive signal output terminal of-1 shift register cell connects, z 1Number for the shift register cell that is in this reset unit (RU-2-1) higher level can comprise working shift register unit and redundant shift register cell, z 1Be less than or equal to n-1, z 1Be natural number; The reset signal output terminal (RESETOUT) of reset unit (RU-2-1) need with z 1The reset signal input end (RESETIN) of individual shift register cell connects.。First signal input part (INPUT1) of another reset unit (RU-2-2) need be connected with the gate drive signal output terminal of n-1 shift register cell (m-1 redundant shift register cell just); The reset signal output terminal (RESETOUT) of reset unit (RU-2-2) need be connected with the reset signal input end (RESETIN) of n shift register cell.。For like Figure 12,13 or 14 described LCD device grid drive devices; The structure of a plurality of reset units wherein can be different; For example; For Figure 12; Wherein, the structure of the reset unit that is connected with the reset signal input end (RESETIN) of n shift register cell can adopt the structure shown in Fig. 4 a or 4c, and the structure of the reset unit that is connected with the reset signal input end (RESETIN) of n-1 shift register cell can adopt the structure shown in Fig. 6 a or 6c; At this moment, adopted first signal input part (INPUT1) of the reset unit of structure shown in Fig. 6 a or the 6c to be connected with the gate drive signal output terminal of n-2 shift register cell.
A plurality of reset units adopt various structure respectively, can be combined into the structure of a plurality of LCD device grid drive devices, and the described mode of concrete implementation and preamble is similar, repeats no more here.
The present invention can produce long-term reset signal through in LCD device grid drive device, increasing one or more reset units, can guarantee that n shift register cell resets reliably.And this reset unit shared area in LCDs can be accomplished less; Can not cause the remarkable increase of screen design difficulty; The input signal of reset unit adopts the signal of available liquid crystal display apparatus grid drive unit; Need not import new signal, can not cause the raising of signal controlling difficulty, convenient resetting of realizing LCD device grid drive device reliably.
What should explain at last is: above embodiment is only in order to technical scheme of the present invention to be described but not limit it; Although the present invention has been carried out detailed explanation with reference to preferred embodiment; Those of ordinary skill in the art is to be understood that: it still can make amendment or be equal to replacement technical scheme of the present invention, also can not make amended technical scheme break away from the spirit and the scope of technical scheme of the present invention and these are revised or be equal to replacement.

Claims (18)

1. a LCD device grid drive device comprises n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, it is characterized in that, also comprises reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number;
Said reset unit comprises: the first film transistor and second thin film transistor (TFT);
The transistorized grid of said the first film connects first clock signal input terminal that links to each other with said clock cable; Drain electrode connects high voltage signal input end or said first clock signal input terminal that links to each other with said power supply signal line, and source electrode connects the drain electrode of said second thin film transistor (TFT) and the reset signal output terminal of said reset unit;
The grid of said second thin film transistor (TFT) connects the second clock signal input part that links to each other with said clock cable, and drain electrode connects the transistorized source electrode of said the first film, and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal that said reset unit produces.
2. LCD device grid drive device according to claim 1; It is characterized in that; Comprise m redundant shift register cell and n-m working shift register unit in the said n shift register cell; Said m redundant shift register cell is arranged on the subordinate of n-m working shift register unit, and m redundant shift register cell is n shift register cell;
M is a natural number.
3. LCD device grid drive device according to claim 2; It is characterized in that; Gate drive signal output terminal in the individual redundant shift register cell of part or all of said m connects delegation's first grid line respectively, and the drain electrode of the thin film transistor (TFT) that is connected with said first grid line is not connected with data line.
4. a LCD device grid drive device comprises n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, it is characterized in that, also comprises reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number;
Said reset unit also is connected with the gate drive signal output terminal of n-1 shift register cell;
Said reset unit comprises: the first film transistor and second thin film transistor (TFT);
The transistorized grid of said the first film connects first clock signal input terminal that links to each other with said clock cable; Drain electrode connects high voltage signal input end or said first clock signal input terminal that links to each other with said power supply signal line, and source electrode connects the drain electrode of said second thin film transistor (TFT) and the reset signal output terminal of said reset unit;
The grid of said second thin film transistor (TFT) connects first signal input part; Said first signal input part connects the gate drive signal output terminal of n-1 shift register cell; Drain electrode connects the transistorized source electrode of said the first film, and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said reset signal output terminal is used to export the reset signal that said reset unit produces.
5. LCD device grid drive device according to claim 4; It is characterized in that; Comprise m redundant shift register cell and n-m working shift register unit in the said n shift register cell; Said m redundant shift register cell is arranged on the subordinate of n-m working shift register unit, and m redundant shift register cell is n shift register cell;
M is a natural number.
6. LCD device grid drive device according to claim 5; It is characterized in that; Gate drive signal output terminal in the individual redundant shift register cell of part or all of said m connects delegation's first grid line respectively, and the drain electrode of the thin film transistor (TFT) that is connected with said first grid line is not connected with data line.
7. a LCD device grid drive device comprises n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, it is characterized in that, also comprises reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number;
Said reset unit also is connected with the gate drive signal output terminal of n shift register cell;
Said reset unit comprises: the first film transistor, second thin film transistor (TFT), the 3rd thin film transistor (TFT) and the 4th thin film transistor (TFT);
Said the first film transistor drain connects the second clock signal input part that links to each other with said clock signal signal wire, and source electrode connects the reset signal output terminal of said reset unit;
The drain electrode of said second thin film transistor (TFT) connects the transistorized source electrode of said the first film, and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects first clock signal input terminal;
The grid of said the 3rd thin film transistor (TFT) connects the secondary signal input end; Said secondary signal input end connects the gate drive signal output terminal of n shift register cell; The high voltage signal input end that drain electrode connects said grid or links to each other with said power supply signal line, source electrode connects the transistorized grid of said the first film;
The drain electrode of said the 4th thin film transistor (TFT) connects the source electrode of said the 3rd thin film transistor (TFT), and source electrode connects said low voltage signal input end, and grid connects said first clock signal input terminal;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal that said reset unit produces.
8. LCD device grid drive device according to claim 7; It is characterized in that; Comprise m redundant shift register cell and n-m working shift register unit in the said n shift register cell; Said m redundant shift register cell is arranged on the subordinate of n-m working shift register unit, and m redundant shift register cell is n shift register cell;
M is a natural number.
9. LCD device grid drive device according to claim 8; It is characterized in that; Gate drive signal output terminal in the individual redundant shift register cell of part or all of said m connects delegation's first grid line respectively, and the drain electrode of the thin film transistor (TFT) that is connected with said first grid line is not connected with data line.
10. a LCD device grid drive device comprises n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, it is characterized in that, also comprises reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number;
Also comprise at least one Load Balance Unit, said Load Balance Unit is used to keep being input to all load clock signals equilibriums of said LCD device grid drive device;
The number of said Load Balance Unit is one, and the clock signal number of importing said LCD device grid drive device is two;
Said reset unit comprises the one one thin film transistor (TFT) and the one or two thin film transistor (TFT), and said Load Balance Unit comprises the 21 thin film transistor (TFT) and the two or two thin film transistor (TFT);
The drain electrode of said the one one thin film transistor (TFT) connect grid or with the high voltage signal input end of said power supply signal line; Source electrode connects the drain electrode of said the one or two thin film transistor (TFT) and the reset signal output terminal of said reset unit, and grid connects first clock signal input terminal that links to each other with said clock cable;
The drain electrode of said the one or two thin film transistor (TFT) connects the source electrode of said the one one thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects the gate drive signal output terminal of n-1 shift register cell;
The drain electrode of said the 21 thin film transistor (TFT) connect grid or with the high voltage signal input end of said power supply signal line; Source electrode connects the drain electrode of said the two or two thin film transistor (TFT) and the reset signal output terminal of said Load Balance Unit, and grid connects the input end of the second clock signal that links to each other with said clock cable;
The drain electrode of said the two or two thin film transistor (TFT) connects the source electrode of said the 21 thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects z 1The gate drive signal output terminal of-1 shift register cell; z 1Be the number of the shift register cell that is in said Load Balance Unit higher level, z 1Be less than or equal to n-1, z 1Be natural number;
Reset signal output terminal in the said reset unit connects the reset signal input end of said n shift register cell, and the reset signal output terminal connects z in the said Load Balance Unit 1The reset signal input end of individual shift register cell;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal of said reset unit or the generation of said Load Balance Unit.
11. LCD device grid drive device according to claim 10; It is characterized in that; Comprise m redundant shift register cell and n-m working shift register unit in the said n shift register cell; Said m redundant shift register cell is arranged on the subordinate of n-m working shift register unit, and m redundant shift register cell is n shift register cell;
M is a natural number.
12. LCD device grid drive device according to claim 11; It is characterized in that; Gate drive signal output terminal in the individual redundant shift register cell of part or all of said m connects delegation's first grid line respectively, and the drain electrode of the thin film transistor (TFT) that is connected with said first grid line is not connected with data line.
13. a LCD device grid drive device comprises n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, it is characterized in that, also comprises reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number;
Also comprise at least one Load Balance Unit, said Load Balance Unit is used to keep being input to all load clock signals equilibriums of said LCD device grid drive device;
The number of said Load Balance Unit is one, and the clock signal number of importing said LCD device grid drive device is two;
Said reset unit comprises the one one thin film transistor (TFT) and the one or two thin film transistor (TFT), and said Load Balance Unit comprises the 21 thin film transistor (TFT) and the two or two thin film transistor (TFT);
The grid of said the one one thin film transistor (TFT) connects first clock signal input terminal that links to each other with said clock cable; Drain electrode connects high voltage signal input end or said first clock signal input terminal that links to each other with said power supply signal line, and source electrode connects the drain electrode of said the one or two thin film transistor (TFT) and the reset signal output terminal of said reset unit;
The grid of said the one or two thin film transistor (TFT) connects the second o'clock signal input part that links to each other with said clock cable, and drain electrode connects the source electrode of said the one one thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
The grid of said the 21 thin film transistor (TFT) connects the second clock signal input part that links to each other with said clock cable; Drain electrode connects high voltage signal input end or the said second clock signal input part that links to each other with said power supply signal line, and source electrode connects the drain electrode of said the two or two thin film transistor (TFT) and the reset signal output terminal of said Load Balance Unit;
The grid of said the two or two thin film transistor (TFT) connects first clock signal input terminal that links to each other with said clock cable, and drain electrode connects the source electrode of said the 21 thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line;
Reset signal output terminal in the said reset unit connects the reset signal input end of said n shift register cell; Reset signal output terminal in the said Load Balance Unit connects z 1The reset signal input end of individual shift register cell; z 1Be the number of the shift register cell that is in said Load Balance Unit higher level, z 1Be less than or equal to n-1, z 1Be natural number;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal of said reset unit or the generation of said Load Balance Unit.
14. LCD device grid drive device according to claim 13; It is characterized in that; Comprise m redundant shift register cell and n-m working shift register unit in the said n shift register cell; Said m redundant shift register cell is arranged on the subordinate of n-m working shift register unit, and m redundant shift register cell is n shift register cell;
M is a natural number.
15. LCD device grid drive device according to claim 14; It is characterized in that; Gate drive signal output terminal in the individual redundant shift register cell of part or all of said m connects delegation's first grid line respectively, and the drain electrode of the thin film transistor (TFT) that is connected with said first grid line is not connected with data line.
16. a LCD device grid drive device comprises n shift register cell, clock cable, power supply signal line and gate drive signal output terminal, it is characterized in that, also comprises reset unit;
Said reset unit is connected with said clock cable, power supply signal line and n shift register cell; Be used for after the gate drive signal output terminal output gate drive signal of said n shift register cell; The generation duration makes the gate drive signal output terminal of said n shift register cell be able to reset more than or equal to the reset signal of said gate drive signal duration;
N is a natural number;
Also comprise at least one Load Balance Unit, said Load Balance Unit is used to keep being input to all load clock signals equilibriums of said LCD device grid drive device;
The number of said Load Balance Unit is one, and the clock signal number of importing said LCD device grid drive device is two;
Said reset unit comprises the one one thin film transistor (TFT), the one or two thin film transistor (TFT), the one or three thin film transistor (TFT) and the one or four thin film transistor (TFT), and said Load Balance Unit comprises the 21 thin film transistor (TFT), the two or two thin film transistor (TFT), the two or three thin film transistor (TFT) and the two or four thin film transistor (TFT);
The drain electrode of said the one one thin film transistor (TFT) connects the second clock signal input part that links to each other with said clock cable, and source electrode connects the reset signal output terminal of said reset unit;
The drain electrode of said the one or two thin film transistor (TFT) connects the source electrode of said the one one thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects first clock signal input terminal that links to each other with said clock cable;
The high voltage signal input end that the drain electrode of said the one or three thin film transistor (TFT) connects grid or links to each other with said power supply signal line, source electrode connects the grid of said the one one thin film transistor (TFT), and grid connects the gate drive signal output terminal of n shift register cell;
The drain electrode of said the one or four thin film transistor (TFT) connects the source electrode of said the one or three thin film transistor (TFT), and source electrode connects said low voltage signal input end, and grid connects said first clock signal input terminal;
The drain electrode of said the 21 thin film transistor (TFT) connects first clock signal input terminal that links to each other with said clock cable, and source electrode connects the reset signal output terminal of said Load Balance Unit;
The drain electrode of said the two or two thin film transistor (TFT) connects the source electrode of said the 21 thin film transistor (TFT), and source electrode connects the low voltage signal input end that links to each other with said power supply signal line, and grid connects the second clock signal input part that links to each other with said clock cable;
The high voltage signal input end that the drain electrode of said the two or three thin film transistor (TFT) connects grid or links to each other with said power supply signal line, source electrode connects the grid of said the 21 thin film transistor (TFT), and grid connects z 1The gate drive signal output terminal of individual shift register cell; z 1Be the number of the shift register cell that is in said Load Balance Unit higher level, z 1Be less than or equal to n-1, z 1Be natural number;
The drain electrode of said the two or four thin film transistor (TFT) connects the source electrode of said the two or three thin film transistor (TFT), and source electrode connects said low voltage signal input end, and grid connects said second clock signal input part;
The reset signal output terminal connects said z in the said Load Balance Unit 1The reset signal input end of individual shift register cell, the reset signal output terminal in the said reset unit connects the reset signal input end of said n shift register cell;
Said high voltage signal input end is used to import high voltage signal;
Said low voltage signal input end is used to import low voltage signal;
Said first clock signal input terminal is used to import first clock signal;
Said second clock signal input part is used to import the second clock signal with the said first clock signal anti-phase;
Said reset signal output terminal is used to export the reset signal of said reset unit or Load Balance Unit generation.
17. LCD device grid drive device according to claim 16; It is characterized in that; Comprise m redundant shift register cell and n-m working shift register unit in the said n shift register cell; Said m redundant shift register cell is arranged on the subordinate of n-m working shift register unit, and m redundant shift register cell is n shift register cell;
M is a natural number.
18. LCD device grid drive device according to claim 17; It is characterized in that; Gate drive signal output terminal in the individual redundant shift register cell of part or all of said m connects delegation's first grid line respectively, and the drain electrode of the thin film transistor (TFT) that is connected with said first grid line is not connected with data line.
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