CN109686334B - Gate drive circuit, drive method thereof and display device - Google Patents
Gate drive circuit, drive method thereof and display device Download PDFInfo
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- CN109686334B CN109686334B CN201910119638.XA CN201910119638A CN109686334B CN 109686334 B CN109686334 B CN 109686334B CN 201910119638 A CN201910119638 A CN 201910119638A CN 109686334 B CN109686334 B CN 109686334B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
- G09G2310/0264—Details of driving circuits
- G09G2310/0286—Details of a shift registers arranged for use in a driving circuit
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Abstract
The invention provides a grid driving circuit, a driving method thereof and a display device, wherein the grid driving circuit comprises N stages of sequentially cascaded shift register units, and the grid driving circuit also comprises: the clock signal ends of the N-level shift register units are respectively connected with the 2M clock signal lines, wherein the continuous M clock signal lines are sequentially connected with the input end of the previous M-level shift register unit and used for providing pull-up signals for the previous M-level shift register unit; n is an integral multiple of 2M, and M is a positive integer greater than 1; and the frame starting signal line is used for controlling the conduction or the separation between the continuous M clock signal lines and the input end of the shift register unit of the previous M stages. The gate driving circuit, the driving method thereof and the display device provided by the invention can facilitate the narrow frame design of the display device.
Description
Technical Field
The invention relates to the technical field of display, in particular to a gate driving circuit, a driving method thereof and a display device.
Background
The Gate Drive on Array (GOA) refers to a shift register that integrates Gate Drive of a Liquid Crystal Display (LCD) on a glass substrate. The GOA circuit is connected with the grid line of the array substrate and used as a shift register control grid line signal.
In the prior art, the time for precharging and charging the GOA circuit is prolonged by adding a clock signal line (CLK line), and the precharging time of the pixel is prolonged, so that the display effect of the display device can be improved. However, the conventional connection method requires the addition of a frame start signal line (STV line) while increasing the number of CLK lines, which is not favorable for the narrow frame trend of the display device.
Disclosure of Invention
Embodiments of the present invention provide a gate driving circuit, a driving method thereof, and a display device, so as to solve the problem that the conventional connection method requires a corresponding increase of an STV line while increasing a CLK line, which is not favorable for the narrow frame trend of the display device.
In order to solve the above technical problems, the present invention provides the following technical solutions:
in a first aspect, an embodiment of the present invention provides a gate driving circuit, including N stages of sequentially cascaded shift register units, where each shift register unit is configured to provide a gate scanning signal for a gate line corresponding to the shift register unit, and the gate driving circuit further includes:
the clock signal ends of the N-level shift register units are respectively connected with the 2M clock signal lines, wherein the continuous M clock signal lines are sequentially connected with the input end of the previous M-level shift register unit and used for providing pull-up signals for the previous M-level shift register unit; n is an integral multiple of 2M, and M is a positive integer greater than 1;
and the frame starting signal line is used for controlling the conduction or the separation between the continuous M clock signal lines and the input end of the shift register unit of the previous M stages.
The shift register further comprises M switch thin film transistors, the grids of the M switch thin film transistors are all connected with the frame starting signal line, the sources of the M switch thin film transistors are respectively connected with the M continuous clock signal lines, and the drains of the M switch thin film transistors are respectively connected with the input end of the shift register unit of the previous M stages.
Furthermore, the frame start signal line is further connected to a reset terminal of the shift register unit of the next M-stage, and is configured to provide a pull-down signal to the shift register unit of the next M-stage.
Further, said M ═ 3;
the first clock signal line is connected with the input end of the first-stage shift register unit, and the fourth clock signal line is connected with the clock signal end of the first-stage shift register unit;
the second clock signal line is connected with the input end of the second-stage shift register unit, and the fifth clock signal line is connected with the clock signal end of the second-stage shift register unit;
and the sixth clock signal line is connected with the clock signal end of the third-stage shift register unit.
In a second aspect, an embodiment of the present invention further provides a driving method of the gate driving circuit, where the method includes:
controlling the frame start signal line to conduct the connection between the continuous M clock signal lines and the input end of the front M-level shift register unit in the display time period of one frame of picture, wherein the continuous M clock signal lines sequentially input pull-up signals to the front M-level shift register unit;
and after the pull-up signal is input, controlling the frame starting signal line to cut off the connection between the continuous M clock signal lines and the input end of the front M-level shift register unit before the continuous M clock signal lines are output next time.
Further, the step of controlling the frame start signal line to conduct the connection between the consecutive M clock signal lines and the input end of the shift register unit of the previous M stages includes:
controlling the frame starting signal line to output a conducting signal to enable the source electrodes and the drain electrodes of the M switch thin film transistors to be conducted;
the step of controlling the frame start signal line to block the connection between the consecutive M clock signal lines and the input end of the preceding M-stage shift register unit before the next output of the consecutive M clock signal lines after the pull-up signal is input, includes:
and after the pull-up signal is input, controlling the frame starting signal line to output a cut-off signal before the continuous M clock signal lines are output next time, so that the source electrodes and the drain electrodes of the M switch thin film transistors are cut off.
Further, the frame start signal line is controlled to provide a pull-down signal to the rear M-stage shift register unit after the rear M-stage shift register unit outputs the gate scanning signal.
Further, the step of controlling the frame start signal line to provide a pull-down signal to the M-stage shift register unit after the M-stage shift register unit outputs the gate scan signal includes:
and controlling the frame starting signal line to provide a pull-down signal for a target shift register unit after the target shift register unit outputs a grid scanning signal, wherein the target shift register unit is a shift register unit in the rear M-stage shift register unit.
Further, the step of driving the frame start signal line to provide a pull-down signal to the M-stage shift register unit after the M-stage shift register unit outputs the gate scan signal includes:
and controlling the frame starting signal line to provide a pull-down signal for the rear M-level shift register unit after the Nth-level shift register unit outputs a grid scanning signal.
In a third aspect, an embodiment of the present invention further provides a display device, including the gate driving circuit as described above.
In the technical scheme provided by the invention, continuous M clock signals are connected with the input end of the front M-level shift register unit, the continuous M clock signal lines are controlled to be respectively conducted or separated with the input end of the front M-level shift register unit through one STV line, and the front M-level shift register unit sequentially obtains pull-up signals provided by the continuous M clock signals when the continuous M clock signal lines are conducted, so that the number of the STV lines is not required to be increased while the clock signal lines are increased, and the narrow frame design of the display device is facilitated. Therefore, the technical scheme provided by the invention can facilitate the narrow frame design of the display device.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive exercise.
Fig. 1 is a schematic connection diagram of an STV signal line, a front M-stage shift register unit and a rear M-stage shift register unit in a gate driving circuit according to an embodiment of the present invention;
fig. 2 is a timing diagram of a turn-on signal output from an STV signal line and pull-up signals output from three consecutive clock signal lines in a gate driving circuit according to an embodiment of the present invention;
fig. 3 is a waveform diagram of an output of an STV signal line in a gate driving circuit according to an embodiment of the invention;
fig. 4 is a connection diagram of a gate driving circuit according to an embodiment of the invention;
fig. 5 is a waveform diagram of gate scan signals output by the front stage shift register unit and the rear stage shift register unit in the gate driving circuit according to an embodiment of the present invention;
fig. 6 is a flowchart of a driving method of a gate driving circuit according to an embodiment of the invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
In the prior art, the time for precharging and charging the GOA circuit is prolonged by adding a clock signal line (CLK line), and the precharging time of the pixel is prolonged, so that the display effect of the display device can be improved. However, in the conventional gate driving circuit, in the connection manner of the multi-phase circuit (i.e., the plurality of CLK signal lines are respectively connected to the shift register unit), the four-phase circuit requires at least two STV signal lines, the six-phase circuit requires at least three STV signal lines, the eight-phase circuit requires at least four STV signal lines … …, and so on, and the STV signal lines increase with the increase of the CLK lines, which increases the width of the frame while improving the display effect of the display device, and is not favorable for the development trend of the display device toward a narrow frame.
Embodiments of the present invention provide a gate driving circuit, a driving method thereof, and a display device to solve the problem that the conventional connection method requires an additional STV line while increasing the CLK line, which is not favorable for the narrow frame trend of the display device.
The embodiment of the present invention provides a gate driving circuit, including N stages of sequentially cascaded shift register units, each shift register unit being configured to provide a gate scanning signal for a gate line corresponding to the shift register unit, the gate driving circuit further including:
2M clock signal lines, the clock signal ends of the N-stage shift register units are respectively connected with the N-stage shift register units
The 2M clock signal lines are connected, wherein the M continuous clock signal lines are sequentially connected with the input end of the shift register unit of the previous M level and used for providing a pull-up signal for the shift register unit of the previous M level; n is an integral multiple of 2M, and M is a positive integer greater than 1;
and the frame starting signal line is used for controlling the conduction or the separation between the continuous M clock signal lines and the input end of the shift register unit of the previous M stages.
In the embodiment of the invention, the continuous M clock signals are connected with the input end of the front M-level shift register unit, the continuous M clock signal lines are controlled to be respectively conducted or separated with the input end of the front M-level shift register unit through one STV line, and the front M-level shift register unit sequentially obtains the pull-up signals provided by the continuous M clock signals when the front M-level shift register unit is conducted, so that the number of the STV lines is not required to be increased when the clock signal lines are increased, and the narrow frame design of the display device is convenient. Therefore, the technical scheme provided by the invention can facilitate the narrow frame design of the display device.
The N stages of shift register units which are sequentially cascaded comprise N shift register units, wherein the output end of the X-th stage shift register unit is connected with the input end of the X + M-th stage shift register unit, and a pull-up signal can be provided for the X + M-th stage shift register unit when the X-th stage shift register unit outputs a grid scanning signal; the output end of the X + M stage shift register unit is connected with the reset end of the X stage shift register unit, and a pull-down signal can be provided for the X stage shift register unit when the X + M stage shift register unit outputs a grid scanning signal. And X is a positive integer which is larger than M and smaller than N-M.
And the clock signal ends of the N-stage sequentially cascaded shift register units are respectively connected with the continuous 2M clock signal lines in a one-to-one correspondence manner. The signals of the 2M clock signal lines are cyclic, and for example, when M is 2, CLK1, CLK2, CLK3, and CLK4 may be one cycle, or CLK3, CLK4, CLK1, and CLK2 may be one cycle.
The input end of the shift register unit of the front M level is sequentially connected with M continuous clock signals, and the switching on or off of the shift register unit of the front M level and the M continuous clock signals is controlled through 1 STV signal line; when the shift register is turned on, the M continuous clock signals sequentially transmit the pull-up signals to the first-stage shift register unit, the second-stage shift register unit, … … and the Mth-stage shift register unit. Thus, the N-stage shift registers can start to operate sequentially to supply gate scan signals to the corresponding gate lines.
The reset terminal of the shift register unit of the next M-stage may provide a pull-down signal through an additional circuit (dummy circuit), or may provide a pull-down signal through an STV signal line, which is not limited herein.
Further, as shown in fig. 1, the gate driving circuit further includes M switching thin film transistors, gates of the M switching thin film transistors are all connected to the frame start signal line, sources of the M switching thin film transistors are respectively connected to the M consecutive clock signal lines, and drains of the M switching thin film transistors are respectively connected to the input end of the shift register unit of the previous M stages.
In this embodiment, the STV signal line is connected to the gate of the switching thin film transistor, and the STV signal line outputs a high level, so that the source and the drain of the switching thin film transistor are connected, the clock signal line is connected to the input terminal of the shift register unit, and the shift register unit obtains a pull-up signal. After the front M-stage shift register units all receive the pull-up signal, the STV signal line outputs low level, so that the source electrode and the drain electrode of the switch thin film transistor are separated, and the clock signal line is separated from the input end of the shift register unit.
As shown in fig. 2, taking M ═ 3 as an example, the STV signal line outputs a high level in a period from T1 to T2, so that the source and drain of the switching thin film transistor are turned on in a period from T1 to T2, i.e., the clock signal line is turned on with the input terminal of the shift register unit. Three clock signal lines (CLK1, CLK2, and CLK3) consecutive in a period from T1 to T2 sequentially supply pull-up signals to the preceding three-stage shift register unit, thereby enabling the N-stage shift register unit to start normally outputting gate scan signals.
The switch thin film transistor is used for controlling the conduction or the separation of the continuous M clock signal lines and the front M-level shift register units, so that the power consumption of control can be reduced, the stability of control can be improved, and the display device can be thinned.
In some optional embodiments, the frame start signal line is further connected to a reset terminal of the shift register unit of the next M stages, and is configured to provide a pull-down signal to the shift register unit of the next M stages.
In this embodiment, the output waveform of the STV signal line is as shown in fig. 3, and after outputting the on signal and the off signal, the STV signal line is further used to provide a pull-down signal to the rear M-stage shift register unit.
The STV signal line may provide a pull-down signal to the shift register unit after the shift register unit in the shift register unit of the rear M stage outputs the gate scan signal, so as to provide a pull-down signal to each shift register unit belonging to the rear M stage. And when the shift register unit outputs the grid scanning signal, the source electrode and the drain electrode of the switch thin film transistor are conducted, so that the shift register unit obtains a pull-down signal provided by the STV signal line.
In addition, the STV signal line may also uniformly supply a pull-down signal to the shift register unit of the next M stages after the shift register unit of the mth stage outputs the gate scan signal (the connection relationship is shown in fig. 1). The M-level shift register unit only needs to obtain a pull-down signal before a clock signal of a next frame comes, so that the pull-down signal can be uniformly provided after the M-level shift register unit outputs a grid scanning signal, and the power consumption is reduced.
In this embodiment, pull-down signals are provided to the M-stage shift register units through the STV signal lines, so that a frame space occupied by the dummy circuit can be omitted, and the narrow frame design of the display device is further facilitated.
As shown in fig. 4, taking M ═ 3 as an example, the gate driving circuit includes 6 clock signal lines, namely a first clock signal line CLK1, a second clock signal line CLK2, a third clock signal line CLK3, a fourth clock signal line CLK4, a fifth clock signal line CLK5, and a sixth clock signal line CLK 6.
The first clock signal line CLK1 is connected to the input terminal of the first stage shift register cell GOA1, and the fourth clock signal line CLK4 is connected to the clock signal terminal of the first stage shift register cell GOA 1;
the second clock signal line CLK2 is connected to the input terminal of the second stage shift register unit GOA2, and the fifth clock signal line CLK5 is connected to the clock signal terminal of the second stage shift register unit GOA 2;
the third clock signal line CLK3 is connected to the input terminal of the third stage shift register cell GOA3, and the sixth clock signal line CLK6 is connected to the clock signal terminal of the third stage shift register cell GOA 3.
The operation of the N-stage shift register unit is illustrated in time order:
providing a pull-up signal to the first stage shift register unit by CLK1, providing a pull-up signal to the second stage shift register unit by CLK2, and finally providing a pull-up signal to the third stage shift register unit by CLK 3;
the first stage shift register unit obtains a pull-up signal, outputs a grid scanning signal when receiving a clock signal of CLK4, and provides the pull-up signal to the fourth stage shift register unit while outputting the grid scanning signal; then, the second stage shift register unit obtains a pull-up signal, outputs a gate scanning signal when receiving a clock signal of CLK5, and provides the pull-up signal to the fifth stage shift register unit while outputting the gate scanning signal; then, the third stage shift register unit obtains a pull-up signal, outputs a gate scanning signal when receiving the clock signal of the CLK6, and provides the pull-up signal to the sixth stage shift register unit while outputting the gate scanning signal;
the fourth-stage shift register unit obtains a pull-up signal, outputs a grid scanning signal when receiving a clock signal of CLK1, and provides the pull-up signal to the seventh-stage shift register unit while outputting the grid scanning signal; then, the fifth stage shift register unit obtains a pull-up signal, outputs a gate scanning signal when receiving the clock signal of CLK2, and provides the pull-up signal to the eighth stage shift register unit while outputting the gate scanning signal; then, the sixth stage shift register unit obtains a pull-up signal, outputs a gate scanning signal when receiving the clock signal of the CLK3, and provides the pull-up signal to the ninth stage shift register unit while outputting the gate scanning signal;
and repeating the steps until the N-2 stage shift register unit, the N-1 stage shift register unit and the N stage shift register unit output the grid scanning signals in sequence, and finishing the output of the N rows of grid scanning signals in one frame of picture display time period. As shown in fig. 5, when M is 3, the waveforms of the gate scan signals output from the first three stage shift register unit and the second three stage shift register unit.
An embodiment of the present invention further provides a driving method of the gate driving circuit, as shown in fig. 6, the method includes:
step 601: controlling the frame start signal line to conduct the connection between the continuous M clock signal lines and the input end of the front M-level shift register unit in the display time period of one frame of picture, wherein the continuous M clock signal lines sequentially input pull-up signals to the front M-level shift register unit;
step 602: and after the pull-up signal is input, controlling the frame starting signal line to cut off the connection between the continuous M clock signal lines and the input end of the front M-level shift register unit before the continuous M clock signal lines are output next time.
In the embodiment of the invention, the continuous M clock signals are connected with the input end of the front M-level shift register unit, the continuous M clock signal lines are controlled to be respectively conducted or separated with the input end of the front M-level shift register unit through one STV line, and the front M-level shift register unit sequentially obtains the pull-up signals provided by the continuous M clock signals when the front M-level shift register unit is conducted, so that the number of the STV lines is not required to be increased when the clock signal lines are increased, and the narrow frame design of the display device is convenient. Therefore, the technical scheme provided by the invention can facilitate the narrow frame design of the display device.
As shown in fig. 3, at the beginning stage in the display period of one frame of picture, the STV signal line outputs a turn-on signal, and the connections between the consecutive M clock signal lines and the input terminals of the shift register units of the previous M stages are turned on, so that the consecutive M clock signal lines sequentially input pull-up signals to the shift register units of the previous M stages during the turn-on period. After the pull-up signal is input, the STV signal line outputs a blocking signal to block the connection between the continuous M clock signal lines and the input end of the front M-stage shift register unit, so that the subsequent continuous M clock signal lines provide clock signals for the shift register.
After the first M-stage shift register units sequentially obtain the pull-up signal, the N-stage shift register units can start to sequentially operate to provide the gate scanning signal to the corresponding gate line through the connection relationship and signal conduction (refer to the illustration corresponding to fig. 4, which is not described here again).
Further, as shown in fig. 1, in a case that the gate driving circuit further includes M switching thin film transistors, gates of the M switching thin film transistors are all connected to the frame start signal line, sources of the M switching thin film transistors are respectively connected to the consecutive M clock signal lines, and drains of the M switching thin film transistors are respectively connected to the input terminals of the M-stage shift register units, the step of controlling the frame start signal line to turn on the connection between the consecutive M clock signal lines and the input terminals of the M-stage shift register units includes:
controlling the frame starting signal line to output a conducting signal to enable the source electrodes and the drain electrodes of the M switch thin film transistors to be conducted;
the step of controlling the frame start signal line to block the connection between the consecutive M clock signal lines and the input end of the preceding M-stage shift register unit before the next output of the consecutive M clock signal lines after the pull-up signal is input, includes:
and after the pull-up signal is input, controlling the frame starting signal line to output a cut-off signal before the continuous M clock signal lines are output next time, so that the source electrodes and the drain electrodes of the M switch thin film transistors are cut off.
In this embodiment, the STV signal line is connected to the gate of the switching thin film transistor, and the STV signal line outputs a high level, so that the source and the drain of the switching thin film transistor are connected, the clock signal line is connected to the input terminal of the shift register unit, and the shift register unit obtains a pull-up signal. After the front M-stage shift register units all receive the pull-up signal, the STV signal line outputs low level, so that the source electrode and the drain electrode of the switch thin film transistor are separated, and the clock signal line is separated from the input end of the shift register unit.
As shown in fig. 2, taking M ═ 3 as an example, the STV signal line outputs a high level in a period from T1 to T2, so that the source and drain of the switching thin film transistor are turned on in a period from T1 to T2, i.e., the clock signal line is turned on with the input terminal of the shift register unit. Three clock signal lines (CLK1, CLK2, and CLK3) consecutive in a period from T1 to T2 sequentially supply pull-up signals to the preceding three-stage shift register unit, thereby enabling the N-stage shift register unit to start normally outputting gate scan signals.
The switch thin film transistor is used for controlling the conduction or the separation of the continuous M clock signal lines and the front M-level shift register units, so that the power consumption of control can be reduced, the stability of control can be improved, and the display device can be thinned.
In an optional embodiment, the frame start signal line is further connected to a reset terminal of the shift register unit of the next M stages; the driving method of the gate driving circuit further includes:
and controlling the frame starting signal line to provide a pull-down signal for the rear M-level shift register unit after the rear M-level shift register unit outputs the grid scanning signal.
In this embodiment, pull-down signals are provided to the M-stage shift register units through the STV signal lines, so that a frame space occupied by the dummy circuit can be omitted, and the narrow frame design of the display device is further facilitated.
In an optional implementation manner, the step of controlling the frame start signal line to provide a pull-down signal to the M-stage shift register unit after the M-stage shift register unit outputs the gate scan signal includes:
and controlling the frame starting signal line to provide a pull-down signal for a target shift register unit after the target shift register unit outputs a grid scanning signal, wherein the target shift register unit is a shift register unit in the rear M-stage shift register unit.
In this embodiment, the STV signal line provides a pull-down signal to the target shift register unit after the target shift register unit in the shift register unit of the next M-stage outputs the gate scan signal, so as to provide a pull-down signal to each shift register unit belonging to the next M-stage. And when the shift register unit outputs the grid scanning signal, the source electrode and the drain electrode of the switch thin film transistor are conducted, so that the shift register unit obtains a pull-down signal provided by the STV signal line.
The STV signal line provides a pull-down signal for the target shift register unit after the target shift register unit outputs the grid scanning signal, so that the target shift register unit can prepare to deal with the pull-up signal of the next frame of picture, and the normal work of the target shift register is ensured.
In another optional implementation, the step of driving the frame start signal line to provide a pull-down signal to the M-stage shift register unit after the M-stage shift register unit outputs the gate scan signal includes:
and controlling the frame starting signal line to provide a pull-down signal for the rear M-level shift register unit after the Nth-level shift register unit outputs a grid scanning signal.
In this embodiment, the STV signal line supplies pull-down signals to the M-stage shift register units in a unified manner after the nth stage shift register unit outputs the gate scan signal (the connection relationship is shown in fig. 1).
Since the M-stage shift register units only need to obtain the pull-down signal before the clock signal of the next frame comes, the pull-down signals can be uniformly provided after the M-stage shift register units output the grid scanning signals, and the power consumption is reduced.
The embodiment of the invention also provides a display device which comprises the gate driving circuit. The display device may be: the display device comprises a television, a display, a digital photo frame, a mobile phone, a tablet personal computer, a navigator and other products or components with display functions, wherein the display device further comprises a flexible circuit board, a printed circuit board and a back plate.
Unless defined otherwise, technical or scientific terms used herein shall have the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The use of "first," "second," and similar terms in this disclosure is not intended to indicate any order, quantity, or importance, but rather is used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that the element or item listed before the word covers the element or item listed after the word and its equivalents, but does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", and the like are used merely to indicate relative positional relationships, and when the absolute position of the object being described is changed, the relative positional relationships may also be changed accordingly.
It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.
While the present invention has been described with reference to the embodiments shown in the drawings, the present invention is not limited to the embodiments, which are illustrative and not restrictive, and it will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (10)
1. A kind of grid drive circuit, including N cascaded shift register units sequentially, each stated shift register unit is used for providing the grid scanning signal for its correspondent grating line, characterized by, the stated grid drive circuit also includes:
the clock signal ends of the N-level shift register units are respectively connected with the 2M clock signal lines, wherein the continuous M clock signal lines are sequentially connected with the input end of the previous M-level shift register unit and used for providing pull-up signals for the previous M-level shift register unit; n is an integral multiple of 2M, and M is a positive integer greater than 1;
and the frame starting signal line is used for controlling the conduction or the separation between the continuous M clock signal lines and the input end of the shift register unit of the previous M stages.
2. The gate driving circuit according to claim 1, further comprising M switching thin film transistors, wherein gates of the M switching thin film transistors are all connected to the frame start signal line, sources of the M switching thin film transistors are respectively connected to the M consecutive clock signal lines, and drains of the M switching thin film transistors are respectively connected to the input terminals of the shift register units of the previous M stages.
3. The gate driving circuit according to claim 1, wherein the frame start signal line is further connected to a reset terminal of the M-stage shift register unit for providing a pull-down signal to the M-stage shift register unit.
4. A gate drive circuit as claimed in claim 1, wherein M-3;
the first clock signal line is connected with the input end of the first-stage shift register unit, and the fourth clock signal line is connected with the clock signal end of the first-stage shift register unit;
the second clock signal line is connected with the input end of the second-stage shift register unit, and the fifth clock signal line is connected with the clock signal end of the second-stage shift register unit;
and the sixth clock signal line is connected with the clock signal end of the third-stage shift register unit.
5. A method of driving a gate drive circuit as claimed in any one of claims 1 to 4, the method comprising:
controlling the frame start signal line to conduct the connection between the continuous M clock signal lines and the input end of the front M-level shift register unit in the display time period of one frame of picture, wherein the continuous M clock signal lines sequentially input pull-up signals to the front M-level shift register unit;
and after the pull-up signal is input, controlling the frame starting signal line to cut off the connection between the continuous M clock signal lines and the input end of the front M-level shift register unit before the continuous M clock signal lines are output next time.
6. The method of claim 5, applied to the gate driving circuit of claim 2; the step of controlling the frame start signal line to connect the consecutive M clock signal lines to the input end of the shift register unit of the previous M stages includes:
controlling the frame starting signal line to output a conducting signal to enable the source electrodes and the drain electrodes of the M switch thin film transistors to be conducted;
the step of controlling the frame start signal line to block the connection between the consecutive M clock signal lines and the input end of the preceding M-stage shift register unit before the next output of the consecutive M clock signal lines after the pull-up signal is input, includes:
and after the pull-up signal is input, controlling the frame starting signal line to output a cut-off signal before the continuous M clock signal lines are output next time, so that the source electrodes and the drain electrodes of the M switch thin film transistors are cut off.
7. The method of claim 5, applied to the gate driving circuit of claim 3; the method further comprises the following steps:
and controlling the frame starting signal line to provide a pull-down signal for the rear M-level shift register unit after the rear M-level shift register unit outputs the grid scanning signal.
8. The method according to claim 7, wherein the step of controlling the frame start signal line to provide a pull-down signal to the next M-stage shift register unit after the next M-stage shift register unit outputs the gate scan signal comprises:
and controlling the frame starting signal line to provide a pull-down signal for a target shift register unit after the target shift register unit outputs a grid scanning signal, wherein the target shift register unit is a shift register unit in the rear M-stage shift register unit.
9. The method according to claim 7, wherein the step of driving the frame start signal line to provide a pull-down signal to the next M-stage shift register unit after the next M-stage shift register unit outputs the gate scan signal comprises:
and controlling the frame starting signal line to provide a pull-down signal for the rear M-level shift register unit after the Nth-level shift register unit outputs a grid scanning signal.
10. A display device comprising the gate driver circuit according to any one of claims 1 to 4.
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| CN110264937B (en) * | 2019-06-27 | 2023-04-11 | 京东方科技集团股份有限公司 | Gate drive circuit, test method thereof and display device |
| CN112331120A (en) * | 2020-11-05 | 2021-02-05 | 北海惠科光电技术有限公司 | Array substrate row driving reset circuit and method and display device |
| CN114519977B (en) * | 2020-11-19 | 2023-07-25 | 上海和辉光电股份有限公司 | Array substrate and display panel |
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