JP2006074524A - Serial signal transmitting device, serial signal receiving device, serial transmitting device, and serial transmitting method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a serial transmitting device capable of reducing the number of signal lines, and having high reliability in response to disturbance such as noises, static electricity, etc. <P>SOLUTION: A data signal and a synchronous pattern which is consist of the same data length as a command signal and composed of different values in a start bit and a stop bit are to be transmitted before the data signal or a command signal is started a transmission from a transmission side circuit 2 to a reception side circuit 3 by using signal lines 14P, 14N for transmitting the data signal and the command signal. And in the reception side circuit 3, a phase of an output signal PLL_OUT is made to be synchronized to the phase of the data signal and the command signal by controlling the phase of the output signal PLL_OUT received by a PLL 12 based on the synchronous pattern received by a receiver 10R. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a serial signal transmission device that converts an input data signal into a serial signal based on a clock signal and transmits the serial signal, a serial signal reception device that converts a received serial signal into a parallel signal, the serial signal transmission device, and The present invention relates to a serial transmission device including a serial signal receiving device and a serial transmission method.

  In recent years, the serial transmission method is frequently used for data transmission between communication devices or electronic parts such as integrated circuits. Data transmission by the serial transmission method has an advantage that the number of signal lines required is smaller than that of the parallel transmission method because data is transmitted serially bit by bit using one transmission line.

  FIG. 12 is a circuit diagram showing an example of a conventional serial transmission device. The serial transmission apparatus shown in this figure includes a transmission side circuit 101 and a reception side circuit 102.

  The transmission side circuit 101 includes a latch circuit 103, a parallel / serial conversion circuit 104, a transmitter 105T, and a transmitter 106T. The reception side circuit 102 includes a receiver 105R, a receiver 106R, a latch circuit 107, and a serial / parallel conversion circuit 108.

  The latch circuit 103 provided in the transmission side circuit 101 outputs the parallel data signal PD input via the bus line to the parallel / serial conversion circuit 104 at a timing corresponding to the clock signal CK.

  The parallel-serial conversion circuit 104 converts the parallel data signal PD input from the latch circuit 103 into a serial data signal SD based on the clock signal CK, and outputs the serial data signal SD to the transmitter 105T.

  The transmitter 105T generates a pair of differential data signals SD + and SD− from the serial data signal SD input from the parallel-serial conversion circuit 104, and transmits the pair of differential data signals SD + and SD− to the receiver 105R provided in the reception-side circuit 102.

  In addition, the clock signal CK is input to the transmitter 106T provided in the transmission side circuit 101, and the transmitter 106T generates differential clock signals CK + and CK− from the input clock signal CK. It transmits to the receiver 106R with which it is equipped.

  On the other hand, the receiver 105R provided in the receiving circuit 102 generates a serial data signal SD based on the differential data signals SD + and SD− received from the transmitter 105T and outputs the serial data signal SD to the latch circuit 107.

  Further, the receiver 106R generates a clock signal CK based on the differential clock signals CK + and CK− received from the transmitter 106T, and outputs the clock signal CK to the latch circuit 107.

  The latch circuit 107 outputs the serial data signal SD input from the receiver 106R to the serial / parallel conversion circuit 109 at a timing according to the clock signal CK.

  The serial / parallel conversion circuit 108 converts the serial data signal SD input from the latch circuit 107 into a parallel data signal PD and outputs the parallel data signal PD.

  As described above, in the conventional serial transmission device, the synchronous serial communication is performed by transmitting the data signal and the clock signal by two differential pairs.

For example, Patent Documents 1 and 2 describe techniques for reducing the number of signal lines and reducing the size of a device in a device that performs synchronous serial communication.
JP 2004-104522 A (published April 2, 2004) JP 2001-282714 A (released on October 12, 2001)

  However, in the above conventional technique, since the data signal and the clock signal are transmitted by two differential pairs, at least four signal lines are necessary. For the reduction of the number of signal lines and the miniaturization of the apparatus. There was a limit. In addition, when transmission is performed at high speed, transmission cannot be performed when a delay difference (skew) between a clock and data occurs, which greatly restricts board design.

  Further, in the above conventional technique, since the clock signal is serially transmitted (serial clock signal is transmitted), if the clock signal is disturbed by the influence of noise, static electricity, etc., the reception side circuit is likely to malfunction. was there.

  The present invention has been made in view of the above-described problems, and its purpose is to reduce the number of signal lines and to provide a highly reliable serial signal transmission device, serial signal reception device with respect to disturbances such as noise and static electricity, A serial transmission device and a serial transmission method are provided.

  In order to solve the above-described problem, a serial signal transmission device according to the present invention is a serial signal transmission device that converts an input data signal into a serial signal based on a clock signal and transmits the serial signal. Synchronization pattern generating means for generating a synchronization pattern having the same data length as the signal and different values of the start bit and the stop bit, and transmitting the serial signal and the synchronization pattern using a common signal line It is characterized by doing.

  According to the above configuration, the receiving device that receives the signal transmitted from the serial signal transmitting device can perform synchronization based on the synchronization pattern. That is, the device on the receiving side can be synchronized with the serial signal transmission device based on the synchronization pattern transmitted by the common signal line with the serial signal without transmitting the clock signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  In the above configuration, transmission of the synchronization pattern may be continued while the serial signal is not transmitted. In this case, in the receiving-side apparatus that receives the signal transmitted from the serial signal transmitting apparatus, synchronization based on the synchronization pattern can be continuously performed and the synchronization state can be maintained.

  Further, the serial signal and the synchronization pattern may be transmitted as a differential transmission type signal. Noise and unnecessary radiation can be reduced by transmitting signals using a differential transmission method.

  The LVDS method may be used as the differential transmission method. When the LVDS method is used, the power consumption is almost the same between when the signal is transmitted and when the signal is not transmitted. For this reason, the transmission of the synchronization pattern can be continued during a period in which the serial signal is not transmitted without substantially increasing the power consumption.

  In addition, after the synchronization pattern is transmitted, the serial signal transmission may be started when a fixed notification signal indicating that synchronization of the transmission destination device is established is received from the transmission destination device.

  According to the above configuration, the transmission of the serial signal is started after the synchronization between the receiving device that receives the signal transmitted from the serial signal transmitting device and the serial signal transmitting device is established. Therefore, more reliable signal transmission can be performed.

  In addition, after the start of transmission of the serial signal, when a lock release signal indicating that the transmission destination device is out of synchronization is received from the transmission destination device, the transmission of the serial data is awaited. The transmission of the serial data may be resumed when a pattern is transmitted and a fixed notification signal indicating that synchronization of the transmission destination device has been established is received from the transmission destination device.

  According to the above configuration, when the transmission destination device is out of synchronization, the transmission of the serial signal can be stopped and the transmission of the synchronization pattern can be started. Then, after the synchronization in the transmission destination device is established again, the transmission of the serial data can be resumed. Thereby, signal transmission with higher reliability can be performed.

  In order to solve the above problems, a serial signal receiving apparatus according to the present invention is a serial signal receiving apparatus that converts a received serial signal into a parallel signal, and controls and fixes the phase of an output signal. The phase fixing means receives the phase of the signal output from the phase fixing means via a signal line common to the serial signal, has the same data length as the serial signal, and has a start bit and stop It is characterized by synchronizing with the phase of the serial signal by controlling based on a synchronization pattern consisting of a value different from the bit.

  According to the above configuration, the phase fixing means receives the phase of the signal output from the phase fixing means via the signal line common to the serial signal, and has the same data length as the serial signal, and By controlling based on the synchronization pattern in which the start bit and the stop bit have different values, the phase of the serial signal is synchronized. As a result, the phase of the signal output from the phase fixing means can be synchronized with the phase of the serial signal based on the synchronization pattern received by the common signal line with the serial signal without receiving the clock signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  Further, the phase fixing means includes a synchronization detecting means for detecting whether or not the phase of the signal output from the phase fixing means is synchronized with the phase of the serial signal, and the phase of the signal output from the phase fixing means. A configuration may be provided that includes a fixed notification means for generating a fixed notification signal indicating the phase and transmitting it to the transmission source device of the serial signal when the phase is synchronized with the phase of the serial signal.

  According to said structure, the said synchronous detection means detects whether the phase of the signal which the said phase fixing means outputs is synchronizing with the phase of the said serial signal. The fixed notification means generates a fixed notification signal indicating that the phase of the signal output from the phase fixing means is synchronized with the phase of the serial signal as a result of detection by the synchronization detection means. To the serial signal transmission source device. Thereby, in the serial signal transmission source device, the synchronization state in the serial signal reception device can be grasped. Thus, for example, the transmission source device transmits the serial signal only when the synchronization state in the serial signal reception device is established, and transmits the synchronization pattern when the synchronization state is not established. Therefore, more reliable signal transmission can be performed.

  Further, the synchronization detection means, during the period of receiving the synchronization pattern, by comparing the edge of a specific pulse in the signal output from the phase fixing means with the edge of the start bit in the synchronization pattern, It is good also as a structure which detects whether the phase of the signal which the said phase fixing means outputs is synchronizing with the phase of the said serial signal.

  According to said structure, the said synchronous detection means detects whether the phase of the signal which the said phase fixing means outputs is synchronizing with the phase of the said serial signal based on the said synchronous pattern. Thus, for example, after controlling the phase of the signal output from the phase fixing means based on the synchronization pattern to synchronize with the phase of the serial signal, the transmission side transmitting the serial signal indicates that synchronization has been established. The device can be notified and the transmission of the serial signal can be started. Therefore, more reliable signal transmission can be performed.

  In addition, the synchronization detection unit compares the edge of the specific pulse in the signal output from the phase fixing unit with the edge of the start bit of the serial signal during the period of receiving the serial signal, It is detected whether the phase of the signal output from the phase fixing means is synchronized with the phase of the serial signal, and the fixing notification means is configured to detect the phase of the signal output from the phase fixing means and the phase of the serial signal. When the synchronization with the serial signal is lost, a fixed release signal indicating that may be generated and transmitted to the device that has transmitted the serial signal.

  According to the above configuration, the synchronization detection means detects whether or not the phase of the signal output from the phase fixing means is synchronized with the phase of the serial signal based on the edge of the start bit of the serial signal. To do. When the phase of the signal output from the phase fixing unit and the phase of the serial signal are out of synchronization, the fixing notification unit generates a fixing release signal indicating that and transmits the source of the serial signal To the device. Therefore, if the phase of the signal output from the phase fixing means and the phase of the serial signal are out of synchronization during the reception of the serial signal, this is notified to the transmission side device that transmits the serial signal. be able to. Thereby, for example, the transmission-side apparatus can stop the transmission of the serial signal and start the transmission of the synchronization pattern, and can perform signal transmission with higher reliability.

  The phase locking means includes phase comparison means for detecting a phase shift between both signals by comparing the edge of a specific pulse in the signal output from the phase locking means with the edge of the start bit of the serial signal. The phase of the signal output from the phase fixing unit may be controlled so that the phase shift between the two signals detected by the phase comparison unit is small.

  According to said structure, the phase of the signal which the said phase fixing means outputs is controlled based on the said serial signal. Thus, the phase of the signal output from the phase fixing means can be controlled even during reception of the serial signal, and signal transmission with higher reliability can be performed.

  The serial signal receiving apparatus of the present invention further comprises signal determining means for determining whether the received signal is the synchronization pattern or the serial signal, and only when the received signal is a serial signal. The parallel signal may be output to the outside.

  According to the above configuration, the synchronization pattern received via the common signal line and the serial signal can be discriminated, and only the parallel signal corresponding to the serial signal can be output.

  The serial transmission device of the present invention includes any one of the serial signal transmission devices described above and one of the serial signal reception devices described above. Here, the serial transmission device of the present invention may transmit a serial signal between the serial signal transmission device and the serial signal reception device via a transmission line, a network, or the like, or may be a common device. A serial signal may be transmitted between electronic components such as an integrated circuit provided in the apparatus.

  According to the above configuration, the serial signal receiving device can perform synchronization based on the synchronization pattern transmitted from the serial signal transmitting device using a signal line common to the signal line for transmitting the serial signal. . That is, the serial signal receiving device can be synchronized with the serial signal transmitting device based on a synchronization pattern transmitted through a signal line common to the serial signal without transmitting a clock signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  In order to solve the above-described problem, the serial signal transmission method of the present invention converts an input data signal into a serial signal based on a clock signal, transmits the serial signal from the serial signal transmission device, and changes the phase of the output signal. A serial transmission method for receiving and converting the transmitted serial signal to a parallel signal by a serial signal receiving device having phase fixing means for controlling and fixing, and having the same data length as the transmitted serial signal, And generating a synchronization pattern having different values of the start bit and the stop bit, transmitting the synchronization pattern using a signal line that is common to the signal line for transmitting the serial signal, and fixing the phase. The phase of the serial signal is controlled by controlling the phase of the signal output from the means based on the synchronization pattern. It is characterized in that it comprises a step of synchronizing a.

  According to the above method, the serial signal receiving device can perform synchronization based on the synchronization pattern transmitted from the serial signal transmitting device using a signal line that is common to the signal line for transmitting the serial signal. . That is, the serial signal receiving device can be synchronized with the serial signal transmitting device based on a synchronization pattern transmitted through a signal line common to the serial signal without transmitting a clock signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  As described above, the serial signal transmission device of the present invention includes synchronization pattern generation means for generating a synchronization pattern having the same data length as the serial signal to be transmitted and having different values of the start bit and the stop bit. The serial signal and the synchronization pattern are transmitted using a common signal line.

  Therefore, the receiving-side device that receives the signal transmitted from the serial signal transmitting device can perform synchronization based on the synchronization pattern. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  The serial signal receiving device of the present invention comprises phase fixing means for controlling and fixing the phase of the output signal, and the phase fixing means sets the phase of the signal output from the phase fixing means in common with the serial signal. Control is made based on a synchronization pattern having the same data length as that of the serial signal received via the signal line and different values of the start bit and the stop bit, thereby synchronizing with the phase of the serial signal.

  Therefore, the phase of the signal output from the phase fixing means can be synchronized with the phase of the serial signal based on the synchronization pattern received by the signal line common to the serial signal without receiving the clock signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  The serial transmission device of the present invention includes any one of the serial signal transmission devices described above and one of the serial signal reception devices described above.

  Therefore, the serial signal receiving device can perform synchronization based on the synchronization pattern transmitted from the serial signal transmitting device using a signal line that is common to the signal line for transmitting the serial signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  The serial transmission method of the present invention includes a step of generating a synchronization pattern having the same data length as the serial signal to be transmitted and different values of a start bit and a stop bit, and the synchronization pattern is converted to the serial signal. Transmitting using a signal line that is common to the signal line to be transmitted, and synchronizing the phase of the serial signal by controlling the phase of the signal output from the phase fixing means based on the synchronization pattern; ,including.

  Therefore, the serial signal receiving device can perform synchronization based on the synchronization pattern transmitted from the serial signal transmitting device using a signal line that is common to the signal line for transmitting the serial signal. Therefore, highly reliable signal transmission against disturbances such as noise and static electricity can be performed. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  An embodiment of the present invention will be described. FIG. 1 is a block diagram illustrating a schematic configuration of a serial transmission device 1 according to the present embodiment. The serial transmission device 1 performs data communication including clock information using one differential pair (one channel). In addition, the serial transmission device 1 uses an LVDS (Low Voltage Differential Signaling) type signal for data communication including clock information.

  As shown in this figure, the serial transmission device 1 according to this embodiment includes a transmission side circuit 2 and a reception side circuit 3. Further, in the example shown in this figure, when data to be transmitted is prepared in the transmission side circuit 2, the link enable signal P is set to active “H”, and a communication start request is output from the transmission side. When receiving the signal P, the receiving side circuit 3 starts up the current source in the LVDS buffer and makes it usable, and simultaneously starts oscillation of the PLL and tries to synchronize with the received synchronization pattern. A transmission side circuit (serial signal transmission device) 2 includes a latch circuit 4, a frequency divider 5, a parallel serial (P / S) conversion circuit 6, a serial data insertion circuit 7, a timing control circuit 8, a synchronization pattern generation circuit 9, and a transmission 10T is provided.

  The reception side circuit (serial signal reception device) 3 includes a receiver 10R, a serial / parallel (S / P) conversion circuit 11, a PLL 12, and a timing control circuit 13. The receiver 10R has a built-in termination resistor (not shown).

An input data signal D _in and an input clock signal CLK _in are input to the transmission side circuit 2 from the outside. More specifically, the input data signal D _in is input to the data input terminal of the latch circuit 4 provided _{in the} transmission side circuit 2, and the frequency divider 5 and the timing control circuit provided in the transmission side circuit 2 are provided with the input clock signal CLK _in. 8 is input. Note that the data size of the input data signal D _in is not particularly limited, but in the present embodiment, a case of 20 bits will be described.

The frequency divider 5, 1 / n times the frequency of the input clock signal _{CLK in} inputted (n is an integer) lowered to (divides). In the present embodiment, the input clock signal CLK _in of 129.024 MHz is input to the transmission side circuit 2, and the frequency divider 5 reduces the frequency of the input clock signal CLK _in to 5.376 MHz that is 1/24 times. The transmission clock signal TCLK is generated. Then, the frequency divider 5 outputs the transmission clock frequency TCLK generated in this way to the clock terminal of the latch circuit 4.

The latch circuit 4 outputs the input data signal D _in input to the data input terminal to the parallel-serial conversion circuit 6 at a timing according to the transmission clock signal TCLK input to the clock terminal.

The parallel-serial conversion circuit 6 converts the inputted input data signal (parallel data signal) _Din into a serial data signal SD and outputs it to the serial data insertion circuit 7. Note that the conversion method to the serial data signal SD is not particularly limited, but in the present embodiment, the parallel data signal D _in is converted to the serial data signal SD by the LVDS method.

On the other hand, the input clock signal CLK _in input to the transmission side circuit 2 is input not only to the frequency divider 5 described above but also to the timing control circuit 8.

The timing control circuit 8, in response to the PLL lock signal nLOCK output and the input clock signal CLK _in inputted from the receiving side circuit 3, and outputs a synchronization pattern generation instruction signal α to the sync pattern generating circuit 9, the serial data A serial data insertion instruction signal β is output to the insertion circuit 7. The PLL lock signal nLOCK will be described later.

  The synchronization pattern generation circuit 9 generates a 24-bit synchronization pattern SYNC (see Table 1 described later) in response to the synchronization pattern generation instruction signal α from the timing control circuit 8 and outputs the synchronization pattern to the serial data insertion circuit 7. To do.

  The serial data insertion circuit 7 is a 24-bit data signal (serial signal) obtained by adding a start bit, a synchronization pattern discrimination bit, a parity bit, and a stop bit to the 20-bit serial data signal SD input from the parallel-serial conversion circuit 6. Alternatively, a 24-bit command signal (serial signal) indicating the start or end of the frame and line is generated. Then, the generated data signal (data) or command signal (command) is inserted between the synchronization patterns according to the serial data insertion instruction signal β input from the timing control circuit 8 and output to the transmitter 10T. The serial data insertion circuit 7 continues to output the synchronization pattern SYNC to the transmitter 10T when there is no serial data signal SD (data signal or command signal) to be transmitted. Even when there is serial data to be transmitted, if nLOCK is “H” (when the receiving side circuit 3 is not synchronized), the synchronization pattern SYNC is continuously output and the serial data is kept waiting. In the present embodiment, a signal output from the serial data insertion circuit 7 to the transmitter 10T and transmitted, that is, the above-described 24-bit data signal, command signal, and synchronization pattern are referred to as a transmission data signal TDATA.

  Table 1 below shows the data format of the transmission data signal TDATA.

  As shown in this table, in the synchronization pattern SYNC, 12 bits starting from the most significant bit (MSB: Most Significant Bit) are all “1” and 12 bits from the 13th bit to the least significant bit (LSB (Least Significant Bit)). The bits are all “0” and are composed of a total of 24 bits. That is, the synchronization pattern SYNC has the same data length (1 symbol = 24 bits) as the data signal and the command signal.

  On the other hand, the transmission data signal TDATA has a start bit (most significant bit) of “1”. The next bit (the second bit from the most significant bit) is “0” as a synchronization pattern distinguishing bit for distinguishing between the synchronization pattern SYNC and the transmission data signal TDATA.

  The next bit (the third bit from the most significant bit) is a data / command identification bit for identifying the data signal and the command signal. In the case of the command signal, “1”, in the case of the data signal Becomes “0”. The next bit (fourth bit from the most significant bit) is assigned “0” as a reserve bit in both the data signal and the command signal.

  In both the data signal and the command signal, the stop bit (the least significant bit) is “0”, and the bit immediately before it (the 23th bit from the most significant bit) is used for error checking. Of parity bits are allocated.

  The bits from the most significant bit to the 5th to 22nd bits are bits indicating the contents of the command signal and the data signal.

  In the case of a command signal, the fifth to 19th bits from the most significant bit are all “0”, and the contents of the command signal are shown by the 20th to 22nd bits. That is, of the 20th to 22nd bits, when only the 22nd bit is “1”, it indicates the start of the frame. When only the 21st bit is “1”, it indicates the end of the frame, and 20 bits. When only the eye is “0”, it indicates the start of the line, and when only the 20th bit is “1”, it indicates the end of the line.

  In the case of a data signal, data signals such as 8 bits × 2, 16 bits, 18 bits, RGB565 (16 bits), RGB666 (18 bits) are shown in Table 1 between the 5th and 22nd bits. Allocated as shown.

  The transmitter 10T converts the transmission data signal TDATA input from the serial data insertion circuit 7 into a pair of differential signals TxP and TxN, and from the positive terminal to the signal line 14P at a timing according to the transmission clock signal TCLK. The differential signal TxP is output, and the differential signal TxN is output from the negative terminal to the signal line 14N. As shown in FIG. 1, the link enable signal P input to the transmitter 10T, the receiver 10R, and the PLL 12 (VCO 25 provided in the PLL 12) is input from a control unit (not shown).

FIG. 2 is a timing chart showing the relationship among the input data signal D _in , the transmission clock signal TCLK, the differential signal TxP, and the differential signal TxN. As shown in this figure, 20 bits of the input data signal D _in is converted into 1 symbol = 24 bits of the differential signals TxP and TxN, is output from the start bit in order at a timing corresponding to the rising of the transmission clock signal TCLK The

  Since the serial transmission apparatus 1 according to the present embodiment employs the LVDS method, even if the synchronization pattern SYNC is continuously transmitted during a period in which the serial data signal SD is not transmitted, the power consumption does not transmit the synchronization pattern. And almost the same.

  The receiver 10R provided in the reception side circuit 3 is connected to the transmitter 10T provided in the transmission side circuit 2 via the signal line 14P and the signal line 14N. The receiver 10R receives the differential signals TxP and TxN output from the transmitter 10T as differential signals RxP and RxN, respectively, and the transmitter 10T performs differential processing based on the received differential signals RxP and RxN. The transmission data signal TDATA before being converted into the signals TxP and TxN is converted into a reception data signal RDATA, that is, a 24-bit data signal or a command signal or a synchronization pattern SYNC shown in Table 1 above. The converted reception data signal RDATA is output to the serial / parallel conversion circuit 11 and the PLL 12.

  A PLL (Phase Locked Loop) 12 generates a frequency signal synchronized with the received data signal RDATA. More specifically, the PLL 12 synchronizes the phase of the output frequency signal (oscillation signal) PLL_OUT with the synchronization pattern SYNC included in the reception data signal RDATA at initialization, and upon reception of the data signal or command signal, the reception data signal It is locked (fixed) in synchronization with the data signal or command signal included in RDATA. That is, as shown in FIG. 3, the PLL 12 synchronizes the phase of the output signal PLL_OUT using the start bit and stop bit included in the received data signal RDATA during data transmission, and when there is no received data signal RDATA, The phase of the output signal PLL_OUT is synchronized using a synchronization pattern that is continuously transmitted. Then, the PLL 12 outputs the output signal PLL_OUT synchronized as described above to the timing control circuit 13.

  The PLL 12 detects the phase lock state, and outputs a PLL lock signal nLOCK indicating the detection result to the timing control circuit 8 provided in the transmission side circuit 2. When the lock is released during communication (the phase is In the case of deviation, the PLL lock signal nLOCK is switched from “L (fixed notification signal)” to “H (fixed release signal)”.

  FIG. 4 shows a synchronization sequence when the serial transmission device 1 is initialized. As shown in this figure, in the serial transmission device 1, a 12-bit "" included in a pair of differential signals TxP (RxP) and TxN (RxN) transmitted between the transmitter 10T and the receiver 10R. The output signal PLL_OUT of the PLL 12 is synchronized with the received data signal RDATA based on a synchronization pattern SYNC composed of a repetition pattern of “1” and “0” of 12 bits. This synchronization process is performed by starting oscillation of the PLL by the link enable signal P and further locking the phase to the synchronization pattern. When synchronization is established, a signal indicating that the phase of the output signal PLL_OUT is synchronized and locked (PLL lock signal nLOCK = “L”) is transmitted to the transmission side circuit 2, and data transmission becomes possible. Details of the PLL 12 will be described later.

The timing control circuit 13 outputs an output clock signal CLK _out corresponding to the output from the PLL 12 to the outside of the serial / parallel conversion circuit 11 and the reception side circuit 3 (a circuit at the subsequent stage).

The serial / parallel conversion circuit (command / data recognition circuit, signal discriminating means) 11 performs serial / parallel conversion on the received data signal RDATA input from the receiver 10R based on the output clock signal CLK _out input from the timing control circuit 13. Then, it is determined whether it is a synchronization pattern, a command or data, and an output data signal _Dout is generated only when it is a command or data, and is output to the outside of the reception side circuit 3 (a circuit at the subsequent stage). As a result, the synchronization pattern transmitted using the common signal line and the command signal or the data signal (serial signal) can be discriminated, and only the parallel signal corresponding to the command signal and the data signal can be output appropriately. .

  Here, the configuration of the receiving circuit 3 will be described in more detail. FIG. 5 is a block diagram showing a configuration of the reception side circuit 3. As shown in this figure, the PLL 12 includes a reference generator 21, a reference signal generator 22, a phase comparator 23, an LPF 24, and a VCO 25.

  The reference generator 21 generates a reference signal REF_R indicating the edge of the reception data signal RDATA (the rising edge of the start bit of the reception data signal RDATA) and outputs it to the phase comparator 23.

  The reference signal generator 22 generates an edge signal REF_EDGE that becomes “H” for a specific one pulse every 24 pulses of the oscillation signal of the VCO 25 (output signal of the PLL 12) PLL_OUT, and indicates an edge comparison period, In order to compare with the edge of the received data signal RDATA, the reference signal REF_PLL for detecting the phase shift is generated by extracting the edge of the edge signal REF_EDGE of the output signal PLL_OUT, and is output to the phase comparator 23.

  The phase comparator 23 compares the reference signal REF_R input from the reference generator 21 with the reference signal REF_PLL input from the reference signal generator 22, and controls the oscillation frequency of the VCO 25 based on the comparison result. A control signal PC_OUT is generated and output to the LPF 24.

  The phase comparator 23 detects the synchronization state between the phase of the output signal PLL_OUT of the PLL 12 (VCO 25) and the phase of the reception data signal RDATA. If both signals are locked in synchronization, the phase comparator 23 is “L”. When not synchronized and not locked, a PLL lock signal nLOCK which becomes “H” is generated and output to the transmission side circuit 2 and the reference signal generator 22.

  The LPF 24 removes the high frequency component of the control signal PC_OUT input from the phase comparator 23 and outputs the low frequency component to the VCO 25.

  The VCO 25 generates an oscillation signal PLL_OUT having a frequency based on the control signal input from the LPF 24 and outputs it to the timing control circuit 13. The oscillation signal PLL_OUT is fed back to the reference signal generator 22 as described above.

  FIG. 6 is a circuit diagram showing a configuration example of the reference generator 21 and the reference signal generator 22. The example shown in this figure shows an example (reference / reference signal generator 21a) in which the reference generator 21 and the reference signal generator 22 are configured by one circuit. However, the configurations of the reference generator 21 and the reference signal generator 22 are not limited to this, and for example, both may be configured by different circuits.

  The reference / reference signal generator 21a (reference generator 21 and reference signal generator 22) shown in FIG. 6 includes a shift register 30, a flip-flop 33, and an inverter including one flip-flop 31 and 23 flip-flops 32. An element 34, an OR circuit 35, an AND circuit 36, a flip-flop 37, and an inverter element 38 are provided.

  The reference / reference signal generator 21a includes a received data signal RDATA output from the receiver 10R, an oscillation signal PLL_OUT output from the VCO 25, a reset signal nRES output from a control unit (not shown), and a phase comparator 23. The output PLL lock signal nLOCK is input.

  The oscillation signal PLL_OUT is input to the clock terminal CK of each flip-flop constituting the shift register 30 and the inverter element 34. The inverter element 34 inverts “H” and “L” of the oscillation signal PLL_OUT and outputs the inverted signal to the clock terminal CK of the flip-flop 33.

  The reset signal nRES is input to the set input terminal SB of the flip-flop 31, the reset input terminal RB of each flip-flop 32, and the reset input terminal RB of the flip-flop 33.

  The output terminal Q of the flip-flop 31 is connected to the data input terminal D of the first-stage flip-flop 32. Further, the data input terminal D of the second and subsequent flip-flops 32 is connected to the output terminal Q of the preceding flip-flop 32. As a result, the output from the output terminal Q of the flip-flop 32 at the final stage (the output of the shift register 30) becomes “H” for one pulse every time the pulse of the oscillation signal PLL_OUT of the VCO 25 is input 24 times.

  The output signal of the shift register 30 is input to the data input terminal D of the flip-flop 31, the data input terminal D of the flip-flop 33, and the input terminal A of the OR circuit 35, and the edge signal REF_EDGE is input to the phase comparator 23. Is output as.

  The flip-flop 33 phase-shifts the output signal from the shift register 30 input to the data input terminal D from the output terminal Q at a timing corresponding to the oscillation signal PLL_OUT that is inverted by the inverter element 34 and input to the clock terminal CK. The reference signal REF_PLL is output to the comparator 23. As a result, each time the pulse of the oscillation signal PLL_OUT of the VCO 25 is input 24 times, the signal becomes “H” for one pulse, and the rise from “L” to “H” is the fall of the transmission signal PLL_OUT. A reference signal REF_PLL that is a matched signal is output to the phase comparator 23.

  As described above, the OR circuit 35 receives the output signal of the shift register 30 at one input terminal (terminal A) and the PLL lock signal output from the phase comparator 23 at the other input terminal (terminal B). nLOCK is input. The OR circuit 35 is connected to the AND circuit 36 from the output terminal X when either the signal output from the shift register 30 or the PLL lock signal nLOCK output from the phase comparator 23 is “H”. A signal EDGE_EN is output to the input terminal B. Therefore, the signal EDGE_EN is always “H” during a period in which the oscillation signal PLL_OUT and the reception data signal RDATA are not synchronized (while the PLL lock signal nLOCK is “H”), and the signal EDGE_EN is received from the oscillation signal PLL_OUT. When the data signal RDATA is synchronized (when the PLL lock signal nLOCK is “L”), the output signal of the shift register 30 becomes “H” for one clock at which the output signal becomes “H”.

  The reception data signal RDATA output from the receiver 10 </ b> R is input to the other input terminal (terminal A) of the AND circuit 36. The AND circuit 36 outputs the clock signal from the output terminal X to the clock terminal of the flip-flop 37 when both the signal EDGE_EN input from the OR circuit 35 and the reception data signal RDATA input from the receiver 10R are “H”. An “H” signal is output to CK.

  The signal input terminal D of the flip-flop 37 is always supplied with the “H” signal VDD. Further, an output signal from the output terminal Q of the first-stage flip-flop 32 is input to the reset input terminal RB via the inverter element 38. As a result, the output signal of the first-stage flip-flop 32 is inverted by the inverter element 38 and input to the clock terminal CK. Then, the flip-flop 37 outputs the reference signal REF_R to the phase comparator 23 in accordance with the output signal of the AND circuit 36 input to the clock terminal CK. Thereby, the rising edge of the reference signal REF_R coincides with the rising edge of the start bit of the reception data signal RDATA (synchronization pattern SYNC or data signal or command signal). The falling edge of the reference signal REF_R coincides with the falling edge of the received data signal RDATA (synchronization pattern SYNC) when synchronization is not established (when the PLL lock signal nLOCK is “H”), and synchronization is established. When (when the PLL lock signal nLOCK is “L”), after REF_EDGE becomes “H”, it coincides with the rising edge of the second pulse of PLL_OUT.

  FIG. 7 is a circuit diagram illustrating a configuration example of the phase comparator 23. As shown in this figure, the phase comparator 23 includes a phase comparator 40 and a PLL lock signal generator 41.

  The phase comparison unit 40 detects rising edges of the reference signal REF_R and the reference signal REF_PLL, and outputs a pulse proportional to the phase difference between the two, and inverter elements 42 and 43 and two-input NAND circuits 44 to 49. It consists of a 4-input NAND circuit 50, a 3-input NAND circuit 51, 52, a 2-input AND circuit 53, and a tri-state gate 54.

  A reference signal REF_PLL is input to the inverter element 42. The inverter element 42 inverts the input reference signal REF_PLL and inputs the inverted signal to the input terminal B of the NAND circuit 44.

  The output signal PU output from the output terminal X of the three-input NAND circuit 51 is input to the input terminal A of the NAND circuit 44. The NAND circuit 44 outputs “L” when the output signal PU of the 3-input NAND circuit 51 and the signal obtained by inverting the reference signal REF_PLL input via the inverter element 42 are both “H”. In other cases, “H” is output. The output of the NAND circuit 44 is input to the input terminal A of the NAND circuit 45, the input terminal A of the 4-input NAND circuit 50, and the input terminal A of the 3-input NAND circuit 51, respectively.

  The input terminal B of the NAND circuit 45 is connected to the output terminal X of the NAND circuit 46. The NAND circuit 45 is “L” when the signals input to the input terminals A and B are both “H”, and “H” in the other cases, and the input terminal A of the NAND circuit 46 and the NAND circuit. 50 input terminals B and NAND circuit 51 input terminal B.

  The output of the NAND circuit 50 is input to the input terminal B of the NAND circuit 46. The NAND circuit 46 outputs “L” when the signals input to the input terminals A and B are both “H”, and outputs “H” to the input terminal B of the NAND circuit 45 in other cases. .

  A reference signal REF_R is input to the inverter element 43. Then, the inverter element 43 inverts the input reference signal REF_R and causes the input terminal A of the NAND circuit 49 to be inverted.

  The output signal PD output from the output terminal X of the three-input NAND circuit 52 is input to the input terminal B of the NAND circuit 49. The NAND circuit 49 outputs “L” when the output signal PD of the NAND circuit 52 and the signal obtained by inverting the reference signal REF_R input via the inverter element 43 are both “H”. In this case, “H” is output. The output of the NAND circuit 49 is input to the input terminal B of the NAND circuit 48, the input terminal D of the 4-input NAND circuit 50, and the input terminal C of the 3-input NAND circuit 52, respectively.

  The input terminal A of the NAND circuit 48 is connected to the output terminal X of the NAND circuit 47. The NAND circuit 48 selects “L” when both of the signals input to the input terminals A and B are “H”, and “H” in the other cases. Output to the input terminal C of the NAND circuit 50 and the input terminal B of the NAND circuit 52 having three inputs.

  The output of the NAND circuit 50 is input to the input terminal A of the NAND circuit 47. The NAND circuit 47 outputs “L” to the input terminal A of the NAND circuit 47 when the signals input to the input terminals A and B are both “H” and “H” in other cases. .

  The 4-input NAND circuit 50 is “L” when all the signals input to the input terminals A to D are “H”, and “H” in all other cases, and the input terminal of the 3-input NAND circuit 51. C output to the input terminal A of the NAND circuit 52 having three inputs, the input terminal B of the NAND circuit 46, and the input terminal A of the NAND circuit 47, respectively.

  The three-input NAND circuit 51 is “L” when all the signals at the input terminals A to C are “H”, and “H” otherwise, and the input terminal A of the AND circuit 53 and the NAND circuit 44 Output to input terminal A.

  The three-input NAND circuit 52 is “L” when all the signals at the input terminals A to C are “H”, otherwise “H”, and the input terminal B of the AND circuit 53 and the NAND circuit 49 The data is output to the input terminal B and the tristate gate 54, respectively.

  The AND circuit 53 outputs “H” as a control signal to the tri-state gate 54 when the signals input to the input terminals A and B are both “H”, and otherwise “L”.

  In addition to the outputs of “H” and “L”, the tri-state gate 54 can output a high impedance Z (equivalent to a state where the connection of the output is disconnected) which is neither of these (in the middle of both). . More specifically, when the output from the AND circuit 53 is “H”, the tristate gate 54 outputs the high impedance Z as the output signal PC_OUT to the LPF 24 regardless of the output of the 3-input NAND circuit 52. When the output from the AND circuit 53 is “L”, “H” is output when the output of the NAND circuit 52 is “H” in accordance with the output of the 3-input NAND circuit 52. When “L” is “L”, “L” is output to the LPF 24 as the output signal PC_OUT.

  Thereby, in the phase comparison unit 40, when the phase of the oscillation signal (reference signal REF_PLL) of the VCO 25 is advanced, the 3-input NAND circuit 51 sets the output signal PU to “L” and lowers the control voltage of the VCO 25. When the phase of the oscillation signal of the VCO 25 is advanced, the 3-input NAND circuit 51 sets the output signal PD to “L” and raises the control voltage of the VCO 25.

  The PLL lock signal generation unit 41 includes a flip-flop 55, an inverter element 56, an AND circuit 57, a selector circuit 58, a flip-flop 59, and an inverter element 60.

  The oscillation signal PLL_OUT output from the VCO 25 is input to the clock terminals CK of the flip-flop 55 and the flip-flop 59. The reset signal nRES is input to the reset input terminal RB of the flip-flop 55 and the flip-flop 59.

  The reference signal REF_R is input to the data input terminal D of the flip-flop 55. The reference signal REF_R is also input to the input terminal (terminal A) of the AND circuit 57.

  The flip-flop 55 outputs the reference signal REF_R input to the input terminal D to the inverter element 56 at a timing according to the oscillation signal PLL_OUT output from the VCO 25 input to the clock terminal CK.

  The inverter element 56 inverts the input signal and outputs the inverted signal to the input terminal (terminal C) of the AND circuit 57. The selector circuit 58 receives the output signal from the output terminal X of the AND circuit 57, the output signal of the flip-flop 59, and the edge signal REF_EDGE. When the edge signal REF_EDGE is "L", the output of the flip-flop 59 is output. When the edge signal REF_EDGE is “H”, the output signal of the AND circuit 57 is output to the data input terminal D of the flip-flop 59.

  The flip-flop 59 outputs the signal input to the input terminal D to the inverter element 60 and feeds it back to the selector circuit 58 at a timing according to the oscillation signal PLL_OUT of the VCO 25 input to the clock terminal CK.

  The inverter element 60 inverts the input signal and outputs the inverted signal to the reference signal generator 22 and the transmission side circuit 2 as a PLL lock signal nLOCK.

  Thereby, the PLL lock signal generation unit 41 sets “L” as the PLL lock signal nLOCK when the output signal PLL_OUT of the PLL 12 is synchronized with the received data signal RDATA, and “H” when not synchronized. It is designed to output.

  Next, the operation of the reception side circuit 3 will be described using a timing chart. FIGS. 8A and 8B are timing charts showing signal waveforms when the output signal PLL_OUT of the PLL 12 is not synchronized with the received data signal RDATA (when synchronization is not established). 8A shows a case where the phase of the output signal PLL_OUT of the PLL 12 is advanced, and FIG. 8B shows a case where the phase of the output signal PLL_OUT of the PLL 12 is delayed.

  As shown in FIG. 8A, the output signal EDGE_EN of the OR circuit 35 in the reference / reference signal generator 21a is a PLL lock signal when the output signal PLL_OUT of the PLL 12 and the received data signal RDATA are not synchronized. Since nLOCK is “H”, it is always “H”.

  Therefore, since “H” is input to the input terminal B of the AND circuit 36 in the reference / reference signal generator 21a, the rising and falling edges of the reference signal REF_R are the same as the rising and falling edges of the received data signal RDATA. Match. FIG. 8A shows a case where the received data signal RDATA is a synchronization pattern SYNC. In this case, the reference signal REF_R has 12 bits from the start bit as “H” and the subsequent 12 bits as “L”. It becomes.

  The rising edge of the reference signal REF_PLL coincides with the falling edge of the output signal PLL_OUT of the PLL 12, and the rising edge of the reference signal REF_PLL coincides with the next falling edge of the output signal PLL_OUT of the PLL 12. Note that the reference signal REF_PLL is “H” for one pulse (one cycle) of the output signal PLL_OUT, and the rise and fall thereof coincide with the fall of the output signal PLL_OUT.

  When the reference signal REF_PLL rises before the reference signal REF_R rises, the output signal PU of the NAND circuit 51 in the phase comparator 23 switches from “H” to “L”. Thereafter, when the reference signal REF_R rises, the output signal PU of the NAND circuit 51 returns from “L” to “H”. Thereby, the phase difference between the phase of the received data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12 is detected. The output signal PD of the NAND circuit 52 in the phase comparator 23 remains “H” during this period. As a result, the output signal PC_OUT from the phase comparator 23 (phase comparison unit 40) is output from the high impedance (Hi-Z) state only during the period when the output signal PU of the NAND circuit 51 is “L”. Switch to “H”.

  In the example of FIG. 8A, the phase of the output signal PLL_OUT of the PLL 12 is advanced by more than a half clock with respect to the phase of the reception data signal RDATA. As described above, when the phase of the output signal PLL_OUT of the PLL 12 is shifted by more than a half clock with respect to the phase of the received data signal RDATA, the transmitted data cannot be properly received. Therefore, in order to perform appropriate reception, it is preferable to lock the phase of the output signal PLL_OUT of the PLL 12 in synchronization with the phase of the reception data signal RDATA with an error within half a clock.

  On the other hand, as shown in FIG. 8B, when the reference signal REF_R rises before the reference signal REF_PLL rises, the output signal PD of the NAND circuit 52 in the phase comparator 23 changes from “H” to “L”. ”. Thereafter, when the reference signal REF_PLL rises, the output signal PD of the NAND circuit 52 returns from “L” to “H”. Thereby, the phase difference between the phase of the received data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12 is detected. Note that the output signal PU of the NAND circuit 51 in the phase comparator 23 remains “H” during this period. As a result, the output signal PC_OUT from the phase comparator 23 (phase comparison unit 40) is changed from the high impedance (Hi-Z) state to “L” only during the period when the output signal PD of the NAND circuit 52 is “L”. ”.

  FIGS. 9A and 9B show signal waveforms when the output signal PLL_OUT of the PLL 12 shifts from a state where it is not synchronized with the received data signal RDATA to a state where it is synchronized (when synchronization is established). It is a timing chart. FIG. 9A shows a case where the phase advance is within a half clock from the state where the phase of the output signal PLL_OUT of the PLL 12 is advanced by more than a half clock with respect to the received data signal RDATA. FIG. 9B shows a case where the phase delay is within half a clock from the state in which the phase of the output signal PLL_OUT of the PLL 12 is delayed by more than a half clock with respect to the received data signal RDATA.

  As shown in FIG. 9A, when the output signal PLL_OUT of the PLL 12 is not synchronized with the received data signal RDATA (the phase difference between them is half a clock (1/2 or more times the period of the received data signal RDATA) or more) In this case, since the PLL lock signal nLOCK is “L”, the output signal EDGE_EN of the OR circuit 35 in the reference / reference signal generator 21a is always “H”. Therefore, since “H” is input to the input terminal B of the AND circuit 36 in the reference / reference signal generator 21a, the rising and falling edges of the reference signal REF_R are the same as the rising and falling edges of the received data signal RDATA. Match.

  The rising edge of the reference signal REF_PLL coincides with the falling edge of the output signal PLL_OUT of the PLL 12, and the rising edge of the reference signal REF_PLL coincides with the next falling edge of the output signal PLL_OUT of the PLL 12.

  Then, after the reception of the stop bit of the reception data signal RDATA is started, when the reference signal REF_PLL rises before the reference signal REF_R rises, the output signal PU of the NAND circuit 51 in the phase comparator 23 changes from “H”. Switch to “L”. Thereafter, when the reference signal REF_R rises, the output signal PU of the NAND circuit 51 returns from “L” to “H”. Thereby, the phase difference between the phase of the received data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12 is detected. The output signal PD of the NAND circuit 52 in the phase comparator 23 remains “H” during this period. As a result, the output signal PC_OUT from the phase comparator 23 (phase comparison unit 40) is output from the high impedance (Hi-Z) state only during the period when the output signal PU of the NAND circuit 51 is “L”. Switch to “H”.

  The output signal PC_OUT from the phase comparator 23 is input to the VCO 25 via the LPF 24, and the VCO 25 controls the oscillation frequency so that the phase of the output signal PLL_OUT of the PLL 12 is delayed and synchronized with the received data signal RDATA. Is done.

  Thereafter, the same phase difference detection operation as described above is performed once every 24 pulses of the output signal PLL_OUT of the PLL 12. When the phase difference between the output signal PLL_OUT of the PLL 12 and the received data signal RDATA is within half a clock (when synchronization is established), the output of the PLL 12 is locked and the PLL lock signal nLOCK is switched to “L”. . As a result, the output signal EDGE_EN of the OR circuit 35 in the reference / reference signal generator 21a is only in a period corresponding to one pulse of the output signal PLL_OUT of the PLL 12 when the output of the shift register 30 is “H”. , “H”.

  On the other hand, as shown in FIG. 9B, when the reference signal REF_R rises before the reference signal REF_PLL rises, the output signal PD of the NAND circuit 52 in the phase comparator 23 changes from “H” to “L”. ”. Thereafter, when the reference signal REF_PLL rises, the output signal PD of the NAND circuit 52 returns from “L” to “H”. Thereby, the phase difference between the phase of the received data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12 is detected. Note that the output signal PU of the NAND circuit 51 in the phase comparator 23 remains “H” during this period. As a result, the output signal PC_OUT from the phase comparator 23 (phase comparison unit 40) is output from the high impedance (Hi-Z) state only during the period when the output signal PU of the NAND circuit 51 is “L”. Switch to “H”.

  The output signal PC_OUT from the phase comparator 23 is input to the VCO 25 via the LPF 24, and the oscillation frequency is controlled so that the VCO 25 advances the phase of the output signal PLL_OUT of the PLL 12 and synchronizes with the received data signal RDATA. Is done.

  Thereafter, the same phase difference detection operation as described above is performed once every 24 pulses of the output signal PLL_OUT of the PLL 12. When the phase difference between the output signal PLL_OUT of the PLL 12 and the received data signal RDATA is within half a clock (when synchronization is established), the output of the PLL 12 is locked and the PLL lock signal nLOCK is switched to “L”. . As a result, the output signal EDGE_EN of the OR circuit 35 in the reference / reference signal generator 21a is only in a period corresponding to one pulse of the output signal PLL_OUT of the PLL 12 when the output of the shift register 30 is “H”. , “H”.

  FIGS. 10A and 10B are timing charts showing signal waveforms when the output signal PLL_OUT of the PLL 12 is synchronized with the received data signal RDATA (when data communication is being performed after synchronization is established). .

  The output signal EDGE_EN of the OR circuit 35 in the reference / reference signal generator 21a is the shift register 30 when the output signal PLL_OUT of the PLL 12 is synchronized with the received data signal RDATA and the PLL lock signal nLOCK is “L”. Is “H” only during a period when the output of “H” is “H”, that is, during a period corresponding to one pulse of the output signal PLL_OUT of the PLL 12.

  If the reception data signal RDATA rises (changes from “0” to “1”) while the output signal EDGE_EN of the OR circuit 35 is “H”, the output of the AND circuit 36 becomes “H”. The reference signal REF_R is switched to “H”. Since the output of the flip-flop 32 of the first stage is inverted and input to the reset terminal RB of the flip-flop 37, the reference signal REF_R is switched to “H” and then the pulse of the output signal PLL_OUT of the PLL 12 is output. When it occurs twice, it is returned to “L”.

  Further, the reference signal REF_PLL becomes “H” when the output signal PLL_OUT of the PLL 12 falls during the period in which the output of the shift register 30 is “H”. Then, the output signal PLL_OUT of the next PLL 12 returns to “L” at the falling edge.

  As shown in FIG. 10A, when the rising edge of the reference signal REF_PLL is earlier than the rising edge of the reference signal REF_R, the output signal PU of the NAND circuit 51 provided in the phase comparator 23 is changed to the reference signal REF_PLL. Becomes “L” simultaneously with the rise of the reference signal, and returns to “H” simultaneously with the rise of the reference signal REF_R. Then, during the period when the output signal PU of the NAND circuit 51 is “L”, the output signal PC_OUT of the phase comparator 23 is switched from the high impedance state to “H”. As a result, the serial transmission device 1 controls the VCO 25 so as to reduce the difference between the phase of the reception data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12.

  On the other hand, as shown in FIG. 10B, when the rising edge of the reference signal REF_R is earlier than the rising edge of the reference signal REF_PLL, the output signal PD of the NAND circuit 52 provided in the phase comparator 23 is the reference signal REF_R. It becomes “L” simultaneously with the rise of the reference signal REF and returns to “H” simultaneously with the rise of the reference signal REF_PLL. Then, during the period when the output signal PD of the NAND circuit 52 is “L”, the output signal PC_OUT of the phase comparator 23 is switched from the high impedance state to “L”. As a result, the serial transmission device 1 controls the VCO 25 so as to reduce the difference between the phase of the reception data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12.

  When the difference between the rising edge of the reference signal REF_R and the rising edge of the reference signal REF_PLL (the phase difference between the reception data signal RDATA and the output signal PLL_OUT of the PLL 12) is within half a clock, the PLL lock signal nLOCK continues to be “L”. Then, the lock of the PLL 12 is continued.

  FIG. 11A and FIG. 11B show signal waveforms when the output signal PLL_OUT of the PLL 12 shifts from a state in which it is synchronized with the received data signal RDATA to a state in which synchronization is lost (when synchronization is lost). It is the timing chart shown.

  The output signal EDGE_EN of the OR circuit 35 in the reference / reference signal generator 21a is the shift register 30 when the output signal PLL_OUT of the PLL 12 is synchronized with the received data signal RDATA and the PLL lock signal nLOCK is “L”. Is “H” only during a period when the output of “H” is “H”, that is, during a period corresponding to one pulse of the output signal PLL_OUT of the PLL 12.

  If the reception data signal RDATA rises (changes from “0” to “1”) while the output signal EDGE_EN of the OR circuit 35 is “H”, the output of the AND circuit 36 becomes “H”. The reference signal REF_R is switched to “H”. Since the output of the flip-flop 32 of the first stage is inverted and input to the reset terminal RB of the flip-flop 37, the reference signal REF_R is switched to “H” and then the pulse of the output signal PLL_OUT of the PLL 12 is output. When it occurs twice, it is returned to “L”.

  Further, the reference signal REF_PLL becomes “H” when the output signal PLL_OUT of the PLL 12 falls during the period in which the output of the shift register 30 is “H”. Then, the output signal PLL_OUT of the next PLL 12 returns to “L” at the falling edge.

  As shown in FIG. 11A, when the rising edge of the reference signal REF_PLL is earlier than the rising edge of the reference signal REF_R, the output signal PU of the NAND circuit 51 provided in the phase comparator 23 is changed to the reference signal REF_PLL. Becomes “L” simultaneously with the rise of the reference signal, and returns to “H” simultaneously with the rise of the reference signal REF_R. Then, during the period when the output signal PU of the NAND circuit 51 is “L”, the output signal PC_OUT of the phase comparator 23 is switched from the high impedance state to “H”.

  When the difference between the rising edge of the reference signal REF_R and the rising edge of the reference signal REF_PLL (the phase difference between the reception data signal RDATA and the output signal PLL_OUT of the PLL 12) is within half a clock, the PLL lock signal nLOCK continues to be “L”. Then, the lock of the PLL 12 is continued.

  On the other hand, when the phase difference between the received data signal RDATA and the output signal PLL_OUT of the PLL 12 becomes more than half a clock, the PLL 12 is unlocked and the PLL lock signal nLOCK is switched to “H”.

  Also, as shown in FIG. 11B, when the rising edge of the reference signal REF_R is earlier than the rising edge of the reference signal REF_PLL, the output signal PD of the NAND circuit 52 provided in the phase comparator 23 is the reference signal REF_R. It becomes “L” simultaneously with the rise of the reference signal REF and returns to “H” simultaneously with the rise of the reference signal REF_PLL. Then, during the period when the output signal PD of the NAND circuit 52 is “L”, the output signal PC_OUT of the phase comparator 23 is switched from the high impedance state to “L”.

  When the phase difference between the received data signal RDATA and the output signal PLL_OUT of the PLL 12 is within a half clock, the PLL lock signal nLOCK is continuously set to “L” and the PLL 12 is kept locked.

  On the other hand, when the phase difference between the received data signal RDATA and the output signal PLL_OUT of the PLL 12 becomes more than half a clock, the PLL 12 is unlocked and the PLL lock signal nLOCK is switched to “H”.

  As described above, the serial transmission device 1 according to the present embodiment has the signal line for transmitting the data signal and the command signal before starting the transmission of the data signal or the command signal from the transmission side circuit 2 to the reception side circuit 3. And a common signal line are used to transmit a synchronization pattern SYNC having the same data length as that of the data signal and the command signal and having different values of the start bit and the stop bit. In the reception side circuit 3, the PLL 12 controls the phase of the output signal PLL_OUT based on the synchronization pattern SYNC included in the reception data signal RDATA received by the receiver 10R, thereby changing the phase of the data signal and the command signal. Synchronize.

  As a result, the serial transmission device 1 synchronizes the reception side circuit 3 with the transmission side circuit 2 on the basis of the synchronization pattern transmitted by the common signal line with the data signal and the command signal without transmitting a clock signal. Can be made. Therefore, highly reliable signal transmission with respect to disturbances such as noise and static electricity can be performed between the transmission side circuit 2 and the reception side circuit 3. In addition, since it is not necessary to provide a dedicated signal line for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  Further, in the serial transmission device 1, the PLL 12 provided in the reception side circuit 3 fixes the phase of the reception data signal RDATA and the phase of the output signal PLL_OUT of the PLL 12 in synchronization, and sets the PLL lock signal nLOCK to “L”. (A signal indicating that synchronization is established is transmitted to the transmission side circuit 2). Then, after the synchronization is established, the transmission side circuit 2 starts transmission of a command signal or a data signal.

  More specifically, when the PLL lock signal generation unit 41 in the phase comparator 23 provided in the PLL 12 detects the synchronization between the reception data signal RDATA (synchronization pattern SYNC) and the output signal PLL_OUT of the PLL 12, and synchronization is established. In addition, the PLL lock signal nLOCK transmitted to the timing control circuit 8 provided in the transmission side circuit 2 is switched from “H” to “L”. Then, the transmission side circuit 2 starts transmission of a command signal or a data signal after the PLL lock signal nLOCK is switched to “L”.

  Thereby, in the serial transmission device 1, the command signal and the data signal can be transmitted in a state where the transmission side circuit 2 and the reception side circuit 3 are reliably synchronized.

  Further, in the serial transmission device 1, the transmission of the synchronization pattern SYNC from the transmission side circuit 2 to the reception side circuit 3 is continued during a period in which the data signal or the command signal is not transmitted. As a result, the PLL 12 in the reception side circuit 3 continuously synchronizes the output signal PLL_OUT of the PLL 12 and the reception data signal RDATA based on the synchronization pattern SYNC, and locks the phase of the output signal PLL_OUT of the synchronized PLL 12 Can keep synchronized.

  Further, the serial transmission device 1 detects the synchronization state between the received data signal RDATA and the output signal PLL_OUT of the PLL 12 by using the transmitted command signal or data signal during the transmission period of the command signal or data signal. To do.

  More specifically, the reference / reference signal generator 21a (reference generator 21) provided in the PLL 12 generates a reference signal REF_R that rises simultaneously with the rising edge of the start bit of the received data signal RDATA. Then, the reference / reference signal generator 21a (reference signal generator 22) generates a reference signal REF_PLL that rises simultaneously with the fall of a specific pulse (1 pulse in 24 pulses) in the output signal PLL_OUT of the PLL 12. When the PLL lock signal generation unit 41 in the phase comparator 23 provided in the PLL 12 detects the synchronization between the received data signal RDATA (data signal or command signal) and the output signal PLL_OUT of the PLL 12 and is synchronized. Keeps the PLL lock signal nLOCK transmitted to the timing control circuit 8 provided in the transmission side circuit 2 at “L”, and transmits to the timing control circuit 8 provided in the transmission side circuit 2 when synchronization is lost. The PLL lock signal nLOCK being switched is switched to “H” (a signal indicating that synchronization has been lost is generated and transmitted to the transmission side circuit 2). If the synchronization state is ensured, the command signal or data signal is continuously transmitted.

  As a result, if the output signal PLL_OUT of the PLL 12 and the received data signal RDATA (data signal or command signal) are out of synchronization during reception of the data signal or command signal, this is notified to the transmission side circuit 2. it can. For this reason, the transmission side circuit 2 stops transmission of the data signal and the command signal, and starts transmission of the synchronization pattern SYNC. Therefore, more reliable signal transmission can be performed.

  Further, in the serial transmission device 1, the phase comparison unit 40 in the phase comparator 23 compares the rising edge of the reference signal REF_R generated as described above with the rising edge of the reference signal REF_PLL, based on the result of comparison with the received data signal RDATA. The oscillation frequency and phase of the VCO 25 are controlled so as to reduce the difference between the phase of the VCO 25 and the phase of the output signal PLL_OUT of the PLL 12.

  As a result, the serial transmission device 1 does not transmit the clock signal simultaneously with the data signal or the command signal, and transmits the serial data signal or command signal in a state where the transmission side circuit 2 and the reception side circuit 3 are appropriately synchronized. Transmission can be performed. Accordingly, since it is not necessary to provide a dedicated signal line (differential pair) for transmitting the clock signal, the apparatus configuration can be simplified and downsized.

  The serial transmission device 1 uses the LVDS method for transmission from the transmission side circuit 2 to the reception side circuit 3. Signal transmission by the LVDS method has a characteristic that power consumption hardly changes between a period during which a signal is transmitted and a period during which no signal is transmitted. For this reason, the serial transmission device 1 continuously transmits the synchronization pattern during a period when the data signal or the command signal is not transmitted, but the power consumption is almost the same as when the synchronization pattern is not transmitted.

  In this embodiment, in order to transmit a 20-bit input data signal, a 24-bit transmission data signal TDATA to which a start bit, a synchronization pattern distinction bit, a parity bit, and a stop bit are added is generated and transmitted. As described above, the data size of the transmission data signal TDATA (reception data signal RDATA) is not limited to this, and may be appropriately determined according to the data size of the input data.

  In this embodiment, a signal having a configuration in which the first 12 bits are “1” and the second 12 bits is “0” is used as the synchronization pattern. However, the configuration of the synchronization pattern is not limited to this. The data signal and the command signal have the same data length as long as the start bit and the stop bit have different values. Note that the synchronization pattern is preferably distinguishable from the data signal and the command signal. Further, the synchronization pattern is preferably a signal in which there is only one change between “1” and “0” in one symbol (24 bits in the present embodiment).

  In the present embodiment, the case where LVDS transmission is performed between the transmitter 10T included in the transmitter circuit 2 and the receiver 10R included in the receiver circuit 3 has been described. However, the present invention is not limited to this. Absent. For example, the signal may be serially transmitted by a differential transmission method other than the LVDS method, or a transmission method other than the differential transmission method may be used.

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately changed within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to all devices that transmit data by serial transmission between communication devices or between electronic components such as integrated circuits.

It is a block diagram which shows the structure of the serial transmission apparatus concerning one Embodiment of this invention. 4 is a timing chart showing a relationship among an input data signal, a transmission clock signal, and a differential signal in the serial transmission device according to the embodiment of the present invention. It is explanatory drawing for demonstrating the method of the synchronous process in the PLL circuit with which the receiving side circuit of the serial transmission apparatus concerning one Embodiment of this invention is equipped. It is a timing chart which shows the synchronous sequence in the serial transmission apparatus concerning one Embodiment of this invention. It is a block diagram which shows the structure of the receiving side circuit of the serial transmission apparatus concerning one Embodiment of this invention. It is a circuit diagram which shows the structure of the reference generator with which the receiving side circuit of the serial transmission apparatus concerning one Embodiment of this invention is equipped, and a reference signal generator. It is a circuit diagram which shows the structure of the phase comparator with which the receiving side circuit of the serial transmission apparatus concerning one Embodiment of this invention is equipped. It is a timing chart which shows operation | movement of the PLL circuit in the serial transmission apparatus concerning one Embodiment of this invention, (a) shows the case where the phase of the output signal of PLL has advanced with respect to the phase of a received data signal. (B) shows a case where the phase of the output signal of the PLL is delayed with respect to the phase of the received data signal. It is a timing chart which shows operation | movement of the PLL circuit in the serial transmission apparatus concerning one Embodiment of this invention, (a) is synchronized from the state from which the phase of the output signal of PLL is advanced with respect to the phase of a received data signal FIG. 5B shows a case where the phase of the output signal of the PLL shifts from a state delayed from the phase of the received data signal to a state where it is synchronized. It is a timing chart which shows the operation | movement of the PLL circuit in the serial transmission apparatus concerning one Embodiment of this invention, (a) is synchronizing although the phase of the output signal of PLL is slightly advanced with respect to the phase of a received data signal (B) shows a synchronized state although the phase of the output signal of the PLL is slightly delayed from the phase of the received data signal. It is a timing chart which shows the operation | movement of the PLL circuit in the serial transmission apparatus concerning one Embodiment of this invention, (a) is synchronizing because the phase of the output signal of PLL advances with respect to the phase of a received data signal. The case where the state goes out is shown, and (b) shows the case where the phase of the output signal of the PLL is out of the synchronized state by being delayed with respect to the phase of the received data signal. It is a circuit diagram which shows an example of the conventional serial transmission apparatus.

Explanation of symbols

1 Serial transmission device 2 Transmission side circuit (serial signal transmission device)
3 Receiver circuit (serial signal receiver)
4 Frequency Divider 5 Latch Circuit 6 Parallel Serial Conversion Circuit 7 Serial Data Insertion Circuit 8 Timing Control Circuit 9 Synchronization Pattern Generation Circuit (Synchronization Pattern Generation Means)
10T transmitter 10R receiver 11 serial parallel conversion circuit (signal discrimination means)
12 PLL (phase locking means)
13 Timing control circuit 14P, 14N Signal line 21 Reference generator 21a Reference / reference signal generator 22 Reference signal generator 23 Phase comparator (synchronization detection means, phase comparison means, fixed notification means)
24 LPF
25 VCO
40 Phase comparison unit (synchronization detection means, phase comparison means)
41 PLL lock signal generator (synchronization detection means, fixed notification means)

Claims (14)

A serial signal transmission device that converts an input data signal into a serial signal based on a clock signal and transmits the serial signal,
A synchronization pattern generating means for generating a synchronization pattern having the same data length as the serial signal to be transmitted and having different values of the start bit and the stop bit;
A serial signal transmitting apparatus, wherein the serial signal and the synchronization pattern are transmitted using a common signal line.   The serial signal transmission device according to claim 1, wherein transmission of the synchronization pattern is continued during a period in which the serial signal is not transmitted.   3. The serial signal transmission device according to claim 1, wherein the serial signal and the synchronization pattern are transmitted as a differential transmission system signal.   The serial signal transmission apparatus according to claim 3, wherein an LVDS system is used as the differential transmission system. After transmitting the synchronization pattern, when receiving a fixed notification signal indicating that the synchronization of the destination device is established from the destination device,
The serial signal transmission apparatus according to claim 1, wherein transmission of the serial signal is started. After the start of transmission of the serial signal, when receiving a lock release signal indicating that the transmission destination device is out of synchronization from the transmission destination device, it waits for transmission of the serial data and sets the synchronization pattern. Send
The transmission of the serial data is resumed when a fixed notification signal indicating that synchronization of the transmission destination device is established is received from the transmission destination device. Item 2. The serial signal transmission device according to item 1. A serial signal receiving device that converts a received serial signal into a parallel signal,
Phase fixing means for controlling and fixing the phase of the output signal;
The phase fixing means receives the phase of the signal output from the phase fixing means via a signal line common to the serial signal, has the same data length as the serial signal, and has a start bit and a stop bit. A serial signal receiving apparatus, wherein the serial signal is synchronized with the phase of the serial signal by controlling based on synchronization patterns having different values. The phase locking means is
Synchronization detecting means for detecting whether or not the phase of the signal output from the phase fixing means is synchronized with the phase of the serial signal;
When the phase of the signal output from the phase fixing means is synchronized with the phase of the serial signal, a fixed notification means for generating a fixed notification signal indicating that and transmitting the fixed notification signal to the transmission source device of the serial signal; The serial signal receiving device according to claim 7, further comprising:   The synchronization detecting unit compares the edge of a specific pulse in the signal output from the phase fixing unit with the edge of the start bit in the synchronization pattern during a period of receiving the synchronization pattern, thereby obtaining the phase. 9. The serial signal receiving apparatus according to claim 8, wherein it detects whether or not the phase of the signal output from the fixing means is synchronized with the phase of the serial signal. The synchronization detection means compares the edge of a specific pulse in the signal output from the phase fixing means with the edge of the start bit of the serial signal during the period of receiving the serial signal, Detecting whether the phase of the signal output from the fixing means is synchronized with the phase of the serial signal,
When the phase of the signal output from the phase fixing unit and the phase of the serial signal are out of synchronization, the fixed notification unit generates a fixed release signal indicating the phase and transmits the serial signal from the device The serial signal receiving device according to claim 8 or 9, wherein   The phase locking means includes phase comparison means for comparing the edge of a specific pulse in the signal output from the phase locking means and the edge of the start bit of the serial signal to detect a phase shift between both signals, The phase of the signal output from the phase fixing means is controlled so that the phase shift between the two signals detected by the phase comparing means is small. Serial signal receiver. Comprising signal determining means for determining whether the received signal is the synchronization pattern or the serial signal;
The serial signal receiving apparatus according to claim 7, wherein the parallel signal is output to the outside only when the received signal is a serial signal.   A serial transmission device comprising the serial signal transmission device according to any one of claims 1 to 6 and the serial signal reception device according to any one of claims 7 to 12. The input data signal is converted into a serial signal based on the clock signal and transmitted from the serial signal transmission device, and the transmission is performed by the serial signal reception device having phase fixing means for controlling and fixing the phase of the output signal. A serial transmission method for receiving a received serial signal and converting it into a parallel signal,
Generating a synchronization pattern having the same data length as the serial signal to be transmitted and having different values of the start bit and the stop bit;
Transmitting the synchronization pattern using a signal line common to the signal line for transmitting the serial signal;
A step of synchronizing the phase of the signal output from the phase fixing means with the phase of the serial signal by controlling the phase of the signal based on the synchronization pattern.

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