JP2016152576A - Data transmission device, transmitter and receiver - Google Patents

Abstract

PROBLEM TO BE SOLVED To use a preamble for transmitting data by serial transmission in a transmitting device and a receiving device. The present invention latches a data signal supplied from the outside based on a predetermined clock, and whether a predetermined timing indicated by the predetermined clock is a data signal output period or a synchronization signal output period A data signal control unit that determines the frequency, a synchronization signal generation unit that generates a synchronization signal based on a multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification, And a selection circuit that outputs either the data signal latched by the data signal control unit or the synchronization signal in accordance with a result of the determination. [Selection] Figure 1

Description

  The present invention relates to a data transmission device, a transmission device, and a reception device, and more particularly to a data transmission device, a transmission device, and a reception device that transmit data by a serial transmission method.

  There are a parallel transmission method and a serial transmission method as transmission methods for performing data transmission between information processing devices. The parallel transmission method is a method of transmitting each of a plurality of data as individual signals through a plurality of signal lines, and the serial transmission method is a method of transmitting a plurality of data as one signal through one signal line. . The parallel transmission system has problems such as the occurrence of skew due to the difference in signal delay in each signal line and the increase in circuit area due to the use of a plurality of signal lines. In recent data transmission, in order to avoid such a problem that occurs in the parallel transmission system, the chance of using the serial transmission system is increasing.

  In the serial transmission method, since a plurality of data is transmitted through one signal line, a means for discriminating each data is required. A data transmission apparatus using a serial transmission method typically uses a code called a preamble, and discriminates each data by attaching the code to the beginning of each data.

  For example, Patent Document 1 below discloses a signal processing device that uses a serial transmission method. Specifically, the signal processing device has an input unit to which a predetermined number of data and a first enable signal that is in synchronization with a first clock and takes an active state in a valid section of the data are input. And a count unit that counts the number of clocks in a period in which the first enable signal is in an inactive state with reference to a second clock that is faster than the first clock, and the second clock as a reference In addition, an enable signal control unit that activates the second enable signal by the number of clocks equal to the predetermined number and inactivates the second enable signal by the number of clocks counted by the count unit. And an enable signal output unit that outputs the second enable signal, and a section in which the second enable signal is in an active state. In synchronization with the lock and a data output unit for outputting data of the predetermined number.

JP 2012-134848 A

  The conventional signal processing apparatus as disclosed in Patent Document 1 needs to use the above-described preamble in order to transmit data by serial transmission. Since the preamble code is a very long code, the conventional signal processing apparatus has a problem that a large transmission load is applied to the network between the transmission apparatus and the reception apparatus by using the preamble.

  Therefore, an object of the present invention is to provide a new transmission apparatus that can transmit a plurality of types of data by a serial transmission method without using a preamble.

  It is another object of the present invention to provide a new receiving apparatus that can receive a plurality of types of data transmitted by a serial transmission method without using a preamble.

  The present invention for solving the above problems includes the following technical features or invention specific matters.

  That is, the present invention according to a certain aspect latches a data signal supplied from the outside based on a predetermined clock, and the predetermined timing indicated by the predetermined clock is either the data signal output period or the synchronization signal output period. A data signal control unit for determining whether or not there is a synchronization signal for generating a synchronization signal based on a frequency-multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification A transmission apparatus comprising: a generation unit; and a selection circuit that outputs either the data signal latched by the data signal control unit or the synchronization signal according to a result of the determination by the data signal control unit.

  As a result, the transmission device determines whether the predetermined timing is the data signal output period or the synchronization signal output period, and based on the determination result, transmits signals based on clocks of different frequencies from the selection circuit. It can be output as one signal.

  Here, the data signal control unit may determine whether the predetermined timing is the data signal output period or the synchronization signal output period based on the number of alternations of the predetermined clock.

  Accordingly, the transmission device can determine whether the predetermined timing is the data signal output period or the synchronization signal output period based on the number of alternating clocks.

  The synchronization signal generation unit selects one pattern from a plurality of predetermined patterns according to a pattern selection signal supplied from the outside, and generates the synchronization signal so as to include the selected pattern. You may do it.

  Thereby, the transmission apparatus can give a variation to the generated synchronization signal by generating the synchronization signal so as to include one of a plurality of predetermined patterns.

  Further, when the data signal control unit determines that the predetermined timing is the data signal output period, the synchronization signal generation unit stops generation of the synchronization signal, while the data signal control unit When the timing is determined to be the synchronization signal output period, the generation of the synchronization signal is started, and the selection circuit determines that the data signal control unit determines that the predetermined timing is the data signal output period. In this case, the data signal output from the data signal control unit may be output, and the synchronization signal may be output when the data signal control unit determines that the predetermined timing is the synchronization signal output period.

  Thus, the transmission device outputs the data signal from the selection circuit when the predetermined timing is the data signal output period, and outputs the synchronization signal from the selection circuit when the predetermined timing is the synchronization signal output period. Will be able to.

  Further, the present invention according to another aspect is generated by delaying a serial data signal supplied from the outside based on a predetermined clock and multiplying the frequency of the predetermined clock by a predetermined magnification. Based on a multiplied clock different from the predetermined clock, it is determined whether the serial data signal includes a predetermined pattern. If the predetermined pattern is included in the serial data signal, the predetermined data And a pattern detection circuit that outputs a pattern as a synchronization signal.

  Thereby, the receiving device determines whether or not the predetermined pattern is included by a clock having a frequency corresponding to the predetermined pattern with respect to the serial data signal in which a plurality of signals are superimposed at different frequencies, When the predetermined pattern is included, the predetermined pattern can be output as a synchronization signal.

  Here, the receiving apparatus may further include an output control circuit that outputs the serial data signal latched by the delay circuit as a data signal when the serial data signal does not include a predetermined pattern.

  Thus, the receiving device can output the latched serial data signal as a data signal when the serial data signal does not include a predetermined pattern.

  The receiving device further includes a deserializer that converts the serial data signal from a serial signal to a parallel signal, and the pattern detection circuit receives an output of the deserializer and converts the serial data signal into a predetermined pattern according to the output. It may be determined whether or not is included.

  Thereby, the receiving device converts the serial data signal from the serial signal to the parallel signal by the deserializer, and can determine whether or not the serial data signal includes a predetermined pattern according to the converted parallel signal. become.

  The receiving apparatus further includes a plurality of pattern detection circuits, and the predetermined pattern is different in each pattern detection circuit, and the output control circuit is configured so that each of the pattern detection circuits includes the serial data signal. If it is determined that the predetermined pattern is not included, a serial data signal latched by the delay circuit may be output as the data signal.

  Thereby, the receiving apparatus can detect a plurality of predetermined patterns corresponding to each pattern detection circuit by including a plurality of pattern detection circuits.

  Furthermore, the present invention according to another aspect is a data transmission device including a transmission device and a reception device, wherein the transmission device latches a data signal supplied from the outside based on a predetermined clock, and A data signal control unit that determines whether the predetermined timing indicated by the clock is a data signal output period or a synchronization signal output period, and the frequency generated by multiplying the frequency of the predetermined clock by a predetermined magnification A synchronization signal generation unit that generates a synchronization signal based on a multiplied clock different from the predetermined clock so as to include a predetermined pattern, and is latched by the data signal control unit according to the result of the determination by the data signal control unit A selection circuit for outputting either a data signal or the synchronization signal as a serial data signal; The receiving apparatus determines whether or not the predetermined pattern is included in the serial data signal based on the delay clock that latches the serial data signal based on the predetermined clock and the multiplied clock. A data transmission device including a pattern detection circuit that determines and outputs the predetermined pattern as a synchronization signal when the serial data signal includes the predetermined pattern.

  As a result, the data transmission device superimposes a plurality of signals on a serial data signal, which is a single signal, using clocks having different frequencies, and superimposes the serial data signal on the serial data signal using a clock having a frequency corresponding to a predetermined pattern. Since the predetermined pattern included in one of the received signals can be detected, a plurality of types of data can be transmitted and received by a serial transmission method without using a preamble. become able to.

  Furthermore, the present invention according to another aspect is a method for generating a serial data signal, wherein a data signal supplied from the outside and a predetermined clock are received, and a predetermined timing indicated by the predetermined clock is a synchronization signal output It is different from the predetermined clock generated by determining whether it is a period, and when the predetermined timing is the synchronization signal output period, by multiplying the frequency of the predetermined clock by a predetermined magnification. Based on the multiplied clock, a synchronization signal is generated, the synchronization signal is selected, and when the predetermined timing is not the synchronization signal output period, the data signal is latched by the predetermined clock, and the latched data Selecting a signal and outputting the selected signal as the serial data signal. It is a method of generating a data signal.

  As a result, the transmission apparatus determines whether or not the predetermined timing is the synchronization signal output period, and outputs a signal based on a clock having a different frequency as one signal from the selection circuit based on the determination result. Will be able to.

  Furthermore, the present invention according to another aspect is a method for detecting a predetermined pattern from a serial data signal, wherein data is received by receiving the serial data signal and latching the serial data signal with a predetermined clock. The serial data signal is latched based on a multiplied clock different from the predetermined clock generated by generating and outputting a signal and multiplying the frequency of the predetermined clock by a predetermined magnification, and the latched It is determined whether or not a predetermined pattern is included in the result, and when the latched result includes a predetermined pattern, the output of the data signal is stopped, and based on the latched result Detecting a predetermined pattern from a serial data signal, including generating and outputting a synchronization signal It is.

  Thereby, the receiving device determines whether or not the predetermined pattern is included by a clock having a frequency corresponding to the predetermined pattern with respect to the serial data signal in which a plurality of signals are superimposed at different frequencies, When the predetermined pattern is included, the predetermined pattern can be output as a synchronization signal.

  According to the present invention, the transmission apparatus can transmit a plurality of types of data by a serial transmission method without using a preamble.

  Further, according to the present invention, the receiving apparatus can receive a plurality of types of data transmitted by the serial transmission method without using a preamble.

  Other technical features, objects, effects, and advantages of the present invention will become apparent from the following embodiments described with reference to the accompanying drawings.

It is a figure which shows an example of schematic structure of the data transmission apparatus which concerns on one Embodiment of this invention. It is a figure which shows an example of the output control part which concerns on one Embodiment of this invention. It is a figure which shows an example of the synchronous signal generation part which concerns on one Embodiment of this invention. It is a figure which shows the other example of the synchronous signal generation part which concerns on one Embodiment of this invention. It is a figure which shows the other example of a structure of the transmitter which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the synchronous signal detection part which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the delay circuit in the synchronous signal detection part which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the delay circuit in the synchronous signal detection part which concerns on one Embodiment of this invention. It is a figure which shows an example of a structure of the delay circuit in the synchronous signal detection part which concerns on one Embodiment of this invention. It is a flowchart which shows operation | movement of the transmitter which concerns on one Embodiment of this invention. It is a flowchart which shows operation | movement of the receiver which concerns on one Embodiment of this invention. It is a timing chart of various signals in a transmitting device and a receiving device concerning one embodiment of the present invention.

  Next, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a schematic configuration of a data transmission apparatus according to an embodiment of the present invention. As shown in the figure, the data transmission device 1 according to the present embodiment includes, for example, a transmission device 10 and a reception device 20.

  The transmission device 10 is, for example, an eDP (embedded Display Port) source device (for example, a personal computer, a set-top box, a control board, or the like). Anything is ok. Based on a predetermined clock CLK, the transmission device 10 transmits either the data signal DATA_T supplied from the outside or the synchronization signal SYNC_T generated internally to the reception device 20 as a serial data signal SDATA. In one example, the transmission device 10 uses a pattern selection signal PAT_SEL supplied from the outside when generating the synchronization signal SYNC_T. The transmission device 10 includes, for example, a data signal control unit 11, a multiplication circuit 12, a synchronization signal generation unit 13, and a selection circuit 14.

  The data signal controller 11 should latch the externally supplied data signal DATA_T based on a predetermined clock CLK and output either the latched data signal DATA_T or the internally generated synchronization signal SYNC_T. Determine whether. The data signal control unit 11 includes, for example, an output control unit 110 and an AND circuit 111.

  That is, the output control unit 110 outputs a data signal DATA_T based on a predetermined clock CLK supplied from the outside (data signal output period) or a period when the synchronization signal SYNC_T should be output (synchronization signal output period). The determination result is output to the selection circuit 14 and the synchronization signal generation unit 13 as the selection signal SEL, and the determination result is output to the AND circuit 111 as the assert signal ASSERT.

  More specifically, when the output control unit 110 determines that the data signal output period is at a predetermined timing indicated by the predetermined clock CLK (for example, a timing at which the predetermined clock CLK is received or latched). A signal for setting the state of the selection signal SEL to “0” is output to the selection terminal SL of the selection circuit 14 and the synchronization signal generation unit 13, and a signal for setting the state of the assert signal ASSERT to “1” is an AND circuit. To 111. On the other hand, when the output control unit 110 determines that the synchronization signal output period is at a predetermined timing indicated by the predetermined clock CLK, the output control unit 110 sets the state of the selection signal SEL to “1” and the signal to the selection terminal SL of the selection circuit 14 And a signal for setting the state of the assert signal ASSERT to “0” is output to the AND circuit 111. Typically, the data signal output period and the synchronization signal output period are mutually exclusive.

  Further, the logical product circuit 111 latches the data signal DATA_T supplied from the outside, performs a logical product on the data signal DATA_T and the assert signal ASSERT output from the output control unit 110, and the result of the logical product Is output to the input terminal A0 of the selection circuit 14 as the data signal DATA_T2.

  The multiplication circuit 12 multiplies a predetermined clock CLK supplied from the outside by a predetermined magnification (for example, 2 to the nth power) to generate a multiplied clock CLK_MUL1. The multiplier circuit 12 outputs the generated multiplied clock CLK_MUL1 to the synchronization signal generator 13.

  When the data signal control unit 11 determines that the synchronization signal output period is in effect, the synchronization signal generation unit 13 generates a synchronization signal SYNC_T having a pattern according to the pattern selection signal PAT_SEL supplied from the outside based on the multiplied clock CLK_MUL1. Then, the signal is output to the selection circuit 14. The synchronization signal generation unit 13 acquires a determination result of whether or not the data signal control unit 11 is in the synchronization signal output period from the selection signal SEL output from the data signal control unit 11, and the state of the selection signal SEL is “1”. ", The synchronization signal SYNC_T is generated and the signal is output to the selection terminal A1 of the selection circuit 14. On the other hand, when the state of the selection signal SEL is “0”, the synchronization signal generation unit 13 stops generating and outputting the synchronization signal SYNC_T.

  The selection circuit 14 is, for example, a multiplexer, but is not limited thereto, and may be, for example, a data selector or a signal switch. The selection circuit 14 selects either the data signal DATA_T2 or the synchronization signal SYNC_T based on the selection signal SEL, and outputs the selection result to the reception device 20 as the serial data signal SDATA. Specifically, when the state of the selection signal SEL is “0”, the selection circuit 14 selects the data signal DATA_T2 and outputs the selection result to the reception device 20 as the serial data signal SDATA. On the other hand, when the state of the selection signal SEL is “1”, the selection circuit 14 selects the synchronization signal SYNC_T and outputs the selection result to the reception device 20 as the serial data signal SDATA.

  The receiving device 20 is, for example, an eDP sink device (for example, a display or a projector), but is not limited thereto, and may be any sink device of a transmission device that performs serial transmission. The receiving device 20 detects the data signal DATA_R2 and the synchronization signal SYNC_R from the serial data signal SDATA transmitted from the transmitting device 10, and performs various processes according to the data signal DATA_R2 based on the two signals (for example, display of an image) Etc.). The receiving device 20 includes, for example, a multiplication circuit 21, a synchronization signal detection unit 22, and an output unit 23.

  The multiplication circuit 21 multiplies the predetermined clock CLK supplied from the transmission apparatus 10 by the predetermined magnification (for example, 2 to the nth power) described above to generate the multiplied clock CLK_MUL2. The multiplier circuit 21 outputs the generated multiplied clock CLK_MUL2 to the synchronization signal detection unit 22. The predetermined clock CLK supplied to the receiving device 20 is typically output from the transmitting device 10, but is not limited to this, and is supplied from another external element or internal May be generated. The multiplier circuit 21 may typically have the same circuit configuration as the multiplier circuit 12.

  The synchronization signal detection unit 22 detects the content of the data signal DATA_T2 superimposed on the serial data signal SDATA as the data signal DATA_R2 from the serial data signal SDATA transmitted from the transmission device 10 based on the predetermined clock CLK. The detection result is output to the output unit 23, and based on the multiplied clock CLK_MUL2, the content of the synchronization signal SYNC_T superimposed on the serial data signal SDATA is changed from the serial data signal SDATA transmitted from the transmission device 10 to a plurality of synchronization signals SYNC_R 1) to SYNC_R (m) (where m is a positive integer), and the detection result is output to the output unit 23. Note that there can be as many patterns of the synchronization signal SYNC_R as the number of patterns of the synchronization signal SYNC_T (that is, the number of patterns indicated by the pattern selection signal PAT_SEL). The synchronization signal detection unit 22 selects one synchronization signal SYNC_R corresponding to the detected pattern from the plurality of synchronization signals SYNC_R, and outputs the selection result to the output unit 23.

  The output unit 23 is, for example, a liquid crystal display panel, a plasma display panel, an organic electroluminescence display panel, or a print head, but is not limited thereto. The output unit 23 performs various processes according to the data signal DATA_R2 output from the synchronization signal detection unit 22 based on the plurality of synchronization signals SYNC_R (1) to SYNC_R (m) output from the synchronization signal detection unit 22 (for example, Image display).

  In the data transmission device 1 configured as described above, the transmission device 10 outputs the data signal DATA_T as the serial data signal SDATA based on a predetermined clock CLK during the period of outputting the data signal DATA_T, while the synchronization signal SYNC_T Is generated based on the multiplied clock CLK_MUL1, and the signal is output as the serial data signal SDATA. Further, the data transmission device 1 detects the data signal DATA_R2 from the serial data signal SDATA based on the predetermined clock CLK by the receiving device 20, and also detects the synchronization signal SYNC_R from the serial data signal SDATA based on the multiplied clock CLK_MUL2. (1) to SYNC_R (m) are detected.

  As a result, the data transmission device 1 superimposes a plurality of signals on the serial data signal SDATA, which is one signal, using clocks having different frequencies, and detects each of the superimposed signals using the clocks having different frequencies. Therefore, it is possible to transmit a plurality of types of data and to receive a plurality of types of data by using a serial transmission method without using a preamble.

  FIG. 2 is a diagram illustrating an example of an output control unit according to an embodiment of the present invention. The output control unit 110 according to the present embodiment includes, for example, a counter 1101 and decoders 1102 and 1103.

  The counter 1101 counts the number of alternations of a predetermined clock CLK supplied from the outside. The counter 1101 outputs the result of counting the number of alternating times of the predetermined clock CLK to the decoders 1102 and 1103.

  Based on the count result of the predetermined clock CLK output from the counter 1101, the decoder 1102 determines whether or not the predetermined timing indicated by the predetermined clock CLK is the data signal output period. When the decoder 1102 determines that the predetermined timing indicated by the predetermined clock CLK is the data signal output period, the decoder 1102 sets the state of the assert signal ASSERT to “1” and outputs the signal to the AND circuit 111. On the other hand, when the decoder 1102 determines that the predetermined timing indicated by the predetermined clock CLK is not the data signal output period, the decoder 1102 sets the state of the assert signal ASSERT to “0” and outputs the signal to the AND circuit 111.

  Based on the count result of the predetermined clock CLK output from the counter 1101, the decoder 1103 determines whether or not the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period. When the decoder 1103 determines that the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period, the state of the selection signal SEL is set to “1”, and the signal is output to the synchronization signal generation unit 13 and the selection circuit 14. To do. On the other hand, when the decoder 1103 determines that the predetermined timing indicated by the predetermined clock CLK is not the synchronization signal output period, the state of the selection signal SEL is set to “0”, and the signal is output to the synchronization signal generation unit 13 and the selection circuit 14. Output to.

  FIG. 3 is a diagram illustrating an example of a synchronization signal generation unit according to an embodiment of the present invention. The synchronization signal generation unit 13 according to the present embodiment includes, for example, a counter 131, a plurality of pattern generation circuits 132 (1) to 132 (m), and a selection circuit 133.

  The counter 131 counts a predetermined number of alternating times of the multiplied clock CLK_MUL1 output from the multiplier circuit 12 in accordance with the selection signal SEL, and a plurality of pattern generation circuits 132 (1) to 132 for the predetermined number of clocks. Output to (m). Specifically, when the state of the selection signal SEL is “1”, the counter 131 counts the number of alternations of the multiplied clock CLK_MUL1, and the plurality of pattern generation circuits 132 (1) for the predetermined number of clocks. To 132 (m). On the other hand, when the state of the selection signal SEL is “0”, the counter 131 stops counting the multiplied clock CLK_MUL1 and outputs the clock.

  The pattern generation circuits 132 (1) to 132 (m) generate signals having corresponding patterns when the counting result of the number of alternating times of the multiplied clock CLK_MUL1 output from the counter 131 becomes a predetermined value, The signal is output to the input terminals A0 to Am of the selection circuit 133.

  The selection circuit 133 is, for example, a multiplexer, but is not limited thereto, and may be a data selector, a signal switcher, or the like. The selection circuit 133 selects any one of the signals output from the plurality of pattern generation circuits 132 (1) to 132 (m) according to the pattern selection signal PAT_SEL supplied from the outside, and selects the selection result. It outputs to the selection circuit 14 as a synchronizing signal SYNC_T.

  FIG. 4 is a diagram illustrating another example of the synchronization signal generation unit according to the embodiment of the present invention. The synchronization signal generation unit 13A according to the present embodiment includes a plurality of pattern generation circuits 132A (1) to 132A (m) and a selection circuit 133. Note that the selection circuit 133 is the same as that of the synchronization signal generation unit 13, and thus the description thereof is omitted.

  The pattern generation circuits 132A (1) to 132A (m) each generate a signal having a corresponding pattern based on the multiplied clock CLK_MUL1 according to the state of the selection signal SEL, and output the signal to the selection circuit 133. Specifically, when the state of the selection signal SEL is “1”, the pattern generation circuits 132A (1) to 132A (m) generate signals having corresponding patterns based on the multiplied clock CLK_MUL1, The signal is output to the selection circuit 133. On the other hand, when the state of the selection signal SEL is “0”, the pattern generation circuits 132A (1) to 132A (m) stop generating the signal having the corresponding pattern.

  FIG. 5 is a diagram illustrating another example of the configuration of the transmission apparatus according to an embodiment of the present invention. The transmission apparatus 10A according to the present embodiment corresponds to a case where the period during which the data signal DATA_T is output and the period during which the synchronization signal SYNC_T is output do not overlap at the same time. More simplified. The transmitting apparatus 10A according to the present embodiment includes a data signal control unit 11A, a multiplication circuit 12, a synchronization signal generation unit 13, and an OR circuit 15. Note that the multiplication circuit 12 and the synchronization signal generation unit 13 are the same as those of the transmission device 10, and thus description thereof is omitted.

  The output control unit 110A determines, based on a predetermined clock CLK supplied from the outside, whether a predetermined timing indicated by the predetermined clock CLK is a period during which a data signal output period or a synchronization signal output period is output. The determination result is output as a selection signal SEL to the logic negation circuit 112 and the synchronization signal generator 13. Specifically, when the output control unit 110 determines that the predetermined timing indicated by the predetermined clock CLK is the data signal output period, the output control unit 110 outputs a signal that sets the state of the selection signal SEL to “0” as the logic negation circuit 112 and Output to the synchronization signal generator 13. On the other hand, when the output control unit 110A determines that the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period, the output control unit 110A generates a signal that sets the state of the selection signal SEL to “1” and the logic negation circuit 112 and the synchronization signal generation To the unit 13. The output control unit 110A constitutes the data signal control unit 11A together with the logical product circuit 111 and the logical negation circuit 112 described later.

  The logical negation circuit 112 performs logical negation on the selection signal SEL output from the output control unit 110 </ b> A and outputs the logical negation result to the logical product circuit 111. The logical product circuit 111 performs a logical product on the data signal DATA_T supplied from the outside and the logical negation of the selection signal SEL output from the logical negation circuit 112, and the result of the logical product is used as the data signal DATA_T2. Output to the OR circuit 15.

  The OR circuit 15 performs an OR operation on the data signal DATA_T2 output from the data signal control unit 11A and the synchronization signal SYNC_T output from the synchronization signal generation unit 13, and the result of the OR operation is obtained as a serial data signal. It outputs to the receiver 20 as SDATA.

  The transmission apparatus 10A configured as described above uses the OR circuit 15 instead of the selection circuit 14 for the transmission apparatus 10, so that the data signal output period and the synchronization signal output period are respectively Only when there is no overlap at the same time, the serial data signal SDATA can be generated with a simpler circuit configuration as in the case of the transmitter 10.

  FIG. 6 is a diagram illustrating an example of a configuration of a synchronization signal detection unit according to an embodiment of the present invention. The synchronization signal detection unit 22 according to the present embodiment includes a deserializer 221, a plurality of pattern detection circuits 222 (1) to 222 (m), delay circuits 223 (1) to 223 (m), 225 and 226, A sum circuit 224, a logical NOT circuit 227, and a logical product circuit 228 are included.

  The deserializer 221 converts the serial data signal SDATA from a serial signal to a parallel signal. Specifically, the deserializer 221 latches the serial data signal SDATA transmitted from the transmission device 10 based on the multiplied clock CLK_MUL2 output from the multiplier circuit 21, and converts the latched signal from a serial signal to a parallel signal. The conversion result is output to the plurality of pattern detection circuits 222 (1) to 222 (m) as a parallel data signal PDATA.

  Each of the plurality of pattern detection circuits 222 (1) to 222 (m) determines whether or not the parallel data signal PDATA includes a predetermined pattern corresponding to itself. When each pattern detection circuit 222 determines that the parallel data signal PDATA includes a predetermined pattern corresponding to itself, the pattern detection circuit 222 sets the state of the decode signal DECODE to “1” and the signal corresponds to the OR circuit 224. Output to the delay circuit 223. On the other hand, if the pattern detection circuit 222 determines that the parallel data signal PDATA does not include a predetermined pattern corresponding to itself, the pattern detection circuit 222 sets the state of the decode signal DECODE to “0” and sets the corresponding signal to the OR circuit 224. To the delay circuit 223.

  The delay circuit 223 gives a delay time based on the predetermined clock CLK and the multiplied clock CLK_MUL2 to the decode signal DECODE output from the corresponding pattern detection circuit 222, and extends the period during which the state becomes “1”. The processing result is output to the output unit 23 as the synchronization signal SYNC_R.

  The logical sum circuit 224 performs a logical sum on the decode signals DECODE (1) to DECODE (m) output from the plurality of pattern detection circuits 222 (1) to 222 (m), and masks the result of the logical sum. The signal MASK1 is output to the delay circuit 225.

  The delay circuit 225 gives a delay time based on the predetermined clock CLK and the multiplied clock CLK_MUL2 to the mask signal MASK1 output from the OR circuit 224, and extends the period during which the state becomes “1”. The result is output to the logic negation circuit 227 as a mask signal MASK2.

  The delay circuit 226 gives a delay time based on a predetermined clock and the multiplied clock CLK_MUL2 to the serial data signal SDATA transmitted from the transmission apparatus 10, and outputs the delay time to the AND circuit 228 as the data signal DATA_R1.

  The logical negation circuit 227 performs logical negation on the mask signal MASK2 output from the delay circuit 225, and outputs the logical negation result to the logical product circuit 228. The logical product circuit 228 performs a logical product on the logical negation of the data signal DATA_R1 output from the delay circuit 226 and the mask signal MASK2 output from the logical negation circuit 227, and the result of the logical product is used as the data signal DATA_R2. The signal is output to the output unit 23.

  FIG. 7 is a diagram illustrating an example of a configuration of a delay circuit in the synchronization signal detection unit according to the embodiment of the present invention. As shown in the figure, the delay circuit 223 according to the present embodiment includes sequential circuits 2231 and 2233 and an OR circuit 2232.

  The sequential circuit 2231 is, for example, a D-type flip-flop. The sequential circuit 2231 outputs the decode signal DECODE input to the data input terminal D from the data output terminal Q to the OR circuit 2232 based on the multiplied clock CLK_MUL2 input to the clock terminal CK.

  The logical sum circuit 2232 performs a logical sum on the decode signal DECODE output from the pattern detection circuit 222 and the signal output from the sequential circuit 2231, and outputs the logical sum result to the sequential circuit 2233.

  The sequential circuit 2233 is, for example, a D-type flip-flop. The sequential circuit 2233 outputs the output from the OR circuit 2232 input to the data input terminal D from the data output terminal Q as the synchronization signal SYNC_R to the output unit 23 based on the predetermined clock CLK input to the clock terminal CK. To do.

  FIG. 8 is a diagram illustrating an example of a configuration of a delay circuit in the synchronization signal detection unit according to the embodiment of the present invention. As shown in the figure, the delay circuit 225 according to the present embodiment includes sequential circuits 2251 and 2253 and OR circuits 2252 and 2254.

  The sequential circuit 2251 is, for example, a D-type flip-flop. The sequential circuit 2251 outputs the mask signal MASK1 input from the OR circuit 224 to the data input terminal D to the OR circuit 2252 from the data output terminal Q based on the multiplied clock CLK_MUL2 input to the clock terminal CK.

  The logical sum circuit 2252 performs a logical sum on the mask signal MASK1 output from the logical sum circuit 224 and the signal output from the sequential circuit 2251, and the result of the logical sum is the sequential circuit 2253 and the logical sum circuit 2254. Output to.

The sequential circuit 2253 is, for example, a D-type flip-flop. The sequential circuit 2253 outputs a signal output from the OR circuit 2252 from the data output terminal Q to the OR circuit 2254 based on a predetermined clock CLK input to the clock terminal CK.

  The logical sum circuit 2254 performs a logical sum on the signal output from the logical sum circuit 2252 and the signal output from the sequential circuit 2253, and outputs the result of the logical sum to the output control circuit 227 as a mask signal MASK2. To do.

  FIG. 9 is a diagram illustrating an example of a configuration of a delay circuit in the synchronization signal detection unit according to the embodiment of the present invention. As shown in the figure, the delay circuit 226 according to the present embodiment includes sequential circuits 2261 to 2263.

  The sequential circuits 2261 to 2263 are D-type flip-flops. The D-type flip-flop outputs a signal input to the data input terminal D from the data output terminal Q based on the clock input to the clock terminal CK. Specifically, the sequential circuit 2261 outputs the serial data signal SDATA output from the transmission device 10 to the sequential circuit 2262 based on the multiplied clock CLK_MUL2. The sequential circuit 2262 outputs a signal output from the sequential circuit 2261 to the sequential circuit 2263 based on the multiplied clock CLK_MUL2. The sequential circuit 2263 outputs a signal output from the sequential circuit 2262 as the data signal DATA_R2 to the output unit 23 based on a predetermined clock CLK.

  FIG. 10 is a flowchart showing the operation of the transmission apparatus according to an embodiment of the present invention. As shown in the figure, the transmitting apparatus 10 first receives a data signal DATA_T and a predetermined clock CLK supplied from the outside (S1001).

  Next, the transmitting apparatus 10 determines whether or not the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period (S1002). When determining that the predetermined timing indicated by the predetermined clock CLK is the synchronization signal output period (Yes in S1002), the transmission device 10 generates the synchronization signal SYNC_T based on the multiplied clock CLK_MUL1 (S1003). The synchronized signal SYNC_T thus selected is selected as the serial data signal SDATA (S1004).

  On the other hand, when determining that the predetermined timing indicated by the predetermined clock CLK is not the synchronization signal output period (No in S1002), the transmitting apparatus 10 latches the data signal DATA_T based on the predetermined clock CLK (S1005), The latched data signal DATA_T is selected as the serial data signal SDATA (S1006).

  The transmitting apparatus 10 outputs the serial data signal SDATA (that is, the synchronization signal SYNC_T or the data signal DATA_T) selected in the process of step S1004 or the process of step S1006 to the receiving apparatus 20 (S1007), and ends the operation.

  As described above, the transmission apparatus 10 according to the present embodiment outputs the data signal DATA_T as the serial data signal SDATA based on the predetermined clock CLK in the data signal output period, while the multiplied clock CLK_MUL1 is output in the synchronization signal output period. Based on this, a synchronization signal SYNC_T is generated, and this signal is output as a serial data signal SDATA. As a result, the transmission apparatus 10 can superimpose a plurality of signals on the serial data signal SDATA, which is a single signal, using clocks having different frequencies, so that a plurality of types can be selected depending on the serial transmission method without using a preamble. Data can be transmitted.

  FIG. 11 is a flowchart showing an operation of the receiving apparatus according to the embodiment of the present invention. As shown in the figure, the receiving device 20 first receives the serial data signal SDATA output from the transmitting device 10 (S1101). The receiving device 20 generates and outputs a data signal DATA_R2 by latching the serial data signal SDATA with a predetermined clock CLK (S1102).

  Next, the receiving device 20 latches the serial data signal SDATA by the multiplied clock CLK_MUL2 (S1103). The receiving apparatus 20 determines whether or not the signal latched by the multiplied clock CLK_MUL2 includes a predetermined pattern (S1104). When the reception device 20 determines that the signal latched by the multiplied clock CLK_MUL2 includes a predetermined pattern (Yes in S1104), the reception device 20 generates and outputs a synchronization signal SYNC_R based on the predetermined pattern (S1105). A mask signal MASK2 is generated based on the signal SYNC_R (S1106), and the output of the data signal DATA_R2 is stopped based on the mask signal MASK2 (S1107).

  On the other hand, when the receiving apparatus 20 determines that the signal latched by the multiplied clock CLK_MUL2 does not include a predetermined pattern (No in S1104), the receiving apparatus 20 ends the operation.

  As described above, the receiving device 20 according to the present embodiment detects the data signal DATA_R2 from the serial data signal SDATA based on the predetermined clock CLK, and synchronizes from the serial data signal SDATA based on the multiplied clock CLK_MUL2. A signal SYNC_R is detected. As a result, the receiving device 20 can detect each of the signals superimposed by the clocks of different frequencies from the serial data signal SDATA on which a plurality of signals are superimposed, so that the serial transmission method can be used without using a preamble. It becomes possible to receive a plurality of types of data transmitted by.

  FIG. 12 is a timing chart of various signals in the transmission device and the reception device according to the embodiment of the present invention. In the figure, it is assumed that the frequency of the multiplied clock CLK_MUL1 is twice the frequency of the predetermined clock CLK. In the figure, timings at which a predetermined clock CLK alternates are defined as times t1201 to t1213. Further, the time at which the multiplied clock CLK_MUL1 first alternates after time t1207 is defined as time t1207 ', and the time at which the multiplied clock CLK_MUL1 first alternates after time t1208 is defined as time t1208'.

  First, the operation of the transmission device 10 will be described. As described above, the data signal control unit 11 determines whether the predetermined timing indicated by the predetermined clock CLK is the data signal output period or the synchronization signal output period, and outputs the determination result as the selection signal SEL. . At times t1201 to t1207, the data signal control unit 11 determines that the predetermined timing indicated by the predetermined clock CLK is a period for outputting the data signal DATA_T, outputs the data signal DATA_T as the data signal DATA_T2, and selects the selection signal. The signal is output with the SEL state set to “0”. From time t1201 to t1207, the synchronization signal generator 13 stops generating and outputting the synchronization signal SYNC_T based on the state “0” of the selection signal SEL. From time t1201 to time t1207, the selection circuit 14 outputs the data signal DATA_T2 output from the data signal control unit 11 to the reception device 20 as the serial data signal SDATA based on the state “0” of the selection signal SEL.

  From time t1207 to t1209, the data signal control unit 11 determines that the predetermined clock CLK is in the synchronization signal output period, stops outputting the data signal DATA_T2, and sets the state of the selection signal SEL to “1”. Is output. From time t1207 to t1209, the synchronization signal generation unit 13 generates the synchronization signal SYNC_T based on the state “1” of the selection signal SEL. Here, the synchronization signal generation unit 13 generates the synchronization signal SYNC_T so as to have a predetermined pattern that can be determined by the multiplied clock CLK_MUL1 and the multiplied clock CLK_MUL2 of the reception device 20 but cannot be determined by the predetermined clock CLK. In this example, the synchronization signal generator 13 takes “1” at time t1207, “0” at time t1207 ′, “1” at time t1208, and “0” at time t1208 ′ ( That is, the synchronization signal SYNC_T is generated so that the pattern “1010” is taken. From time t1207 to time t1209, the selection circuit 14 outputs the synchronization signal SYNC_T output from the synchronization signal generation unit 13 to the reception device 20 as the serial data signal SDATA based on the state “1” of the selection signal SEL.

  Further, the data signal control unit 11 determines that the predetermined timing indicated by the predetermined clock CLK is the data signal output period from time t1209 to t1213, outputs the data signal DATA_T2 again, and changes the state of the selection signal SEL. The signal is output as “0”. From time t1209 to t1213, the synchronization signal generator 13 stops generating and outputting the synchronization signal SYNC_T based on the state “0” of the selection signal SEL. From time t1209 to t1213, the selection circuit 14 outputs the data signal DATA_T2 output from the data signal control unit 11 to the reception device 20 as the serial data signal SDATA based on the state “0” of the selection signal SEL.

  Next, the operation of the receiving device 20 will be described. At times t1201 to t1207, the synchronization signal detection unit 22 does not detect a predetermined pattern from the serial data signal SDATA output from the transmission device 10. The synchronization signal detection unit 22 delays the serial data signal SDATA by two clocks of a predetermined clock CLK, and outputs the delayed signal to the output unit 23 as the data signal DATA_R2.

  From time t1207 to t1209, the synchronization signal detection unit 22 detects a predetermined pattern (in this example, “1010”) from the serial data signal SDATA by the multiplied clock CLK_MUL2. At this time, the synchronization signal detection unit 22 receives a predetermined pattern from the pattern detection circuits 222 (1) to 222 (m), detects a predetermined pattern by the pattern detection circuit 222 corresponding to the predetermined pattern, and outputs the decoded signal DECODE. (See FIG. 6). Then, the synchronization signal detection unit 22 sets the state of the decode signal DECODE to “1” by the pattern detection circuit 222, delays the signal by three clocks of the predetermined clock CLK by the delay circuit 223, and synchronizes the delayed signal. The signal is output to the output unit 23 as the signal SYNC_R. The synchronization signal detector 22 stops outputting the data signal DATA_R2 while outputting the synchronization signal SYNC_R.

  From time t1209 to t1213, the synchronization signal detection unit 22 does not detect a predetermined pattern from the serial data signal SDATA. The synchronization signal detection unit 22 delays the serial data signal SDATA by two clocks of a predetermined clock CLK, and outputs the delayed signal to the output unit 23 as the data signal DATA_R2.

  As described above, in the data transmission device 1 according to the present embodiment, the transmission device 10 outputs the data signal DATA_T as the serial data signal SDATA based on the predetermined clock CLK during the period of outputting the data signal DATA_T. During the period for outputting the synchronization signal SYNC_T, the synchronization signal SYNC_T is generated based on the multiplied clock CLK_MUL1, and the signal is output as the serial data signal SDATA. Further, the data transmission device 1 detects the data signal DATA_R2 from the serial data signal SDATA based on the predetermined clock CLK by the receiving device 20, and also detects the synchronization signal SYNC_R from the serial data signal SDATA based on the multiplied clock CLK_MUL2. Is detected.

  As a result, the data transmission device 1 superimposes a plurality of signals on the serial data signal SDATA, which is one signal, using clocks having different frequencies, and detects each of the superimposed signals using the clocks having different frequencies. Therefore, a plurality of types of data can be transmitted by the serial transmission method and a plurality of types of data transmitted by the serial transmission method can be received without using a preamble.

  Each of the above embodiments is an example for explaining the present invention, and is not intended to limit the present invention only to these embodiments. The present invention can be implemented in various forms without departing from the gist thereof.

  For example, in the method disclosed herein, steps, operations, or functions may be performed in parallel or in a different order, as long as the results do not conflict. The steps, operations, and functions described are provided as examples only, and some of the steps, operations, and functions may be omitted and combined with each other without departing from the spirit of the invention. There may be one, and other steps, operations or functions may be added.

  Further, although various embodiments are disclosed in this specification, a specific feature (technical matter) in one embodiment is appropriately improved and added to another embodiment or the other implementation. Specific features in the form can be substituted, and such form is also included in the gist of the present invention.

  The present invention can be widely used in the field of equipment including a transmission device and / or a reception device that transmits data.

DESCRIPTION OF SYMBOLS 1 ... Data transmission apparatus 10 ... Transmission apparatus 11 ... Data signal control part 110 ... Output control part 1101 ... Counter 1102,1103 ... Decoder 111 ... Logical product circuit 112 ... Logical negation circuit 12 ... Multiplication circuit 13 ... Synchronization signal generation part 131 ... Counter 132... Pattern generation circuit 133... Selection circuit 14... Selection circuit 15... OR circuit 20... Receiver 21. , 2233, 2251, 2253, 2261, 2262, 2263 ... sequential circuits 2232, 2252, 2254 ... logical sum circuit 224 ... logical sum circuit 227 ... logical negation circuit 228 ... logical product circuit 23 ... output section

Claims (11)

A data signal control unit that latches a data signal supplied from the outside based on a predetermined clock and determines whether a predetermined timing indicated by the predetermined clock is a data signal output period or a synchronization signal output period When,
A synchronization signal generating unit that generates a synchronization signal based on a frequency-multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification;
A selection circuit that outputs either the data signal latched by the data signal control unit or the synchronization signal according to the result of the determination by the data signal control unit;
A transmission device comprising:   The transmission device according to claim 1, wherein the data signal control unit determines whether the predetermined timing is the data signal output period or the synchronization signal output period based on the number of alternations of the predetermined clock. .   The synchronization signal generation unit selects one pattern from a plurality of predetermined patterns according to a pattern selection signal supplied from the outside, and generates the synchronization signal so as to include the selected one pattern. The transmission device according to claim 1. The synchronization signal generation unit stops generation of the synchronization signal when the data signal control unit determines that the predetermined timing is the data signal output period, while the data signal control unit stops the predetermined timing. Is determined to be the synchronization signal output period, start generating the synchronization signal,
The selection circuit outputs a data signal output from the data signal control unit when the data signal control unit determines that the predetermined timing is the data signal output period, and the data signal control unit When it is determined that the predetermined timing is the synchronization signal output period, the synchronization signal is output.
The transmission device according to claim 1. A delay circuit that latches an externally supplied serial data signal based on a predetermined clock;
Determining whether the serial data signal includes a predetermined pattern based on a multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification; A pattern detection circuit that outputs the predetermined pattern as a synchronization signal when the serial data signal includes the predetermined pattern;
A receiving device.   The receiving device according to claim 5, further comprising: an output control circuit that outputs the serial data signal latched by the delay circuit as a data signal when the serial data signal does not include a predetermined pattern. A deserializer for converting the serial data signal from a serial signal to a parallel signal;
The pattern detection circuit receives an output of the deserializer, and determines whether or not a predetermined pattern is included in the serial data signal according to the output.
The receiving device according to claim 5. A plurality of pattern detection circuits;
The predetermined pattern is different in each pattern detection circuit,
When the output control circuit determines that none of the pattern detection circuits includes the predetermined pattern in the serial data signal, the output control circuit outputs the serial data signal latched by the delay circuit as the data signal. To
The receiving device according to claim 6. A data transmission device comprising a transmission device and a reception device,
The transmitter is
A data signal control unit that latches a data signal supplied from the outside based on a predetermined clock and determines whether a predetermined timing indicated by the predetermined clock is a data signal output period or a synchronization signal output period When,
A synchronization signal generating unit that generates a synchronization signal so as to include a predetermined pattern based on a multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification;
In accordance with the result of the determination by the data signal control unit, a selection circuit that outputs either the data signal latched by the data signal control unit or the synchronization signal as a serial data signal,
The receiving device is:
A delay circuit that latches the serial data signal based on the predetermined clock;
Based on the multiplied clock, it is determined whether or not the predetermined pattern is included in the serial data signal. When the predetermined pattern is included in the serial data signal, the predetermined pattern is used as a synchronization signal. Output as a pattern detection circuit,
Data transmission equipment. A method for generating a serial data signal,
Receiving a data signal and a predetermined clock supplied from the outside;
Determining whether a predetermined timing indicated by the predetermined clock is a synchronization signal output period;
When the predetermined timing is the synchronization signal output period, a synchronization signal is generated based on a multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification, Selecting the synchronization signal;
When the predetermined timing is not the synchronization signal output period, latching the data signal by the predetermined clock, and selecting the latched data signal;
Outputting the selected signal as the serial data signal;
A method for generating a serial data signal, including: A method for detecting a predetermined pattern from a serial data signal,
Receiving the serial data signal;
Generating and outputting a data signal by latching the serial data signal with a predetermined clock; and
The serial data signal is latched based on a multiplied clock different from the predetermined clock generated by multiplying the frequency of the predetermined clock by a predetermined magnification, and the latched result includes a predetermined pattern. To determine whether or not
When the latched result includes a predetermined pattern, the output of the data signal is stopped, and a synchronization signal is generated and output based on the latched result;
A method for detecting a predetermined pattern from a serial data signal.