JP2005327286A - Memory system and main data loading method for safely loading main data - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a memory system and a main data loading method for safely loading main data.
A memory system according to the present invention includes a main memory, a reference data storage device, and a controller. The main memory stores main data and dummy data. The reference data storage device stores the same reference data as the dummy data. The controller accesses the dummy data from the main memory at power-up, and accesses the main data from the main memory when the dummy data accessed from the main memory matches the reference data stored in the reference data storage device. According to the present invention, main data can be safely accessed at power-up.
[Selection] Figure 2

Description

  The present invention relates to a memory system, and more particularly to a memory system and a main data loading method for stably loading main data (for example, boot code) at power-up.

  Semiconductor memory devices are generally classified into volatile memory devices such as DRAM and SRAM, and non-volatile memory devices such as PROM, EPROM, EEPROM, and FRAM. The volatile memory device loses the stored data when the power is cut off, but the non-volatile memory device stores the stored data even when the power is cut off. Accordingly, nonvolatile memory devices (particularly flash memory devices) are widely used as recording storage media in various application fields (for example, computer systems) where there is a high possibility that power supply will be interrupted. In addition, since the flash memory device has advantages such as high programming speed and low electrode consumption, it is used as a storage medium such as BIOS (Basic Input / Output System) and boot code (Boot code) in a computer system.

  The flash memory device includes a boot block for storing specific information such as BIOS code data, a boot code, or a password. The boot block is the first area accessed by the host when the system is powered on. Such boot block erase and program operations are performed more often than ordinary data blocks. When the power supply voltage Vcc is applied to the system, the host accesses the boot code necessary for system initialization.

  However, when the power supply voltage Vcc is applied to the system, the power supply voltage normally becomes a full-swing over several hundred μsec. Therefore, there is a possibility that the boot code is read from the flash memory during the full swing of the power supply voltage or within a minimum margin of the power supply voltage Vcc. At this time, a voltage required for the boot code read operation is not supplied, and an error may occur in the booting operation. If a failure occurs in the boot code necessary for system initialization, the operation of the system itself becomes impossible. In order to solve such a problem, the boot code is loaded after a certain time (for example, about 300 μsec) elapses by placing an oscillator (Oscillator) or the like inside the flash memory device. However, since the full swing time of the power supply voltage is variable each time the system power is turned on, it is possible to stably load important data such as a boot code even with an element such as an oscillator. There are still problems that cannot be done.

  The present invention has been proposed to solve the above-described problems, and an object of the present invention is to stably load main data such as a boot code when a power supply voltage is applied to the system. To provide a memory system and a main data loading method.

  Another object of the present invention is to provide a memory system and a booting method capable of safely executing a booting operation in a memory system including a NAND flash memory.

  The memory system according to the present invention includes a main memory, a first storage device, and a controller. The main memory stores main data and dummy data. The reference data storage device stores the same reference data as the dummy data. The controller accesses the dummy data from the main memory at power-up, and when the dummy data accessed from the main memory matches the reference data stored in the first storage device, the main data is transferred to the second storage device. To load.

  In this embodiment, the main data includes a boot code. The dummy data and the reference data are predetermined codes preloaded in the main memory and the first storage device.

  In this embodiment, the main memory is a non-volatile memory. The dummy data is stored in advance in the OTP block of the main memory. The non-volatile memory is a flash memory.

  In this embodiment, the first storage device is a register and the second storage device is a RAM. The first storage device is built in the controller. The controller and the main memory are built in a single chip. The memory system is a memory card.

  Another aspect of the memory system according to the present invention includes a memory storing a boot code and dummy data, and a controller having a register storing the same reference data as the dummy data. Here, the controller accesses dummy data from the memory at power-up, compares the accessed dummy data with the reference data stored in the register, and if they match, the boot code is stored in the boot RAM. To load.

  In this embodiment, the memory system further includes a delay circuit that delays accessing the dummy data for a predetermined time when a power supply voltage is applied. The delay circuit is an oscillator. The predetermined time is 100 μS to 200 μS.

  In this embodiment, the memory is a non-volatile memory. The dummy data is stored in the OTP block of the nonvolatile memory. The memory is a flash memory. The flash memory is a NAND flash memory.

  In this embodiment, the memory system is integrated on a single chip.

  The data loading method according to the present invention includes a step of storing main data and dummy data in a main memory, a step of storing reference data identical to the dummy data in a first storage device, and a power-up signal is applied. Accessing the dummy data from the main memory; comparing the dummy data accessed from the main memory with reference data stored in the first storage; and a reference stored in the first storage device Loading the main data into the second storage device when the data matches the dummy data accessed from the main memory.

  In this embodiment, the first storage device is a register and the second storage device is a RAM. The main memory is a nonvolatile memory. The dummy data is stored in the OTP block of the nonvolatile memory. The nonvolatile memory is a NAND flash memory.

  In this embodiment, the main data includes a boot code.

  In this embodiment, the main data and the dummy data are stored in advance in the main memory, the reference data is stored in advance in the first storage device, and the power-up signal is generated when a power supply voltage is applied. .

  In this embodiment, the method further includes re-accessing the dummy data from the main memory if the dummy data accessed from the main memory does not match the reference data stored in the first storage device.

  The booting method according to the present invention includes a step of storing a boot code and dummy data in a main memory, a step of storing reference data identical to the dummy data in a register, and the main memory from when the power supply voltage is applied. Accessing dummy data; comparing dummy data accessed from the main memory with reference data stored in the register; and dummy data from which the reference data stored in the register is accessed from the main memory If it matches, the boot code is loaded into the boot RAM, and if not, the access step and the comparison step are repeated.

  In this embodiment, the booting method further includes performing a booting operation using a boot code loaded in the boot RAM.

  In this embodiment, when a power supply voltage is applied, access to dummy data from the main memory is delayed for 100 μS to 200 μS.

  In this embodiment, the main memory is a non-volatile memory. The dummy data is stored in the OTP block of the nonvolatile memory.

  According to the memory system of the present invention, it is possible to prevent main data such as a boot code from being loaded before the power supply voltage is fully swung or before the voltage reaches the minimum margin. Through this, it is possible to safely load the main data regardless of changes in the time during which the power supply voltage is fully swung.

  DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Reference will now be made in detail to the most preferred embodiments of the present invention, examples of which are illustrated in the accompanying drawings so that those skilled in the art can easily implement the technical ideas of the present invention. To explain.

  FIG. 1 is a block diagram showing a first embodiment of a memory system according to the present invention. Referring to FIG. 1, the memory system 10 includes a memory 100, a reference data storage device 200, and a controller 300.

  The memory 100 includes a main area 101 that stores main data essential for the operation of the memory system 10. The main data includes, for example, a boot code, a BIOS code, an operation system code, and the like. The memory 100 includes a dummy area 102 for storing test data (hereinafter referred to as “dummy data”). The dummy data is used to test the readiness of the power supply voltage applied to the memory system 10. The memory 100 includes a non-volatile memory such as a ROM, a NOR flash memory, and a NAND flash memory.

  The reference data storage device 200 stores the same reference data as the dummy data stored in the memory 100. The reference data storage device 200 can be realized in various forms such as a register, a RAM, and a ROM. The reference data storage device 200 may be included in the controller 300.

  The controller 300 includes a processor (not shown) that controls the operation of the memory system 10, and reads data from the memory 100 and the reference data storage device 200.

  When a power supply voltage is applied to the memory system 10, the controller 300 reads an operating system code such as a boot code from the memory 100 to boot the memory system 10. When a power supply voltage is applied or when a power-on-reset (POR) signal is applied, the controller 300 reads dummy data in the dummy area 102 of the memory 100, and the reference data storage device 200. Compare with the reference data stored in As a result of the comparison, if the dummy data and the reference data match, the controller 300 outputs true. On the other hand, if the dummy data and the reference data do not match, the controller 300 outputs false. If the comparison result is false, the controller 300 reads the dummy data and repeats the operation of comparing with the reference data.

  Here, the output of true indicates that the power supply voltage supplied to the memory system 10 has reached a full swing state, or that data can be accurately read from the memory 100 without error. It means that a voltage of a certain level has been reached. At this time, the controller 300 loads main data stored in the main area 101 of the memory 100.

  FIG. 2 is a conceptual diagram showing an operation of loading dummy data repeatedly until main data is loaded in the memory system shown in FIG. The memory system shown in FIG. 1 repeatedly loads dummy data from the time of power-up until the dummy data matches the reference data. The main data loading operation starts when the dummy data matches the reference data.

  Here, power-up means when a reset signal is generated by a system initialization circuit such as a POR (Power On Reset) circuit (not shown) provided in the memory system 10. Generally, a memory system is designed to apply a reset signal to an appropriate memory system in an initial state for stable operation, and to perform a normal operation after the reset signal is applied. In particular, if the memory system includes elements such as filters or flip-flops, the initial state cannot be predicted, so if the memory system is operated without resetting, an error occurs and the user wishes It is difficult to execute the operation. Such a reset signal can be generated after a predetermined time has elapsed after a power supply voltage is applied by creating a separate pin to be input from the outside. In addition, when a system initialization circuit such as a POR circuit is built in the memory system and power is applied, a reset signal can be automatically generated.

  Referring again to FIG. 2, when the dummy data matches the reference data, the main data loading operation is started. In FIG. 2, reference numerals 1a, 2a, and 3a denote the time when loading of main data is started, that is, the time when dummy data and reference data match. In FIG. 2, as an example, it is shown that main data starts to be loaded at a time point 1a when the power supply voltage is fully swung. However, the present invention is not limited to this, and the main data is loaded if the dummy data matches the reference data at the time point 3a before the power supply voltage is fully swung or at the time point 2a after the full swing. start.

  FIG. 3 is a flow chart showing a main data loading operation of the memory system shown in FIG. When the power supply voltage Vcc is input to the memory system 10 (S100) and the memory system 10 is powered up by a system initialization circuit (for example, a POR circuit) (S110), the controller 300 loads dummy data from the dummy area 102. (S200). Then, the controller 300 checks whether the dummy data matches the reference data stored in the reference data storage device 200 (S300). If the dummy data and the reference data do not match, the dummy data is reloaded from the dummy area 102. While dummy data is repeatedly loaded, the power supply voltage becomes close to a full swing. When the power supply voltage reaches the full swing section or the minimum power supply voltage margin section and the dummy data and the reference data coincide with each other, the controller 300 starts loading the main data from the main area 101 (S400).

  Referring back to FIG. 1, the memory system 10 repeatedly loads dummy data in order to stably load main data when a power supply voltage is applied. The reason for this is to prevent the main data from being loaded before the power supply voltage Vcc is fully swung, and more precisely before reaching the minimum margin of the power supply voltage. This is because if the main data is loaded before the power supply voltage is fully swung, a failure is likely to occur. That is, in order to load the main data stably by loading the main data when there is no obstacle in the dummy data loading operation before loading the main data having important information. is there.

  FIG. 4 is a block diagram showing a second embodiment of the memory system according to the present invention. Here, the same reference numerals as those in FIG. 1 indicate the same members that perform the same functions. Referring to FIG. 4, the memory system 20 further includes a delay circuit 400. The delay circuit 400 delays the time when dummy data is loaded for a certain time from the time of power-up. The delay circuit 400 can be realized by, for example, an oscillator or a timer. It is obvious to those skilled in the art that a delay circuit such as an oscillator or a timer can delay the start of a data loading operation for a certain time.

  The reason why the loading circuit automatically delays the loading operation for a predetermined time from the time of power-up by the delay circuit 400 is that it usually takes about several hundred μsec until the power supply voltage is applied and the full swing is made. That is, by delaying the loading operation through the delay circuit 400, a margin of a minimum power supply voltage necessary for normal loading operation is ensured. Another reason is to prevent a time delay due to the repeated loading operation of dummy data.

  FIG. 5 shows an operation of repeatedly loading dummy data after the memory system shown in FIG. 4 is powered up and after a predetermined time delay until before main data is loaded. Referring to FIG. 6, dummy data starts to be loaded after a certain time (for example, 100 μS to 200 μS) has been delayed from the time of power-up. When the dummy data matches the reference data, the main data loading operation starts. Reference numerals 1b, 2b, and 3b in FIG. 5 are the same as those in FIG.

  FIG. 6 is a flowchart showing a main data loading operation of the memory system shown in FIG. The order and method of data loading operations in the memory system 20 are the same as those described with reference to FIG. However, FIG. 6 further includes a step (S120) of delaying the time when dummy data is loaded between the power-up step (S110) and the dummy data loading step (S200).

  FIG. 7 is a block diagram showing a third embodiment of the memory system according to the present invention. The memory system 30 shown in FIG. 7 is for stably loading the boot code in the boot block 121 when the power supply voltage Vcc is applied. For this, the memory system 30 includes a NAND flash memory 110, a register 210, a memory controller 310, a boot RAM 320, and a POR circuit 330.

  The NAND flash memory 110 includes a memory cell array 120 having a plurality of blocks Boot_Block, Block 1 to Blockn, and OTP_Block. The memory cell array 120 includes a boot block 121 that stores a boot code and an OTP block 122 that stores data.

  Here, the boot block Boot_Block 121 stores a boot code for executing a booting operation. The OTP block (One-Time Programmable Block) 122 is a data that is repeatedly loaded before the boot code is loaded in order to stably load the boot code stored in the boot block 121 during the booting operation. (Hereinafter referred to as OTP data). Here, the OTP block is a block for storing programmable data only once. Due to the complexity of the information processing system, the user tries to store the ID of the flash memory to be used, that is, the serial number of the manufacturer, the date of manufacture, data that requires security, and the like in the flash memory. An area for storing such security data is an OTP block. The OTP block is programmed with security data only once according to its original purpose, and once programmed data can be safely protected for any external operation. Therefore, the OTP data stored in the OTP block 122 is safely maintained.

  The register 210 stores reference data corresponding to the OTP data stored in the OTP block 122. The memory controller 310 controls various operations of the memory system during a booting operation. The memory controller 310 repeatedly loads OTP data before loading the boot code for stable loading of the boot code after the power supply voltage Vcc is applied and the memory system 30 is powered up by the POR circuit 330. . Then, the OTP data and the reference data stored in the register 210 are compared. If the OTP data matches the reference data, the memory controller 310 loads the boot code from the boot block 121 and transmits it to the boot RAM 320.

  The boot RAM 320 stores the boot code transmitted from the NAND flash memory 110. The booting operation is performed through an operation of accessing the boot code stored in the boot RAM 320 by the host.

  Meanwhile, the NAND flash memory, boot RAM, register, and memory controller can be integrated on one single chip. The boot RAM, registers, and memory controller can also be integrated on one single chip.

  FIG. 8 is a flow chart showing a booting operation of the memory system shown in FIG. When the power supply voltage Vcc is input to the memory system 30 (S100) and the system is powered up by the POR circuit 330 (S110), the memory controller 310 loads OTP data from the OTP block 122 (S210). Then, the memory controller 310 checks whether the OTP data matches the reference data stored in the register 210 (S310). If the OTP data and the reference data do not match, the OTP data is reloaded from the OTP block 122. While the OTP data is repeatedly loaded, the power supply voltage is almost fully swung. When the power supply voltage is fully swung and the OTP data and the reference data match, the memory controller 310 loads the boot code from the boot block 121 (S410). The boot code loaded in the memory controller 310 is transmitted to the boot RAM 320 (S510). Then, the boot code stored in the boot RAM 320 is accessed by the host to execute the booting operation (S610).

  FIG. 9 is a block diagram showing a fourth embodiment of the memory system according to the present invention. Here, the same reference numerals as in FIG. 7 indicate the same members that perform the same functions. The memory system 40 shown in FIG. 9 further includes an oscillator 340. The oscillator 340 delays the time point when the OTP data is loaded for a certain time (for example, 100 μS to 200 μS) from the time of power-up.

  Meanwhile, the NAND flash memory 110, the register 210, the memory controller 310, the boot RAM 320, the POR circuit 330, and the oscillator 340 shown in FIG. 9 can be integrated on one single chip.

  FIG. 10 is a flow chart showing a booting operation of the memory system shown in FIG. The operation of loading the boot code in the memory system 40 and the booting operation by the host are the same as described in FIG. However, in FIG. 10, there is a step (S120) of delaying the time point when the OTP data is loaded between the power-up step (S110) and the OTP data loading step (S210) for a certain time (eg, 100 μS to 200 μS). Also included.

  Although the detailed description of the present invention has been described with reference to specific embodiments, it should be understood that various modifications can be made without departing from the scope of the present invention. Therefore, the scope of the present invention is not limited to the above-described embodiments, but must be determined not only by the claims but also by the equivalents of the claims of the present invention.

1 is a block diagram showing a first embodiment of a memory system according to the present invention. FIG. FIG. 2 is a conceptual diagram showing a loading operation by repeating dummy data before loading main data in the memory system shown in FIG. 1. FIG. 2 is a flowchart illustrating a main data loading operation of the memory system illustrated in FIG. 1. It is a block diagram which shows 2nd Embodiment of the memory system by this invention. FIG. 5 is a flow chart showing an operation of repeatedly loading dummy data after being powered up by the memory system shown in FIG. 4 and delaying a predetermined time before loading main data. FIG. 5 is a flowchart illustrating a main data loading operation of the memory system illustrated in FIG. 4. It is a block diagram which shows 3rd Embodiment of the memory system by this invention. FIG. 8 is a flowchart illustrating a booting operation of the memory system illustrated in FIG. 7. It is a block diagram which shows 4th Embodiment of the memory system by this invention. FIG. 10 is a flowchart illustrating a booting operation of the memory system illustrated in FIG. 9.

Explanation of symbols

10, 20, 30, 40 Memory system 100 Non-volatile memory 110 NAND flash memory 120 Memory cell array 121 Boot block 122 OTP block 200 Reference data storage device 210 Register 300 Controller 310 Memory controller 320 Boot RAM
330 POR circuit 340 Oscillator 400 Delay circuit

Claims (32)

Main memory for storing main data and dummy data;
A first storage device for storing the same reference data as the dummy data;
When powering up, the dummy data is accessed from the main memory, and when the dummy data accessed from the main memory matches the reference data stored in the first storage device, the main data is loaded into the second storage device. A memory system.   The memory system according to claim 1, wherein the main data includes a boot code.   2. The memory system according to claim 1, wherein the dummy data and the reference data are codes stored in advance in the main memory and the first storage.   The memory system according to claim 1, wherein the main memory is a nonvolatile memory.   5. The memory system according to claim 4, wherein the dummy data is stored in advance in an OTP block of the main memory.   The memory system according to claim 1, wherein the main memory is a flash memory.   The memory system according to claim 1, wherein the first storage device is a register and the second storage device is a RAM.   The memory system according to claim 1, wherein the first storage device is built in the controller.   The memory system according to claim 1, wherein the controller and the main memory are built in a single chip.   The memory system according to claim 1, wherein the memory system is a memory card. A memory storing boot code and dummy data; and
A controller having a register storing reference data identical to the dummy data,
The controller accesses dummy data from the memory at power-up, compares the accessed dummy data with reference data stored in the register, and loads the boot code into the boot RAM when they match. A memory system characterized by that.   12. The memory system of claim 11, further comprising a delay circuit that delays access to the dummy data for a predetermined time when a power supply voltage is applied.   The memory system according to claim 11, wherein the delay circuit is an oscillator.   The memory system according to claim 12, wherein the predetermined time is 100 μS to 200 μS.   The memory system according to claim 11, wherein the memory is a nonvolatile memory.   The memory system according to claim 15, wherein the dummy data is stored in an OTP block of the nonvolatile memory.   The memory system according to claim 17, wherein the memory is a flash memory.   The memory system according to claim 17, wherein the flash memory is a NAND flash memory.   The memory system of claim 11, wherein the memory system is integrated on a single chip. Storing main data and dummy data in main memory;
Storing the same reference data as the dummy data in a first storage device;
Accessing the dummy data from the main memory when a power-up signal is applied;
Comparing dummy data accessed from the main memory with reference data stored in the first storage device;
And loading the main data into the second storage device when the reference data stored in the first storage device matches the dummy data accessed from the main memory.   21. The data loading method of claim 20, wherein the first storage device is a register and the second storage device is a RAM.   The data loading method according to claim 20, wherein the main memory is a non-volatile memory.   The data loading method according to claim 22, wherein the dummy data is stored in an OTP block of the main memory.   21. The data loading method according to claim 20, wherein the main memory is a NAND flash memory.   The data loading method of claim 20, wherein the main data includes a boot code.   The main data and the dummy data are stored in advance in the main memory, the reference data is stored in advance in the first storage device, and the power-up signal is generated when a power supply voltage is applied. The data loading method according to claim 20.   The method of claim 20, further comprising re-accessing the dummy data from the main memory if the dummy data accessed from the main memory does not match the reference data stored in the first storage device. Data loading method described in Storing boot code and dummy data in main memory;
Storing the same reference data as the dummy data in a register;
Accessing a dummy data from the main memory when a power supply voltage is applied;
Comparing dummy data accessed from the main memory with reference data stored in the register;
If the reference data stored in the register matches the dummy data accessed from the main memory, the boot code is loaded into the boot RAM; otherwise, the access step and the comparison step are repeated. A booting method comprising:   The booting method of claim 28, further comprising performing a booting operation using a boot code loaded in the boot RAM.   29. The booting method according to claim 28, wherein access to dummy data from the main memory is delayed for 100 μS to 200 μS when a power supply voltage is applied.   The booting method according to claim 28, wherein the main memory is a non-volatile memory. 32. The booting method according to claim 31, wherein the dummy data is stored in an OTP block of the nonvolatile memory.

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