JPH11272472A - Microcomputer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To permit the rewriting of the program instruction of the first storage area of a flash memory according to the rewriting instruction of the second storage area of the flash memory only when protected data are correct. SOLUTION: At the time of rewriting the program instruction of an address area A of a flash memory 9 according to the decoded result of the rewriting instruction of an address area B of the flash memory 9, an on-board signal OB is always turned into a logical value '1'. Therefore, when protected data are not used, a protected data identifying circuit 16 outputs a logical value '0', and a page buffer 14 stores 128 word program data, and a control signal WRT is risen so that the flash memory 9 can be turned into a writing inhibiting state. Therefore, only when the protected data are correct, the flash memory 9 can be turned into the writing allowable state.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer having a built-in non-volatile memory (flash memory) having characteristics capable of collectively or partially erasing data and writing / reading data.

[0002]

2. Description of the Related Art FIG. 9 is a block diagram showing a flash memory device, which is built in a microcomputer and functions. In FIG. 9, reference numeral (1) denotes a flash memory, which collectively or partially stores data (for example, page (1)
28 words), and has a nonvolatile property of repeatedly writing and reading data. The flash memory (1) functions as a program memory of the microcomputer. The internal cells of the address area A store program instructions for executing various logical operations, and the internal cells of the address area B store the program of the address area A. A rewrite instruction for rewriting the instruction is stored. The flash memory (1) normally jumps from the address area A so that the address area A is designated and the address area B is designated only when an interrupt request for rewriting the program contents of the address area A is generated. The microcomputer executes various logical operations in accordance with the result of decoding the program instruction read from the address area A of the flash memory (1), while the microcomputer executes the rewrite instruction read from the address area B of the flash memory (1). The rewriting operation of the contents of the address area A is executed in accordance with the result of decryption. The rewrite data in the address area A of the flash memory (1) is prepared in advance in the microcomputer (eg, a mask ROM is separately provided and stored as table data) or supplied from outside the microcomputer. Any method (such as a method of supplying from a PROM writer) may be used.

An address decoder (2) decodes address data for addressing the flash memory (1). Reference numeral (3) denotes a detection circuit for preventing a problem that the program instruction in the address area A of the flash memory (1) is erroneously rewritten against the user's intention. Specifically, the detection circuit (3)
It includes a plurality of registers (4) and a decoder (5). The plurality of registers (4) store protection data (AAH, 55H, etc.) prepared in advance by the user before rewriting the program instruction (in page units) of the address area A of the flash memory (2). Things. The decoder (5) decodes whether the values of the plurality of registers (4) are values intended by the user, and rewrites the flash memory (1) if all the values of the plurality of registers (4) are correct. The logic structure is such that the operation is permitted, and the rewriting operation of the flash memory (1) is prohibited if at least one of the values of the plurality of registers (4) is incorrect. (6) is a page buffer (volatile memory such as static RAM)
And has a storage capacity of 128 words for rewriting the program instruction in the address area A of the flash memory (1) in units of one page. The page buffer (6) has an increment function for addressing itself. The rewrite data is temporarily stored in the page buffer (6), and then stored in the address area A of the flash memory (1).
Is written to the specified page.

[0004]

A method for rewriting a program instruction in the address area A of the flash memory (1) includes an external control method using a PROM writer and an internal control method using a rewrite instruction for the address area B in the flash memory (1). A method is conceivable. Here, the flash memory (1) has, in addition to the internal cells in the address area A and the address area B, a protection cell (7) for determining whether protection data is necessary. The protection cell (7) may be 1 bit. The detection circuit (3) is controlled according to the value of the protection cell (7). That is, the detection circuit (3) includes the protection cell (7)
Is a logical value "0" (reset state), a signal for permitting the rewriting operation of the address area A of the flash memory (1) is output regardless of the presence or absence of the protection data. On the other hand, when the content of the protection cell (7) is a logical value "1" (set state) and the protection data does not exist, the detection circuit (3) performs the rewriting operation of the address area A of the flash memory (1). Forbidden, and only when the protected data exists and is correct, the rewriting operation of the address area A of the flash memory (1) is permitted.

In the case of the former external control method using a PROM writer, a logic value "0" or a logic value "1" is stored in a protection cell (7) while the operation of the microcomputer is stopped, and the protection data is stored. Can be selected. For example, a PROM writer prepares fixed protection data in advance, and if the PROM writer supplies the protection data to two different microcomputers, only one of the microcomputers may recognize the protection data. . Therefore, when it is desired to always maintain compatibility between the PROM writer and the various microcomputers, the logic value "0" may be stored in the protection cell (7). As a result, the detection circuit (3) operates the flash memory (1) regardless of the existence and state of the protection data.
Rewriting operation of the address area A is permitted. That is, the compatibility is the main factor that enables the selection of the necessity of protected data. PROM writer is a flash memory (1)
Of the address area A, the program instruction of 128 words to be rewritten is supplied to the page buffer (6),
After that, the address data of the page unit to be rewritten in the address area A of the flash memory (1) is sequentially supplied to the address decoder (2). Therefore, the contents of the page buffer (6) are written to the designated page in the address area A of the flash memory (1), and the rewrite operation ends.

In the case of the latter internal control method using a rewrite instruction of the address area B of the flash memory (1), it has not been possible to control the contents of the protection cell (7) conventionally. Specifically, the address area A of the flash memory (1) is rewritten in the initial state (normally the reset state) of the protection cell (7) or in the protection cell (7) after external control using a PROM writer. Depending on one of the states. In the case of the latter internal control method, it is not necessary to have compatibility with other microcomputers, so it is preferable to use protected data for preventing erroneous writing. However, if the logic value "0" is stored in the protection cell (7) contrary to the user's intention, when the rewriting operation is executed in accordance with the result of decoding the rewriting instruction, the protection data is run out due to the runaway of the program processing. Is set in the register (4) in an erroneous state, the program instruction in the address area A is rewritten. As a result, the program instruction in the address area A cannot be correctly rewritten.

Therefore, the present invention relates to a second nonvolatile memory.
An object of the present invention is to allow a rewrite operation to be permitted only when protected data is correct when rewriting a program instruction in a first storage area using a rewrite instruction for a storage area.

[0008]

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has a characteristic that data can be collectively or partially electrically erased and data can be written and read. A nonvolatile memory in which program instructions for executing various logical operations are stored in a first storage area, and a rewrite instruction for rewriting the contents of the first storage area are stored in a second storage area; A register in which protection data for preventing erroneous rewriting of the first storage area is set, a decoder for decoding a value of the register and permitting or prohibiting rewriting of the first storage area of the nonvolatile memory according to a result of the decoding; When rewriting a program instruction in a first storage area using a rewrite instruction in a second storage area of the nonvolatile memory, If the correct protection data to serial register is set only, characterized in that a means for permitting a rewriting of the first storage area of the nonvolatile memory.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be specifically described with reference to the drawings. FIG. 1 is a circuit block diagram showing a microcomputer of the present invention. In FIG. 1, reference numeral (8) denotes a clock generator to which an oscillation clock of an oscillation circuit (which may be either free-running oscillation provided with an oscillator such as crystal or ceramic or other free-running oscillation) is supplied. It is to generate a system clock for performing various logical operations by performing logical processing such as a round.

A flash memory (non-volatile memory) (9) has a non-volatile characteristic in which data can be electrically erased collectively or partially (for example, in units of pages (128 words)) and data can be repeatedly written and read. . The flash memory (9) functions as a program memory of the microcomputer. The internal cells of the address area A store program instructions for executing various logical operations, and the internal cells of the address area B store the program of the address area A. A rewrite instruction for rewriting the instruction is stored. The flash memory (9) normally jumps from the address area A so that the address area A is designated and the address area B is designated only when an interrupt request for rewriting the program content of the address area A is generated. The microcomputer executes various logical operation operations according to the result of decoding the program instruction read from the address area A of the flash memory (9), and on the other hand, the rewrite instruction read from the address area B of the flash memory (9). The rewriting operation of the contents of the address area A is executed in accordance with the result of decryption. The rewrite data in the address area A of the flash memory (9) is prepared in advance in the microcomputer (eg, a mask ROM is separately provided and stored as table data) or supplied from outside the microcomputer. Any method (such as a method of supplying from a PROM writer) may be used.

The flash memory (9) includes the following peripheral circuits in addition to the data storage internal cells. An address decoder (10) decodes address data (m bits) for addressing the flash memory (9). (11) is a detection circuit for preventing a problem that the program instruction in the address area A of the flash memory (9) is erroneously rewritten against the user's intention. Specifically, the detection circuit (11) includes a plurality of registers (12) and a decoder (13). The plurality of registers (12) store protection data (AAH, 55H, etc.) prepared in advance by the user before rewriting the program instruction (in page units) of the address area A of the flash memory (9). Things. The decoder (13) decodes whether the value of the plurality of registers (12) is a value intended by the user, and decodes the plurality of registers (1).
If all values of 2) are correct, flash memory (9)
The rewriting operation of the flash memory (9) is prohibited, and the rewriting operation of the flash memory (9) is prohibited if at least one of the values of the plurality of registers (12) is incorrect.
Reference numeral (14) denotes a page buffer (volatile memory such as a static RAM), which has a storage capacity of 128 words for rewriting a program instruction in the address area A of the flash memory (9) in units of one page. The page buffer (14) has an increment function for addressing itself. The rewrite data is temporarily stored in the page buffer (14) and then stored in the flash memory (9).
Is written to the designated page in the address area A of the first address.

Reference numeral (15) denotes a protection cell which stores a logical value "0" or a logical value "1" in accordance with a control instruction of the PROM writer when rewriting the program instruction of the address area A using the PROM writer. It is. When the protection cell (15) has a logical value “0” (reset state),
The detection circuit (11) sets the flash memory (9) to a rewrite permission state regardless of the presence or absence of protection data for preventing erroneous writing to the address area A. On the other hand, when the protection cell (15) has the logical value "1" (set state), the detection circuit (11) sets the flash memory (9) to the rewrite permission state only when the protection data exists and is correct.

(16) is a protection data identification circuit, and when protection data is set in a plurality of registers (12),
It outputs a logical value "1". Here, C
The PU outputs an on-board signal OB having a logical value "1" when rewriting the program instruction in the address area A using the rewrite instruction in the address area B of the flash memory (9). Protection cell (15) value and on-board signal O
B is supplied to a NOR gate (17). That is, when the value of the protection cell (15) is a logical value "0", the output of the NOR gate (17) changes according to the value of the on-board signal OB. Further, the value of the protected data identification circuit (16) and the NO
The output logic value of the R gate (17) is the NOR gate (18)
Supplied to That is, when the value of the protection cell (15) or the on-board signal OB is a logical value "1", the NOR gate (1
The output of 8) changes according to the value of the protection data identification circuit (16). In the D-type flip-flop (19), the page buffer (14) stores the program instruction of one page unit after the flash memory (9) is in a write operation enabled state according to the result of decoding the values of the plurality of registers (12). In synchronization with the clock CLK2 generated immediately after
This holds the output logic value of the gate (19).

A control circuit (20) operates in accordance with the result of decoding the program instruction in the address area A of the flash memory (9), and supplies an operation enable signal * CE and a write enable signal * WE to the flash memory (9). , A read enable signal * OE, a write inhibit signal WI, and a write end signal EOW. (21) is an identification circuit, which includes an operation permission signal * CE and a write permission signal * W
The logic value "1" is output in synchronization with the fall of E. An output logical value of the D-type flip-flop (19),
The write inhibit signal WI and the write end signal EOW are OR
It is supplied to a gate (22). (25) is an RS-type flip-flop composed of NOR gates (23) and (24), and the output logic value of the identification circuit (21) is NOR gate (2).
3) supplied to one input terminal (set terminal)
The output logical value of the gate (22) is supplied to one input terminal (reset terminal) of the NOR gate (24), and the control signal WRT for enabling the internal cell in the address area A of the flash memory (9) to be in a writable state. Is output. More specifically, the control signal WRT rises when the value of the identification circuit (21) becomes a logical value "1", and is one of the value of the D-type flip-flop (19), the write inhibit signal WI, and the write end signal EOW. One falls when the logical value becomes “1”. The control signal WRT is set to high active. FIG. 2 is a time chart showing the relative relationship among the operation permission signal * CE, the write permission signal * WE, the read permission signal * OE, and the write prohibition signal WI. The write inhibit signal WI is generated after a lapse of a predetermined time from the change of the operation enable signal * CE and the write enable signal * WE to the low level in accordance with the result of decoding the rewrite instruction of the address area B of the flash memory (9). Specifically, the write inhibit signal WI includes an operation enable signal * CE and a write enable signal *
Immediately after WE changes to high level, the operation permission signal * C
This occurs between the time when E and the read enable signal * OE change to low level.

The control circuit (20) includes a flag (26). The flag (26) is set so that the forcible setting signal PL for forcibly setting the flash memory (9) to the writable state regardless of the state of the control signal WRT corresponds to the instruction for rewriting the address area B of the flash memory (9). This is set according to the decoding result. The flag (26) indicates the falling WRTDOWN of the control signal WRT at the time when writing from the page buffer (14) to the address area A is completed.
It is reset according to N. The control signal WRT and the forcible setting signal PL are supplied to the detection circuit (1) via the OR gate (27).
A plurality of registers (5) supplied to the reset terminal of (1)
Is reset when the output of the OR gate (27) changes to a low level. As an effect of the forced setting signal PL, since the values of the plurality of registers (12) are not reset even when the control signal WRT falls, the detection circuit (11)
Can reliably detect whether the protected data is correct or not.

Reference numeral (28) denotes a CPU which executes various logical operation operations in accordance with the result of decoding the instructions read from the address areas A and B of the flash memory (9), and includes ALU, ACC, various registers and the like. including. (29)
Is a program counter, and a flash memory (9)
To generate address data (m bits) for specifying the address. The program counter (29)
Used when reading an instruction from the flash memory (9). Reference numeral (30) denotes m latch circuits, which designate a partial area of the address area A generated by the CPU (28) according to the result of decoding the rewrite instruction read from the address area B of the flash memory (9). Address data (m bits) is latched in synchronization with the clock CK0. Similarly, (31) is an n number of latch circuits, and new program data (n bits) for rewriting the address area A of the flash memory (9) is clocked by the clock C.
It latches in synchronization with K1. Latch circuit (3
0) and (31) are used when rewriting the program instruction in the address area A of the flash memory (9). AN
The switching circuit including the D gates (32) and (33) and the OR gate (34) switches and outputs one of the address data of the program counter (29) and the latch circuit (30) to the flash memory (9). is there. (35)
Is a selection circuit for supplying a selection signal SELECT for instructing the switching circuit to switch address data. That is, the selection signal SELECT goes high when the value of the program counter (29) is supplied to the flash memory (9), and goes low when the value of the latch circuit (30) is supplied to the flash memory (9). Address data switched and output from the switching circuit is supplied to an address decoder (10) for addressing the flash memory (9), and is also supplied to a detection circuit (11) for selecting a plurality of registers (12). Supplied, the address decoder (10) and the detection circuit (11)
There is no problem because the simultaneous operation cannot be performed. Program data output from the latch circuit (31) is supplied to a plurality of registers (12) and a page buffer (14).

When the CPU (28) rewrites the program instruction in the address area A using the rewrite instruction in the address area B of the flash memory (9), it outputs a high-level on-board signal OB and outputs the high-level on-board signal OB. ) Is supplied to the NOR gate (17). First, PR
A case will be described in which the OM writer is used to rewrite the program instruction in the address area A of the flash memory (9).

FIG. 3 is a time chart showing the operation when resetting the protection cell (15) and supplying the protection data. While the operation of the microcomputer is stopped, various signals are supplied from the PROM writer to the flash memory (9). When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the setting of the RS flip-flop (25), and the internal cells in the address area A of the flash memory (9) become in a writable state. Become. The protection data is set in the register (12) in synchronization with the change of the operation permission signal * CE and the write permission signal * WE. The protection cell (1
Since the value of 5) is a logical value "0", the protected data identification circuit (1
Regardless of the output of 6), the D-type flip-flop (19)
Is a logical value "0". Further, no write inhibit signal WI is generated. Therefore, when the write end signal EOW is generated, the control signal WRT falls with the reset of the RS flip-flop (25). In other words, the control signal WRT remains at the high level after the first operation enable signal * CE and the write enable signal * WE are generated until the write end signal EOW is generated. Register (1
When the protection data setting for 2) and the storage of the 128-word program data in the page buffer (14) are completed, an erase signal ERASE is generated, and the contents of the page to be rewritten in the address area A of the flash memory (9) are erased. , A write signal PROGRAM is generated, and the contents of the page buffer (14) are written to the address area A of the flash memory (9). Here, when the write signal PROGRAM rises, the protection cell (15) becomes a logical value "1". That is, in order to execute rewriting of the address area A of the flash memory (9) in the future, protection data will be required. When the write signal PROGRAM falls, the write end signal E
OW occurs. That is, the RS flip-flop (2
With the reset of 5), the control signal WRT falls.

FIG. 4 is a time chart showing an operation when the protection cell (15) is reset and protection data is not supplied. With the operation of the microcomputer stopped, the flash memory (9) is read from the PROM writer.
Supply various signals to When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises in accordance with the setting of the RS flip-flop (25), and the internal cells in the address area A of the flash memory (9) become in a writable state. Become. In addition, the protection cell (15)
Is the logical value "0", the protected data identification circuit (16)
, The input of the D-type flip-flop (19) has the logical value "0". Also, the write inhibit signal WI
Does not occur. Therefore, when the write end signal EOW is generated, the control signal WRT falls with the reset of the RS flip-flop (25). In other words, the control signal WRT remains at the high level after the first operation enable signal * CE and the write enable signal * WE are generated until the write end signal EOW is generated. Page buffer (1
When the storage of the 128-word program data for 4) is completed, an erase signal ERASE is generated, the contents of the page to be rewritten in the address area A of the flash memory (9) are erased, a write signal PROGRAM is generated, and the page buffer ( The content of 14) is written to the address area A of the flash memory (9). Here, the value of the protection cell (15) remains at the logical value “0”. When the write signal PROGRAM falls, a write end signal EOW is generated. That is, the control signal WRT falls with the reset of the RS flip-flop (25).

FIG. 5 shows the setting of the protection cell (15),
9 is a time chart illustrating an operation when supplying protection data. While the operation of the microcomputer is stopped, various signals are supplied from the PROM writer to the flash memory (9). When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises with the setting of the RS flip-flop (25),
The internal cells in the address area A of the flash memory (9) are in a writable state. Protected data is an operation enable signal *
It is set in the register (12) in synchronization with the change of the CE and the write enable signal * WE. In addition, the protection cell (15)
Is a logical value “1”, the D-type flip-flop (1
The input of 9) depends on the output of the protected data identification circuit (16). That is, since the output of the protection data identification circuit (16) has the logical value "1", the input of the D-type flip-flop (19) has the logical value "0". Further, no write inhibit signal WI is generated. Therefore, when the write end signal EOW is generated, the control signal WRT falls for the first time due to the reset of the RS flip-flop (25). In other words, the control signal WRT remains at the high level after the first operation enable signal * CE and the write enable signal * WE are generated until the write end signal EOW is generated. If the result of decoding the protected data is correct, the write operation of the flash memory (9) is permitted, and the page buffer (14) stores 128 words of program data. Thereafter, an erase signal ERASE is generated, and the contents of the page to be rewritten in the address area A of the flash memory (9) are erased. Thereafter, a write signal PROGRAM is generated, and the contents of the page buffer (14) are written to the address area A of the flash memory (9). Write signal PROGRA
When M falls, a write end signal EOW is generated, and the control signal WRT falls with the reset of the RS flip-flop (25).

FIG. 6 shows the setting of the protection cell (15),
6 is a time chart illustrating an operation when protection data is not supplied. While the operation of the microcomputer is stopped, various signals are supplied from the PROM writer to the flash memory (9). When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises with the setting of the RS flip-flop (25),
The internal cells in the address area A of the flash memory (9) are in a writable state. Since the value of the protection cell (15) is a logical value "1", the input of the D-type flip-flop (19) depends on the output of the protection data identification circuit (16).
That is, since the output of the protection data identification circuit (16) has the logical value "0", the input of the D-type flip-flop (19) has the logical value "1". Further, no write inhibit signal WI is generated. Therefore, a predetermined time (for example, 300 μsec) from the end of the data storage operation to the page buffer (14)
The D-type flip-flop (19) holds the logical value "1" in synchronization with the clock CLK2 generated after the elapse. That is, the control signal WRT falls with the reset of the RS flip-flop (25), and the write operation of the flash memory (9) is prohibited.

Next, a case in which a program instruction in the address area A is rewritten by using a rewrite instruction in the address area B of the flash memory (9) will be described. FIG. 7 is a time chart showing an operation when supplying protection data. Microcomputer is flash memory (9)
During execution of various logical operations in accordance with the result of decoding the program instruction in the address area A, when an interrupt request for rewriting the program instruction in the address area A occurs, the value of the program counter (29) changes from the address area A to Jump to address area B. Then, the microcomputer starts the rewriting operation in accordance with the result of decoding the rewriting instruction in the address area B. At this time, CPU
(28) constantly outputs the on-board signal OB having the logical value "1". Operation enable signal * CE and write enable signal * W
When E falls, the control signal WRT rises with the setting of the RS flip-flop (25), and the internal cells in the address area A of the flash memory (9) are in a writable state. The protection data is stored in the register (1) in synchronization with the change of the operation permission signal * CE and the write permission signal * WE.
Set to 2). Since the on-board signal OB has the logical value "1", the input of the D-type flip-flop (19) depends on the output of the protection data identification circuit (16). That is, since the output of the protection data identification circuit (16) is a logical value "1",
The input of the D-type flip-flop (19) has a logical value "0". The write prohibition signal WI is generated at periodic intervals until the storage in the page buffer (14) is completed. However, since the forcible setting signal PL has the logical value "1", there is no problem in reading the register (12). If the decryption result of the protected data is correct, an erase signal ERASE is generated,
The contents of the page to be rewritten in the address area A of the flash memory (9) are erased. After that, the write signal P
ROGRAM is generated, and the operation permission signal * CE and the write permission signal * WE are synchronized with the fall of the control signal WR.
T rises, and the contents of the page buffer (14) are written to the address area A of the flash memory (9).
When the write signal PROGRAM falls, a write end signal EOW is generated, so that the control signal WRT falls with the reset of the RS flip-flop (25).

FIG. 8 is a time chart showing the operation when no protection data is supplied. When the microcomputer is performing various logical operations in accordance with the result of decoding the program instruction in the address area A of the flash memory (9), when an interrupt request for rewriting the program instruction in the address area A occurs, the program counter (2)
The value of 9) jumps from the address area A to the address area B. Then, the microcomputer starts the rewriting operation in accordance with the result of decoding the rewriting instruction in the address area B. At this time, the CPU (28) constantly outputs the on-board signal OB having the logical value "1". When the operation permission signal * CE and the write permission signal * WE fall, the control signal WRT rises with the setting of the RS flip-flop (25), and the address area A of the flash memory (9).
Are in a writable state. The protection data is set in the register (12) in synchronization with the change of the operation permission signal * CE and the write permission signal * WE. Since the on-board signal OB has the logical value "1", the input of the D-type flip-flop (19) depends on the output of the protection data identification circuit (16). That is, since the output of the protection data identification circuit (16) has the logical value "0", the input of the D-type flip-flop (19) has the logical value "1". Also, the write inhibit signal W
I occurs at a periodic interval until the storage in the page buffer (14) is completed. However, since the forcible setting signal PL has the logical value "1", there is no problem in decoding the register (12). Then, the D-type flip-flop (19) holds the logical value “1” in synchronization with the clock CLK2 generated after a predetermined time (for example, 300 μsec) has elapsed from the end of the data storage operation to the page buffer (14). That is, when the RS flip-flop (25) is reset, the control signal W
RT falls, and the write operation of the flash memory (9) is prohibited.

As described above, according to the embodiment of the present invention,
When rewriting the program instruction in the address area A using the rewrite instruction in the address area B of the flash memory (9), regardless of the state of the protection cell (15), the flash memory (9) is used only when the result of decoding the protected data is correct. ) Is allowed to be rewritten. Therefore, when the program processing of the microcomputer runs away and the protection data is erroneous, the rewriting operation of the address area A of the flash memory (9) can be reliably inhibited.

[0025]

According to the present invention, the second nonvolatile memory can be used.
When rewriting the program instruction of the first storage area using the rewrite instruction of the storage area, the rewrite operation of the nonvolatile memory is permitted only when the result of decoding the protected data is correct, regardless of the state of the protection cell. Therefore, when the program processing of the microcomputer runs away and the protection data is erroneous, an advantage is obtained that the rewriting operation of the first storage area of the nonvolatile memory can be reliably inhibited.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram showing a microcomputer of the present invention.

FIG. 2 is a time chart showing a relative relationship between waveforms.

FIG. 3 is a time chart showing an operation in a case where protection data is used in a state where a protection cell is reset using a PROM writer.

FIG. 4 is a time chart showing an operation in a case where protection data is not used in a state where a protection cell is reset using a PROM writer.

FIG. 5 is a time chart showing an operation in a case where protection data is used with a protection cell set using a PROM writer.

FIG. 6 is a time chart showing an operation when protection data is not used in a state where a protection cell is set using a PROM writer.

FIG. 7 is a time chart showing an operation in a case where protection data is used by using a rewrite instruction of an address area B of a flash memory.

FIG. 8 is a time chart showing an operation in the case where a rewrite instruction for an address area B of a flash memory is used and protection data is not used.

FIG. 9 is a block diagram showing a conventional flash memory device.

[Explanation of symbols]

 (9) Flash memory (12) Register (13) Decoder (14) Page buffer (15) Protecting cell (28) CPU

Claims (1)

[Claims] 1. It has a characteristic that data can be collectively or partially electrically erased, and data can be written and read,
A nonvolatile memory in which program instructions for executing various logical operations are stored in a first storage area, and a rewrite instruction for rewriting the contents of the first storage area are stored in a second storage area; A register in which protection data for preventing erroneous rewriting of the first storage area is set, a decoder for decoding a value of the register and permitting or prohibiting rewriting of the first storage area of the nonvolatile memory according to a result of the decoding; When rewriting the program instruction of the first storage area using the rewrite instruction of the second storage area of the nonvolatile memory, only when correct protection data is set in the register, the microcomputer of the nonvolatile memory A microcomputer provided with means for permitting rewriting of the first storage area.