JPH11328089A - Id information write circuit in device for pci bus interface - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a circuit which can set arbitrary ID information to a device for PCI interface. SOLUTION: A means is provided, which reads out and sets ID information to registers, where a device ID 7, a vendor ID 8, a sub-system ID 9, a sub-system vendor ID 10, etc., in a device for PCI bus interface, are stored, from a storage means before the start of a configuration cycle of a PCI interface from a host. The host recognizes the ID information set as aforementioned in the configuration cycle of the PCI interface 2. An ID write register 13 which sets each ID information through the PCI interface 2 and a means which performs the control to store a value in a prescribed area of the said storage means at the time of setting this value to the ID write register 13 are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control method for an input / output device in an information processing apparatus, and more particularly to an ID information writing circuit in a device for a PCI bus interface.

[0002]

2. Description of the Related Art PCI (periheral component intercon
nect) Configuration on the bus (configur
ation: Configuration) Register device I
D, a vendor ID, a subsystem ID, and a subsystem vendor ID are configured such that values initially set in a PCI bus LSI are read out during a configuration cycle of a PCI interface of a computer such as a personal computer. A device connected to the PCI bus has a configuration register for setting the characteristics, type, operation mode, and the like of the device. An address space for accessing the register group is a configuration address space. A PCI bus cycle for accessing the address space is called a configuration bus cycle.

[0003]

The initial value is limited to one, or the number of settings is limited by the terminal setting, and it is impossible to change the ID setting after LSI development. Met.

For this reason, a plurality of arbitrary I
It was impossible to have a D.

Therefore, the present invention has been made in view of the above-mentioned problems, and its object is to carry out before the start of the configuration cycle of the PCI interface, and to provide a device ID, a vendor ID, and a subsystem ID.
D. An object of the present invention is to provide an ID number writing circuit that enables a single device to have a plurality of IDs by easily changing a subsystem vendor ID or the like.

[0006]

In order to achieve the above object, in a device in which a register storing device-specific information is accessed from a computer via a bus interface in a predetermined bus cycle, the device may be provided with a bus interface before the start of the bus cycle. Means for reading the unique information stored in the storage means and setting the read information in the register, so that the value of the set register is recognized in the bus cycle. According to the present invention, there is provided means for writing the unique information received from the computer into the storage means.

[0007]

Embodiments of the present invention will be described below. In a preferred embodiment of the present invention, the PCI interface device is provided with a vendor ID, a subsystem I and a sub system I in the PCI bus interface device before the configuration cycle of the PCI interface from the host (personal computer) side starts.
D, means for reading and setting ID information to a register for storing each ID information such as a subsystem vendor ID, etc. from the storage means, and the host side stores the set ID information in the configuration cycle of the PCI interface. Recognize on the side. That is, referring to FIG. 1, before the PCI interface (2) of the computer such as a personal computer starts the configuration cycle with respect to the configuration register (3), the CPU (4), the memory (5), and the decoder (6). ), The device ID register (7), the vendor ID register (8), the subsystem ID register (9), and the subsystem vendor ID register (1) of the configuration register (3).
An arbitrary ID number is written in 0). Host PCI
The configuration cycle is started by the interface (2), and the device ID, the vendor ID,
When the subsystem ID and the subsystem vendor ID are recognized by the personal computer, the above-described arbitrary ID is recognized.

[0008] Further, in an embodiment of the present invention,
An ID for setting each ID information of the PCI interface device from the host via the PCI interface
A register for writing D is provided, and when a value is set in the register for writing ID, there is provided means for controlling so as to store the set value in a predetermined area of the storage means.

As described above, in the embodiment of the present invention, writing of the device ID, the vendor ID, the subsystem ID, the subsystem vendor ID, and the like in the PCI bus interface device is performed by the PC of the computer.
It is possible to easily change the device ID, vendor ID, subsystem ID, subsystem vendor ID, etc., before the start of the configuration cycle of the I interface. It is possible.

[0010]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of the present invention; FIG. 1 is a diagram showing a configuration of an ID number writing circuit in a PCI bus interface device according to an embodiment of the present invention.

In FIG. 1, 1 is an ID number writing circuit, 2 is a PCI interface of a personal computer, 3 is a configuration register, 4 is a CPU, 5 is a memory, 6 is a decoder, 7, 8, 9, and 10 are configurations. A register for device ID, a register for vendor ID, a register for subsystem ID, a register for subsystem ID, and a register for subsystem vendor ID, which are readable / writable registers among the registers 5, are shown.

Reference numeral 12 denotes an I / O of the ID number writing circuit 3.
An O address 13 is an ID setting register in the I / O address of the ID number writing circuit 3.

21 is a PCI bus, 22 is an address bus,
23 is a data bus, 24 is an interrupt signal, and 31 to 35 are selection signals.

The PCI interface 2 of the personal computer is connected to the configuration register 3 via a PCI bus 21. The device ID register 7, the vendor ID register 8, the subsystem ID register 9, and the subsystem vendor ID register 10 in the configuration register 3 can be read through the PCI bus 21.

Also, a PCI interface 2 of a personal computer
Is connected to the ID setting register 13 in the I / O address 12 of the ID number writing circuit 3 by the PCI bus 21. Normal I / O of PCI interface 2
The personal computer can write to the ID setting register 13 by writing the O address.

The CPU 4 uses an address bus 22 to
The data bus 2 is connected to the memory 5 and the decoder 6.
3, the device ID register 7, the vendor ID register 8, the subsystem ID register 9, the subsystem vendor ID register 10 of the memory 5 and the configuration register 3, and the I / O address of the ID number writing circuit 3 ID setting register 1 in 12
3 respectively.

The decoder 6 decodes the address output from the CPU 6 and outputs selection signals 31 to 35. The selection signals 31 to 35 are the device ID register 7 in the configuration register 3 and the vendor I
It is connected to the D register 8, the subsystem ID register 9, the subsystem vendor ID register 10, and the ID setting register 13 in the I / O address 12.

The ID setting register 13 in the I / O address 12 is connected to the CPU 4 by an interrupt signal 24. The ID setting register 13 outputs an interrupt signal 24 to the CPU 4 when writing to the register is performed.

With the above-described configuration, the CPU 4 has the memory 5
Are stored in the device ID register 7 of the configuration register 3, the vendor ID register 8,
It can be written to the subsystem ID register 9 and the subsystem vendor ID register 10, and the I / O
The CPU 4 can read data written by the personal computer into the ID setting register 13 in the address 12 via the PCI interface 2 and write the data into the memory 5.

Next, the operation of one embodiment of the present invention will be described.

Referring to FIG. 1, before the PCI interface 2 of the personal computer instructs the configuration register 3 to start a configuration cycle, the CPU 4 controls the device 5 stored in the memory 5 as a part of the program. The data of the ID, the vendor ID, the subsystem ID, and the subsystem vendor ID are read. Next, the CPU 4 sequentially selects the device ID register 7, the vendor ID register 8, the subsystem ID register 9, and the subsystem vendor ID register 10 in the configuration register 3 via the decoder 6, and 5 is written.

The configuration cycle is started by the PCI interface 2 of the personal computer, and when the device ID, the vendor ID, the subsystem ID, and the subsystem vendor ID are recognized by the personal computer, the previously written IDs are recognized. You.

A flash memory (EEP) is used as an electrically writable and nonvolatile memory in the memory 5.
When the ROM is used, the data of the ID in the memory 5 can be rewritten.

The personal computer recognizes the ID setting register 13 in the I / O address 12 by the configuration cycle of the PCI bus. PC is PC
When the ID data is written to the ID setting register 13 in the I / O address 12 via the I interface 2,
An interrupt signal 24 is output to the CPU 4. CPU
4 confirms this interrupt, reads the data written in the ID setting register 13 in the I / O address 12 and writes the data in the ID area of the memory 5. By rewriting the ID in the memory 5 in this manner, when the personal computer starts up next time and performs a configuration cycle, the personal computer side performs a different ID.
Can be recognized.

[0025]

As described above, according to the present invention,
The device ID, the vendor ID, the subsystem ID, the subsystem vendor ID, and the like of the device for the PCI bus interface are written before the configuration cycle of the PCI interface of the personal computer starts, and the device ID, the vendor ID, and the subsystem I are written.
D, since it is possible to easily change the subsystem vendor ID, etc., the same device can have a plurality of IDs.

Therefore, according to the present invention, the same PCI
Even if a bus-compatible board is manufactured, the personal computer recognizes it as a different board by changing the ID at the time of shipment. Also, in the case where the personal computer recognizes the vendor ID and displays the company name, the present invention enables the display of the company name of the supply destination.

Further, according to the present invention, since the part storing the ID of the memory can be rewritten after the personal computer is started, the ID can be easily rewritten by the same program at the time of factory shipment. be able to.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of an embodiment of the present invention.

[Explanation of symbols]

 1 ID number writing circuit 2 PCI interface 3 Configuration register 4 CPU 5 Memory 6 Decoder 7 Device ID register 8 Vendor ID register 9 Subsystem ID register 10 Subsystem vendor ID register 12 I / O address 13 ID setting register 21 PCI bus 22 address bus 23 data bus 24 interrupt signal 31-35 selection signal

Claims (5)

[Claims] 1. A device in which a register for holding device-specific information is accessed in a predetermined bus cycle from a computer via a bus interface, wherein the device stores the unique information stored in a storage means before the start of the bus cycle. An ID information writing circuit comprising means for reading and setting the register, wherein the value of the set register is recognized on the computer side in the bus cycle. 2. An ID information writing circuit according to claim 1, further comprising means for writing the unique information received from said computer into said storage means. 3. The ID according to claim 1, wherein said register comprises a register of a device ID, a vendor ID, a subsystem ID, and a subsystem vendor ID of a configuration register in a PCI bus interface device. Information writing circuit. 4. A device for a PCI bus interface, wherein a vendor ID, a subsystem ID, and a subsystem vendor ID are included in configuration registers of the PCI bus interface device before a configuration cycle of the PCI interface from a host is started. Means for reading and setting ID information to a register holding each ID information from the storage means, and the host recognizes the ID information set to each register in a PCI interface configuration cycle. , An ID information writing circuit. 5. An ID writing register for setting each ID information from the host via the PCI interface, and a predetermined area of the storage means when a value is set in the ID writing register. 4. A means for controlling so as to store the value in the memory device.
D information writing circuit.