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JP2005057245A - Bump junction and electronic component - Google Patents

Bump junction and electronic component Download PDF

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Publication number
JP2005057245A
JP2005057245A JP2004151943A JP2004151943A JP2005057245A JP 2005057245 A JP2005057245 A JP 2005057245A JP 2004151943 A JP2004151943 A JP 2004151943A JP 2004151943 A JP2004151943 A JP 2004151943A JP 2005057245 A JP2005057245 A JP 2005057245A
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Prior art keywords
solder
gold
tin
zinc
layer
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Inventor
Izuru Komatsu
出 小松
Kimihiro Tadauchi
仁弘 忠内
Shinichi Nakamura
新一 中村
Hiroshi Funakura
寛 舩倉
Susumu Kamata
丞 鹿俣
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Toshiba Corp
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Toshiba Corp
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484Connecting portions
    • H01L2224/48463Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

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  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To use a tin-zinc solder, since it is impeded to form a weak intermetallic compound consisting of tin, gold and nickel by bonding zinc concentrating on a solder ball surface with nickel plating, thereby a mechanical reliability of a solder bump joint is improved. <P>SOLUTION: In place of a tin-lead solder constituting a former solder vamp, since a solder ball configured by a solder alloy which bases on tin and includes zinc is used, zinc layers concentrating on the solder ball surface participate with all bondings, thereby a reaction of the tin forming the weak intermetallic compound is impeded. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、錫亜鉛はんだ合金からなるバンプ接合体および電子部品に関する。   The present invention relates to a bump bonded body and an electronic component made of a tin-zinc solder alloy.

近年、電子機器の高機能化、小型化に伴い、使用される電子部品の高密度化、軽量化が求められるようになってきた。これまで主流であったSOPやQFPは、パッケージの両側面または四側面にリードが配置されていたが、側面長によってリード数が制限されてしまうため、リードを多ピン化するには限界があった。また微細ピッチや多ピンリードになると、リード間にはんだのブリッジが発生し、基板上へのマウント精度が問題になり技術的にも限界が見られる。   In recent years, with the increase in functionality and size of electronic devices, it has been required to increase the density and weight of electronic components used. SOP and QFP, which have been the mainstream until now, had leads arranged on both sides or four sides of the package. However, the number of leads is limited by the side length, so there is a limit to increasing the number of leads. It was. In addition, when a fine pitch or a multi-pin lead is used, a solder bridge is generated between the leads, and the mounting accuracy on the substrate becomes a problem, and there is a technical limit.

そこで最近では、リードを用いない接合方法であるBGA、CSP等が開発され、量産、使用され始めている。これらは、SOP、QFPのようにパッケージ側面に位置するリードによる接合ではなく、パッケージ裏面に格子状に配列するはんだボール等で電極と基板を接合するため、多ピン化、狭ピッチ化の点で有利となる。従って、これまで以上に高集積化された回路設計が可能となり、電子部品はより小型化されてきている。現在では、BGA、CSPに見られるバンプ接続法を用いた電子部品の需要は非常に高まっている。   Therefore, recently, BGA, CSP, and the like, which are bonding methods that do not use leads, have been developed, and are being mass-produced and used. These are not joined by leads located on the side of the package like SOP and QFP, but the electrodes and the substrate are joined by solder balls arranged in a lattice pattern on the back of the package, so that the number of pins and the pitch are reduced. It will be advantageous. Therefore, it is possible to design a circuit that is more highly integrated than ever before, and electronic components have become smaller. At present, the demand for electronic components using the bump connection method found in BGA and CSP is very high.

現在、錫鉛はんだボールを用いたBGAの製造工程において、BGAの電極部及び内部配線を構成する銅上にはニッケルめっきと金めっきが施されている。内部配線部分は、金ワイヤーによって集積回路とボンディングするため、内部配線上の金めっきの厚さは1μm程度を要する。従って、はんだボールを搭載する裏面の銅電極上にも、同様に1μm程度のめっきが施されている。   Currently, in the manufacturing process of a BGA using tin-lead solder balls, nickel plating and gold plating are applied on the copper constituting the BGA electrode portion and internal wiring. Since the internal wiring portion is bonded to the integrated circuit by a gold wire, the thickness of the gold plating on the internal wiring requires about 1 μm. Accordingly, the copper electrode on the back surface on which the solder balls are mounted is similarly plated with about 1 μm.

製造工程におけるはんだボールの搭載は、BGAパッケージが完成する最終工程である。ニッケルめっきと金めっきが施された銅電極上にフラックスを印刷し、その上にはんだボールをマウントして、リフローにより電極部とはんだボールの接合が行われる。リフロー後の電極部とはんだボールの接合界面は、リフローの際に金がはんだ中に拡散するため、実質的にははんだ表面の錫とめっきのニッケルが接合しており、この事象はよく知られている。   The mounting of solder balls in the manufacturing process is the final process for completing the BGA package. A flux is printed on a copper electrode on which nickel plating and gold plating have been applied, a solder ball is mounted thereon, and the electrode portion and the solder ball are joined by reflow. This phenomenon is well known at the joint between the electrode and solder ball after reflow because the gold diffuses into the solder during reflow, so the tin on the solder surface and the plated nickel are actually joined. ing.

特に、マザーボード基板にパッケージ類を実装する際に、基板上の電極部には金フラッシュ/ニッケルめっきされる場合があるが、金フラッシュめっき厚は0.1μm以下であるため、同様にはんだ中に拡散する金が問題になることはない。   In particular, when a package is mounted on a mother board, the electrode part on the board may be gold flash / nickel plated, but since the gold flash plating thickness is 0.1 μm or less, similarly in the solder Spreading gold is not a problem.

しかし、はんだボール搭載後にBGAの高温放置試験を行うと、試験時間や温度条件によっては破壊モードが異なって現われ、例えば錫とニッケルの界面にクラックが生じ破断することもあり、引張強度が大幅に低下する場合がある。これは、高温時効によって一度はんだ中に拡散していた金が錫とニッケルの接合界面に移動し、強度的に脆い、錫と金とニッケルの金属間化合物が形成したためと考えられている。   However, when the BGA is subjected to a high temperature standing test after mounting the solder balls, the fracture mode appears different depending on the test time and temperature conditions. For example, a crack may occur at the interface between tin and nickel, resulting in a significant increase in tensile strength. May decrease. This is presumably because gold once diffused in the solder due to high temperature aging moved to the joint interface between tin and nickel, and was brittle in strength, and an intermetallic compound of tin, gold and nickel was formed.

また、同様に電子部品の小型化に伴い内部配線も高密度化しており、集積回路と外部電極とを結ぶ金ワイヤーボンディングも、集積回路裏面の電極上に配置されたバンプを電気的導通に利用する、フリップチップ方式の内部接合形態が使用されるようになってきている。   Similarly, with the miniaturization of electronic components, the internal wiring has also been densified, and gold wire bonding that connects the integrated circuit and external electrodes also uses bumps arranged on the electrodes on the back of the integrated circuit for electrical conduction. Flip chip type internal bonding forms have been used.

フリップチップ方式にも様々な形態があるが、金−金、はんだ−金、はんだ−はんだ接合を利用する場合が多い。その中でも、集積回路裏面の電極上に形成した金バンプと基板電極上に形成したはんだを接合する方式は、金バンプがワイヤーボンド式で容易に形成可能な上、安価なはんだを利用できることもあり、使用範囲は広い。   There are various types of flip chip methods, but gold-gold, solder-gold, and solder-solder joints are often used. Among them, the method of joining the gold bump formed on the electrode on the back surface of the integrated circuit and the solder formed on the substrate electrode can easily form the gold bump by a wire bond type and can use an inexpensive solder. The range of use is wide.

しかし金が多量に存在するために、はんだバンプの場合と同様に、錫との接合界面或いは金層中に金と錫の金属間化合物が形成されることによって、接合は強度的に脆くなり、信頼性に問題が生じる場合がある。
特開平11−17321号公報
However, because of the large amount of gold, as in the case of solder bumps, the formation of an intermetallic compound of gold and tin in the bonding interface with gold or in the gold layer makes the bonding brittle in strength. There may be problems with reliability.
Japanese Patent Laid-Open No. 11-17321

従来のはんだボールは、高温時に一度はんだ中に拡散していた金が錫とニッケルの接合界面に移動し、錫と金とニッケルの強度的に脆い金属間化合物が形成されるため、強度の低下を引き起こす問題があった。   In conventional solder balls, the gold once diffused into the solder at high temperature moves to the joint interface between tin and nickel, and a strong brittle intermetallic compound of tin, gold and nickel is formed. There was a problem causing.

また、フリップチップ方式の金バンプと錫鉛はんだとの接合においては、金と錫の強度的に脆い金属間化合物が形成されるため、同様に強度の低下を引き起こす問題があった。   Further, in the bonding between the flip-chip gold bump and tin-lead solder, there is a problem in that the strength is similarly lowered because a brittle intermetallic compound of gold and tin is formed.

本発明は、従来使用されていた錫鉛はんだに代えて、錫亜鉛はんだ合金を金−はんだ接合に使用することにより、脆い金属間化合物の形成を阻害することで、錫鉛はんだが引き起こす接合力低下の問題を解決し、機械的接合力を向上させたバンプ接合体及び電子部品の提供を課題とする。   The present invention uses a tin-zinc solder alloy for gold-solder bonding in place of the conventionally used tin-lead solder, thereby inhibiting the formation of brittle intermetallic compounds, thereby causing the bonding force caused by tin-lead solder. It is an object of the present invention to provide a bump bonded body and an electronic component that solve the problem of decrease and improve the mechanical bonding force.

本発明のバンプ接合体は、表面に電極配線が形成された基板と、この電極配線上に形成された8wt%以上15wt%以下の亜鉛および残部が実質的に錫のはんだ合金のはんだ層と、このはんだ層上に形成された膜厚0.5μm以上250μm以下の金バンプとを有することを特徴とする。   The bump bonded body of the present invention comprises a substrate having an electrode wiring formed on the surface thereof, a solder layer of 8 wt% or more and 15 wt% or less of zinc formed on the electrode wiring and a solder layer of which the balance is substantially tin, And a gold bump having a thickness of 0.5 μm or more and 250 μm or less formed on the solder layer.

本発明の電子部品は、表面に電極配線が形成された基板と、この電極配線上に形成された8wt%以上15wt%以下の亜鉛および残部が実質的に錫のはんだ合金のはんだ層と、このはんだ層上に形成された膜厚0.5μm以上250μm以下の金バンプと、前記基板の裏面に形成される集積回路と、この集積回路と前記電極配線を電気的に接続する接続手段とを具備することを特徴とする。   The electronic component of the present invention includes a substrate having an electrode wiring formed on the surface thereof, a solder layer of 8 wt% or more and 15 wt% or less of zinc formed on the electrode wiring and a solder layer of which the balance is substantially tin, A gold bump having a thickness of 0.5 μm or more and 250 μm or less formed on the solder layer; an integrated circuit formed on the back surface of the substrate; and a connecting means for electrically connecting the integrated circuit and the electrode wiring. It is characterized by doing.

前記電極配線と前記金層の間にニッケル層が介在することが好ましい。  It is preferable that a nickel layer is interposed between the electrode wiring and the gold layer.

本発明は、従来使用されていた錫鉛はんだに代えて、錫亜鉛はんだ合金を金−はんだ接合に使用する事により、脆い金属間化合物の形成を防止することができ、機械的接合力を向上させたバンプ接合体及び
これを使用した電子部品を提供できる。
The present invention can prevent the formation of brittle intermetallic compounds by using tin-zinc solder alloy for gold-solder bonding instead of tin-lead solder that has been used in the past, and improve mechanical bonding strength. A bump bonded body and an electronic component using the bump bonded body can be provided.

本発明者らは、錫を基体とし亜鉛を含むはんだ合金からなる金−はんだ接合を使用することで、錫亜鉛はんだ表面に濃縮する亜鉛層が接合に関与し、金、錫及び場合によってニッケルとの脆い金属間化合物を形成する錫の反応性を阻害することを見出す事によって、本発明に至った。   The present inventors use a gold-solder joint made of a solder alloy containing tin as a base and containing zinc, whereby a zinc layer concentrated on the surface of the tin-zinc solder is involved in the joint, and gold, tin, and optionally nickel. The present invention has been found by inhibiting the reactivity of tin forming the brittle intermetallic compound.

本実施形態のはんだバンプは、亜鉛を3wt%〜15wt%含有し、その他は実質的に錫を主体とするはんだ合金に対して効果的である。ここで、主成分は錫であり、亜鉛、それ以外の第3成分の順に割合は少なくなる。また、この第3成分は、鉛、銀、ビスマス、銅、インジウム、アンチモン、ゲルマニウム、ニッケル、金、パラジウム、アルミニウム、その他の不可避の金属であり亜鉛よりも蒸気圧の低い金属を添加する場合、亜鉛がはんだの最表面に濃縮するため望ましいが、限定されるものではない。また、この第3成分はそれぞれ単独の量について5wt%以下、トータルでも7wt%以下であることが望ましい。また錫亜鉛はんだ中の酸素含有量は10ppm以下が望ましいが、30ppm以下であれば本実施形態の効果を確実に奏することができる。   The solder bump of this embodiment contains 3 wt% to 15 wt% of zinc, and the others are effective for a solder alloy that is substantially composed mainly of tin. Here, the main component is tin, and the ratio decreases in the order of zinc and other third components. In addition, this third component is lead, silver, bismuth, copper, indium, antimony, germanium, nickel, gold, palladium, aluminum, and other inevitable metals, and when adding a metal having a lower vapor pressure than zinc, Although zinc is desirable because it concentrates on the outermost surface of the solder, it is not limited. In addition, it is desirable that the third component is 5 wt% or less, and the total amount is 7 wt% or less for each amount. Further, the oxygen content in the tin-zinc solder is desirably 10 ppm or less, but if it is 30 ppm or less, the effect of the present embodiment can be reliably achieved.

通常はんだ合金を作成する場合、用いる各種金属を所定量溶融し、大気中又は不活性雰囲気中又は還元雰囲気中又は真空中等の雰囲気において鋳造するが、錫亜鉛はんだの場合は亜鉛が酸化し易いため不活性雰囲気中で鋳造している。錫亜鉛はんだは、溶融後冷却され固化する過程において錫よりも蒸気圧の高い亜鉛が最表面に濃縮層を形成し、中心部には錫相中に亜鉛相が分散する組織構造が形成されている。また、更に亜鉛は酸化し易いため最表面の濃縮層の更に最表面側に酸化亜鉛層を形成し、最終的に錫亜鉛はんだは大きく三層の組織構造になる。   Usually, when making a solder alloy, a predetermined amount of various metals to be used is melted and cast in the atmosphere, in an inert atmosphere, in a reducing atmosphere, or in an atmosphere such as a vacuum. However, in the case of tin-zinc solder, zinc is easily oxidized. Casting in an inert atmosphere. Tin-zinc solder has a structure in which zinc, which has a higher vapor pressure than tin, forms a concentrated layer on the outermost surface in the process of cooling and solidifying after melting, and a structure in which the zinc phase is dispersed in the tin phase is formed at the center. Yes. Further, since zinc is easily oxidized, a zinc oxide layer is further formed on the outermost surface side of the concentrated layer on the outermost surface. Finally, the tin-zinc solder has a large three-layer structure.

従って、錫亜鉛はんだ合金で作成したはんだバンプを、ニッケル/金めっきした銅パッド上に接合する際には、はんだバンプ表面に亜鉛層が濃縮するため、従来の錫鉛はんだにおいてはんだ最表面に存在していた錫の反応は抑制され、接合界面において錫と金からなる脆い金属間化合物は形成されることはない。この反応を抑制するためには、はんだ合金中に亜鉛が3wt%〜15wt%含有されていることが必要である。この場合、錫亜鉛はんだは必ずしもバンプ状でなくてもよく、板状でも同様である。同様の作用は錫・亜鉛はんだの層と金パンプとの接合領域についても同様に生じる。   Therefore, when solder bumps made of tin-zinc solder alloy are joined onto a nickel / gold plated copper pad, the zinc layer concentrates on the surface of the solder bumps, so it exists on the outermost solder surface of conventional tin-lead solder. The reaction of tin that has been performed is suppressed, and a brittle intermetallic compound composed of tin and gold is not formed at the bonding interface. In order to suppress this reaction, it is necessary that the solder alloy contains 3 wt% to 15 wt% of zinc. In this case, the tin-zinc solder does not necessarily have a bump shape, and the same applies to a plate shape. The same effect occurs in the joint region between the tin / zinc solder layer and the gold pump.

また、本実施形態において使用するはんだバンプの一例である錫亜鉛はんだボールはBGAのみに適合可能ではなく、これまで錫鉛はんだボールを使用していたCSP等のあらゆるボール型はんだ接合体デバイスに適合可能であり、またフリップチップボンディングのような内部配線の接合にも適合可能であり、その使用方法、或いはデバイス上へのはんだバンプの形成方法について限定されるものではない。   In addition, tin-zinc solder balls, which are examples of solder bumps used in this embodiment, are not compatible only with BGA, and are compatible with all ball-type solder joint devices such as CSP that have previously used tin-lead solder balls. It is also possible to adapt to internal wiring bonding such as flip chip bonding, and there is no limitation on the method of use or the method of forming solder bumps on the device.

また本実施形態において、接合に錫亜鉛はんだ中の亜鉛が直接関与することは、はんだとアルミニウムとの接合を容易にする大きなメリットもある。電子デバイス中でアルミニウムからなる内部配線を用いる際には、アルミニウムにはんだ付け困難な錫鉛はんだで接合を行うために、アルミニウム配線上にニッケル/金めっき等の表面処理を施す必要があるが、錫亜鉛はんだボールを適応することにより、必要であったアルミニウム上の表面処理が不要となる。更に化合物半導体の場合、金からなる配線がなされるため、表面処理を施さずに直接錫亜鉛はんだバンプを形成することが可能となり、接合信頼性の向上ばかりではなく、大幅にコストを削減でき、まためっき廃水処理による環境汚染の問題も解消できる。   In the present embodiment, the fact that zinc in the tin-zinc solder is directly involved in the joining also has a great merit of facilitating the joining of the solder and aluminum. When using internal wiring made of aluminum in an electronic device, it is necessary to perform surface treatment such as nickel / gold plating on the aluminum wiring in order to perform bonding with tin-lead solder that is difficult to solder to aluminum. By adapting the tin-zinc solder balls, the necessary surface treatment on the aluminum becomes unnecessary. Furthermore, in the case of compound semiconductors, since wiring made of gold is made, it becomes possible to directly form tin-zinc solder bumps without performing surface treatment, not only improving bonding reliability, but also drastically reducing costs, In addition, the problem of environmental pollution caused by plating wastewater treatment can be solved.

(参考例1)
図1は電子部品の断面図を示したものである。1ははんだバンプとして準備したボール状のはんだ、2はソルダレジスト、3はBT基板、4は半導体を形成母材とする集積回路(IC)、5は金リード線、6はモールド樹脂である。さらに、このはんだボール1の周辺部を拡大して説明したのが図2であり、7は金めっき層、8はニッケルめっき層、9は銅電極である。この銅電極は、配線としても機能し基板1の表面から裏面にまで延在して金リード線5と電気的に接続している。1は、はんだ(Sn91.0 wt %-Zn9.0 wt %)からなる直径500μmのボール状のはんだであるが、ボール状である必要はなく、場合によってピラミット状、円錐状、或いは円筒状など種種の形状を呈したバンプであれば良い。
(Reference Example 1)
FIG. 1 shows a cross-sectional view of an electronic component. 1 is a ball-shaped solder prepared as a solder bump, 2 is a solder resist, 3 is a BT substrate, 4 is an integrated circuit (IC) having a semiconductor as a base material, 5 is a gold lead wire, and 6 is a mold resin. Further, FIG. 2 is an enlarged view of the periphery of the solder ball 1, 7 is a gold plating layer, 8 is a nickel plating layer, and 9 is a copper electrode. The copper electrode also functions as a wiring and extends from the front surface to the back surface of the substrate 1 and is electrically connected to the gold lead wire 5. 1 is a ball-shaped solder having a diameter of 500 μm made of solder (Sn91.0 wt% -Zn9.0 wt%), but it is not necessary to be ball-shaped, and in some cases, pyramid-shaped, conical, cylindrical Any bump may be used as long as it has various shapes.

また、ここで使用したBT基板3は、ビルドアップ構造を持つ多層の樹脂系プリント配線板だが、場合によっては多層構造ではなく単層構造であり、或いは樹脂製ではなくセラミック系のプリント配線板である。BT基板3中の電極部材は銅からなり、その上に厚さ5μmのニッケルめっき層8を、更にその上に1μmの金めっき層7を形成している。このニッケルめっき層は必ずしも必要ではない。   The BT substrate 3 used here is a multilayer resin-based printed wiring board having a build-up structure, but in some cases it is not a multilayer structure but a single-layer structure, or a ceramic-based printed wiring board that is not made of resin. is there. The electrode member in the BT substrate 3 is made of copper, and a nickel plating layer 8 having a thickness of 5 μm is formed thereon, and a gold plating layer 7 having a thickness of 1 μm is further formed thereon. This nickel plating layer is not always necessary.

錫亜鉛はんだボール搭載BT基板3は、ニッケル/金めっき処理した銅電極9上にフラックスを塗布し、更に錫亜鉛はんだボール1をマウントして、大気中、230℃でリフローすることで製造した。ここでの金層は純金を含み50wt%以上金の部分を称している。この実施例では金層の金のピーク値は90wt%であった。   The tin-zinc solder ball mounting BT substrate 3 was manufactured by applying a flux on the nickel / gold plated copper electrode 9, mounting the tin-zinc solder ball 1, and reflowing at 230 ° C. in the atmosphere. The gold layer here refers to a gold part including pure gold of 50 wt% or more. In this example, the gold peak value of the gold layer was 90 wt%.

はんだボール1と銅電極9の接合の機械的信頼性を評価するため、高温放置試験を行った。条件は、大気中150℃でBGA実装基板を放置し、24時間毎に引張強度を測定した。その結果、96時間放置後には初期引張強度から変化は見られなかったが、120時間後には初期引張強度の97%、144時間後には95%となり、良好な結果が得られた。その結果を図3に示した。図3中で実線の黒丸は実施例1のシェア強度を示したもので、実線の黒三角印は比較として従来はんだ(Sn63.0 wt %-Pb37.0 wt %)の結果を示した。破壊モードは同じくバルク中で破壊しており、はんだボール接合部の機械的信頼性に問題はなかった。   In order to evaluate the mechanical reliability of the bonding between the solder ball 1 and the copper electrode 9, a high temperature storage test was performed. The condition was that the BGA mounting substrate was left at 150 ° C. in the atmosphere, and the tensile strength was measured every 24 hours. As a result, no change was observed from the initial tensile strength after being allowed to stand for 96 hours, but it was 97% of the initial tensile strength after 120 hours and 95% after 144 hours, and good results were obtained. The results are shown in FIG. In FIG. 3, the solid line black circles indicate the shear strength of Example 1, and the solid line black triangle marks indicate the results of conventional solder (Sn63.0 wt% -Pb 37.0 wt%) as a comparison. The failure mode was also broken in the bulk, and there was no problem in the mechanical reliability of the solder ball joint.

さらに、はんだボール中の亜鉛の組成を変えると共に金層の厚みを種種変化させた電子部品を作成し、同様の評価を行った結果を示したのが表1である。測定に際して、150℃において168時間経過後に引張強度を測定した。尚、初期引張強度は、いずれも錫鉛はんだと同等以上の結果を示した。  Further, Table 1 shows the results of the same evaluations made by changing the composition of zinc in the solder balls and changing the thickness of the gold layer. Upon measurement, the tensile strength was measured after 168 hours at 150 ° C. The initial tensile strength was the same or higher than that of tin-lead solder.

Figure 2005057245
Figure 2005057245

この表では、二重丸は144時間後には初期引張強度95%以上であった場合、一重丸は144時間後には初期引張強度95%未満、90%以上であった場合、バツ印はボンディング不良であった場合をそれぞれ示している。   In this table, if the double circle has an initial tensile strength of 95% or more after 144 hours, the single circle has an initial tensile strength of less than 95% and 90% or more after 144 hours, the cross mark indicates a bonding failure. Each case is shown.

以上の結果から、十分な実用強度である144時間後に初期引張強度95%以上を達成するにははんだバンプ中の亜鉛の組成は3wt%以上、15wt%以下であることが必要である。この場合には、金と錫の金属間化合物の生じる接合強度低下の問題を回避できることがわかった。さらに、金は0.5μm以上250μm以下であることが望ましい。これ以上金層の厚みが厚くなるとコスト的に不利になるばかりでなく、はんだバンプ中に多量の金が混在しはんだの優れた機械的特性が損なわれるという問題が生じ、また、少ない場合には金ボンディングで十分な接合を得ることができないと言う問題が生じるので望ましくない。   From the above results, in order to achieve an initial tensile strength of 95% or more after 144 hours, which is a sufficient practical strength, the composition of zinc in the solder bumps needs to be 3 wt% or more and 15 wt% or less. In this case, it was found that the problem of reduction in bonding strength caused by an intermetallic compound of gold and tin can be avoided. Furthermore, it is desirable that gold is 0.5 μm or more and 250 μm or less. If the gold layer is thicker than this, not only will the cost be disadvantageous, but there will be a problem that a large amount of gold will be mixed in the solder bumps and the excellent mechanical properties of the solder will be impaired. This is not desirable because there arises a problem that sufficient bonding cannot be obtained by gold bonding.

以上の参考例では、集積回路と基板を接続する接続手段として、金のワイヤーボンディングを使用したが、金バンプによって接続しても構わない。この場合には図2で示した構造をさらに採用することができる。
(実施例1)
この実施例は、参考例1の金層の代わりに金バンプを使用し、はんだボールの代わりにはんだ層を使用した点が異なる。図4に沿って実施例1を説明する。
In the above reference example, gold wire bonding is used as the connection means for connecting the integrated circuit and the substrate, but the connection may be made by gold bumps. In this case, the structure shown in FIG. 2 can be further employed.
(Example 1)
This embodiment differs in that gold bumps are used instead of the gold layer of Reference Example 1, and solder layers are used instead of solder balls. Example 1 will be described with reference to FIG.

図4はフリップチップ方式で接合したバンプ接合体の構造を持つ、電子部品内部の断面図を示したものである。10は半導体チップで、11のアルミニウムパッド電極を配した構造を持ち、ワイヤボンド用に設計されている。12はワイヤボンド法により形成された金バンプであるが、場合によってはめっき法等の他の方法で金バンプは形成される。また、金めっきの上に錫亜鉛はんだめっきを施し、リフローにより形成される金コア型の錫亜鉛はんだバンプを使用する場合も可能である。形状はボール状接合体であるが、ボール状である必要はなく、場合によってピラミット状、円錐状、或いは円筒状など種種の形状を呈したバンプでも構わない。この時の金バンプ12は、高さ50μm、幅75μmであった。3はBT基板で、BT基板3上に配置された9の銅電極には、5μmのニッケルめっき8と1μmの金めっき7が施されており、リフローソルダリング方式により、13のはんだ(Sn91.0 wt %-Zn9.0 wt %)を介し金バンプ12と接合している。   FIG. 4 is a cross-sectional view of the inside of an electronic component having a structure of a bump bonded body bonded by a flip chip method. A semiconductor chip 10 has a structure in which 11 aluminum pad electrodes are arranged and is designed for wire bonding. Reference numeral 12 denotes a gold bump formed by a wire bond method. In some cases, the gold bump is formed by another method such as a plating method. It is also possible to use a gold-core type tin-zinc solder bump that is formed by reflowing by applying tin-zinc solder plating on the gold plating. The shape is a ball-shaped joined body, but it is not necessary to be a ball shape, and may be a bump having various shapes such as a pyramid shape, a conical shape, or a cylindrical shape. At this time, the gold bump 12 had a height of 50 μm and a width of 75 μm. Reference numeral 3 denotes a BT substrate. The 9 copper electrodes arranged on the BT substrate 3 are provided with 5 μm nickel plating 8 and 1 μm gold plating 7, and 13 solder (Sn91. 0 wt% -Zn9.0 wt%) and bonded to the gold bump 12.

ここで使用したBT基板3は、ビルドアップ構造を持つ多層の樹脂系プリント配線板だが、場合にっては多層構造ではなく単層構造であり、或いは樹脂製ではなくセラミック系のプリント配線板である。また、銅電極9はアルミニウム電極でもよく、或いは電極表面にパラジウムめっき、錫めっき等のニッケル/金めっき以外の表面処理が施されていても良く、或いは全く表面処理が施されていなくても構わない。   The BT substrate 3 used here is a multilayer resin-based printed wiring board having a build-up structure, but in some cases, it is not a multilayer structure but a single-layer structure, or a ceramic-based printed wiring board that is not made of resin. is there. The copper electrode 9 may be an aluminum electrode, or the electrode surface may be subjected to a surface treatment other than nickel / gold plating such as palladium plating or tin plating, or may not be subjected to any surface treatment. Absent.

また、13のはんだは銅電極9上のニッケル/金めっきの上にソルダペーストを塗布後、リフローソルダリング方式により金バンプ12と接合しているが、場合によっては、銅電極9上に予めはんだをプリコートしはんだ層を形成しておき、その後熱圧着、或いはリフローソルダリングにより金バンプ12と接合する。
はんだプリコートの方法は、スーパージャフィット法、めっき法、はんだボールを搭載する等の種々の方法があるが、必要とするはんだ量を供給可能であれば限定されない。
Further, the solder 13 is applied to the gold bumps 12 by a reflow soldering method after applying a solder paste on the nickel / gold plating on the copper electrode 9. Is pre-coated to form a solder layer, and then bonded to the gold bump 12 by thermocompression bonding or reflow soldering.
There are various solder pre-coating methods, such as a super just method, a plating method, and mounting of solder balls, but there is no limitation as long as the required amount of solder can be supplied.

金バンプ12とはんだ13との接合の機械的信頼性を評価するため、ヒートサイクル試験を行い接合信頼性を評価した。試験は大気中、-25℃〜100℃の温度範囲内で、1時間に1サイクルの条件で行った。サイクル毎に接合部の電気抵抗を測定し、接合部の破断数からそのサイクル数での破断率を求めた。その結果、175サイクルまでは破断は生じず、200サイクル後には破断率は50%、310サイクル後に100%破断となり、良好な結果が得られた。その結果を図5に示した。図5中で実線の黒丸は実施例2の接合破断率を示したもので、実線の黒三角印は比較として従来はんだ(Sn63.0 wt %-Pb37.0 wt %)の結果を示した。従来はんだの破断モードは、はんだバルク中以外で破断する場合があるのに対し、実施例2のはんだ(Sn91.0 wt %-Zn9.0 wt %)の破断モードは、殆どはんだバルク中で破壊していたので、はんだボール接合部の機械的信頼性に問題はなかった。   In order to evaluate the mechanical reliability of the bonding between the gold bump 12 and the solder 13, a heat cycle test was performed to evaluate the bonding reliability. The test was performed in the air at a temperature range of -25 ° C to 100 ° C under the condition of one cycle per hour. The electrical resistance of the joint was measured for each cycle, and the rupture rate at the number of cycles was determined from the number of ruptures of the joint. As a result, no fracture occurred until 175 cycles, the fracture rate was 50% after 200 cycles, and 100% fracture after 310 cycles, and good results were obtained. The results are shown in FIG. In FIG. 5, the solid line black circles indicate the joint fracture rate of Example 2, and the solid line black triangle marks indicate the results of the conventional solder (Sn63.0 wt% -Pb 37.0 wt%) for comparison. While the conventional solder break mode may break outside the solder bulk, the break mode of the solder of Example 2 (Sn91.0 wt% -Zn 9.0 wt%) is mostly broken in the solder bulk. Therefore, there was no problem in the mechanical reliability of the solder ball joint.

さらに、はんだ層中の亜鉛の組成を変えると共に、金バンプの高さを種々変化させた電子部品を作成し、同様の評価を行った結果を示したのが表2である。測定に際して、0〜100℃の温度範囲において1時間に1サイクルの条件でヒートサイクル試験を行い、175サイクルの時の破断率を求めた。尚、破断開始時のサイクル数は、いずれも錫鉛はんだと同等以上の結果を示した。   Further, Table 2 shows the results of making electronic parts with various changes in the composition of zinc in the solder layer and various heights of the gold bumps and carrying out similar evaluations. In the measurement, a heat cycle test was performed under the condition of 1 cycle per hour in a temperature range of 0 to 100 ° C., and the fracture rate at 175 cycles was determined. Note that the number of cycles at the start of breakage was the same or better than that of tin-lead solder.

Figure 2005057245
Figure 2005057245

この表では、二重丸は175サイクル後には破断率が0%であった場合、一重丸は175時間後に破断率が0%以上10%未満であった場合、バツ印は金−はんだ接合不良であった場合をそれぞれ示している。
以上の結果から、十分な実用強度である175サイクル後に破断率0%を達成するには、はんだバンプ中の亜鉛の組成は8wt%以上、15wt%以下であることが必要である。この場合には、金と錫の金属間化合物の生じる接合強度低下の問題を回避できることがわかった。さらに、金バンプは0.5μm以上250μm以下望ましくは、0.5μm以上75μm以下さらに望ましくは0.5μm以上10μm以下であることが良い。これ以上金バンプの高さが高くなるとコスト的に不利になるばかりでなく、はんだが金バンプ中に取り込まれ、はんだの優れた機械的特性が損なわれるという問題が生じ、また低い場合には、はんだ層との熱圧着工程において、困難が生じるので望ましくない。
In this table, the double circle indicates that the fracture rate is 0% after 175 cycles, and the single circle indicates that the fracture rate is 0% or more and less than 10% after 175 hours. Each case is shown.
From the above results, in order to achieve a fracture rate of 0% after 175 cycles, which is a sufficient practical strength, the composition of zinc in the solder bumps needs to be 8 wt% or more and 15 wt% or less. In this case, it was found that the problem of reduction in bonding strength caused by an intermetallic compound of gold and tin can be avoided. Further, the gold bump is 0.5 μm or more and 250 μm or less, preferably 0.5 μm or more and 75 μm or less, and more preferably 0.5 μm or more and 10 μm or less. If the height of the gold bump is higher than this, not only is it disadvantageous in terms of cost, but also the problem that the solder is taken into the gold bump and the excellent mechanical properties of the solder are impaired, and if it is low, In the thermocompression bonding process with the solder layer, it is not desirable because it causes difficulties.

電子部品の断面図。Sectional drawing of an electronic component. 図1の電子部品のはんだボールの周辺部を拡大した図。FIG. 2 is an enlarged view of a peripheral portion of a solder ball of the electronic component in FIG. 参考例1の効果を説明する図。The figure explaining the effect of the reference example 1. FIG. 本発明の実施例1の断面図Sectional drawing of Example 1 of this invention 本発明の実施例1の効果を説明する図The figure explaining the effect of Example 1 of this invention

符号の説明Explanation of symbols

1 ボール状のはんだ
2 ソルダレジスト
3 BT基板
4 集積回路(IC)
5 金リード線
6 モールド樹脂
7 金めっき層
8 ニッケルめっき層
9 銅電極
1 Ball-shaped solder 2 Solder resist 3 BT substrate 4 Integrated circuit (IC)
5 Gold lead wire 6 Mold resin 7 Gold plating layer 8 Nickel plating layer 9 Copper electrode

Claims (3)

表面に電極配線が形成された基板と、この電極配線上に形成された8wt%以上15wt%以下の亜鉛および残部が実質的に錫のはんだ合金のはんだ層と、このはんだ層上に形成された膜厚0.5μm以上250μm以下の金バンプとを有することを特徴とするバンプ接合体。   A substrate having an electrode wiring formed on the surface, a solder layer of 8 wt% or more and 15 wt% or less of zinc and the balance being substantially tin solder formed on the electrode wiring, and a solder layer formed on the solder layer A bump bonded body comprising a gold bump having a thickness of 0.5 μm or more and 250 μm or less. 表面に電極配線が形成された基板と、この電極配線上に形成された8wt%以上15wt%以下の亜鉛および残部が実質的に錫のはんだ合金のはんだ層と、このはんだ層上に形成された膜厚0.5μm以上250μm以下の金バンプと、前記基板の裏面に形成される集積回路と、この集積回路と前記電極配線を電気的に接続する接続手段とを具備することを特徴とする電子部品。   A substrate having an electrode wiring formed on the surface, a solder layer of 8 wt% or more and 15 wt% or less of zinc and the balance being substantially tin solder formed on the electrode wiring, and a solder layer formed on the solder layer An electronic device comprising: a gold bump having a thickness of 0.5 μm or more and 250 μm or less; an integrated circuit formed on the back surface of the substrate; and a connecting means for electrically connecting the integrated circuit and the electrode wiring. parts. 前記電極配線と前記金層の間にニッケル層が介在することを特徴とする請求項5に記載の電子部品。

The electronic component according to claim 5, wherein a nickel layer is interposed between the electrode wiring and the gold layer.

JP2004151943A 2004-05-21 2004-05-21 Bump junction and electronic component Pending JP2005057245A (en)

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