JP2004327649A - Semiconductor device, thin film transistor, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor (TFT) which has a suppressed off-state current and therefore has a high reliability, and to provide a method of manufacturing a semiconductor device which can shorten the time required for production. <P>SOLUTION: On an insulating substrate 1, a foundation film 21 and an insulation film 22 are formed by a CVD method under the condition that the substrate 1 is not exposed to plasmas (Figure (b)). At that time, the foundation film 21 is formed thicker than the insulation film 22. A fixed density of electric charge of the insulation film 22 is set to less than 1×10<SP>12</SP>cm<SP>-2</SP>. Then, an amorphous silicon film 3 is deposited on the insulation film 22 (Figure (c)), and laser is radiated to turn the amorphous silicon film 3 into a crystalline silicon film 31 (Figure (d)). Thereafter, a gate insulation film 4 is deposited, and then the insulation film 4 and the crystalline silicon film 31 are patterned into the shape of an island (Figure (e)). Then, a gate electrode is formed and ions are doped to complete the TFT. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

評価した素子のチャネル幅は２μｍ、チャネル長は２μｍである。また、印加したストレス条件のうち、ドレイン電圧を＋５Ｖ、ゲート電圧を＋２．５Ｖとした。図４は、上記のストレス条件を印加したときにおける、しきい値電圧シフト量と時間の関係を示している。ＴＦＴ−Ａと比べて、ＴＦＴ−Ｂでは、ストレス印加時間に対するしきい値のシフト量が減少していることがわかる。５０万秒後のシフト量はＴＦＴ−Ａで約０．１６Ｖ、ＴＦＴ−Ｂで約０．０５Ｖであった。
【００２０】
【表２】

【００２１】
次に、下地膜２１をシリコン酸化膜の単層とし、下地膜２１と絶縁膜２２の膜厚を変えて形成したＴＦＴを評価した。ここでは下地膜２１と絶縁膜２２との合計した膜厚は３００ｎｍと固定している。下地膜２１、絶縁膜２２の膜厚、固定電荷密度および下地膜２１と絶縁膜２２の積層膜を形成するのにかかった、基板１枚あたりの時間を表２に記載した。下地膜２１と絶縁膜２２は同一装置の同一チャンバ内で形成し、下地膜２１と絶縁膜２２の成膜速度はＳｉＨ_４流量を変えることによって制御した。
これらのＴＦＴに、ドレイン電圧が＋５Ｖ、ゲート電圧が＋２．５Ｖのストレス条件下でストレス試験を行った。これらのＴＦＴは、ほぼ同じしきい値を示した。また、ストレス試験におけるしきい値のシフト量が０．１Ｖ以下と高い信頼性を有するＴＦＴであることがわかった。さらに、表２から下地膜２１を２５０ｎｍ、絶縁膜２２を５０ｎｍに設定したＴＦＴは、下地膜２１と絶縁膜２２の積層膜の形成にかかる時間が少ないことがわかった。よって、下地膜２１と絶縁膜２２という積層構造を有するＴＦＴは、高い信頼性を有し、さらに量産性に優れることが示された。
【００２２】
〔第２の実施の形態〕
本発明の第２の実施の形態を、図５〜７を参照して詳細に説明する。
最初に、図５（ａ）に示すようにガラス等からなる絶縁性基板１上に下地膜２１を形成する。下地膜２１には、酸化シリコン膜、シリコン窒化膜等の絶縁膜、もしくはこれらの２層以上の膜から積層される積層膜を用いる。
下地膜２１の形成には、リモートプラズマＣＶＤ法や熱ＣＶＤ法といった、プラズマに曝されることによるダメージを受けることがないＣＶＤ法を用いることが望ましい。プラズマやイオンのダメージによる基板の荒れや反り等による変形を防ぐためである。
【００２３】
次に、下地膜２１上にアモルファスシリコン膜２３を形成する（図５（ｂ））。このアモルファスシリコン膜２３を形成する場合、リモートプラズマＣＶＤ法もしくは減圧熱ＣＶＤ法を用いることが望ましい。アモルファスシリコン膜２３の膜厚は、量産を考慮すると、１０〜３０ｎｍ程度であることが望ましい。
次に、アモルファスシリコン膜２３を酸化させ、酸化シリコン膜２４を形成する。この場合、１×１０^１２ｃｍ^−２未満という低い固定電荷密度を持つ酸化シリコン膜を形成するために、ＶＨＦ、ＵＨＦ等の高周波で励起した酸素ラジカルを照射させる方法が適している（図５（ｃ））。
下地膜２１と酸化シリコン膜２４とを足した膜厚は２００〜５０００ｎｍ程度になるように設定することが望ましい。これは、絶縁性基板１に含まれるアルカリ金属等の不純物が結晶化シリコン膜３１に拡散するのを防ぐために必要なことである。
【００２４】
次に、図５（ｄ） に示すようにアモルファスシリコン膜３を、減圧ＣＶＤ法等によって形成する。このアモルファスシリコン膜３の膜厚は、レーザアニールによる結晶化を考慮すると、１０〜１００ｎｍ程度であることが望ましい。さらに、アモルファスシリコン膜３にレーザビームを照射して結晶化を行い、図６（ｅ）に示すように結晶化シリコン膜３１を形成する。この結晶化にはエキシマレーザアニール装置等が用いられる。
続いて、図６（ｆ）に示すように結晶化シリコン膜３１上にプラズマＣＶＤ法等でゲート絶縁膜４を形成した後、ドライエッチング法を用いて、所望のアイランド形状にパターニングする。その後、スパッタリング法等を用いて、金属膜を成膜後、所望の形状にパターニングしてゲート電極５を形成する（図６（ｇ））。
次に、ｎチャネルＴＦＴを形成する場合、リンイオンをドーピングし、活性化することによって、ソース・ドレイン領域６を形成する（図７（ｈ））。ｐチャネルＴＦＴを形成する場合は、ボロンイオンをドーピングし、活性化することによって、ソース・ドレイン領域６を形成する。この時、ドーピングした不純物イオンを低温で活性化させるために、エキシマレーザアニール装置によって、レーザアニール処理を施す。その後、シリコン中のダングリングボンドを終端させるために水素プラズマ処理を施す。この水素プラズマ処理は、プラズマＣＶＤ装置に水素ガスを導入し、高周波電力を印加することによって行う。
【００２５】
次に、図７（ｉ）に示すように、層間絶縁膜７を成膜した後、ドライエッチング等によってソース・ドレイン領域上にコンタクトホールを形成する。層間絶縁膜７としては、酸化シリコン膜、窒化シリコン膜、酸化シリコン膜と窒化シリコン膜の積層膜等を用いる。図には示さないが、ソース、ドレイン領域にコンタクトホールを形成する工程の直前、もしくは直後にゲート電極とのコンタクトがとられる。
最後に、金属膜を堆積しこれをパターニングしてソース・ドレイン電極８を形成することによって図７（ｊ）に示されるＴＦＴを得る。ソース・ドレイン電極形成用の金属膜に用いる材料は、ソース、ドレイン領域とのコンタクト抵抗を低減するため、シリサイド化しやすいＳｉを含有した金属を用いることが好ましい。
以上の工程を経て、ＴＦＴの作製工程が完了するが、さらに外部の雰囲気による影響を抑制するために、この上部に絶縁膜が形成されることもある。
【００２６】
〔第３の実施の形態〕
本発明の第３の実施の形態を、図８、９を参照して詳細に説明する。図８（ａ）に示すように絶縁性基板上１に下地膜２を形成する。下地膜２は酸化シリコン膜等の絶縁膜が適当である。さらに、絶縁性基板１に含まれるアルカリ金属等の不純物が結晶化シリコン膜３１に拡散するのを防ぐために、下地膜の膜厚は２００ｎｍ以上であることが望ましく、量産を考慮すると、５μｍ以下になるように設定することが望ましい。また、下地膜２の固定電荷密度が１×１０^１２ｃｍ^−２未満になるように形成する。下地膜の形成にはリモートプラズマＣＶＤ法や熱ＣＶＤ法といった、プラズマに曝されることによるダメージを受けることがないＣＶＤ法を用いることが望ましい。これは、プラズマやイオンのダメージによる基板の荒れや反り等による変形を防ぐためである。
次に、図８（ｂ）に示すようにアモルファスシリコン膜３を減圧熱ＣＶＤ法等で形成する。このアモルファスシリコン膜３の膜厚は、結晶化を行うことを考慮して、１０〜１００ｎｍ程度であることが望ましい。さらに、アモルファスシリコン膜３にレーザビームを照射して結晶化を行い、図８（ｃ）に示すように、結晶化シリコン膜３１を形成する。この結晶化にはエキシマレーザアニール装置等が用いられる。
【００２７】
続いて、図８（ｄ）に示すように結晶化シリコン膜３１上にプラズマＣＶＤ法等でゲート絶縁膜４を形成した後、ドライエッチング法を用いて、所望のアイランド形状にパターニングする。その後、スパッタリング法等を用いて、金属膜を成膜した後、所望の形状にパターニングしてゲート電極５を形成する（図８（ｅ））。
次に、ｎチャネルＴＦＴを形成する場合、リンイオンをドーピングし、活性化することによって、ソース・ドレイン領域６を形成する（図９（ｆ））。ｐチャネルＴＦＴを形成する場合は、ボロンイオンをドーピングし、活性化することによって、ソース・ドレイン領域６を形成する。この時、ドーピングした不純物イオンを低温で活性化させるために、エキシマレーザアニール装置によって、レーザアニール処理を施す。その後、シリコン中のダングリングボンドを終端させるために水素プラズマ処理を施す。この水素プラズマ処理は、プラズマＣＶＤ装置に水素ガスを導入し、高周波電力を印加することによって行う。
【００２８】
次に、図９（ｇ）に示すように、層間絶縁膜７を成膜した後、ドライエッチング等によってソース・ドレイン領域上にコンタクトホールを形成する。層間絶縁膜７としては、酸化シリコン膜、窒化シリコン膜、酸化シリコン膜と窒化シリコン膜の積層膜等を用いる。図には示さないが、ソース、ドレイン領域にコンタクトホールを形成する工程の直前、もしくは直後にゲート電極とのコンタクトがとられる。
最後に、金属膜の堆積とそのパターニングによってソース・ドレイン電極８を形成することによって図９（ｈ）に示されるＴＦＴを得る。ソース・ドレイン電極８に用いる材料は、ソース、ドレイン領域とのコンタクト抵抗を低減するため、シリサイド化しやすいＳｉを含有した金属を用いる。
以上の工程を経て、ＴＦＴの作製工程が完了するが、さらに外部の雰囲気による影響を抑制するために、この上部に絶縁膜が形成されることもある。
ここで、下地膜の形成方法および形成条件を変え、様々な固定電荷密度を有する下地膜を作製し、図８、９のプロセスを経たｎチャネルＴＦＴのストレス試験におけるしきい値電圧シフトを評価した。評価した素子のチャネル幅は２μｍ、チャネル長は２μｍである。また、印加したストレス条件のうち、ドレイン電圧を＋５Ｖ、ゲート電圧を＋２．５Ｖとした。
【００２９】
【表３】

評価した結果、下地膜２の固定電荷密度が約３×１０^１２ｃｍ^−２であるＴＦＴ−Ｃのしきい値は、ストレスを印加した５０万秒後に０．２５Ｖもシフトをしたのに対して、下地膜２の固定電荷密度が約３×１０^１１ｃｍ^−２であるＴＦＴ−Ｄのしきい値は、そのシフト量が０．１Ｖ以下と小さいことが判明した。つまり、下地膜２の固定電荷密度が１×１０^１２ｃｍ^−２以下と小さいＴＦＴは高い信頼性を持つことがわかる。
【００３０】
〔第４の実施の形態〕
本発明の第４の実施の形態を、図１０、１１を参照して詳細に説明する。図１０（ａ）に示すように絶縁性基板１上に下地膜２を形成する。下地膜２は酸化シリコン膜が適当である。さらに、絶縁性基板１に含まれるアルカリ金属等の不純物が結晶化シリコン膜３１に拡散するのを防ぐために、下地膜の膜厚は２００ｎｍ以上であることが望ましく、量産を考慮すると、５μｍ以下になるように設定することが望ましい。製法や形成条件によっては、下地膜２の固定電荷密度が１×１０^１２ｃｍ^−２未満となるように形成することができない場合がある。この時は、固定電荷密度が１×１０^１２ｃｍ^−２未満となるように後処理を施すことによって、所望の特性を示す下地膜を実現する。酸化シリコン膜の後処理には、水蒸気雰囲気のもとで、高い圧力を印加しながら施す熱処理や酸素ガスに高周波を印加して励起した酸素ラジカルを照射する処理がある。
【００３１】
次に、図１０（ｂ）に示すようにアモルファスシリコン膜３を減圧熱ＣＶＤ法等で形成する。このアモルファスシリコン膜３の膜厚は、結晶化を行うことを考慮して、１０〜１００ｎｍ程度であることが望ましい。さらにアモルファスシリコン膜３にレーザビームを照射して結晶化を行い、図１０（ｃ）に示すように結晶化シリコン膜３１を形成する。この結晶化にはエキシマレーザアニール装置等が用いられる。
続いて、図１０（ｄ）に示すように結晶化シリコン膜３１上にプラズマＣＶＤ法等でゲート絶縁膜４を形成した後、ドライエッチング法を用いて、所望のアイランド形状にパターニングする。その後、スパッタリング法等を用いて、金属膜を成膜後、所望の形状にパターニングしてゲート電極５を形成する（図１０（ｅ））。
次に、ｎチャネルＴＦＴを形成する場合、リンイオンをドーピングし、活性化することによって、ソース・ドレイン領域６を形成する（図１１（ｆ））。ｐチャネルＴＦＴを形成する場合は、ボロンイオンをドーピングし、活性化することによって、ソース・ドレイン領域６を形成する。この時、ドーピングした不純物イオンを低温で活性化させるために、エキシマレーザアニール装置等によって、レーザアニール処理を施す。その後、シリコン中のダングリングボンドを終端させるために水素プラズマ処理を施す。この水素プラズマ処理は、プラズマＣＶＤ装置に水素ガスを導入し、高周波電力を印加することによって行う。
【００３２】
次に、図１１（ｇ）に示すように、層間絶縁膜７を成膜した後、ドライエッチング等によってソース・ドレイン領域上にコンタクトホールを形成する。層間絶縁膜７としては、酸化シリコン膜、窒化シリコン膜、酸化シリコン膜と窒化シリコン膜の積層膜等を用いる。図には示さないが、ソース・ドレイン領域にコンタクトホールを形成する工程の直前、もしくは直後にゲート電極とのコンタクトがとられる。
最後に、金属膜の堆積とそのパターニングによってソース・ドレイン電極８をすることによって図１１（ｈ）に示されるＴＦＴを得る。ソース・ドレイン電極８に用いる材料は、ソース、ドレイン領域とのコンタクト抵抗を低減するため、シリサイド化しやすいＳｉを含有した金属を用いる。
以上の工程を経て、ＴＦＴの作製工程が完了するが、さらに外部の雰囲気による影響を抑制するために、この上部に絶縁膜を形成することもある。
【００３３】
【実施例】
以下、実施例を参照して本発明を具体的に説明する。
〔第一の実施例〕
図１、２に示す工程順により、本発明の第一の実施例におけるｎチャネルＴＦＴの製造方法を以下に説明する。
まず、図１（ａ）に示すように、絶縁性基板１であるガラス基板上に下地膜２１として、２５０ｎｍの酸化シリコン膜の単層を、図３の構成を持つリモートプラズマＣＶＤ装置を用いることによって成膜した。この下地膜２１を形成する際、プラズマ発生領域に７００ｓｃｃｍのＯ_２ガスを導入し、６０ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させた。一方、堆積領域には、４００ｓｃｃｍのＨｅガスと２００ｓｃｃｍのＳｉＨ_４ガスを導入し、成膜をした。この時、下地膜２１の固定電荷密度は約３×１０^１２ｃｍ^−２であった。
【００３４】
次に、同じ装置によって、堆積領域に４００ｓｃｃｍのＨｅガスと４ｓｃｃｍ のＳｉＨ_４ガスを導入し、絶縁膜２２を５０ｎｍ形成した（図１（ｂ））。この時、絶縁膜２２の固定電荷密度は約３×１０^１１ｃｍ^−２であった。
次に、図１（ｃ）に示すように、減圧ＣＶＤ法を用いて６０ｎｍのアモルファスシリコン膜３を形成した。この時、Ｓｉ_２Ｈ_６、Ｈｅの混合ガスを原料として形成した。さらに、図１（ｄ）に示すように、ＸｅＣｌエキシマレーザアニール装置を用いて、結晶化を行った。
続いて、図３で示されるリモートプラズマＣＶＤ装置を用いて、４０ｎｍのゲート絶縁膜４を形成し、ドライエッチング法等によって、ゲート絶縁膜４と結晶化シリコン膜３１とを所望のアイランド形状にパターニングした（図１（ｅ））。
その後、スパッタリング法で膜厚２００ｎｍのＷＳｉ膜を堆積し、ドライエッチング法を用いて所望の形状にパターニングしてゲート電極５を形成した（図２（ｆ））。
【００３５】
次に、イオンドーピング装置を用いて、リンイオンをドーピングし、ソース・ドレイン領域６を形成した（図２（ｇ））。続いて、ＸｅＣｌレーザアニール装置を用いてアニール処理を行い、リンイオンを活性化させた。その後、プラズマＣＶＤ装置に水素ガスを導入後、１３．５６ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させ、１時間の水素化処理を施した。
次に、図２（ｈ）に示すように、プラズマＣＶＤ法によって、層間絶縁膜７として酸化シリコン膜を４００ｎｍ厚に成膜した後、ドライエッチング等によってソース・ドレイン領域６上にコンタクトホールを形成した。
次に、スパッタリング法を用いてＡｌＳｉ膜を形成した。さらにドライエッチング法によって所望の形状にパターニングし、ソース・ドレイン電極８を形成した（図２（ｉ））。
このようにして作製された本実施例のＴＦＴにおいて、ドレイン電圧が＋５Ｖ、ゲート電圧が＋２．５Ｖのストレス条件下でストレス試験を行ったところ、ストレス印加５０万秒後におけるしきい値のシフト量が０．１Ｖ以下と高い信頼性を有することがわかった。
また、本実施例においては下地膜２１と絶縁膜２２の積層構造を用い、能動層である結晶化シリコン膜３１と接する絶縁膜２２の固定電荷密度を３×１０^１１ｃｍ^−２に設定し、絶縁性基板と接する下地膜２１を絶縁膜２２よりも厚く、早い成膜速度で形成することによって、生産に必要な時間が短縮された。
本発明に係るＴＦＴおよびに製造方法を用いることによって、バックチャネルを抑制することによって、オフ電流を低減し、その結果、高い信頼性を有するＴＦＴの作製が可能であるだけでなく、生産に必要な時間を短縮できることが可能である。
【００３６】
〔第二の実施例〕
次に、図５〜７に示す工程順により、本発明の第二の実施例におけるｎチャネルＴＦＴの製造方法を以下に説明する。
まず、図５（ａ）に示すように、絶縁性基板１であるガラス基板上に下地膜２１として、２８５ｎｍの酸化シリコン膜を、図３の構成を持つリモートプラズマＣＶＤ装置を用いることによって成膜した。この下地膜２１を形成する際、プラズマ発生領域に７００ｓｃｃｍのＯ_２ガスを導入し、６０ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させた。一方、堆積領域には、４００ｓｃｃｍのＨｅガスと２００ｓｃｃｍのＳｉＨ_４ガスを導入し、成膜をした。この時、下地膜の固定電荷密度は約３×１０^１２ｃｍ^−２であった。
【００３７】
次に、図５（ｂ）に示すように、減圧ＣＶＤ法を用いて１５ｎｍのアモルファスシリコン膜２３を堆積した。この時、Ｓｉ_２Ｈ_６、Ｈｅの混合ガスを原料として形成した。さらにアモルファスシリコン膜２３に２．４５ＧＨｚのマイクロ波によって励起した酸素ラジカルを照射し、シリコン酸化膜２４を形成した（図５（ｃ））。
次に、図５（ｄ）に示すように、減圧ＣＶＤ法を用いて６０ｎｍのアモルファスシリコン膜３を形成した。この時、Ｓｉ_２Ｈ_６、Ｈｅの混合ガスを原料として形成した。さらに、図６（ｅ）に示すように、ＸｅＣｌエキシマレーザアニール装置を用いて、結晶化を行った。
続いて、図３で示されるリモートプラズマＣＶＤ装置を用いて、４０ｎｍのゲート絶縁膜４を形成し、ドライエッチング法等によって、ゲート絶縁膜４と結晶化シリコン膜３１とを所望のアイランド形状にパターニングした（図６（ｆ））。
その後、スパッタリング法で膜厚２００ｎｍのＷＳｉ膜を堆積し、ドライエッチング法を用いて所望の形状にパターニングしてゲート電極５を形成した（図６（ｇ））。
【００３８】
次に、イオンドーピング装置を用いて、リンイオンをドーピングし、ソース・ドレイン領域６を形成した（図７（ｈ））。続いて、ＸｅＣｌレーザアニール装置を用いてアニール処理を行い、リンイオンを活性化させた。その後、プラズマＣＶＤ装置に水素ガスを導入後、１３．５６ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させ、１時間の水素化処理を施した。
次に、図７（ｉ）に示すように、プラズマＣＶＤ法によって酸化シリコン膜を４００ｎｍ厚に成膜して層間絶縁膜７を形成した後、ドライエッチング等によってソース、ドレイン領域６上にコンタクトホールを形成した。
次に、スパッタリング法を用いてＡｌＳｉ膜を形成した。さらにドライエッチング法によって所望の形状にパターニングし、ソース・ドレイン電極８を形成した（図７（ｊ））。
このようにして作製された本実施例のＴＦＴにおいては、ドレイン電圧が＋５Ｖ、ゲート電圧が＋２．５Ｖのストレス条件下でストレス試験を行ったところ、第一の実施例と同様に、ストレス印加５０万秒後におけるしきい値のシフト量が０．１Ｖ以下と高い信頼性を有することがわかった。
【００３９】
〔第三の実施例〕
次に、図８、９に示す工程順により、本発明の第三の実施例としてｎチャネルＴＦＴの製造方法を説明する。
まず、図８（ａ）に示すように、絶縁性基板１であるガラス基板上に下地膜２として、３００ｎｍの酸化シリコン膜を、図３の構成を持つリモートプラズマＣＶＤ装置を用いることによって成膜した。下地膜２を形成する際、プラズマ発生領域に７００ｓｃｃｍのＯ_２ガスを導入し、６０ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させた。一方、堆積領域には、４００ｓｃｃｍのＨｅガスと４ｓｃｃｍのＳｉＨ_４ガスを導入し、成膜をした。この時、下地膜の固定電荷密度は約３×１０^１１ｃｍ^−２であった。
次に、図８（ｂ）に示すように、減圧ＣＶＤ法を用いて６０ｎｍのアモルファスシリコン膜３を形成した。この時、Ｓｉ_２Ｈ_６、Ｈｅの混合ガスを原料として形成した。さらに、図８（ｃ）に示すように、ＸｅＣｌエキシマレーザアニール装置を用いて、結晶化を行った。
続いて、図３で示されるリモートプラズマＣＶＤ装置を用いて、４０ｎｍのゲート絶縁膜４を作製し、ドライエッチング法等によって、ゲート絶縁膜４と結晶化シリコン膜３１とを所望のアイランド形状にパターニングした（図８（ｄ））。
その後、スパッタリング法で膜厚２００ｎｍのＷＳｉ膜を堆積し、ドライエッチング法を用いて所望の形状にパターニングしてゲート電極５を形成した（図８（ｅ））。
【００４０】
次に、イオンドーピング装置を用いて、リンイオンをドーピングし、ソース・ドレイン領域６を形成した（図９（ｆ））。続いて、ＸｅＣｌレーザアニール装置を用いてアニール処理を行い、リンイオンを活性化させた。その後、プラズマＣＶＤ装置に水素ガスを導入後、１３．５６ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させ、１時間の水素化処理を施した。
次に、図９（ｇ）に示すように、プラズマＣＶＤ法によって酸化シリコン膜を４００ｎｍ厚に成膜して層間絶縁膜７を形成した後、ドライエッチング等によってソース・ドレイン領域上にコンタクトホールを形成した。
次に、スパッタリング法を用いてＡｌＳｉ膜を形成した。さらにドライエッチング法によって所望の形状にパターニングし、ソース・ドレイン電極８を形成した（図９（ｈ））。
本実施例により作成された本発明のＴＦＴにおいて、ドレイン電圧が＋５Ｖ、ゲート電圧が＋２．５Ｖのストレス条件下でストレス試験を行ったところ、第一、第二の実施例と同様に、ストレス印加５０万秒後におけるしきい値のシフト量が０．１Ｖ以下と高い信頼性を有することがわかった。
これは、本発明に係るＴＦＴおよびに製造方法を用いることによって、バックチャネルを介したオフ電流のリークが抑制され、その結果、高い信頼性を有するＴＦＴの作製が可能であることを示している。
【００４１】
〔第四の実施例〕
図１０、１１に示す工程順により、本発明の第四の実施例としてｎチャネルＴＦＴの製造方法を説明する。
まず、絶縁性基板であるガラス基板上１に下地膜２として、３００ｎｍの酸化シリコン膜を、図３の構成を持つリモートプラズマＣＶＤ装置を用いることによって成膜した。下地膜２を形成する際、プラズマ発生領域に７００ｓｃｃｍのＯ_２ガスを導入し、６０ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させた。一方、堆積領域には、４００ｓｃｃｍのＨｅガスと２００ｓｃｃｍのＳｉＨ_４ガスを導入し、成膜をした。この時、下地膜２の固定電荷密度は約３×１０^１２ｃｍ^−２であった。
【００４２】
この後、水蒸気を導入し、約２ＭＰａの圧力に保たれた圧力容器内にガラス基板を設置し、４００℃の熱処理を１時間施した（図１０（ａ））。この高圧水蒸気アニール後の下地膜２の固定電荷密度は約１×１０^１１ｃｍ^−２であった。
次に、図１０（ｂ）に示すように、減圧ＣＶＤ法を用いて６０ｎｍのアモルファスシリコン膜３を形成した。この時、Ｓｉ_２Ｈ_６、Ｈｅの混合ガスを原料として形成した。さらに、図１０（ｃ）に示すように、ＸｅＣｌエキシマレーザアニール装置を用いて、結晶化を行った。
続いて、図３で示されるリモートプラズマＣＶＤ装置を用いて、４０ｎｍのゲート絶縁膜４を作製し、ドライエッチング法等によって、ゲート絶縁膜４と結晶化シリコン膜３１とを所望のアイランド形状にパターニングした（図１０（ｄ））。
その後、スパッタリング法で膜厚２００ｎｍのＷＳｉ膜を堆積し、ゲート電極用金属膜５を形成し、ドライエッチング法を用いて所望の形状にパターニングした（図１０（ｅ））。
【００４３】
次に、イオンドーピング装置を用いて、リンイオンをドーピングし、ソース・ドレイン領域６を形成した（図１１（ｆ））。続いて、ＸｅＣｌレーザアニール装置を用いてアニール処理を行い、リンイオンを活性化させた。その後、プラズマＣＶＤ装置に水素ガスを導入後、１３．５６ＭＨｚの励起周波数で高周波電力を印加し、プラズマを発生させ、１時間の水素化処理を施した。
次に、図１１（ｇ）に示すように、プラズマＣＶＤ法によって酸化シリコン膜を４００ｎｍ厚に成膜して層間絶縁膜７を形成した後、ドライエッチング等によってソース・ドレイン領域６上にコンタクトホールを形成した。
次に、スパッタリング法を用いてＡｌＳｉ膜を形成した。さらにドライエッチング法によって所望の形状にパターニングし、ソース・ドレイン電極８を形成した（図１１（ｈ））。
本実施例により作成された本発明のＴＦＴにおいて、ドレイン電圧が＋５Ｖ、ゲート電圧が＋２．５Ｖのストレス条件下でストレス試験を行ったところ、第一、第二、第三の実施例と同様に、ストレス印加５０万秒後におけるしきい値のシフト量が０．１Ｖ以下と高い信頼性を有することがわかった。
【００４４】
以上好ましい実施例について説明したが、本発明は上記各実施例に限定されず、本発明の技術思想の範囲内において、各実施例は適宜変更され得る。例えば、第一、第三の実施例においては、絶縁膜２２や下地膜２を一定の成膜速度で形成していたが、絶縁膜２２や下地膜２の成膜工程において、全工程中あるいは工程途中から徐々に成膜速度を低下させるようにしてもよい。
【００４５】
【発明の効果】
以上説明したように、本発明により、絶縁性基板上に形成されるＴＦＴのオフ電流を抑制することができ、高い信頼性を有するＴＦＴが実現できる。さらに、下地膜を絶縁膜よりも厚く、早い成膜速度で形成することによって、生産に必要な時間を低減することができ、低オフ電流、高信頼性のＴＦＴを高スループットで製造することを可能ならしめることができる。
【図面の簡単な説明】
【図１】本発明に係るＴＦＴの製造方法の第１の実施形態の工程順断面図の一部（その１）。
【図２】本発明に係るＴＦＴの製造方法の第１の実施形態の工程順断面図の一部（その２）。
【図３】本発明において用いられるリモートプラズマＣＶＤ装置の概略図。
【図４】絶縁膜の固定電荷密度の異なるＴＦＴのＩｄ−Ｖｇ特性図。
【図５】本発明に係るＴＦＴの製造方法の第２の実施形態の工程順断面図の一部（その１）。
【図６】本発明に係るＴＦＴの製造方法の第２の実施形態の工程順断面図の一部（その２）。
【図７】本発明に係るＴＦＴの製造方法の第２の実施形態の工程順断面図の一部（その３）。
【図８】本発明に係るＴＦＴの製造方法の第３の実施形態の工程順断面図の一部（その１）。
【図９】本発明に係るＴＦＴの製造方法の第３の実施形態の工程順断面図の一部（その２）。
【図１０】本発明に係るＴＦＴの製造方法の第４の実施形態の工程順断面図の一部（その１）。
【図１１】本発明に係るＴＦＴの製造方法の第４の実施形態の工程順断面図の一部（その２）。
【符号の説明】
１ 絶縁性基板
２ 下地膜
２１ 下地膜
２２ 絶縁膜
２３ アモルファスシリコン膜
２４ シリコン酸化膜
３ アモルファスシリコン膜
３１ 結晶化シリコン膜
４ ゲート絶縁膜
５ ゲート電極
６ ソース・ドレイン領域
７ 層間絶縁膜
８ ソース・ドレイン電極
１０ 基板
１１ 真空チャンバ
１２ 高周波印加電極
１３ 高周波電源
１４ 対向電極
１５ プラズマ隔離板
１６ 排気口[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device, a thin film transistor, and a method for manufacturing a semiconductor device, and more particularly to a semiconductor device formed on an insulating substrate and a method for manufacturing the same.
[0002]
[Prior art]
In recent years, technology has been developed to form not only devices for driving each pixel of liquid crystal flat panel displays, but also semiconductor devices such as memories and other multifunctional integrated circuits on transparent insulating substrates such as glass substrates. Has been done. Generally, a thin film transistor (TFT) having a silicon film as an active region is used as a semiconductor element of these devices. Therefore, in order to realize a multifunctional integrated circuit, it is essential to improve the performance of the TFT. Therefore, a crystallized silicon film having excellent characteristics is used for the active layer of the TFT. This crystallized silicon film is generally formed by using a method in which an amorphous silicon film is formed and then crystallized by irradiating an energy beam with an excimer laser annealing device or the like. It is a target.
[0003]
However, when a crystallized silicon film is formed directly on a transparent insulating substrate such as a glass substrate, impurities such as alkali metals, aluminum, and boron contained in the glass substrate are crystallized during the subsequent TFT manufacturing process. There is a problem that the silicon nitride film is contaminated, and characteristics such as a threshold value fluctuate. On the other hand, a method is used in which a base film made of an insulating film such as a silicon oxide film is formed on a glass substrate, and a crystallized silicon film is formed thereon (see, for example, Patent Document 1). . As a result, contamination by impurities contained in the glass substrate is prevented, and a high-performance TFT is manufactured.
In forming the base film, a plasma CVD method, a low-pressure thermal CVD method, or a sputtering method which can form an insulating film at a low temperature of less than 600 ° C. is used to suppress deformation of the glass substrate due to heat. Have been.
[0004]
However, when the fixed charge density of the insulating film constituting the base film is high, the carriers in the channel region located in the crystallized silicon film are attracted by the fixed charges existing in the base film, and a potential difference is generated to form a back channel. As a result, the current flowing between the source and the drain during the off operation through the back channel (off current) increases. As a result, the inventors have found that the reliability is deteriorated. Note that the “fixed charge density of an insulating film” described in this specification is a value converted into an interface fixed charge density of an insulating film formed on silicon.
Therefore, the water (H ₂ O) The concentration is about 1 × 10 ²⁰ Pieces / cm ³ The base film having the following composition, and the concentration of SiOH groups contained in the film is about 1 × 10 ²¹ Pieces / cm ³ There has been proposed a semiconductor device characterized by being a base film (see, for example, Patent Document 2). In Patent Document 2, when crystallization of a silicon film formed on a base film, H ₂ Since oxygen donors generated from O and SiOH groups are mixed into the crystallized silicon film, the threshold voltage V _TH Is shifted in the negative direction, and the leakage current in the off-operation region increases. However, our studies show that H ₂ Even between TFTs using a base film having the same concentration of O and SiOH groups, the off current increases and the threshold voltage tends to shift, and only the oxygen donor mixed into the crystallized silicon film is observed. There was a problem that could not be explained. Thereafter, it was found that this tendency was due to the leakage of the drain current through the back channel formed by the fixed charges existing in the base film.
Further, a TFT in which the threshold voltage is controlled by the polarity and amount of fixed charges contained in the base film and the gate insulating film between the gate insulating film and the base film sandwiching the silicon film above and below has been proposed. (For example, see Patent Document 3). However, according to the study of the present inventors, the fixed charge density of the underlying film is 1 × 10 ¹² cm ^-2 In the case described above, it has been found that a problem of a large increase in off-current occurs regardless of the fixed charge density in the gate insulating film. Furthermore, to reduce power consumption, the gate insulating film needs to be thinner, while the base film needs to prevent contamination from the glass substrate, so it is substantially difficult to reduce the thickness. There is a problem that it is difficult to control the amount of fixed charges in the insulating film having a large gap in the TFT fabrication.
[0005]
Further, a first insulating film over the substrate, a second insulating film in contact with the first insulating film, a channel forming region in contact with the second insulating film, a source region and a drain region, and a gate insulating layer. , A gate wiring, and a semiconductor element characterized in that the thickness of the second insulating film is smaller than that of the first insulating film (for example, see Patent Document 4). In this technique, after the first insulating film is heat-treated, a clean interface is formed between the second insulating film and the semiconductor film in contact with the second insulating film in order to continuously form the second insulating film and the semiconductor film in contact with the second insulating film. can do. However, even if it is possible to form a clean interface between the second insulating film and the semiconductor film as a structure in which the second insulating film and the base film are stacked in this manner, even if a channel forming region is formed, The fixed charge density of the contacting second insulating film is 1 × 10 ¹² cm ^-2 Otherwise, a back channel is formed, so that an increase in off-state current cannot be suppressed. Furthermore, when the base film is formed in two layers, the number of steps increases, and a problem that more production time is required occurs.
[0006]
Further, in order to form an insulating film having a low fixed charge density in a plasma CVD method, a low-pressure thermal CVD method, or a sputtering method used for forming a silicon oxide film, it is necessary to form the insulating film with a low deposition rate. However, there is a problem that a long production time is required (for example, see Non-Patent Document 1).
Therefore, a step of forming a first silicon oxide film on the substrate by sputtering in an atmosphere containing argon and oxygen, and a step of further sputtering on the first silicon oxide film in an atmosphere of 100% oxygen. There has been proposed a method for manufacturing a semiconductor device including a step of forming a second silicon oxide film and a step of forming a semiconductor thin film over the second silicon oxide film (for example, see Patent Document 5). This technology not only can form a second silicon oxide film in contact with a semiconductor thin film so as to be a silicon oxide film of excellent film quality, but also can sputter the first silicon oxide film in a mixed atmosphere of oxygen and argon. By performing the above, the film formation rate is increased, so that a certain effect is achieved in that high productivity can be secured.
[0007]
However, in the sputtering method, ions having high energy collide with the surface of the substrate or the film, and damage the substrate or the film, thereby causing a problem that the substrate is deformed or the characteristics of the film are deteriorated. In addition, when the sputtering method is used, a much larger amount of discharge rare gas molecules than atoms of a thin film material to be formed collide with the substrate and are mixed into the thin film. Therefore, 1 × 10 ¹² cm ^-2 It is feared that an insulating film having such a good characteristic as to exhibit a smaller fixed charge density cannot be formed (for example, see Non-Patent Document 2).
Methods for forming a silicon oxide film at a low temperature of less than 600 ° C. include a plasma CVD method, a low pressure thermal CVD method, a sputtering method, and a method in which a silicon film is oxidized by oxygen radicals generated by microwaves. (For example, see Non-Patent Document 3). According to this method, a silicon oxide film having a low fixed charge density can be formed. However, when a thick oxide film such as a base film is required, there is a problem that an extremely long production time is required.
[0008]
[Patent Document 1]
JP-A-4-11722
[Patent Document 2]
JP-A-10-189988
[Patent Document 3]
JP-A-10-223904
[Patent Document 4]
JP 2000-183360 A
[Patent Document 5]
JP-A-9-260682
[Non-patent document 1]
AM-LCD'02 Digest pp. 115-118 (2002)
[Non-patent document 2]
J. Appl. Phys. Vol. 82 (1997), p. 5680
[Non-Patent Document 3]
Applied Physics, Vol. 69, No. 10 (2000), p. 1200
[0009]
[Problems to be solved by the invention]
As described above, the conventional technique has a problem that it is difficult to manufacture a thin film transistor having low leakage current (off current) with high productivity. An object of the present invention is to solve the above-described problems of the related art, and an object of the present invention is to provide a TFT underlayer that suppresses off-current and exhibits good reliability. An object of the present invention is to provide a method for manufacturing a TFT which has a structure excellent in productivity as a base film and is suitable for mass production.
[0010]
[Means for Solving the Problems]
In the semiconductor device according to the present invention, a base film and an insulating film having a laminated structure are arranged between a crystallized silicon film as an active layer and an insulating substrate, and furthermore, a fixed charge of the insulating film in contact with the crystallized silicon film. The density is lower than the fixed charge density of the underlayer formed on the insulating substrate, and the fixed charge density is 1 × 10 ¹² cm ^-2 Less than.
As described above, by adopting the configuration in which the base film and the insulating film are provided between the crystallized silicon film as the active layer and the insulating substrate, the crystallized silicon film can be formed regardless of the fixed charge density of the base film. The back channel formed in the crystallized silicon film can be easily controlled by the fixed charge density of the insulating film in contact with the substrate. If the fixed charge density of the insulating film is small, formation of a back channel is suppressed. Therefore, by setting the fixed charge density of the insulating film to be smaller than the fixed charge density of the base film and controlling the fixed charge density of the insulating film, the off-current caused by the back channel of the crystallized silicon film can be reduced. It is possible to manufacture a TFT which is suppressed and has high reliability. In particular, the fixed charge density of the insulating film is 1 × 10 ¹² cm ^-2 If less, the effect is significant. Further, in a film formation method such as a CVD method, when a film having a large fixed charge density can be formed at a high film formation rate, the base film is formed using a high film formation rate. It becomes possible.
[0011]
Further, the semiconductor device of the present invention is characterized in that the thickness of the insulating film is smaller than the thickness of the base film.
As described above, the film formation rate of the base film formed on the insulating substrate is made faster than the film formation rate of the insulating film, and further, the film thickness of the insulating film is made smaller than the film thickness of the base film. The time required for forming the base film and the insulating film is reduced. In this case, since the fixed charge density of the insulating film in contact with the active layer is low, the off-state current is suppressed as described above, so that a TFT having excellent mass productivity and high reliability can be realized. .
[0012]
Further, when forming these TFTs, the TFT is characterized in that the insulating substrate and the base film formed on the insulating substrate are formed by a CVD method without being exposed to plasma. As a result, it is possible to obtain a desired TFT without damaging the substrate and the underlying film by plasma and ions having high energy, and without deteriorating the characteristic of suppressing diffusion of impurities on the glass substrate. .
In addition, a film formation rate when forming the insulating film and the base film is controlled by changing a flow rate of a gas containing Si or a pressure in a chamber at the time of formation. Further, an insulating film in contact with the crystallized silicon film is formed by performing an oxidation treatment after forming the crystallized silicon film. Thus, it is possible to easily control the film formation rate and the fixed charge density.
In the case where an insulating film is not provided on the base film, the fixed charge density of the base film is 1 × 10 ¹² cm ^-2 By setting the value to less than that, a TFT having high reliability can be realized.
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Embodiments of the present invention will be described below in detail with reference to the drawings.
[First Embodiment]
1 and 2 are sectional views in the order of steps showing a first embodiment of the present invention.
First, as shown in FIG. 1A, a base film 21 is formed on an insulating substrate 1 made of glass or the like. As the base film 21, an insulating film such as a silicon oxide film or a silicon nitride film, or a laminated film including two or more of these films is used. When two or more films are used for the base film 21, the film formation rate of the base film 21 is hereinafter referred to as the thickness of the base film 21 divided by the time required for forming the base film. ing.
For forming the base film 21, a CVD method such as a remote plasma CVD method or a thermal CVD method, which is not damaged by exposure to plasma, is used. This is to prevent deformation due to roughness or warpage of the substrate due to damage of plasma or ions. Next, the remote plasma CVD method will be briefly described. The remote plasma CVD method is performed by using a parallel plate remote plasma CVD apparatus having the configuration shown in FIG. As shown in FIG. 3, in a vacuum chamber 11, a high-frequency application electrode 12 supplied with high-frequency power from a high-frequency power supply 13, a counter electrode 14 on which a substrate 10 is mounted, and a plasma separator 15 are arranged. And the source gas SiH via the plasma separator 15. ₄ Is supplied to the deposition area, and another reaction gas, O, is supplied from another gas supply port. ₂ And NO ₂ Are supplied to the plasma generation region. The gas in the vacuum chamber 11 is exhausted from an exhaust port 16 via a vacuum pump (not shown). The plasma generation region and the deposition region of this parallel plate remote plasma CVD apparatus are spatially separated by a plasma separator 15 having a large number of holes. Since the plasma generation region and the deposition region are separated by the plasma separator 15, the substrate is not damaged by the plasma. In addition, by using a plasma separator, intermediate species such as radicals can be diffused uniformly over a wide range. ¹² cm ^-2 It is also easy to form an insulating film (for example, a silicon oxide film) having a low fixed charge density of less than a large area.
[0014]
Next, an insulating film 22 is formed on the base film 21 (FIG. 1B). The insulating film 22 in contact with the crystallized silicon film 31 has a fixed charge density of 1 × 10 ¹² cm ^-2 It is necessary to set the thickness to be less than the above, and an insulating film such as a silicon oxide film or a silicon nitride film is used. Further, when the thickness of the insulating film 22 is small, the influence of the back channel formation due to the fixed charge of the base film 21 cannot be avoided.
When the insulating film 22 is formed, a CVD method such as a remote plasma CVD method or a thermal CVD method which is not damaged by exposure to plasma is used. This is because the base film 21 is prevented from being damaged by the plasma, and the characteristic of suppressing the diffusion of impurities in the glass substrate 1 is not deteriorated. It is desirable that the film thickness obtained by adding the film thicknesses of the base film 21 and the insulating film 22 is 200 nm or more in order to prevent impurities such as alkali metals contained in the glass substrate 1 from diffusing into the crystallized silicon film 31. In consideration of mass production, it is desirable to set the thickness to 5 μm or less.
Where 1 × 10 ¹² cm ^-2 In order to form a silicon oxide film having a fixed charge density as low as less than 5 by the CVD method, it is necessary to form the silicon oxide film at a low film formation rate. When the film formation rate is high, the intermediate product reaches the substrate in a state where a sufficient gas phase reaction does not occur, so that a silicon oxide film represented by a composition formula SiOx (x <2) is obtained, and the fixed charge density increases. It is because.
[0015]
On the other hand, the base film 21 is 1 × 10 ¹² cm ^-2 Since it is not necessary to have a low fixed charge density of less than 10 nm, the film can be formed by setting the film forming speed at a high speed. Therefore, the first insulating film is set to be thicker than the second insulating film so that the production time can be shortened. More specifically, it is desirable to set the thickness of the insulating film 22 to about 10 to 100 nm, and to set the film thickness of the base film 21 and the insulating film 22 to about 200 to 5000 nm. As a result, the time required for forming the laminated film including the base film 21 and the insulating film 22 can be significantly reduced.
In addition, if the base film 21 and the insulating film 22 are formed in the same device, the time required for the formation can be further reduced. To control the deposition rate in the same apparatus, use SiH ₄ It is easy by controlling the flow rate of a gas containing Si, as represented by TEOS and TEOS. Further, the film formation rate can be easily controlled by changing the pressure in the chamber during the formation.
Further, when forming the insulating film 22 after the formation of the base film 21, the film forming conditions may be continuously changed, and the base film 21 and the insulating film 22 may be formed continuously.
Next, as shown in FIG. 1C, an amorphous silicon film 3 is formed by a low pressure thermal CVD method or the like. The thickness of the amorphous silicon film is desirably about 10 to 100 nm in consideration of crystallization by laser annealing. Further, the amorphous silicon film 3 is crystallized by irradiating a laser beam to form a crystallized silicon film 31 as shown in FIG. For this crystallization, an excimer laser annealing device or the like is used.
[0016]
Subsequently, as shown in FIG. 1E, a gate insulating film 4 is formed on the crystallized silicon film 31 by a plasma CVD method or the like, and then patterned into a desired island shape by a dry etching method. After that, a metal film for a gate electrode is formed using a sputtering method or the like, and then patterned into a desired shape to form a gate electrode 5 (FIG. 2F).
Next, when an n-channel TFT is formed, the source / drain region 6 is formed by doping and activating phosphorus ions (FIG. 2G). When forming a p-channel TFT, the source / drain region 6 is formed by doping and activating boron ions. At this time, laser annealing is performed by an excimer laser annealing apparatus in order to activate the doped impurity ions at a low temperature. In the activation of the impurity ions, annealing may be performed at about 500 to 600 ° C., but laser annealing is suitable for an inexpensive glass substrate because warpage occurs. After that, hydrogen plasma processing is performed to terminate dangling bonds in silicon. This hydrogen plasma treatment is performed by introducing hydrogen gas into a plasma CVD apparatus and applying high-frequency power.
[0017]
Next, as shown in FIG. 2H, after the interlayer insulating film 7 is formed, contact holes are formed on the source / drain regions by dry etching or the like. As the interlayer insulating film 7, a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film and a silicon nitride film, or the like is used. Although not shown, a contact with the gate electrode is made immediately before or immediately after the step of forming a contact hole on the source and drain regions.
Finally, a metal film is deposited and patterned to form the source / drain electrodes 8, thereby obtaining the TFT shown in FIG. 2 (i). As a material used for the metal film for forming the source / drain electrodes, it is preferable to use a metal containing Si which is easily silicided in order to reduce contact resistance with the source / drain regions.
Through the above steps, the TFT manufacturing step is completed. However, an insulating film may be formed on the TFT in order to further suppress the influence of the external atmosphere.
[0018]
Here, using the insulating films 22 having different forming conditions, an n-channel TFT having undergone the processes of FIGS. 1 and 2 was manufactured, and the threshold voltage shift in the stress test was evaluated. The base film 21 of the manufactured TFT was a single layer of a silicon oxide film. In the TFT-A, the fixed charge density of the insulating film 22 was formed to be higher than the fixed charge density of the base film 21. On the other hand, in the TFT-B, the fixed charge density of the insulating film 22 was formed to be smaller than the fixed charge density of the base film 21.
[0019]
[Table 1]

The channel width of the evaluated element is 2 μm, and the channel length is 2 μm. In the applied stress conditions, the drain voltage was +5 V and the gate voltage was +2.5 V. FIG. 4 shows the relationship between the threshold voltage shift amount and time when the above-mentioned stress condition is applied. It can be seen that the shift amount of the threshold with respect to the stress application time is smaller in the TFT-B than in the TFT-A. The shift amount after 500,000 seconds was about 0.16 V for TFT-A and about 0.05 V for TFT-B.
[0020]
[Table 2]

[0021]
Next, a TFT formed by using the base film 21 as a single layer of a silicon oxide film and changing the thicknesses of the base film 21 and the insulating film 22 was evaluated. Here, the total thickness of the base film 21 and the insulating film 22 is fixed at 300 nm. Table 2 shows the thicknesses of the base film 21 and the insulating film 22, the fixed charge density, and the time required for forming a stacked film of the base film 21 and the insulating film 22 per substrate. The base film 21 and the insulating film 22 are formed in the same chamber of the same apparatus, and the film forming speed of the base film 21 and the insulating film 22 is ₄ It was controlled by changing the flow rate.
A stress test was performed on these TFTs under a stress condition of a drain voltage of +5 V and a gate voltage of +2.5 V. These TFTs showed almost the same threshold. In addition, it was found that the TFT had a high reliability with a threshold shift amount of 0.1 V or less in a stress test. Further, from Table 2, it was found that in the TFT in which the base film 21 was set to 250 nm and the insulating film 22 was set to 50 nm, the time required for forming the stacked film of the base film 21 and the insulating film 22 was short. Therefore, it was shown that the TFT having the laminated structure of the base film 21 and the insulating film 22 has high reliability and is excellent in mass productivity.
[0022]
[Second embodiment]
A second embodiment of the present invention will be described in detail with reference to FIGS.
First, as shown in FIG. 5A, a base film 21 is formed on an insulating substrate 1 made of glass or the like. As the base film 21, an insulating film such as a silicon oxide film or a silicon nitride film, or a laminated film formed by laminating two or more of these films is used.
For forming the base film 21, it is desirable to use a CVD method such as a remote plasma CVD method or a thermal CVD method that does not suffer damage due to exposure to plasma. This is for preventing deformation due to roughness or warpage of the substrate due to damage of plasma or ions.
[0023]
Next, an amorphous silicon film 23 is formed on the base film 21 (FIG. 5B). When forming this amorphous silicon film 23, it is desirable to use a remote plasma CVD method or a low pressure thermal CVD method. The thickness of the amorphous silicon film 23 is desirably about 10 to 30 nm in consideration of mass production.
Next, the amorphous silicon film 23 is oxidized to form a silicon oxide film 24. In this case, 1 × 10 ¹² cm ^-2 In order to form a silicon oxide film having a fixed charge density as low as less than 3, a method of irradiating oxygen radicals excited by a high frequency such as VHF or UHF is suitable (FIG. 5C).
It is desirable that the film thickness obtained by adding the base film 21 and the silicon oxide film 24 is set to be about 200 to 5000 nm. This is necessary to prevent impurities such as alkali metals contained in the insulating substrate 1 from diffusing into the crystallized silicon film 31.
[0024]
Next, as shown in FIG. 5D, an amorphous silicon film 3 is formed by a low pressure CVD method or the like. The thickness of the amorphous silicon film 3 is desirably about 10 to 100 nm in consideration of crystallization by laser annealing. Further, the amorphous silicon film 3 is crystallized by irradiating the amorphous silicon film 3 with a laser beam to form a crystallized silicon film 31 as shown in FIG. For this crystallization, an excimer laser annealing device or the like is used.
Subsequently, as shown in FIG. 6F, a gate insulating film 4 is formed on the crystallized silicon film 31 by a plasma CVD method or the like, and then patterned into a desired island shape by a dry etching method. Thereafter, a metal film is formed by a sputtering method or the like, and then patterned into a desired shape to form the gate electrode 5 (FIG. 6G).
Next, when an n-channel TFT is formed, the source / drain region 6 is formed by doping and activating phosphorus ions (FIG. 7 (h)). When forming a p-channel TFT, the source / drain region 6 is formed by doping and activating boron ions. At this time, laser annealing is performed by an excimer laser annealing apparatus in order to activate the doped impurity ions at a low temperature. After that, hydrogen plasma processing is performed to terminate dangling bonds in silicon. This hydrogen plasma treatment is performed by introducing hydrogen gas into a plasma CVD apparatus and applying high-frequency power.
[0025]
Next, as shown in FIG. 7I, after the interlayer insulating film 7 is formed, contact holes are formed on the source / drain regions by dry etching or the like. As the interlayer insulating film 7, a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film and a silicon nitride film, or the like is used. Although not shown in the figure, a contact with the gate electrode is made immediately before or immediately after the step of forming contact holes in the source and drain regions.
Finally, a metal film is deposited and patterned to form the source / drain electrodes 8, thereby obtaining the TFT shown in FIG. 7 (j). As the material used for the metal film for forming the source / drain electrodes, it is preferable to use a metal containing Si which is easily silicided in order to reduce contact resistance with the source / drain regions.
Through the above steps, the manufacturing process of the TFT is completed. However, in order to further suppress the influence of the external atmosphere, an insulating film may be formed thereon.
[0026]
[Third Embodiment]
A third embodiment of the present invention will be described in detail with reference to FIGS. As shown in FIG. 8A, a base film 2 is formed on an insulating substrate 1. The base film 2 is suitably an insulating film such as a silicon oxide film. Further, in order to prevent impurities such as an alkali metal contained in the insulating substrate 1 from diffusing into the crystallized silicon film 31, the thickness of the base film is desirably 200 nm or more. It is desirable to set so that Further, the fixed charge density of the base film 2 is 1 × 10 ¹² cm ^-2 It is formed so as to be less than. In forming the base film, it is preferable to use a CVD method such as a remote plasma CVD method or a thermal CVD method, which is not damaged by exposure to plasma. This is to prevent deformation due to roughness or warpage of the substrate due to damage of plasma or ions.
Next, as shown in FIG. 8B, an amorphous silicon film 3 is formed by a low pressure thermal CVD method or the like. The thickness of the amorphous silicon film 3 is desirably about 10 to 100 nm in consideration of crystallization. Further, the amorphous silicon film 3 is crystallized by irradiating a laser beam to form a crystallized silicon film 31 as shown in FIG. For this crystallization, an excimer laser annealing device or the like is used.
[0027]
Subsequently, as shown in FIG. 8D, a gate insulating film 4 is formed on the crystallized silicon film 31 by a plasma CVD method or the like, and then patterned into a desired island shape by a dry etching method. Thereafter, a metal film is formed using a sputtering method or the like, and then patterned into a desired shape to form the gate electrode 5 (FIG. 8E).
Next, when an n-channel TFT is formed, the source / drain region 6 is formed by doping and activating phosphorus ions (FIG. 9F). When forming a p-channel TFT, the source / drain region 6 is formed by doping and activating boron ions. At this time, laser annealing is performed by an excimer laser annealing apparatus in order to activate the doped impurity ions at a low temperature. After that, hydrogen plasma processing is performed to terminate dangling bonds in silicon. This hydrogen plasma treatment is performed by introducing hydrogen gas into a plasma CVD apparatus and applying high-frequency power.
[0028]
Next, as shown in FIG. 9G, after the interlayer insulating film 7 is formed, contact holes are formed on the source / drain regions by dry etching or the like. As the interlayer insulating film 7, a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film and a silicon nitride film, or the like is used. Although not shown in the figure, a contact with the gate electrode is made immediately before or immediately after the step of forming contact holes in the source and drain regions.
Finally, the source and drain electrodes 8 are formed by depositing a metal film and patterning the same, thereby obtaining the TFT shown in FIG. 9H. The material used for the source / drain electrodes 8 is a metal containing Si which is easily silicided in order to reduce the contact resistance with the source and drain regions.
Through the above steps, the manufacturing process of the TFT is completed. However, in order to further suppress the influence of the external atmosphere, an insulating film may be formed thereon.
Here, the formation method and the formation conditions of the base film were changed to form base films having various fixed charge densities, and the threshold voltage shift in the stress test of the n-channel TFT passed through the processes of FIGS. 8 and 9 was evaluated. . The channel width of the evaluated element is 2 μm, and the channel length is 2 μm. In the applied stress conditions, the drain voltage was +5 V and the gate voltage was +2.5 V.
[0029]
[Table 3]

As a result of the evaluation, the fixed charge density of the base film 2 was about 3 × 10 ¹² cm ^-2 The threshold voltage of the TFT-C shifted by 0.25 V 500,000 seconds after the application of the stress, while the fixed charge density of the base film 2 was about 3 × 10 ¹¹ cm ^-2 It has been found that the shift amount of the threshold value of TFT-D is as small as 0.1 V or less. That is, the fixed charge density of the base film 2 is 1 × 10 ¹² cm ^-2 It can be seen that TFTs as small as below have high reliability.
[0030]
[Fourth Embodiment]
A fourth embodiment of the present invention will be described in detail with reference to FIGS. As shown in FIG. 10A, a base film 2 is formed on an insulating substrate 1. The base film 2 is suitably a silicon oxide film. Further, in order to prevent impurities such as an alkali metal contained in the insulating substrate 1 from diffusing into the crystallized silicon film 31, the thickness of the base film is desirably 200 nm or more. It is desirable to set so that The fixed charge density of the base film 2 may be 1 × 10 ¹² cm ^-2 In some cases, it cannot be formed so as to be less than. At this time, the fixed charge density is 1 × 10 ¹² cm ^-2 By performing post-processing so as to reduce the thickness to less than that, a base film having desired characteristics is realized. The post-treatment of the silicon oxide film includes a heat treatment performed while applying a high pressure in a water vapor atmosphere and a treatment of applying a high frequency to an oxygen gas to irradiate oxygen radicals excited.
[0031]
Next, as shown in FIG. 10B, an amorphous silicon film 3 is formed by a low pressure thermal CVD method or the like. The thickness of the amorphous silicon film 3 is desirably about 10 to 100 nm in consideration of crystallization. Further, the amorphous silicon film 3 is irradiated with a laser beam to be crystallized to form a crystallized silicon film 31 as shown in FIG. For this crystallization, an excimer laser annealing device or the like is used.
Subsequently, as shown in FIG. 10D, a gate insulating film 4 is formed on the crystallized silicon film 31 by a plasma CVD method or the like, and then patterned into a desired island shape by a dry etching method. After that, a metal film is formed by a sputtering method or the like, and then patterned into a desired shape to form the gate electrode 5 (FIG. 10E).
Next, when an n-channel TFT is formed, the source / drain region 6 is formed by doping and activating phosphorus ions (FIG. 11F). In the case of forming a p-channel TFT, the source / drain region 6 is formed by doping and activating boron ions. At this time, in order to activate the doped impurity ions at a low temperature, laser annealing is performed by an excimer laser annealing apparatus or the like. After that, hydrogen plasma processing is performed to terminate dangling bonds in silicon. This hydrogen plasma treatment is performed by introducing a hydrogen gas into a plasma CVD apparatus and applying high-frequency power.
[0032]
Next, as shown in FIG. 11G, after the interlayer insulating film 7 is formed, contact holes are formed on the source / drain regions by dry etching or the like. As the interlayer insulating film 7, a silicon oxide film, a silicon nitride film, a stacked film of a silicon oxide film and a silicon nitride film, or the like is used. Although not shown, a contact with the gate electrode is made immediately before or immediately after the step of forming a contact hole in the source / drain region.
Finally, the TFT shown in FIG. 11H is obtained by forming the source / drain electrodes 8 by depositing and patterning a metal film. The material used for the source / drain electrodes 8 is a metal containing Si which is easily silicided in order to reduce the contact resistance with the source and drain regions.
Through the above steps, the manufacturing process of the TFT is completed. In order to further suppress the influence of the external atmosphere, an insulating film may be formed thereon.
[0033]
【Example】
Hereinafter, the present invention will be specifically described with reference to examples.
[First embodiment]
A method for manufacturing an n-channel TFT according to the first embodiment of the present invention will be described below in the order of steps shown in FIGS.
First, as shown in FIG. 1A, a single layer of a 250 nm silicon oxide film is used as a base film 21 on a glass substrate which is an insulating substrate 1, and a remote plasma CVD apparatus having the configuration shown in FIG. 3 is used. Was formed. When forming the base film 21, 700 sccm O ₂ Gas was introduced, high frequency power was applied at an excitation frequency of 60 MHz, and plasma was generated. On the other hand, 400 sccm He gas and 200 sccm SiH ₄ Gas was introduced to form a film. At this time, the fixed charge density of the base film 21 is about 3 × 10 ¹² cm ^-2 Met.
[0034]
Next, by the same apparatus, 400 sccm of He gas and 4 sccm of SiH ₄ A gas was introduced to form an insulating film 22 having a thickness of 50 nm (FIG. 1B). At this time, the fixed charge density of the insulating film 22 is about 3 × 10 ¹¹ cm ^-2 Met.
Next, as shown in FIG. 1C, a 60 nm amorphous silicon film 3 was formed by using a low pressure CVD method. At this time, Si ₂ H ₆ , He as a raw material. Further, as shown in FIG. 1D, crystallization was performed using a XeCl excimer laser annealing apparatus.
Subsequently, a gate insulating film 4 of 40 nm is formed using the remote plasma CVD apparatus shown in FIG. 3, and the gate insulating film 4 and the crystallized silicon film 31 are patterned into a desired island shape by a dry etching method or the like. (FIG. 1 (e)).
Thereafter, a WSi film having a thickness of 200 nm was deposited by a sputtering method, and was patterned into a desired shape by a dry etching method to form a gate electrode 5 (FIG. 2F).
[0035]
Next, the source / drain regions 6 were formed by doping with phosphorus ions using an ion doping apparatus (FIG. 2 (g)). Subsequently, annealing was performed using a XeCl laser annealing apparatus to activate phosphorus ions. Then, after introducing hydrogen gas into the plasma CVD apparatus, high-frequency power was applied at an excitation frequency of 13.56 MHz to generate plasma, and hydrogenation treatment was performed for one hour.
Next, as shown in FIG. 2H, a silicon oxide film having a thickness of 400 nm is formed as an interlayer insulating film 7 by a plasma CVD method, and then a contact hole is formed on the source / drain region 6 by dry etching or the like. did.
Next, an AlSi film was formed by a sputtering method. Further, patterning was performed to a desired shape by a dry etching method to form source / drain electrodes 8 (FIG. 2 (i)).
A stress test was performed on the TFT of this example fabricated in this manner under a stress condition of a drain voltage of +5 V and a gate voltage of +2.5 V. The amount of shift of the threshold value after 500,000 seconds of stress application was obtained. Has a high reliability of 0.1 V or less.
In this embodiment, a laminated structure of the base film 21 and the insulating film 22 is used, and the fixed charge density of the insulating film 22 in contact with the crystallized silicon film 31 as the active layer is set to 3 × 10 ¹¹ cm ^-2 By setting the base film 21 in contact with the insulating substrate to be thicker than the insulating film 22 at a high film forming rate, the time required for production was reduced.
By using the TFT according to the present invention and the manufacturing method thereof, the off-state current is reduced by suppressing the back channel, and as a result, not only a TFT having high reliability can be manufactured but also a TFT required for production is required. Time can be shortened.
[0036]
[Second embodiment]
Next, a method for manufacturing an n-channel TFT according to the second embodiment of the present invention will be described below in the order of steps shown in FIGS.
First, as shown in FIG. 5A, a 285 nm-thick silicon oxide film is formed as a base film 21 on a glass substrate as the insulating substrate 1 by using a remote plasma CVD apparatus having the configuration shown in FIG. did. When forming the base film 21, 700 sccm O ₂ Gas was introduced, high frequency power was applied at an excitation frequency of 60 MHz, and plasma was generated. On the other hand, 400 sccm He gas and 200 sccm SiH ₄ Gas was introduced to form a film. At this time, the fixed charge density of the underlayer is about 3 × 10 ¹² cm ^-2 Met.
[0037]
Next, as shown in FIG. 5B, a 15 nm amorphous silicon film 23 was deposited by using a low pressure CVD method. At this time, Si ₂ H ₆ , He as a raw material. Further, the amorphous silicon film 23 was irradiated with oxygen radicals excited by a microwave of 2.45 GHz to form a silicon oxide film 24 (FIG. 5C).
Next, as shown in FIG. 5D, a 60 nm amorphous silicon film 3 was formed by using a low pressure CVD method. At this time, Si ₂ H ₆ , He as a raw material. Further, as shown in FIG. 6E, crystallization was performed using a XeCl excimer laser annealing apparatus.
Subsequently, a gate insulating film 4 of 40 nm is formed using the remote plasma CVD apparatus shown in FIG. 3, and the gate insulating film 4 and the crystallized silicon film 31 are patterned into a desired island shape by a dry etching method or the like. (FIG. 6 (f)).
Thereafter, a WSi film having a thickness of 200 nm was deposited by a sputtering method, and was patterned into a desired shape by a dry etching method to form a gate electrode 5 (FIG. 6G).
[0038]
Next, phosphorus ions were doped using an ion doping apparatus to form source / drain regions 6 (FIG. 7 (h)). Subsequently, annealing was performed using a XeCl laser annealing apparatus to activate phosphorus ions. Then, after introducing hydrogen gas into the plasma CVD apparatus, high-frequency power was applied at an excitation frequency of 13.56 MHz to generate plasma, and hydrogenation treatment was performed for one hour.
Next, as shown in FIG. 7I, a silicon oxide film is formed to a thickness of 400 nm by a plasma CVD method to form an interlayer insulating film 7, and then contact holes are formed on the source and drain regions 6 by dry etching or the like. Was formed.
Next, an AlSi film was formed by a sputtering method. Further, the source / drain electrodes 8 were formed by patterning into a desired shape by a dry etching method (FIG. 7 (j)).
In the TFT of the present embodiment manufactured as described above, a stress test was performed under a stress condition of a drain voltage of +5 V and a gate voltage of +2.5 V. As in the first embodiment, a stress application of 50% was performed. It was found that the amount of shift of the threshold after 10,000 seconds was 0.1 V or less, indicating high reliability.
[0039]
(Third embodiment)
Next, a method of manufacturing an n-channel TFT as a third embodiment of the present invention will be described in the order of steps shown in FIGS.
First, as shown in FIG. 8A, a 300 nm-thick silicon oxide film is formed as a base film 2 on a glass substrate which is an insulating substrate 1 by using a remote plasma CVD apparatus having the configuration shown in FIG. did. When the base film 2 is formed, 700 sccm O ₂ Gas was introduced, high frequency power was applied at an excitation frequency of 60 MHz, and plasma was generated. On the other hand, 400 sccm He gas and 4 sccm SiH ₄ Gas was introduced to form a film. At this time, the fixed charge density of the underlayer is about 3 × 10 ¹¹ cm ^-2 Met.
Next, as shown in FIG. 8B, a 60 nm amorphous silicon film 3 was formed by using a low pressure CVD method. At this time, Si ₂ H ₆ , He as a raw material. Further, as shown in FIG. 8C, crystallization was performed using a XeCl excimer laser annealing apparatus.
Subsequently, a gate insulating film 4 of 40 nm is formed using the remote plasma CVD apparatus shown in FIG. 3, and the gate insulating film 4 and the crystallized silicon film 31 are patterned into a desired island shape by a dry etching method or the like. (FIG. 8D).
Thereafter, a 200 nm-thick WSi film was deposited by a sputtering method, and was patterned into a desired shape by a dry etching method to form a gate electrode 5 (FIG. 8E).
[0040]
Next, the source / drain regions 6 were formed by doping with phosphorus ions using an ion doping apparatus (FIG. 9F). Subsequently, annealing was performed using a XeCl laser annealing apparatus to activate phosphorus ions. Then, after introducing hydrogen gas into the plasma CVD apparatus, high-frequency power was applied at an excitation frequency of 13.56 MHz to generate plasma, and hydrogenation treatment was performed for one hour.
Next, as shown in FIG. 9G, a silicon oxide film is formed to a thickness of 400 nm by a plasma CVD method to form an interlayer insulating film 7, and then a contact hole is formed on the source / drain region by dry etching or the like. Formed.
Next, an AlSi film was formed by a sputtering method. Further, the source / drain electrodes 8 were formed by patterning into a desired shape by a dry etching method (FIG. 9H).
In the TFT of the present invention prepared according to this embodiment, a stress test was performed under a stress condition of a drain voltage of +5 V and a gate voltage of +2.5 V. As in the first and second embodiments, stress was applied. It was found that the shift amount of the threshold value after 500,000 seconds was 0.1 V or less, indicating high reliability.
This indicates that by using the TFT according to the present invention and the manufacturing method thereof, leakage of off-state current through the back channel is suppressed, and as a result, a highly reliable TFT can be manufactured. .
[0041]
(Fourth embodiment)
A method for manufacturing an n-channel TFT according to a fourth embodiment of the present invention will be described in the order of steps shown in FIGS.
First, a 300-nm-thick silicon oxide film was formed as a base film 2 on a glass substrate 1 serving as an insulating substrate by using a remote plasma CVD apparatus having the configuration shown in FIG. When the base film 2 is formed, 700 sccm O ₂ Gas was introduced, high frequency power was applied at an excitation frequency of 60 MHz, and plasma was generated. On the other hand, 400 sccm He gas and 200 sccm SiH ₄ Gas was introduced to form a film. At this time, the fixed charge density of the base film 2 is about 3 × 10 ¹² cm ^-2 Met.
[0042]
Thereafter, water vapor was introduced, the glass substrate was placed in a pressure vessel maintained at a pressure of about 2 MPa, and heat treatment at 400 ° C. was performed for 1 hour (FIG. 10A). The fixed charge density of the base film 2 after the high-pressure steam annealing is about 1 × 10 ¹¹ cm ^-2 Met.
Next, as shown in FIG. 10B, a 60 nm amorphous silicon film 3 was formed by using a low pressure CVD method. At this time, Si ₂ H ₆ , He as a raw material. Further, as shown in FIG. 10C, crystallization was performed using a XeCl excimer laser annealing apparatus.
Subsequently, a gate insulating film 4 of 40 nm is formed using the remote plasma CVD apparatus shown in FIG. 3, and the gate insulating film 4 and the crystallized silicon film 31 are patterned into a desired island shape by a dry etching method or the like. (FIG. 10D).
Thereafter, a WSi film having a thickness of 200 nm was deposited by a sputtering method, a metal film 5 for a gate electrode was formed, and was patterned into a desired shape by a dry etching method (FIG. 10E).
[0043]
Next, using an ion doping apparatus, phosphorus ions were doped to form source / drain regions 6 (FIG. 11F). Subsequently, annealing was performed using a XeCl laser annealing apparatus to activate phosphorus ions. Then, after introducing hydrogen gas into the plasma CVD apparatus, high-frequency power was applied at an excitation frequency of 13.56 MHz to generate plasma, and hydrogenation treatment was performed for one hour.
Next, as shown in FIG. 11 (g), after a silicon oxide film is formed to a thickness of 400 nm by a plasma CVD method to form an interlayer insulating film 7, contact holes are formed on the source / drain regions 6 by dry etching or the like. Was formed.
Next, an AlSi film was formed by a sputtering method. Further, patterning was performed into a desired shape by a dry etching method to form source / drain electrodes 8 (FIG. 11H).
In the TFT of the present invention manufactured according to the present embodiment, a stress test was performed under a stress condition of a drain voltage of +5 V and a gate voltage of +2.5 V. As a result, similar to the first, second, and third embodiments, It was also found that the amount of shift of the threshold value after 500,000 seconds of stress application was 0.1 V or less, indicating high reliability.
[0044]
Although the preferred embodiments have been described above, the present invention is not limited to the above embodiments, and each embodiment may be appropriately modified within the scope of the technical idea of the present invention. For example, in the first and third embodiments, the insulating film 22 and the base film 2 are formed at a constant film forming rate. The film formation rate may be gradually reduced during the process.
[0045]
【The invention's effect】
As described above, according to the present invention, off-current of a TFT formed over an insulating substrate can be suppressed, and a highly reliable TFT can be realized. Furthermore, by forming the base film thicker than the insulating film and at a higher film formation rate, the time required for production can be reduced, and a TFT with low off-current and high reliability can be manufactured with high throughput. Can be done if possible.
[Brief description of the drawings]
FIG. 1 is a part (part 1) of a process order sectional view of a first embodiment of a TFT manufacturing method according to the present invention.
FIG. 2 is a part (part 2) of a step-by-step cross-sectional view of the first embodiment of the method of manufacturing a TFT according to the present invention.
FIG. 3 is a schematic diagram of a remote plasma CVD apparatus used in the present invention.
FIG. 4 is an Id-Vg characteristic diagram of TFTs having different fixed charge densities of insulating films.
FIG. 5 is a part (part 1) of a process order sectional view of a second embodiment of a TFT manufacturing method according to the present invention.
FIG. 6 is a part (part 2) of a step-by-step cross-sectional view of the second embodiment of the method of manufacturing a TFT according to the present invention.
FIG. 7 is a part (part 3) of a step-by-step cross-sectional view of a second embodiment of a method of manufacturing a TFT according to the present invention.
FIG. 8 is a part (part 1) of a step-by-step cross-sectional view of a third embodiment of a method of manufacturing a TFT according to the present invention.
FIG. 9 is a part (part 2) of a step-by-step cross-sectional view of a third embodiment of a method of manufacturing a TFT according to the present invention.
FIG. 10 is a part (part 1) of a process order sectional view of a fourth embodiment of a TFT manufacturing method according to the present invention.
FIG. 11 is a part (part 2) of a step-by-step cross-sectional view of a fourth embodiment of a method of manufacturing a TFT according to the present invention.
[Explanation of symbols]
1 Insulating substrate
2 Underlayer
21 Underlayer
22 insulating film
23 Amorphous silicon film
24 Silicon oxide film
3 Amorphous silicon film
31 Crystallized silicon film
4 Gate insulating film
5 Gate electrode
6. Source / drain regions
7 Interlayer insulating film
8 Source / drain electrodes
10 Substrate
11 Vacuum chamber
12 High frequency application electrode
13 High frequency power supply
14 Counter electrode
15 Plasma separator
16 Exhaust port

Claims (18)

A lower base film formed on the insulating substrate, an insulating film formed on and in contact with the lower base film, and a crystallized silicon film formed on and in contact with the insulating film. A semiconductor device comprising:
A semiconductor device, wherein the fixed charge density of the insulating film is lower than the fixed charge density of the lower base film, and the fixed charge density of the insulating film is less than 1 × 10 ¹² cm ⁻² . 2. The semiconductor device according to claim 1, wherein the thickness of the insulating film is smaller than that of the lower base film. A lower base film formed on the insulating substrate, an insulating film formed on and in contact with the lower base film, and a crystallized silicon film formed on and in contact with the insulating film. A semiconductor device comprising:
The insulating substrate and the lower underlying film formed on the insulating substrate are formed by using a CVD method without being exposed to plasma, and the insulating film has a fixed charge density of the lower underlying film fixed. A semiconductor device formed using a CVD method so as to have a charge density lower than that of the semiconductor device. The film thickness of the insulating film is smaller than the lower base film, and a film forming speed when forming the insulating film is lower than a film forming speed when forming the lower base film. Item 4. The semiconductor device according to item 3. 5. The method according to claim 4, wherein a film forming speed when forming the insulating film and the lower base film is controlled by changing a flow rate of a gas containing Si or a pressure in a chamber during the formation. Semiconductor device. A lower base film formed on the insulating substrate, an insulating film formed on and in contact with the lower base film, and a crystallized silicon film formed on and in contact with the insulating film. A semiconductor device comprising:
The insulating substrate and the lower underlying film formed on the insulating substrate are formed by using a CVD method without being exposed to plasma, and the insulating film has a fixed charge density of the lower underlying film fixed. A semiconductor device formed by forming a silicon film and then oxidizing the silicon film so that the charge density is lower than the charge density. In a semiconductor device including a base film formed on an insulating substrate and a crystallized silicon film formed on and in contact with the base film, the fixed charge density of the base film is 1 × 10 ¹² cm ^<2> . In a semiconductor device including a base film formed on an insulating substrate and a silicon film formed on and in contact with the base film and crystallized, the insulating substrate is not exposed to plasma. A semiconductor device formed by using a CVD method such that the fixed charge density of the base film is less than 1 × 10 ¹² cm ⁻² . In a semiconductor device comprising a base film formed on an insulating substrate and a crystallized silicon film formed on and in contact with the base film, the base film may have a fixed charge density after film formation. Is a film that has been subjected to a post-treatment so that is less than 1 × 10 ¹² cm ⁻² . The semiconductor device according to claim 9, wherein the post-processing is heat treatment or irradiation with radicals. A lower base film formed on the insulating substrate, an insulating film formed on and in contact with the lower base film, and a crystallized silicon film formed on and in contact with the insulating film. A thin film transistor comprising: a gate insulating film formed on and in contact with the silicon film; and a gate electrode formed on and in contact with the gate insulating film,
A thin film transistor, wherein the fixed charge density of the insulating film is lower than the fixed charge density of the lower base film, and the fixed charge density of the insulating film is less than 1 × 10 ¹² cm ⁻² . A lower base film formed on the insulating substrate, an insulating film formed on and in contact with the lower base film, and a crystallized silicon film formed on and in contact with the insulating film. A method for manufacturing a semiconductor device comprising:
The insulating substrate and the lower underlying film formed on the insulating substrate are formed by using a CVD method without being exposed to plasma, and the insulating film has a fixed charge density of the lower underlying film. A method for manufacturing a semiconductor device, wherein the semiconductor device is formed using a CVD method so as to be smaller. The film thickness of the insulating film is smaller than the lower base film, and a film forming speed when forming the insulating film is lower than a film forming speed when forming the lower base film. 13. The method for manufacturing a semiconductor device according to item 12. 14. The semiconductor according to claim 13, wherein a film forming rate when forming the insulating film and the lower base film is controlled by changing a flow rate of a gas containing Si or a pressure in a chamber at the time of forming the film. Device manufacturing method. A lower base film formed on the insulating substrate, an insulating film formed on and in contact with the lower base film, and a crystallized silicon film formed on and in contact with the insulating film. A method for manufacturing a semiconductor device comprising:
Manufacturing a semiconductor device, wherein the insulating film is formed by forming a silicon film and oxidizing the silicon film so that the fixed charge density is lower than the fixed charge density of the lower base film. Method. A method for manufacturing a semiconductor device comprising: a base film formed on an insulating substrate; and a silicon film crystallized and formed on and in contact with the base film.
A method for manufacturing a semiconductor device, wherein the insulating substrate is formed by a CVD method without exposing the insulating substrate to plasma so that the fixed charge density of the base film is less than 1 × 10 ¹² cm ⁻² . A method for manufacturing a semiconductor device comprising: a base film formed on an insulating substrate; and a silicon film crystallized and formed on and in contact with the base film.
A method for manufacturing a semiconductor device, comprising: performing post-processing such that the fixed charge density of the underlying film is less than 1 × 10 ¹² cm ⁻² after forming the underlying film. 18. The method according to claim 17, wherein the post-treatment is a heat treatment or a treatment for radiating radicals.

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