JP2585118B2 - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistorInfo
- Publication number
- JP2585118B2 JP2585118B2 JP2026824A JP2682490A JP2585118B2 JP 2585118 B2 JP2585118 B2 JP 2585118B2 JP 2026824 A JP2026824 A JP 2026824A JP 2682490 A JP2682490 A JP 2682490A JP 2585118 B2 JP2585118 B2 JP 2585118B2
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- gate insulating
- insulating film
- film transistor
- gas
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000010409 thin film Substances 0.000 title claims description 30
- 238000000034 method Methods 0.000 title claims description 22
- 238000004519 manufacturing process Methods 0.000 title claims description 17
- 239000010408 film Substances 0.000 claims description 58
- 239000007789 gas Substances 0.000 claims description 26
- 238000004544 sputter deposition Methods 0.000 claims description 18
- 239000011261 inert gas Substances 0.000 claims description 6
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 239000000758 substrate Substances 0.000 description 16
- 239000004065 semiconductor Substances 0.000 description 14
- 239000013078 crystal Substances 0.000 description 9
- 125000004429 atom Chemical group 0.000 description 7
- 238000006243 chemical reaction Methods 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 239000011521 glass Substances 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 238000000206 photolithography Methods 0.000 description 4
- CBENFWSGALASAD-UHFFFAOYSA-N Ozone Chemical compound [O-][O+]=O CBENFWSGALASAD-UHFFFAOYSA-N 0.000 description 3
- CDBYLPFSWZWCQE-UHFFFAOYSA-L Sodium Carbonate Chemical compound [Na+].[Na+].[O-]C([O-])=O CDBYLPFSWZWCQE-UHFFFAOYSA-L 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 3
- GQPLMRYTRLFLPF-UHFFFAOYSA-N Nitrous Oxide Chemical compound [O-][N+]#N GQPLMRYTRLFLPF-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000001552 radio frequency sputter deposition Methods 0.000 description 2
- 238000005477 sputtering target Methods 0.000 description 2
- 239000013077 target material Substances 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 239000005388 borosilicate glass Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009792 diffusion process Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 230000004807 localization Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000001755 magnetron sputter deposition Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 239000001272 nitrous oxide Substances 0.000 description 1
- 239000003921 oil Substances 0.000 description 1
- 125000004430 oxygen atom Chemical group O* 0.000 description 1
- 239000010453 quartz Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 239000007858 starting material Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
Landscapes
- Formation Of Insulating Films (AREA)
- Physical Deposition Of Substances That Are Components Of Semiconductor Devices (AREA)
- Thin Film Transistor (AREA)
Description
【発明の詳細な説明】 「産業上の利用分野」 本発明は、液晶ディスプレー，イメージセンサー等に
適用可能な薄膜トランジスタの作製方法に関する。Description: TECHNICAL FIELD The present invention relates to a method for manufacturing a thin film transistor applicable to a liquid crystal display, an image sensor, and the like.
「従来の技術」 最近、化学的気相法等によって、作製された非単結晶
半導体薄膜を利用した薄膜トランジスタが注目されてい
る。[Background Art] In recent years, a thin film transistor using a non-single-crystal semiconductor thin film manufactured by a chemical vapor deposition method or the like has attracted attention.
この薄膜トランジスタは、絶縁性基板上に前述の如く
化学的気相法等を用いて形成されるので、その作製雰囲
気温度が最高で450℃程度と低温で形成でき、安価なソ
ーダガラス，ホウケイ酸ガラス等を基板として用いるこ
とができる。Since this thin film transistor is formed on an insulating substrate by using the chemical vapor deposition method as described above, its fabrication atmosphere temperature can be formed at a low temperature of about 450 ° C. at the highest, and it is inexpensive soda glass and borosilicate glass. Can be used as a substrate.
この薄膜トランジスタは電界効果型であり、いわゆる
MOSFETと同様の機能を有しているが、前述の如く安価な
絶縁性基板上に低温で形成でき、さらにその作製する最
大面積は薄膜半導体を形成する装置の寸法にのみ限定さ
れるもので、容易に大面積基板上にトランジスタを作製
できるという利点を持っていた。このため多量の画素を
持つマトリクス構造の液晶ディスプレーのスイッチング
素子や一次元又は二次元のイメージセンサ等のスイッチ
ング素子として極めて有望である。This thin film transistor is a field effect type, and is called a so-called thin film transistor.
Although it has the same function as a MOSFET, it can be formed at a low temperature on an inexpensive insulating substrate as described above, and the maximum area to be manufactured is limited only to the dimensions of a device for forming a thin film semiconductor, This has an advantage that a transistor can be easily manufactured over a large-area substrate. For this reason, it is very promising as a switching element of a liquid crystal display having a matrix structure having a large number of pixels or a one-dimensional or two-dimensional image sensor.
また、この薄膜トランジスタを作製するにはすでに確
立された技術であるフォトリソグラフィーが応用可能
で、いわゆる微細加工が可能であり、IC等と同様に集積
化を図ることも可能であった。In addition, photolithography, which is an established technique, can be applied to fabricate this thin film transistor, so-called fine processing can be performed, and integration can be achieved in the same manner as ICs and the like.
この従来より知られたTFTの代表的な構造を第２図に
概略的に示す。FIG. 2 schematically shows a typical structure of this conventionally known TFT.
（20）はガラスよりなる絶縁性基板であり、（21）は
非単結晶半導体よりなる薄膜半導体、（22），（23）は
ソースドレイン領域で、（24），（25）はソースドレイ
ン電極、（26）はゲイト絶縁膜で（27）はゲイト電極で
あります。(20) is an insulating substrate made of glass, (21) is a thin film semiconductor made of a non-single-crystal semiconductor, (22) and (23) are source / drain regions, (24) and (25) are source / drain electrodes , (26) is the gate insulating film and (27) is the gate electrode.
このように構成された薄膜トランジスタはゲイト電極
（27）に電圧を加えることにより、ソースドレイン（2
2），（23）間に流れる電流を調整するものでありま
す。By applying a voltage to the gate electrode (27), the thin film transistor having the above-described structure allows the source / drain (2
Adjusts the current flowing between 2) and (23).
このような薄膜トランジスタに用いられるゲイト酸化
膜は、半導体材料の直接熱酸化法，減圧または常圧下で
の熱CVD法等によって作製されていた。A gate oxide film used for such a thin film transistor has been manufactured by a direct thermal oxidation method of a semiconductor material, a thermal CVD method under reduced pressure or normal pressure, or the like.
この薄膜トランジスタの素子特性は、チャネルが形成
される部分の半導体膜の膜質と、ゲイト絶縁膜の特性に
大きく左右される。The element characteristics of the thin film transistor largely depend on the film quality of the portion of the semiconductor film where the channel is formed and the characteristics of the gate insulating film.
特に良好な膜質のゲイト絶縁膜を作製することが強く
望まれていた。It has been strongly desired to produce a gate insulating film having particularly good film quality.
前述の方法により、作製されたゲイト絶縁膜を薄膜ト
ランジスタに用いて良好な素子特性を得るためには、ゲ
イト絶縁膜の作製温度を600℃付近に設定する必要があ
り、そのため結晶化ガラス，石英ガラス等の非常に高価
な基板材料を使用しなければならなかった。すなわち、
450℃程度の低温プロセスで作製でき、その結果安価な
基板材料（ゾーダガラス等）を使用できる薄膜トランジ
スタの特徴をなくすものであった。In order to obtain good device characteristics by using the gate insulating film manufactured by the above-described method for a thin film transistor, it is necessary to set the manufacturing temperature of the gate insulating film to around 600 ° C. Very expensive substrate materials, such as, had to be used. That is,
A thin film transistor which can be manufactured by a low-temperature process of about 450 ° C. and can use an inexpensive substrate material (such as soda glass) is eliminated.
また低温にてゲイト絶縁物を作製する方法として、プ
ラズマCVD法やスパッタリング法が知られているが、い
ずれの方法においても、出発材料中に含まれ、かつ反応
中にも存在する原子（例えばAr,Cl,F,N等）が、ゲイト
絶縁膜中に多数取り込み膜中の固定電荷発生の原因とな
る。さらに、反応中に存在する原子のイオン種が、薄膜
トランジスタの活性層表面に衝突し、ゲイト絶縁膜と活
性層との界面近傍に界面準位を形成し、いずれの場合も
良好な薄膜トランジスタの特性を得るに至っていない。In addition, as a method for producing a gate insulator at a low temperature, a plasma CVD method or a sputtering method is known. In any of the methods, atoms (for example, Ar) contained in a starting material and also present during a reaction. , Cl, F, N, etc.) are incorporated in the gate insulating film and cause generation of fixed charges in the film. Furthermore, the ionic species of the atoms present during the reaction collide with the surface of the active layer of the thin film transistor, forming an interface state near the interface between the gate insulating film and the active layer. I haven't gotten it.
さらに、光CVD法によってゲイト絶縁膜を作製するこ
とが試みられており、熱酸化膜とほぼ同様レベルの２×
1010eV-1cm-2程度の界面準位密度が得られているが、膜
作製に必要とする時間が長く（成膜速度が非常に遅い）
工業的な応用には不向きであった。Further, an attempt has been made to fabricate a gate insulating film by a photo-CVD method.
Although an interface state density of about 10 10 eV -1 cm -2 has been obtained, the time required for film formation is long (the film formation speed is very slow)
It was not suitable for industrial applications.
「本発明の目的」 本発明は、従来の問題点を解決する方法であり、良好
な特性の薄膜トランジスタを低温プロセスで作製する方
法を提供するものであります。"Object of the present invention" The present invention is a method for solving the conventional problems, and provides a method for producing a thin film transistor having good characteristics by a low-temperature process.
「発明の構成」 本発明の構成は、薄膜トランジスタを作製する工程に
おいて、ゲイト絶縁膜の作製をスパッタリング法にて行
ない、さらにスパッタリングに用いる気体における不活
性ガスの割合を50％以下、すなわち酸化性ガスの方が不
活性ガスより多い雰囲気下でスパッタリングを行ないゲ
イト絶縁膜を作製することを特徴とするものでありま
す。[Structure of the Invention] In the structure of the present invention, in the step of manufacturing a thin film transistor, a gate insulating film is manufactured by a sputtering method, and the ratio of an inert gas in a gas used for sputtering is 50% or less, that is, an oxidizing gas. The method is characterized in that sputtering is performed in an atmosphere more than the inert gas to produce a gate insulating film.
本発明に用いられるスパッタリング法としては、RFス
パッタ，直流スパッタ等いずれの方法も使用できるが、
スパッタリングターゲットが導電率の悪い酸化物，例え
ばSiO2等の場合、安定した放電を持続するためにRFマグ
ネトロンスパッタ法を用いることが好ましい。As the sputtering method used in the present invention, any method such as RF sputtering and DC sputtering can be used,
When the sputtering target is an oxide having poor conductivity, for example, SiO 2, it is preferable to use the RF magnetron sputtering method in order to maintain stable discharge.
また酸化性気体としては酸素，オゾン，亜酸化窒素等
を挙げることができるが、特にオゾンや酸素を使用した
場合、ゲイト絶縁膜中に取り込まれる不用な原子が存在
しないので、非常に良好なゲイト絶縁膜を得ることがで
きた。Examples of the oxidizing gas include oxygen, ozone, and nitrous oxide. Particularly, when ozone or oxygen is used, there is no unnecessary atom incorporated in the gate insulating film. An insulating film was obtained.
またオゾンは、Ｏラジカルに分解されやすく、単位体
積当りのＯラジカル発生量が多く、成膜速度向上に寄与
することができる。In addition, ozone is easily decomposed into O radicals, generates a large amount of O radicals per unit volume, and can contribute to improving the film formation rate.
従来より行なわれてきたスパッタリング法によるゲイ
ト絶縁膜の作製においては、不活性ガスであるArが酸素
ガスより多く、通常は酸素が０〜10体積％程度で作製さ
れていた。すなわち、従来から行なわれていたスパッタ
は、Arがターゲット材料をたたき成膜することが当然の
如く考えられていた。これはAr等の不活性ガスがターゲ
ット材料をたたき出す確率（スパッタリングイールド）
が高い為であった。本発明者らは、スパッタリング法に
よって作製されたゲイト絶縁膜の特性について鋭意検討
した結果、ゲイト絶縁膜の性能を示す活性層とゲイト絶
縁膜界面の界面準位、及びゲイト絶縁膜中の固定電荷の
数を反映するフラットバンド電圧の理想値よりのズレ
が、スパッタリング時のArガスの割合に大きく依存する
ことが判明した。In the production of a gate insulating film by a conventional sputtering method, Ar, which is an inert gas, is larger than oxygen gas, and oxygen is usually produced at about 0 to 10% by volume. That is, it has naturally been considered that Ar sputtering hits the target material to form a film in the conventionally performed sputtering. This is the probability that an inert gas such as Ar will strike the target material (sputtering yield)
Was high. The present inventors have conducted intensive studies on the characteristics of the gate insulating film manufactured by the sputtering method, and found that the interface state between the active layer and the gate insulating film, which indicates the performance of the gate insulating film, and the fixed charge in the gate insulating film. It has been found that the deviation of the flat band voltage from the ideal value, which reflects the number of GaAs, greatly depends on the ratio of Ar gas during sputtering.
第３図に、気体に占めるArガスの割合と界面準位の関
係を示す。Arガス100％に比べ、Arガスの量を酸化性ガ
ス（第３図では酸素）の量より少なく、50％以下とする
と界面準位密度が約1/10程度に減っていることがわか
り、Arガスの割合が20％以下の場合は、ほぼ一定の低い
界面準位の値となっている。FIG. 3 shows the relationship between the ratio of the Ar gas in the gas and the interface state. Compared to 100% Ar gas, the amount of Ar gas is smaller than the amount of oxidizing gas (oxygen in Fig. 3), and if it is 50% or less, the interface state density is reduced to about 1/10. When the ratio of Ar gas is 20% or less, the value of the interface state is almost constant and low.
第４図にスパッタリング時の気体の占めるArガスの割
合とフラットバンド電圧のズレ量との関係を示す。FIG. 4 shows the relationship between the ratio of the Ar gas occupied by the gas during sputtering and the deviation of the flat band voltage.
フラットバンド電圧の理想電圧からのズレは、Arガス
の割合に大きく依存し、Arガスの割合が20％以下の場
合、ほぼ理想電圧に近い値となっている。The deviation of the flat band voltage from the ideal voltage largely depends on the ratio of the Ar gas, and when the ratio of the Ar gas is 20% or less, the value is almost close to the ideal voltage.
これらのことより、スパッタリングにより成膜時に反
応雰囲気下に存在する活性化されたAr原子が、ゲイト絶
縁膜の膜質に影響を与えており、できるだけAr原子の存
在を減らしてスパッタリング成膜することが望ましいこ
とが判明した。From these facts, activated Ar atoms present in the reaction atmosphere at the time of film formation by sputtering affect the film quality of the gate insulating film, and it is possible to perform sputtering film formation by reducing the presence of Ar atoms as much as possible. It turned out to be desirable.
その理由としては、Arイオン，または活性化されたAr
原子が、界面に衝突して界面での欠陥を形成し、更にゲ
イト絶縁膜に取り込まれて固定電荷発生の原因となって
いることが考えられる。The reason is that Ar ion or activated Ar
It is considered that atoms collide with the interface to form defects at the interface, and are further taken into the gate insulating film to cause generation of fixed charges.
また酸素原子は、Ar原子と比較して質量が軽いため、
界面近傍に衝突しても、重大なダメージを界面付近に与
えることはない。さらに膜中には、主構成成分なので取
り込まれても、固定電荷発生の原因となることはない。Oxygen atoms are lighter in mass than Ar atoms,
Collision near the interface does not cause significant damage near the interface. Furthermore, even if it is taken into the film as a main constituent, it does not cause generation of fixed charges.
また、スパッタリングに用いる材料は全て高純度のも
のが好ましい、例えば、スパッタリングターゲットは4N
以上の合成石英または、LSIの基板に使用される程度に
高純度のシリコン等が最も好ましい。Further, it is preferable that all materials used for sputtering have high purity.For example, the sputtering target is 4N.
The above-described synthetic quartz or silicon having a purity high enough to be used for an LSI substrate is most preferable.
即ち、ゲイト絶縁膜内に存在する不純物を極力少なく
する必要がある。同様にスパッタリングに使用するガス
も高純度（5N以上）の物を用い、不純物がゲイト絶縁膜
中に混入することを極力さけた。That is, it is necessary to minimize impurities present in the gate insulating film. Similarly, a gas used for sputtering is of high purity (5N or more), so that impurities are prevented from entering the gate insulating film as much as possible.
以下に実施例により本発明を詳しく説明する。 Hereinafter, the present invention will be described in detail with reference to examples.
「実施例１」 第１図に本発明の薄膜トランジスタの作製工程を示
す。Example 1 FIG. 1 shows a process for manufacturing a thin film transistor of the present invention.
本実施例においては、基板材料として安価なソーダガ
ラスを基板（１）として用いた。この基板（１）上に公
知のプラズマCVD法により、Ｉ型の非単結晶半導体層
（２）をアイランド状に形成し、第１図（Ａ）の状態を
得る。In this example, inexpensive soda glass was used as the substrate (1) as the substrate material. An I-type non-single-crystal semiconductor layer (2) is formed in an island shape on the substrate (1) by a known plasma CVD method to obtain a state shown in FIG.
その作製条件は以下の通りであった。 The manufacturing conditions were as follows.
基板温度 350℃ 反応時圧力 0.06Torr Rfパワー（13.56MHz） 100W 使用ガス SiH4 膜厚 2000Å またアイランド状に形成する際本実施例ではメタルマ
スクを使用したが、公知のフォトリソグラフィー技術を
使用しても良い。Substrate temperature 350 ° C Reaction pressure 0.06 Torr Rf power (13.56 MHz) 100W Gas used SiH 4 film thickness 2000Å Also, when forming an island, a metal mask was used in this example, but a known photolithography technique was used. Is also good.
次に、第１図（Ｂ）に示すようにエキシマレーザ光
（３）を、非単結晶半導体（２）の素子領域付近に照射
して結晶化し、粒径サイズの大きい多結晶状態、または
ほぼ素子領域に等しいサイズの単結晶状態とする。この
時のエキシマレーザ光の照射条件を以下に示す。Next, as shown in FIG. 1B, an excimer laser beam (3) is irradiated near the element region of the non-single-crystal semiconductor (2) to be crystallized, and a polycrystalline state having a large grain size, or almost A single crystal state having a size equal to the element region is obtained. The irradiation conditions of the excimer laser light at this time are shown below.
レーザ光波長 284nm（KrF） 照射エネルギー量 200mJ/cm2 ショット数 10 光パルス巾 30ns 次に、公知のプラズマCVD法により、Ｎ型の非単結晶
半導体層を全面に形成した後、公知のフォトリソグラフ
ィー技術により、ソース，ドレイン領域（４），（５）
を残すようにパターニングし、第１図（Ｃ）の状態を得
た。Laser light wavelength 284 nm (KrF) Irradiation energy amount 200 mJ / cm 2 Number of shots 10 Light pulse width 30 ns Next, an N-type non-single-crystal semiconductor layer is formed on the entire surface by a known plasma CVD method, and then a known photolithography is performed. Source and drain regions (4), (5)
To obtain the state shown in FIG. 1 (C).
このＮ型非単結晶半導体層の作製条件を以下に示す。 The conditions for forming the N-type non-single-crystal semiconductor layer are described below.
基板温度 250℃ 反応時圧力 0.05Torr Rfパワー（13.56MHz） 150W 使用ガス SiH4＋PH3＋H2 膜厚 500Å このＮ型非単結晶半導体としては、多量のH2ガスに希
釈し、かつRfパワーを高くに微結晶化させ、電気抵抗の
低い膜を使用した。Substrate temperature 250 ° C Reaction pressure 0.05 Torr Rf power (13.56 MHz) 150 W Gas used SiH 4 + PH 3 + H 2 film thickness 500Å This N-type non-single-crystal semiconductor is diluted into a large amount of H 2 gas and the Rf power is reduced. A film having a high microcrystallinity and a low electric resistance was used.
次にRfスパッタリング法により、ゲイト絶縁膜（６）
を700Å形成し、その後ソースドレインのコンタクト用
穴（７），（８）をフォトリソグラフィー技術により形
成し、第１図（Ｄ）の状態を得た。Next, gate insulating film (6) by Rf sputtering method
Then, contact holes (7) and (8) for source / drain were formed by photolithography to obtain the state shown in FIG. 1 (D).
このゲイト絶縁膜の作製条件を以下に示す。 The conditions for forming the gate insulating film are described below.
ターゲット SiO2 99.99％ 反応ガス O2 100％ 反応圧力 0.5Pa Rfパワー 500W 基板温度 100℃ 基板ターゲット間距離 150mm このゲイト絶縁膜の特性を以下に示す。Target SiO 2 99.99% Reaction gas O 2 100% Reaction pressure 0.5Pa Rf power 500W Substrate temperature 100 ° C Distance between substrate targets 150mm The characteristics of this gate insulating film are shown below.
1/10HFエッチング速度 67nm/min 絶縁耐圧 9.1MV/cm 界面準位 2.5×1010eV-1cm-2 次に、ゲイト電極（９），ソース電極（10），ドレイ
ン（11）電極をAlにより形成し、薄膜トランジスタを完
成させた。1 / 10HF etching rate 67 nm / min Dielectric strength 9.1 MV / cm Interface state 2.5 × 10 10 eV -1 cm -2 Next, the gate electrode (9), source electrode (10), and drain (11) electrode are made of Al And completed the thin film transistor.
このような薄膜トランジスタのスレショルド電圧（Vt
h）は1V以下とすることができ、Ar100％で形成された同
様の素子のVthが1V以下にはならなかった。The threshold voltage (Vt) of such a thin film transistor
h) can be 1 V or less, and the Vth of a similar device formed of 100% Ar does not become 1 V or less.
また、ゲイト電圧を一定時間かけ続けた後のVthの変
化率は、熱酸化によって形成されたゲイト絶縁膜の変化
率とほぼ同様であり、1000時間後にわずか0.3程度しか
変化しておらず、ゲイト絶縁膜（６）と非単結晶半導体
（２）界面及び、ゲイト絶縁膜中に局在順位がほとんど
形成されていないことがわかる。The rate of change of Vth after the gate voltage is applied for a certain period of time is almost the same as the rate of change of the gate insulating film formed by thermal oxidation. It can be seen that almost no localization order is formed at the interface between the insulating film (6) and the non-single-crystal semiconductor (2) and in the gate insulating film.
また、この本発明の薄膜トランジスタの移動度は100c
m2/V・Ｓが得られた。The mobility of the thin film transistor of the present invention is 100 c
m 2 / V · S was obtained.
本実施例においては、ゲイト絶縁膜形成時のArガスの
割合を０としたが、約20％以下の割合でArガスが存在す
る条件下でゲイト絶縁膜を作製するなら薄膜トランジス
タの特性上特に問題は生じなかった。In this embodiment, the ratio of the Ar gas at the time of forming the gate insulating film is set to 0. However, if the gate insulating film is manufactured under the condition that the Ar gas is present at a ratio of about 20% or less, there is a particular problem in the characteristics of the thin film transistor. Did not occur.
ただし、Arの割合を０とした方がより特性のよい薄膜
トランジスタを得ることができた。However, when the ratio of Ar was set to 0, a thin film transistor having better characteristics could be obtained.
またArガスを20％以下の割合で混合する場合には、タ
ーゲットと基板との距離をArガス０％で作製する場合よ
り長くすることができ、ほぼ同様の膜質のゲイト絶縁膜
を得ることが可能である。In addition, when Ar gas is mixed at a ratio of 20% or less, the distance between the target and the substrate can be made longer than in the case where Ar gas is formed at 0%, and a gate insulating film having almost the same film quality can be obtained. It is possible.
さらにArガス20％以下の割合で混合して形成したゲイ
ト絶縁膜に対し、エキシマレーザ光を照射し、フラッシ
ュアニールを施し、膜中に取り込れたArを除去し、膜中
の固定電荷の発生原因を取り除くことも可能であった。Further, the gate insulating film formed by mixing at a ratio of Ar gas of 20% or less is irradiated with excimer laser light, flash annealing is performed to remove Ar trapped in the film, and fixed charge in the film is removed. It was also possible to eliminate the cause.
この時、エキシマレーザ光より膜に与えるエネルギー
量を多くし、ゲイト絶縁膜のアニールと同時にその下の
半導体層の結晶化を行なうこともでき、作製工程数を減
らす上で非常に有効な手段であった。At this time, it is possible to increase the amount of energy given to the film from the excimer laser light, and simultaneously anneal the gate insulating film and crystallize the underlying semiconductor layer. This is a very effective means for reducing the number of manufacturing steps. there were.
本実施例において、薄膜トランジスタを作製するプロ
セスに使用した真空装置の排気手段としては全てオイル
等の排気系からの逆拡散のないターボ分子ポンプを使用
し、ゲイト絶縁膜及びその他の半導体層の膜特性に影響
を及ぼさないようにした。In this embodiment, all the exhaust means of the vacuum device used in the process of manufacturing the thin film transistor use a turbo molecular pump without back diffusion from an exhaust system such as oil, and the film characteristics of the gate insulating film and other semiconductor layers are used. Was not affected.
「効果」 本発明方法により、低温プロセスのみで非常に特性の
良い薄膜トランジスタを容易に形成することができた。[Effect] According to the method of the present invention, a thin film transistor having very good characteristics could be easily formed only by a low-temperature process.
またゲイト絶縁膜中に存在する固定電荷の原因を減ら
すことができたので、長期的な使用において特性変化の
少ない信頼性の良い薄膜トランジスタを提供することが
可能となった。Further, since the cause of the fixed charge existing in the gate insulating film could be reduced, it was possible to provide a highly reliable thin film transistor with little characteristic change in long-term use.
第１図は本発明の作製工程を示す。 第２図は一般的な薄膜トランジスタの概略図を示す。 第３図はゲイト絶縁膜作製時におけるArガスの割合と界
面準位密度の関係を示す。 第４図はゲイト絶縁膜作製時におけるArガスの割合とフ
ラットバンド電圧のズレ量との関係を示す。FIG. 1 shows a manufacturing process of the present invention. FIG. 2 is a schematic view of a general thin film transistor. FIG. 3 shows the relationship between the ratio of Ar gas and the interface state density during the fabrication of the gate insulating film. FIG. 4 shows the relationship between the ratio of Ar gas and the amount of deviation of the flat band voltage during the production of the gate insulating film.
Claims (1)
て、ゲイト絶縁膜の作製を酸化性気体と不活性気体との
混合気体であって、不活性気体が20体積％以下の割合で
含まれる雰囲気下において、スパッタリング法によって
形成されることを特徴とする薄膜トランジスタの作製方
法。In a step of manufacturing a thin film transistor, a gate insulating film is manufactured in an atmosphere containing a mixed gas of an oxidizing gas and an inert gas and containing the inert gas at a ratio of 20% by volume or less. A method for manufacturing a thin film transistor, which is formed by a sputtering method.
Priority Applications (7)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2026824A JP2585118B2 (en) | 1990-02-06 | 1990-02-06 | Method for manufacturing thin film transistor |
| EP91101533A EP0445535B1 (en) | 1990-02-06 | 1991-02-05 | Method of forming an oxide film |
| DE69107101T DE69107101T2 (en) | 1990-02-06 | 1991-02-05 | Method of making an oxide film. |
| KR1019910001992A KR950010282B1 (en) | 1990-02-06 | 1991-02-06 | Oxide film formation method |
| US07/966,607 US6586346B1 (en) | 1990-02-06 | 1992-10-26 | Method of forming an oxide film |
| US10/459,430 US6960812B2 (en) | 1990-02-06 | 2003-06-12 | Method of forming an oxide film |
| US11/229,651 US7301211B2 (en) | 1990-02-06 | 2005-09-20 | Method of forming an oxide film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2026824A JP2585118B2 (en) | 1990-02-06 | 1990-02-06 | Method for manufacturing thin film transistor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH03231472A JPH03231472A (en) | 1991-10-15 |
| JP2585118B2 true JP2585118B2 (en) | 1997-02-26 |
Family
ID=12204024
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2026824A Expired - Fee Related JP2585118B2 (en) | 1990-02-06 | 1990-02-06 | Method for manufacturing thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2585118B2 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH01149476A (en) * | 1987-12-07 | 1989-06-12 | Matsushita Electric Ind Co Ltd | Manufacture of thin film transistor |
| JPH0290568A (en) * | 1988-09-28 | 1990-03-30 | Nippon Telegr & Teleph Corp <Ntt> | Manufacture of thin film transistor |
| JPH0393273A (en) * | 1989-09-06 | 1991-04-18 | Seiko Epson Corp | Method for manufacturing thin film semiconductor devices |
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- 1990-02-06 JP JP2026824A patent/JP2585118B2/en not_active Expired - Fee Related
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