JP2004318254A - Testing device for safety protection measuring device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce labor and time used in a test for soundness confirmation or the like of a highly integrated logic integrated circuit used in a safety protection system of a plant. <P>SOLUTION: All test patterns are sequentially inputted in the logic integrated circuit 3 which is the test target from application software of a test pattern input/output controller 4 composed of a PC, its output is read by the test pattern input/output controller 4, and an output pattern 6 is created. By comparing the output pattern with a simulation result, soundness of a logic integrated circuit function is evaluated. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test apparatus for a safety protection measurement device used for a safety protection function of a plant in a nuclear power plant or the like, and particularly to a verification means for a logic integrated circuit that is used in the safety protection measurement device and processes digital signals.
[0002]
[Prior art]
2. Description of the Related Art In a nuclear power plant or the like, a safety protection system is provided in order to prevent or suppress the occurrence of an abnormality that may impair the safety of the plant or the occurrence of an abnormality.
[0003]
The safety protection measuring device used in the safety protection system inputs process signals from sensors for detecting multiple process signals such as temperature, pressure, and furnace output indicating the state of the plant, and outputs information according to the purpose. Process the signal, compare the processed information with a predetermined set value, if it exceeds the set value, determine that an abnormality has occurred or its sign, and output an operation signal such as a trip signal to the plant protection device Has a function.
[0004]
As the instrumentation circuit of the safety protection measurement device, there are a case where a dedicated hardware device is conventionally used, and a case where the instrumentation circuit is constituted by a microprocessor in which software is mounted.
[0005]
When a dedicated hardware device is used, it is necessary to provide a hardware device for each of a plurality of process signals. On the other hand, when a microprocessor is used, all signal processing can be performed with a single microprocessor for a plurality of process signals.
[0006]
The importance of such a plant safety protection system requires a highly reliable design. For this reason, when the instrumentation circuit is configured by a microprocessor, verification and soundness confirmation activities (V & V: Verification & Validation) are performed to prevent common cause failure of software and to secure software reliability.
[0007]
V & V is a verification work to verify that the functions required for a digital type security protection system are correctly reflected from a higher-order process to a lower-order process in each process of software design and manufacturing, and verification work. This is an activity for quality compensation consisting of soundness confirmation work to confirm that the required functions are correctly realized for the system manufactured through the above. More specifically, as a verification operation for verifying that the software is manufactured as required by the design documents, a mutual confirmation operation is performed between a book in which design information is described and a production book. In addition, a simulation signal equivalent to an actual input signal is input to an instrumentation circuit configured by a microprocessor, and the soundness of the operation output is confirmed as to whether the operation output is performed according to the design documents.
[0008]
The implementation of such V & V requires that a third party different from the design and production operators perform it, and requires much more labor and time than the usual software design and production.
[0009]
On the other hand, the conventional dedicated hardware device has realized the function of the safety protection measurement device by processing the analog signal, but in recent years, due to the development of high integration technology of logic integrated circuits such as PLDs, By incorporating a logic integrated circuit, it is possible to realize a security protection measuring device by digital signal processing on a small scale.
[0010]
The PLD (Programmable Logic Device) is a logic integrated circuit that converts a signal processing function of a digital signal into a configuration of a logic circuit, and is realized by hardware wiring without using software.
[0011]
[Problems to be solved by the invention]
However, even if a dedicated hardware device that does not use software is used for the security measurement device, another means such as visual inspection or testing that the product is manufactured in accordance with the control logic described in the design document However, it is extremely difficult to visualize a dense control logic such as a logic integrated circuit constituting a hardware device and its operation state. For this reason, all combinations of ON or OFF input patterns of each digital input to the control logic of the hardware device are input to the device, and the logic operation result is checked with the design document to confirm the logic integrated circuit. The soundness of the logic integrated circuit is verified by performing an all-test-pattern input test that proves that there is no erroneous wiring other than the design in all of the constituent logic wirings. However, such a verification means has a problem that the total number of input patterns increases exponentially because the total number of digital input points increases, and the time and labor required for verification increase.
[0012]
Further, in the case of filter logic, it is necessary to create a test pattern by combining input patterns in chronological order, assuming a temporal change of the input pattern, so that the number of test patterns further increases. Was.
[0013]
SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the related art, and it is an object of the present invention to provide a test apparatus of a safety protection measurement apparatus that can easily confirm the soundness of a logic integrated circuit and can reduce the time and labor required for the test. The purpose is to get.
[0014]
[Means for Solving the Problems]
In order to achieve the above object, the invention according to claim 1 of the present invention provides a method for sequentially inputting a plurality of test patterns to a logic integrated circuit to be tested, reading an output from the logic integrated circuit, A logic integrated circuit test device with a test pattern input / output control device that creates a test pattern, and the result of the simulated design logic for the test pattern input by simulating the logic designed to be incorporated in the logic integrated circuit under test Logic simulation device provided with a design logic verification tool for reading an output pattern and creating an output pattern, and comparison evaluation means for comparing and evaluating the output pattern of the logic integrated circuit test device and the output pattern of the logic simulation device for the same test pattern And characterized by the following.
[0015]
According to another aspect of the present invention, there is provided an operation comparison circuit in which a logic designed to be incorporated in a logic integrated circuit to be tested has already been verified to operate as designed, and a logic integrated circuit and an operation comparison circuit. For the circuit, an input data generation circuit for sequentially inputting a plurality of predetermined test patterns sequentially in the same order, and simultaneously read outputs from the logic integrated circuit and the operation comparison circuit, and compare the respective results, And an output data comparison circuit for sequentially outputting coincidence or non-coincidence information.
[0016]
According to the fifth aspect of the present invention, a sine wave generator, an analog / digital conversion circuit that converts an analog signal from the sine wave generator into a digital signal and inputs the digital signal to a logic integrated circuit to be tested, It consists of a digital / analog conversion circuit that converts the output from the circuit into an analog signal and outputs it to the outside. An analog signal that changes continuously with a periodic waveform is input to the test equipment while changing the frequency, and the output data is output. By monitoring the soundness of the logic integrated circuit.
[0017]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a diagram showing a first embodiment of the present invention. In FIG. 1, reference numeral 1 denotes a logic integrated circuit test device, and 2 denotes a logic integrated circuit (hereinafter referred to as a test target PLD) 3 to be tested. The PLD test board 4 is a test pattern input / output control device constituted by a PC (Programmable Controller), which inputs a test pattern 5 from the outside, controls input / output to the PLD 3 to be tested according to the test pattern 5, and performs a test. Application software for creating an output pattern 6 from the output result of the target PLD 3 after the test is provided.
[0018]
Reference numeral 7 denotes a PLD test board which inputs a test signal to the test target PLD 3 in accordance with a control signal from the test pattern input / output control device 4 and reads out an output from the PLD 3 to the test pattern input / output control device 4. In the interface circuit, the PLD test board 2 and the test pattern input / output control device 4 constitute the logic integrated circuit test device 1.
[0019]
A logic simulation device 8 simulates a logic designed to be incorporated in the PLD 3 to be tested, reads a result of the simulated design logic in response to a test pattern input, and generates a design logic verification tool 10 for creating an output pattern 9. Have.
[0020]
Reference numeral 11 denotes a comparison circuit that compares the output pattern 6 of the logic integrated circuit test device 1 with the output pattern 9 of the logic simulation device 8, and reference numeral 12 denotes a soundness evaluation that evaluates the soundness of the test target PLD 3 from the output of the comparison circuit 11. Means 13 is a logic analyzer that monitors the operation status of input / output signals of the test target PLD 3.
[0021]
In the present embodiment configured as described above, first, the test target PLD 3 is mounted on the PLD test board 2. By inputting in advance all the test patterns 5 of all the pattern input tests to the application software on the test pattern input / output control device 4, the test patterns 5 are input to the test target PLD 3, and the output is input to the test pattern input / output device. The data is read out to the output control device 2 and an output pattern 6 is created. These series of operations are sequentially performed on all test patterns, and all output patterns 6 are accumulated.
[0022]
The output pattern 6 of the logic integrated circuit test apparatus 1 is compared with the output pattern 9 based on the simulation result of the logic designed to be incorporated into the test target PLD 3 by the design verification tool 10 in the comparison circuit 11 for each test pattern, and The sex evaluation means 12 confirms whether or not they match.
[0023]
If the results of the soundness evaluation means 12 match for all test patterns, it is verified that there is no erroneous wiring other than the design in all the logical wirings manufactured in the PLD 3 to be tested.
The operation of the test apparatus can be verified by monitoring the operation status of the input / output signal of the test target PLD 3 by the logic analyzer 13.
[0024]
Furthermore, test patterns having characteristics that pass through all the connected logical configurations held by the test target PLD 3 are extracted in advance by the design logic verification tool 10, and the input of these test patterns causes all the logical paths to be extracted. Operation can be verified.
[0025]
As described above, according to the present embodiment, application software on the test pattern input / output control device 4 sequentially repeats while controlling input / output of a plurality of predetermined test patterns to / from the PLD 3 to be tested. The enormous change of the test pattern input of the integrated circuit can be efficiently performed without wasting time, and the time and labor required for the test can be reduced.
[0026]
Next, a second embodiment of the present invention will be described with reference to FIGS.
In the following description, the same portions as those of the first embodiment shown in FIG. 1 are denoted by the same reference numerals, and detailed description will be omitted.
[0027]
In the present embodiment, as shown in FIG. 2, a PLD test is performed on a PLD 3 to be tested and an operation comparison circuit 14 that has already been verified that logic designed to be incorporated in the PLD 3 to be tested operates as designed. An input data generation circuit 15 mounted on the board 2 and simultaneously inputting a plurality of predetermined test patterns sequentially in the same order to the test target PLD 3 and the operation comparison circuit 14 is provided. The logic integrated circuit test apparatus 1 includes an output data comparison circuit 16 for simultaneously reading out outputs from the application circuit 14, comparing the respective results, and sequentially outputting information on coincidence or disagreement.
[0028]
In the present embodiment configured as described above, a signal is input from the input data generation circuit 15 that generates input data for the entire test pattern input test to both the test target PLD 3 and the operation comparison circuit 14, and the output thereof is output. Are continuously compared by the output data comparison circuit 16.
[0029]
The output data comparison circuit 16 compares the output of the test target PLD 3 with the output of the operation comparison circuit 14 and outputs a match or a mismatch. The check is performed by the check circuit 17 and the soundness of the test target PLD 3 is checked by the soundness evaluation means 12. Assess gender.
If the output does not match, stop shifting to the next test pattern input at that stage and clarify the status of each operation / data.
[0030]
The input data generation circuit 15 sequentially generates all test patterns by a counter circuit (not shown). The operation comparing circuit 14 implements the function of the PLD 3 to be tested with a discrete element (such as a standard logic IC) or a verified PLD element, or a ROM or the like that can output an expected result according to input data. Created with a storage element.
[0031]
FIG. 3 shows an example in which the same logic is realized by means of different designs and tools by applying, as an operation comparison circuit, a PLD 18 having a different manufacturing process from that of the PLD 3 to be tested, such as a PLD made by another company, having a different logic wiring method. This is a method for confirming the soundness of the logic realization of the test target PLD 3 because the same logic result is obtained depending on the diversity of the PLD.
[0032]
According to the present embodiment, since the test apparatus operates only with hardware, it is possible to input and output test patterns at a speed equivalent to the processing speed of the PLD 3 to be tested. It can be easily confirmed and the test can be performed more efficiently.
Further, by using another manufacturer's PLD as the operation comparison circuit, it is possible to save the trouble of newly creating the operation comparison circuit 14 when changing the model.
[0033]
Next, a third embodiment of the present invention will be described with reference to FIG. In the present embodiment, an analog / digital conversion circuit (ADC) 19 that mounts a test target PLD3, converts an external analog signal into a digital signal, and inputs the digital signal to the test target PLD3, and a digital signal from the test target PLD3 A digital-to-analog conversion circuit (DAC) 20 that converts an output to an analog signal and outputs the signal to the outside constitutes a logic integrated circuit test apparatus 1.
In the present embodiment configured as described above, this test is particularly applied to filter verification.
[0034]
Instead of input data equivalent to the entire test pattern input test, a sine wave continuously changing from the sine wave generator 21 is changed in frequency and input to the analog / digital conversion circuit (ADC) 19 of the logic integrated circuit test apparatus 1. Then, the continuity of the output data that has passed through the PLD 3 to be tested and the digital / analog conversion circuit (DAC) 20 is monitored by the oscilloscope 22, and the continuity is checked by the characteristic checking circuit 23.
[0035]
According to the present embodiment, the linearity of the test target PLD 3 can be verified by monitoring the continuity of the output data with respect to the continuously changing input signal. As a result, by obtaining the transfer function from the input / output characteristics, the filter characteristics of the test target PLD 3 can be verified, and the time and labor for creating a digital test pattern can be reduced.
[0036]
【The invention's effect】
As described above, according to the present invention, it is possible to obtain a test apparatus of a safety protection measurement apparatus that can easily check the soundness of a logic integrated circuit and can reduce the time and labor spent for testing.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a first embodiment of the present invention.
FIG. 2 is a block diagram showing a second embodiment of the present invention.
FIG. 3 is a block diagram showing another example of the second embodiment of the present invention.
FIG. 4 is a block diagram showing a third embodiment of the present invention.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Logic integrated circuit test device, 2 ... Test target logic integrated circuit, 3 ... PLD test board, 4 ... Test pattern input / output control device, 5 ... Test pattern, 6, 9 ... Output pattern, 7 ... Interface circuit, 8 ... Logic simulation device, 10 ... Design logic verification tool, 11 ... Comparison circuit, 12 ... Soundness evaluation means, 13 ... Logic analyzer, 14 ... Operation comparison circuit, 15 ... Input data generation circuit, 16 ... Output data comparison circuit, 17: confirmation circuit, 19: analog / digital conversion circuit, 20: digital / analog conversion circuit, 21: sine wave generator, 22: oscilloscope, 23: characteristic confirmation circuit.

Claims (6)

A logic integrated circuit test device including a test pattern input / output control device for sequentially inputting a plurality of test patterns to a logic integrated circuit to be tested, reading an output from the logic integrated circuit, and creating an output pattern; A logic simulation device equipped with a design logic verification tool that simulates logic designed to be incorporated in a logic integrated circuit to be tested, reads out the results of the simulated design logic in response to a test pattern input, and creates an output pattern And a comparing and evaluating means for comparing and evaluating an output pattern of the logic integrated circuit test device and an output pattern of the logic simulation device for the same test pattern. A plurality of predetermined tests are performed on an operation comparison circuit that has already been verified that the logic designed to be incorporated in the logic integrated circuit to be tested operates as designed, and on the logic integrated circuit and the operation comparison circuit. An input data generation circuit for sequentially inputting patterns in the same order and an output data for simultaneously reading outputs from a logic integrated circuit and an operation comparison circuit, comparing respective results, and sequentially outputting information on coincidence or non-coincidence. Test equipment for safety protection measurement equipment consisting of a comparison circuit. 3. The test apparatus according to claim 2, wherein when the output data comparison circuit determines that the results do not match, the shift to the next test pattern is stopped. 3. The test apparatus for a safety protection measurement device according to claim 2, wherein a logic integrated circuit whose manufacturing process is different from that of the test target logic integrated circuit is used as the operation comparison circuit. A sine wave generator, an analog / digital conversion circuit that converts an analog signal from the sine wave generator into a digital signal, and inputs the logic integrated circuit to be tested, and an output from the logic integrated circuit into an analog signal It consists of a digital / analog conversion circuit that converts and outputs to the outside. The analog signal, which changes continuously with a periodic waveform, is input to the test equipment while changing the frequency, and the output data is monitored, whereby the logic integration is performed. A testing device for a safety protection measuring device characterized by checking the soundness of a circuit. By inputting a test pattern that passes through all connected logic configurations held by the logic integrated circuit to be tested to the logic integrated circuit test apparatus, the soundness of the logic integrated circuit is confirmed. A test device for a safety protection measuring device according to claim 1.

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