JP2003338749A - Amplitude-converting circuit and semiconductor device using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an amplitude converting circuit which operates normally, even when the amplitude voltage of an input signal is lower than the threshold of an input transistor. <P>SOLUTION: This level shifter 3 is equipped with p-type TFTs 5 and 6 for latching the levels of output nodes N5 and N6, n-type TFTs 7 and 8 for setting the levels of the output nodes N5 and N6, n-type TFTs 9-14 for giving the voltages higher than threshold voltages VTN of the n-type TFTs 7 and 8, respectively, to the lines between the gates and the sources of the n-type TFTs 7 and 8, in response to the falling and rising edges of the input signal V1, capacitors 15 and 16, and a resistor element 17. Accordingly, this circuit will operate normally, even if the amplitude voltage (3 V) of the input signal V1 is lower than the thresholds VTN of the n-type TFTs 7 and 8. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an amplitude conversion circuit and a semiconductor device using the same, and more particularly to an amplitude conversion circuit for converting the amplitude of a signal and a semiconductor device using the same.

[0002]

2. Description of the Related Art FIG. 27 is a block diagram showing a configuration of a portion related to image display of a conventional mobile phone.

In FIG. 27, this mobile phone is an MO
Control L that is an ST (MOS transistor) type integrated circuit
SI71 and level shifter 7 which is a MOST type integrated circuit
2 and a liquid crystal display device 73 which is a TFT (thin film transistor) type integrated circuit.

The control LSI 71 generates a control signal for the liquid crystal display device 73. The "H" level of this control signal is 3V, and its "L" level is 0V. Although a large number of control signals are actually generated, only one control signal is used here for simplification of description. The level shifter 72 converts the logic level of the control signal from the control LSI 71 to generate an internal control signal. The "H" level of this internal control signal is 7.5V, and its "L" level is 0V.
The liquid crystal display device 73 displays an image according to the internal control signal from the level shifter 72.

FIG. 28 is a circuit diagram showing the structure of the level shifter 72. In FIG. 28, this level shifter 72
Are P-channel MOS transistors 74, 75 and N
Channel MOS transistors 76 and 77 are included. P-channel MOS transistors 74 and 75 are connected to node N71 of power supply potential VCC (7.5 V) and output node N7, respectively.
4 and N75, and their gates are connected to output nodes N75 and N74, respectively. N channel MOS transistors 76 and 77 are connected between output nodes N74 and 75 and a node of ground potential GND, respectively, and their gates receive input signals VI and / VI, respectively.

Now, input signals VI and / VI are set to "L" level (0V) and "H" level (3V), respectively, and output signals VO and / VO are set to "H" level (7.5V) and "V", respectively. It is assumed to be at the "L" level (0V). At this time, the MOS transistors 74 and 77
Is conductive and the MOS transistors 75 and 76 are non-conductive.

In this state, input signal VI is raised from "L" level (0V) to "H" level (3V), and input signal / VI is changed from "H" level (3V) to "L".
When the voltage is lowered to the level (0V), first the N channel MO
The S transistor 76 becomes conductive and the potential of the output node N74 decreases. The potential of the output node N74 is the power source potential VC
When the voltage becomes lower than the potential obtained by subtracting the absolute value of the threshold voltage of the P-channel MOS transistor 75 from C, the P-channel MOS transistor 75 starts to conduct and the output node N
The potential of 75 begins to rise. When the potential of the output node N75 starts to rise, the voltage between the source and gate of the P-channel MOS transistor 74 decreases and the P-channel MO transistor 74
The conduction resistance value of S transistor 74 increases, and the potential of output node N74 further decreases. Therefore, the circuit operates as positive feedback, and the output nodes VO and / VO are at "L" level (0V) and "H" level (7.5V), respectively.
Then, the level conversion operation is completed.

In addition, the P-channel MOS transistor 7
There is also a level shifter with both 4,75 gates connected to one output node N74 or N75. Such a level shifter is disclosed in Patent Document 1, for example.

[0009]

[Patent Document 1] Japanese Patent Laid-Open No. 11-145821

[0010]

As described above, in the conventional level shifter 72, the input signal VI has the "L" level (0
The operation is premised on that the N-channel MOS transistor 76 becomes conductive in response to the rise from V) to the "H" level (3V). N-channel MOS transistor 7
In order for 6 to become conductive, the threshold potential of N-channel MOS transistor 76 is set to "H" level (3
V) or less.

In a general semiconductor LSI, it is easy to set the threshold voltage of the transistor to 3 V or less, but the low temperature polysilicon TFT included in the liquid crystal display device has a large variation in the threshold voltage. It is difficult to set the threshold voltage of 3 V or less. Therefore, FIG.
As shown in, the level shifter 72 composed of a high voltage MOS transistor is provided between the control LSI 71 and the liquid crystal display device 73 to convert the logic level of the signal.

However, if such a level shifter 72 is provided, the cost of the level shifter 72 is added to the system cost, which causes an increase in the system cost.

Therefore, a main object of the present invention is to provide an amplitude conversion circuit which operates normally even when the amplitude voltage of the input signal is lower than the threshold voltage of the input transistor, and a semiconductor device using the same. is there.

[0014]

In the amplitude conversion circuit according to the present invention, a first signal whose amplitude is a first voltage is a second voltage whose amplitude is higher than a first voltage. An amplitude conversion circuit for converting into a second signal, the first electrodes of which both receive a second voltage, and the second electrodes of which output a second signal and its complementary signal. First and second transistors of the first conductivity type connected to a second output node and to a second output node, respectively, and their input electrodes connected to a second and first output node, respectively, and their first electrodes. Are connected to the first and second output nodes, respectively, of the third and fourth of the second conductivity type.
And a third voltage higher than the first voltage in response to the leading edge of the complementary signal of the first signal and the input electrode of the third transistor driven by the first signal and its complementary signal. A third voltage is applied between the second electrodes to make the third transistor conductive, and a third voltage is applied to the fourth transistor in response to the leading edge of the first signal corresponding to the trailing edge of the complementary signal of the first signal. And a drive circuit which is provided between the input electrode and the second electrode to make the fourth transistor conductive.

In another amplitude conversion circuit according to the present invention, the first signal whose amplitude is the first voltage is the first signal whose amplitude is the first voltage.
An amplitude conversion circuit for converting into a second signal, which is a second voltage higher than the voltage of, the first electrodes thereof both receive the second voltage, and the second electrodes of the second electrodes receive the second voltage. A first conductivity type having first and second output nodes respectively for outputting a signal and its complementary signal, and having their input electrodes both connected to a second output node.
And a second transistor, third and fourth transistors of a second conductivity type having their first electrodes connected to the first and second output nodes, respectively, and a first signal and its complementary signal. Driven by the third signal and applying a third voltage higher than the first voltage between the input electrode and the second electrode of the third transistor in response to the leading edge of the complementary signal of the first signal. And applying a third voltage between the input electrode and the second electrode of the fourth transistor in response to the leading edge of the first signal corresponding to the trailing edge of the complementary signal of the first signal. And a drive circuit for making the transistor of No. 4 conductive.

[0016]

1 is a block diagram showing a configuration of a portion related to image display of a mobile phone according to an embodiment of the present invention.

In FIG. 1, the mobile phone is a MOS
The liquid crystal display device 2 includes a control LSI 1 which is a T-type integrated circuit and a liquid crystal display device 2 which is a TFT type integrated circuit. The liquid crystal display device 2 includes a level shifter 3 and a liquid crystal display unit 4.

The control LSI 1 outputs a control signal for the liquid crystal display device 2. "H" level of this control signal is 3V
And its "L" level is 0V. Although a large number of control signals are actually generated, only one control signal is used here for simplification of description. The level shifter 3 is an LS for control
An internal control signal is generated by converting the logic level of the control signal from I1. The "H" level of this internal control signal is 7.
It is 5V and its "L" level is 0V. The liquid crystal display unit 4 displays an image according to the internal control signal from the level shifter 3.

FIG. 2 is a circuit diagram showing the structure of the level shifter 3. In FIG. 2, the level shifter 3 includes P-type TFTs 5 and 6, N-type TFTs 7 to 14, a capacitor 15, and
16 and a resistance element 17. P-type TFT 5,6
Is the node N1 of the power supply potential VCC (7.5 V).
And output nodes N5 and N6, and their gates are connected to output nodes N6 and N5, respectively. The signals appearing at the output nodes N5 and N6 become the output signals VO and / VO of the level shifter 3, respectively. N type T
FT7 is connected between nodes N5 and N7, and its gate is connected to node N11. The N-type TFT 8 is connected between the nodes N6 and N8 and has its gate connected to the node N1.
3 is connected. Input signal VI and its complementary signal / VI are applied to nodes N7 and N8, respectively.

Resistance element 17 and N-type TFTs 9 and 10
Are connected in series between the node N1 of the power supply potential VCC and the node of the ground potential GND. The gate of the N-type TFT 9 is connected to its drain (node N9), and the N-type TFT 1
The gate of 0 is connected to its drain. N-type TFT
Each of 9 and 10 constitutes a diode element, and the resistance element 1
7 and N-type TFTs 9 and 10 form a constant potential generating circuit. If the resistance value of the resistance element 17 is set sufficiently large (for example, 100 MΩ) and the conduction resistance value of the N-type TFTs 9 and 10 is set sufficiently smaller than the resistance value of the resistance element 17,
The potential V9 of the node N9 becomes V9 = 2VTN. Here, VTN is the threshold potential of the N-type TFT.

The N-type TFT 11 is connected between the node N1 and the node N11 of the power supply potential VCC, and its gate receives the potential V9 of the node N9. The N-type TFT 12 is connected between the nodes N11 and N12, and its gate is connected to the node N11. The N-type TFT 12 constitutes a diode element. The capacitor 15 is connected between the nodes N11 and N12. Signal / V is applied to the node N12.
I is given.

The N-type TFT 13 is connected between the node N1 and the node N13 of the power supply potential VCC, and its gate receives the potential V9 of the node N9. The N-type TFT 14 is connected between the nodes N13 and N14, and its gate is connected to the node N13. The N-type TFT 14 constitutes a diode element. Capacitor 16 is connected between nodes N13 and N14. Input signal VI is applied to node N14.

Next, the operation of the level shifter 3 will be described. Now, the input signals VI, / VI are 3V,
Assuming that the voltage is 0V, the N-type TFT 11 operates as a source follower, so that the potential V of the node N11 becomes V.
11 is V11 = 2VTN-VTN = VTN. Further, since the threshold potential of the diode-connected N-type TFT 12 is VTN, almost no current flows from the node N1 of the power supply potential VCC to the node N12. N type TF
The gate potential of T7 is V11 = VTN, and the source potential thereof is 3V, so the N-type TFT 7 is non-conductive. The capacitor 15 is charged to the threshold voltage VTN.

On the other hand, as will be described later, the potential V13 of the node N13 is boosted to VTN or higher, and the node N8 becomes 0.
Since it is set to V, the N-type TFT 8 becomes conductive. As a result, the output node N6 becomes the potential (0V) of the input node N8, the P-type TFT 5 becomes conductive, and the output node N5 becomes the power supply potential VCC. As a result, the P-type TFT 6 becomes non-conductive, and no current flows between the node N1 of the power supply potential VCC and the input node N8.

Next, when the input signal VI falls from 3V to 0V and the input signal / VI rises from 0V to 3V, the potential change of the input signal / VI is capacitively coupled to the node N11 via the capacitor 15. And the potential V11 of the node N11 is boosted. Capacitor 15
When the capacitance value of the node N11 is made sufficiently larger than the capacitance value of the parasitic capacitance (not shown) of the node N11, the potential V11 of the output node N11 becomes V11≅VTN + ΔVI = VTN + 3V. However, ΔVI is the amplitude of the input signals VI and / VI, which is 3V. Source of N-type TFT 7 (node N
Since the potential of 7) is 0V, the gate-source voltage of the N-type TFT 7 is VTN + 3V, and the N-type TFT is
7 becomes conductive. As a result, the potential of the output node N5 is 0V.
And the P-type TFT 6 becomes conductive.

On the other hand, the potential change of the input signal VI from 3V to 0V is transmitted to the node N13 via the capacitor 16 by capacitive coupling, and the potential V13 of the node N13 is lowered. When the change cycle of the input signals VI and / VI is short, the potential V13 of the node N13 before the step-down is V13 = VT
Since it is N + 3V, the potential V13 of the node N13 at the time of stepping down is V13 = VTN + 3V−3V = VTN. When the change cycle of the input signals VI and / VI is long, the potential V13 of the node N13 is a potential boosted by capacitive coupling, and therefore decreases with time. Therefore, the potential V13 of the node N13 is the input signals VI, / V.
Although it is lower than the value VTN when the change cycle of I is short by a decrease amount, in this case, the N-type TFT 13 becomes conductive and the potential V13 of the node N13 is raised to VTN.

As described above, the gate potential V13 of the N-type TFT 8 becomes VTN and the potential of its source (node N8) becomes 3 V, so that the N-type TFT 8 becomes non-conductive. As a result, the potential of the output node N6 becomes 7.5 V, and the P-type TFT 5 becomes non-conductive. In this way, the output nodes N5 and N6 become 0V and 7.5V, respectively, which means that the logic level conversion from 3V to 7.5V is performed.

In this embodiment, the threshold voltage VT of the N-type TFT 7 is responded to in response to the falling edge of the input signal VI.
Since the voltage VTN + 3V obtained by adding the amplitude voltage (3V) of the input signal / VI to N is applied between the gate and the source of the N-type TFT 7, the amplitude voltage (3V) of the input signal / VI is the N-type TF.
The level shifter 3 operates normally even when it is lower than the threshold voltage VTN of T7. Therefore, as shown in FIG. 1, the level shifter 3 and the liquid crystal display unit 4 can be combined into one liquid crystal display device 2 (TFT type integrated circuit). Therefore, the number of parts can be reduced and the system cost can be reduced as compared with the conventional case in which the level shifter 52 and the liquid crystal display device 53 need to be separately provided.

Further, the power supply current transiently flows during the operation, but no direct current flows except the resistance element 17 and the N-type TFTs 9 and 10. Since the resistance value of the resistance element 17 is set to a large value and only a small current flows,
The power consumption of the level shifter 3 is extremely small.

In this embodiment, the TFTs 5 to 1
Although 4 is used, a MOS transistor may be used instead of the TFT. In this case, it operates even when the amplitudes of the input signals VI and / VI are smaller than the threshold voltage of the MOS transistor.

Further, in this embodiment, the TFT which is an insulated gate field effect transistor is used, but it goes without saying that a field effect transistor of another type may be used.

Various modifications of this embodiment will be described below. The level shifter 20 shown in FIG.
The sources of T12 and T14 are grounded. In this modified example,
The currents of the N-type TFTs 12 and 14 are input to the input nodes N12 and N1.
Since the current is not flown to the node 4 but to the node of the ground potential GND, the driving force of the input signals VI and / VI can be small.

In the level shifter 21 shown in FIG. 4, the P-type TFT is used.
The power supply potential VCC (7.5 V) is applied to the sources of 5 and 6, and the positive power supply potential VCC 'different from the power supply potential VCC is applied to the drain of the N-type TFT 11, and one electrode of the resistance element 17 (to the node N9 is connected to the node N9). The power source potentials VCC, VCC 'different from the power source potentials VCC, VCC' are applied to the electrode which is not connected.
Is given. In this modification, for example, the power supply potential VC
The noise generated at the node C causes the nodes N9 and N1
It is possible to prevent the potentials V9, V11, V13 of 1, N13 from varying.

In the level shifter 22 shown in FIG.
7 is a P-type TFT 23. That is, P-type TF
T23 is connected between nodes N1 and N9 of power supply potential VCC, and its gate is connected to a node of ground potential GND. The resistance value per unit area of the resistance element composed of the TFT is larger than the resistance value per unit area of the resistance element composed of the diffusion layer. Therefore, in this modification, the area occupied by the resistance element can be reduced. An N-type T whose gate receives the power supply potential VCC
The same effect can be obtained even if the resistance element 17 is formed of FT.

In the level shifter 24 shown in FIG. 6, the N-type TFT is used.
25 and 26 are added. The N-type TFT 25 has a node N
5 and N7, the gate of which is connected to node N6. The N-type TFT 26 is connected between the nodes N6 and N8, and its gate is connected to the node N5. When the input signals VI and / VI are at "H" level and "L" level and the output signals VO and / VO are at "H" level and "L" level, respectively, the N-type TFT
25 becomes non-conductive and the N-type TFT 26 becomes conductive,
Output nodes N5 and N6 are held at "H" level and "L" level, respectively. When the input signals VI and / VI are at "L" level and "H" level and the output signals VO and / VO are at "L" level and "H" level, respectively, the N-type TFT 25 becomes conductive and the N-type TFT 26 is turned on. Becomes non-conductive, and output nodes N5 and N6 are held at "L" level and "H" level, respectively.

When the change cycle of the input signals VI and / VI is very long, the potentials V11 and V of the nodes N11 and N13 are set.
Both 13 become the threshold potential VTN of the N-type TFT, and the potential relationship between the output nodes N5 and N6 may be reversed. The N-type TFTs 25 and 26 are for preventing such a potential reversal of the output nodes N5 and N6 from being reversed, and the potentials of the output nodes N5 and N6 are set regardless of the potentials V11 and V13 of the nodes N11 and N13. Fix it.

The level shifter 27 of FIG. 7 is obtained by connecting the sources of the N-type TFTs 25 and 26 of the level shifter 24 of FIG. 6 to the node of the ground potential GND. In this modification, the currents of the N-type TFTs 25 and 26 are set to the input nodes N7 and
Since the current is not flown to the node 8 but to the node of the ground potential GND, the driving force of the input signals VI and / VI can be small.

The level shifter 30 of FIG. 8 is such that the sources of the N-type TFTs 7 and 8 of the level shifter 3 of FIG. 2 are both connected to the node of the ground potential GND. In this modified example, the currents of the N-type TFTs 7 and 8 do not flow to the input nodes N7 and N8 but to the node of the ground potential GND, so that the driving force of the input signals VI and / VI can be small.

The level shifter 31 of FIG. 9 has the sources of the N-type TFTs 7, 8, 25 and 26 of the level shifter 27 of FIG. 7 both connected to the node of the ground potential GND.
In this modification, the currents of the N-type TFTs 7, 8, 25 and 26 are made to flow to the node of the ground potential GND instead of being made to flow to the input nodes N7 and N8, so that the driving force of the input signals VI and / VI can be further reduced.

In the level shifter 32 of FIG. 10, the gates of the P-type TFTs 5 and 6 of the level shifter 3 of FIG. 2 are both connected to the node N5. The P-type TFTs 5 and 6 form a current mirror circuit. Currents of the same value flow through the P-type TFTs 5 and 6. The input signals VI and / VI become the “L” level and the “H” level, respectively, and the N-type TFT
When 7 and 8 are turned on and off, respectively, a current having the same value as the current flowing through the TFTs 5 and 7 also flows into the P-type TFT 6, and differential amplification is performed. Output node N
5 and N6 are at "L" level and "H" level, respectively. Also in this modification, the same amplitude conversion effect as that of the level shifter 3 of FIG. 2 can be obtained.

In the level shifter 33 of FIG. 11, the gates of the P-type TFTs 5 and 6 of the level shifter 24 of FIG. 6 are both connected to the node N5. In this modified example, the same effect as that of the level shifter 24 shown in FIG.

The level shifter 34 of FIG. 12 is one in which the sources of the N-type TFTs 7 and 8 of the level shifter 32 of FIG. 10 are both grounded. In this modification, the N-type TFTs 7 and 8 are
Since the current flowing through the input nodes N7 and N8 does not flow into the node of the ground potential GND, the driving force of the input signals VI and / VI can be small.

The level shifter 35 of FIG. 13 is one in which the sources of the N-type TFTs 7, 8, 25 and 26 of the level shifter 33 of FIG. 11 are both grounded. In this modified example, the current flowing through the N-type TFTs 7, 8, 25 and 26 is supplied to the input node N
Since the current is not applied to 7 and N8 but to the node of the ground potential GND, the driving force of the input signals VI and / VI can be small.

In the modification of FIG. 14, a constant potential generation circuit 36 including a resistance element 17 and N-type TFTs 9 and 10 is provided commonly to a plurality of level shifters 38, 39, .... Output node N9 of constant potential generation circuit 36 and ground potential G
A capacitor 3 for stabilizing the potential is provided between the ND node and the node.
7 is connected. In order to increase the resistance value of the resistance element 17, it is necessary to increase the area of the resistance element 17,
In this modified example, the constant potential generation circuit 36 is commonly provided for the plurality of level shifters 38, 39, ... Therefore, the area occupied by the entire circuit can be small.

The level shifter 40 shown in FIG. 15 is obtained by adding P-type TFTs 41 and 42 to the level shifter 3 shown in FIG. The P-type TFT 41 is connected between the drain of the P-type TFT 5 and the output node N5, and its gate is the node N1.
Connected to 1. The P-type TFT 42 is connected between the drain of the P-type TFT 6 and the output node N6, and its gate is connected to the node N13. When the input signal / VI rises from 0V to 3V, the potential V11 of the node N11 becomes VTN + 3V, the P-type TFT 41 becomes non-conductive and the N-type TFT 7 becomes conductive, and the potential of the output node N5 becomes 0V. At this time, since the P-type TFT 41 becomes non-conductive, no current flows from the node N1 of the power supply potential VCC to the output node N5, and the potential of the output node N5 easily falls to 0V. When the input signal / VI falls from 3V to 0V, the potential V11 of the node N11 becomes VTN, the N-type TFT 7 becomes non-conductive and the P-type TFT 41 becomes conductive, and the potential of the output node N5 becomes 7.5V. Become.

When the input signal VI is raised from 0V to 3V, the potential V13 of the node N13 becomes VTN + 3V.
And the P-type TFT 42 becomes non-conductive and the N-type T
The FT8 becomes conductive and the potential of the output node N6 becomes 0V.
At this time, since the P-type TFT 42 becomes non-conductive, no current flows from the node N1 of the power supply potential VCC to the output node N6, and the potential of the output node N6 easily falls to 0V.
When the input signal VI falls from 3V to 0V, the potential V13 of the node N13 becomes VTN, the N-type TFT 8 becomes non-conductive and the P-type TFT 42 becomes conductive, and the potential of the output node N6 becomes 7.5V. . In this modification, since the potentials of the output nodes N5 and N6 are easily lowered to 0V, the amplitudes of the input signals VI and / VI can be reduced accordingly, and the amplitude margins of the input signals VI and / VI can be reduced. growing.

The level shifters 45 to 55 shown in FIGS.
Are the level shifters 20 to 22 of FIGS.
P-type TFTs 41 and 42 are added to 24, 27 and 30 to 35. Even in these modified examples, the same effect as the level shifter 40 of FIG. 15 can be obtained.

The embodiments disclosed this time are to be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description but by the claims, and is intended to include meanings equivalent to the claims and all modifications within the scope.

[0049]

As described above, in the amplitude conversion circuit according to the present invention, the first signal whose amplitude is the first voltage is
A second voltage whose amplitude is a second voltage higher than the first voltage
In order to convert into the signal of 1st, the 1st and 2nd transistor of a 1st conductivity type, the 3rd and 4th transistor of a 2nd conductivity type, and a drive circuit are provided. The first electrodes of the first and second transistors both receive a second voltage, the second electrodes of which are at the first and second output nodes for outputting the second signal and its complementary signal. The input electrodes are respectively connected to the second
And a first output node. Third and fourth
The first electrodes of the transistors are connected to the first and second output nodes, respectively. The drive circuit is driven by the first signal and its complementary signal, and applies a third voltage higher than the first voltage to the input electrode of the third transistor in response to the leading edge of the complementary signal of the first signal. A third voltage is applied between the second electrodes to make the third transistor conductive, and a third voltage is applied to the fourth transistor in response to the leading edge of the first signal corresponding to the trailing edge of the complementary signal of the first signal. Input electrode and second
Is applied between the electrodes of to make the fourth transistor conductive. Therefore, in response to the leading edge of the complementary signal of the first signal or the leading edge of the first signal, a third voltage higher than the first voltage is applied to the input electrode and the second electrode of the third or fourth transistor. Since the third or fourth transistor is applied by being provided between the electrodes to make it conductive, the circuit normally operates even when the amplitude of the first signal is lower than the threshold voltages of the third and fourth transistors.

In another amplitude converting circuit according to the present invention, the first signal whose amplitude is the first voltage is changed to the second signal whose amplitude is the second voltage higher than the first voltage. First and second transistors of a first conductivity type, third and fourth transistors of a second conductivity type, and a drive circuit are provided for converting to a signal. The first electrodes of the first and second transistors both receive a second voltage, the second electrodes of which are at the first and second output nodes for outputting the second signal and its complementary signal. They are connected to each other, and their input electrodes are both connected to the second output node. The first electrodes of the third and fourth transistors are connected to the first and second output nodes, respectively. The drive circuit is driven by the first signal and its complementary signal, and applies a third voltage higher than the first voltage to the input electrode of the third transistor in response to the leading edge of the complementary signal of the first signal. A third voltage is applied between the second electrodes to make the third transistor conductive, and a third voltage is applied to the fourth transistor in response to the leading edge of the first signal corresponding to the trailing edge of the complementary signal of the first signal. It is applied between the input electrode and the second electrode to make the fourth transistor conductive. Therefore, in response to the leading edge of the complementary signal of the first signal or the leading edge of the first signal, a third voltage higher than the first voltage is applied to the input electrode and the second electrode of the third or fourth transistor. Third between electrodes
Alternatively, since the fourth transistor is turned on, it operates normally even when the amplitude of the first signal is lower than the threshold voltages of the third and fourth transistors.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a portion related to image display of a mobile phone according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a configuration of a level shifter shown in FIG.

FIG. 3 is a circuit diagram showing a modified example of this embodiment.

FIG. 4 is a circuit diagram showing another modification of this embodiment.

FIG. 5 is a circuit diagram showing still another modification of this embodiment.

FIG. 6 is a circuit diagram showing still another modification of this embodiment.

FIG. 7 is a circuit diagram showing still another modification of this embodiment.

FIG. 8 is a circuit diagram showing still another modification of this embodiment.

FIG. 9 is a circuit diagram showing still another modification of this embodiment.

FIG. 10 is a circuit diagram showing still another modification of this embodiment.

FIG. 11 is a circuit diagram showing still another modification of this embodiment.

FIG. 12 is a circuit diagram showing still another modification of this embodiment.

FIG. 13 is a circuit diagram showing still another modification of this embodiment.

FIG. 14 is a circuit diagram showing still another modified example of this embodiment.

FIG. 15 is a circuit diagram showing still another modification of this embodiment.

FIG. 16 is a circuit diagram showing still another modification of this embodiment.

FIG. 17 is a circuit diagram showing still another modification of this embodiment.

FIG. 18 is a circuit diagram showing still another modification of this embodiment.

FIG. 19 is a circuit diagram showing still another modification of this embodiment.

FIG. 20 is a circuit diagram showing still another modified example of this embodiment.

FIG. 21 is a circuit diagram showing still another modification of this embodiment.

FIG. 22 is a circuit diagram showing still another modification of this embodiment.

FIG. 23 is a circuit diagram showing still another modification of this embodiment.

FIG. 24 is a circuit diagram showing still another modification of this embodiment.

FIG. 25 is a circuit diagram showing still another modification of this embodiment.

FIG. 26 is a circuit diagram showing still another modification of this embodiment.

FIG. 27 is a block diagram showing a configuration of a portion related to image display of a conventional mobile phone.

28 is a circuit diagram showing a configuration of the level shifter shown in FIG. 27.

[Explanation of symbols]

1,71 control LSI, 2,73 liquid crystal display device,
3,20-22,24,27,30-35,38-4
0,45-55,72 level shifter, 4 liquid crystal display section, 5,6,23,41,42 P-type TFT, 7-1
4, 25, 26 N-type TFT, 15, 16, 37 capacitors, 17 resistance elements, 36 constant potential generation circuit, 7
4,75 P-channel MOS transistor, 76,77
N-channel MOS transistor.

Claims (22)

[Claims] 1. An amplitude conversion circuit for converting a first signal having an amplitude of a first voltage into a second signal having an amplitude of a second voltage higher than the first voltage. , Their first electrodes both receiving said second voltage, and their second electrodes respectively connected to first and second output nodes for outputting said second signal and its complementary signal. , A first of a first conductivity type whose input electrodes are respectively connected to said second and first output nodes.
And a second transistor, the third and fourth of the second conductivity type having their first electrodes respectively connected to said first and second output nodes.
And a third voltage higher than the first voltage in response to the leading edge of the complementary signal of the first signal, the third transistor being driven by the first signal and its complementary signal. Is applied between the input electrode and the second electrode of the second transistor to render the third transistor conductive, and the third transistor is responsive to the leading edge of the first signal corresponding to the trailing edge of the complementary signal of the first signal. An amplitude conversion circuit comprising: a drive circuit for applying the voltage of 4) between an input electrode and a second electrode of the fourth transistor to make the fourth transistor conductive. 2. An amplitude conversion circuit for converting a first signal having an amplitude of a first voltage into a second signal having an amplitude of a second voltage higher than the first voltage. , Their first electrodes both receiving said second voltage, and their second electrodes respectively connected to first and second output nodes for outputting said second signal and its complementary signal. , First and second transistors of a first conductivity type whose input electrodes are both connected to said second output node, their first electrodes being respectively connected to said first and second output nodes Third and fourth of the second conductivity type provided
And a third voltage higher than the first voltage in response to the leading edge of the complementary signal of the first signal, the third transistor being driven by the first signal and its complementary signal. Is applied between the input electrode and the second electrode of the second transistor to render the third transistor conductive, and the third transistor is responsive to the leading edge of the first signal corresponding to the trailing edge of the complementary signal of the first signal. An amplitude conversion circuit comprising: a drive circuit for applying the voltage of 4) between an input electrode and a second electrode of the fourth transistor to make the fourth transistor conductive. 3. The drive circuit includes a first capacitor whose one electrode is connected to an input electrode of the third transistor and whose other electrode receives a complementary signal of the first signal; A second capacitor connected to the input electrode of the fourth transistor, the other electrode of which receives the first signal, and the terminal voltage of each of the first and second capacitors are equal to the third and fourth capacitors. 3. The amplitude conversion circuit according to claim 1, further comprising a charge / discharge circuit for charging / discharging each of the first and second capacitors so that the threshold voltage of the transistor is reached. 4. The charging / discharging circuit comprises:
Voltage generating circuit for generating a voltage approximately twice the threshold voltage of the transistor, and the voltage generating circuits are provided corresponding to the third and fourth transistors, respectively, and each has a voltage higher than the output voltage of the voltage generating circuit. First and second level shift circuits for generating a voltage lower than the threshold voltages of the third and fourth transistors and giving it to the input electrodes of the corresponding transistors, and connected in parallel to the first and second capacitors, respectively. The amplitude conversion circuit according to claim 3, further comprising first and second diode elements. 5. The first and second diode elements are connected in parallel to the first and second capacitors, respectively, and their input electrodes are connected to the input electrodes of the third and fourth transistors, respectively. The amplitude conversion circuit according to claim 4, comprising fifth and sixth transistors of the second conductivity type. 6. The charging / discharging circuit is a voltage generating circuit that generates a voltage approximately twice the threshold voltage of the third and fourth transistors, and corresponds to the third and fourth transistors, respectively. First and second levels, each of which generates a voltage lower than the output voltage of the voltage generating circuit by the threshold voltage of the third and fourth transistors and applies the voltage to the input electrode of the corresponding transistor. 4. The amplitude conversion circuit according to claim 3, including a shift circuit, and first and second diode elements connected between the input electrodes of the third and fourth transistors and a node of a reference voltage, respectively. 7. The first and second diode elements are respectively connected between input electrodes of the third and fourth transistors and a node of the reference voltage, and the input electrodes thereof are respectively connected to the third electrode. The amplitude conversion circuit according to claim 6, further comprising: fifth and sixth transistors of the second conductivity type connected to the input electrodes of the fourth transistor and the fourth transistor. 8. The voltage generating circuit includes a third voltage for outputting a node having a fourth voltage and a voltage that is approximately twice the threshold voltage of the third and fourth transistors.
5. A resistance element connected between the third output node and the output node, and a third and a fourth diode element connected in series between the third output node and the reference voltage node. 7. The amplitude conversion circuit according to any one of 7. 9. The resistance element includes a seventh transistor connected between the node of the fourth voltage and the third output node, the input electrode of which receives a predetermined constant voltage. The amplitude conversion circuit according to claim 8. 10. The third diode element includes an eighth transistor of a second conductivity type, the input electrode and the first electrode of which are connected to the third output node, and the fourth diode. The element has an input electrode and a first
Or a second conductivity type ninth transistor having a second conductivity type connected to a second electrode of the eighth transistor, the second electrode being connected to a node of the reference voltage. Item 9. The amplitude conversion circuit according to Item 9. 11. The amplitude conversion circuit according to claim 8, wherein the fourth voltage is the same as the second voltage. 12. The first level shift circuit comprises a fifth level shift circuit.
A second transistor of the second conductivity type, the input electrode being connected between a node of the second voltage and the input electrode of the third transistor, the input electrode receiving the output voltage of the voltage generating circuit, The level shift circuit is connected between the node of the fifth voltage and the input electrode of the fourth transistor, and the input electrode receives the output voltage of the voltage generation circuit. The amplitude conversion circuit according to claim 4, comprising a transistor. 13. The amplitude conversion circuit according to claim 12, wherein the fifth voltage is the same as the second voltage. 14. The amplitude conversion circuit according to claim 1, wherein the second electrodes of the third and fourth transistors receive the first signal and its complementary signal, respectively. 15. The amplitude conversion circuit according to claim 1, wherein the second electrodes of the third and fourth transistors both receive a reference voltage. 16. The third and fourth parts, respectively.
16. A twelfth and thirteenth transistor of a second conductivity type connected in parallel to the transistor of claim 1, the input electrodes of which are connected to the second and first output nodes, respectively. The amplitude conversion circuit according to any one of claims. 17. The first and second parts, respectively.
12th and 13th of the second conductivity type connected between the output node and the reference voltage node with their input electrodes connected to said second and first output nodes, respectively.
16. The amplitude conversion circuit according to claim 1, comprising the transistor. 18. The first transistor is further connected in series between the second voltage node and the first output node, and is responsive to a leading edge of a complementary signal of the first signal. A first switching element which is non-conductive, and a trailing edge of a complementary signal of the first signal, which is connected in series with the second transistor between the node of the second voltage and the second output node. A second switching element that becomes non-conductive in response to the leading edge of the first signal corresponding to
The amplitude conversion circuit according to any one of claims 1 to 17. 19. The first switching element is connected between a second electrode of the first transistor and the first output node, the input electrode of which is connected to the input electrode of the third transistor. Fourteenth of the first conductive type connected
The second switching element is connected between the second electrode of the second transistor and the second output node, the input electrode of which is connected to the input electrode of the fourth transistor. 19. The amplitude conversion circuit according to claim 18, comprising a fifteenth transistor of the first conductivity type connected. 20. The method according to claim 1, wherein the leading edge is a rising edge and the trailing edge is a falling edge.
9. The amplitude conversion circuit according to any one of 9. 21. The method according to claim 1, wherein each of the first to fourth transistors is a thin film transistor.
The amplitude conversion circuit according to any one of 1. 22. A semiconductor device comprising a plurality of amplitude conversion circuits according to claim 4, wherein the voltage generation circuit is provided commonly to the plurality of amplitude conversion circuits.