JP2003303793A - Polishing equipment and method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the time-varying stability of polishing amount distribution in a wafer surface in a CMP process of a semiconductor manufacturing method. <P>SOLUTION: A plurality of trenches are formed at a bonding surface side between a first layer and a second layer of an abrasive pad having a double layer structure, and negative pressure is applied to the trenches, so that recesses for introducing slurry are formed on the surface of the second layer of the abrasive pad. The plurality of trenches are divided into three regions in the radial direction of the abrasive pad, and negative pressures which are controlled independently of each other are applied, so that the amount of recess on the surface of the abrasive pad can be controlled arbitrarily every region. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a polishing apparatus and a method of manufacturing a semiconductor device, and more particularly, to uniformly polishing the surface of a semiconductor wafer in a semiconductor manufacturing method or to polish the semiconductor wafer at the outer peripheral portion and the central portion. The present invention relates to a polishing apparatus suitable for making an arbitrary amount different and a method for manufacturing a semiconductor device.

[0002]

2. Description of the Related Art In recent semiconductor devices, the miniaturization of elements, the miniaturization of wirings, and the multi-layering have been advanced for the purpose of speeding up operations and reducing power consumption. In the manufacturing process of such a semiconductor device, irregularities are formed by the elements and wirings formed on the surface of the semiconductor wafer. Such unevenness may cause defective pattern formation due to insufficient depth of focus in the photolithography process when forming the next layer, or may lead to wiring loss at the step portion of the unevenness.

Therefore, in the process of manufacturing a high-density semiconductor device, the CMP method (Chemical Mechanical Method) is used to flatten the interlayer insulating film.
nical Polishing) has been introduced. Further, in recent years, the CMP method has been used also in the polishing step of the metal-embedded wiring.

In the CMP method, a slurry in which abrasive grains are mixed in a solvent having a chemical action such as an etching property with respect to a material to be polished is sprayed on a polishing pad made of a resin such as polyurethane to be polished. This is a method of polishing by pressing a semiconductor wafer against a polishing pad and sliding it.

In the CMP process of the interlayer insulating film, it is important that the film thickness after polishing is uniform over the entire surface of the semiconductor wafer. In the process of manufacturing a semiconductor device, contact holes are formed by dry etching on an interlayer insulating film that has been planarized by the CMP method. At this time, it is difficult to control the distribution of the etching amount according to the film thickness distribution of the interlayer insulating film in the semiconductor wafer surface. When the etching is performed by etching, the wiring layer is also etched at a portion where the film is thin, and the wiring is damaged. On the other hand, if etching is performed in accordance with the thin film portion, the contact hole does not reach the surface of the wiring layer in the thick film portion, resulting in poor connection.

Further, in the CMP process of the metal-embedded wiring, the surplus metal film is uniformly polished over the entire surface of the wafer,
Need to be removed. When a difference occurs in the polishing amount within the wafer surface, the polishing progresses early and the portion where the wiring is formed is excessively polished until the wiring is formed over the entire surface of the wafer. For this reason, the wiring formed early may have a reduced wiring height after polishing, so that desired electrical characteristics may not be obtained, or the wiring may be lost in an extreme case.

As described above, in the CMP step in the semiconductor device manufacturing method, it is important to uniformly polish the entire surface of the wafer. However, in a general polishing apparatus, the polishing amount in the central portion of the wafer is small, and the outer peripheral portion tends to have a large polishing amount distribution. This is due to the difference in the slurry supply amount within the wafer surface.

That is, in a general polishing apparatus, the slurry is dropped onto the polishing pad and supplied from the outer peripheral portion of the wafer toward the central portion as the polishing pad rotates.
At this time, the slurry on the polishing pad is easily removed by the outer edge of the wafer, and the amount of slurry reaching the central portion of the wafer is smaller than that of the outer peripheral portion of the wafer. Therefore, the polishing amount distribution is large in the outer peripheral portion of the wafer and small in the central portion of the wafer.

In order to correct such a non-uniform distribution of slurry on the wafer surface, a conventional method is disclosed in Japanese Patent Laid-Open No. 5-146.
As disclosed in Japanese Patent No. 969 or Japanese Patent Laid-Open No. 2001-54856, the surface of the polishing pad is promoted for the purpose of promoting the introduction of the slurry between the wafer and the polishing pad and equalizing the slurry supply amount within the wafer surface. Grooves are provided in the.

[0010]

However, such a method of improving the uniformity of the amount of polishing by the groove provided on the polishing pad has a stable effect because the groove is gradually shallowed by the conditioning of the polishing pad. There is a problem that the period is short.

As another method of promoting the introduction of slurry, there is a method of forming a recess on the surface of the polishing pad by negative pressure from the back surface of the polishing pad, as disclosed in Japanese Patent Laid-Open No. 2000-296458. In such a method, stable introduction of the slurry between the wafer and the polishing pad can be expected regardless of wear of the polishing pad.

However, Japanese Patent Laid-Open No. 2000-29645
In JP-A-8, since the same vacuum source is used for forming a recess on the surface of the polishing pad and for fixing the polishing pad to the polishing platen by suction, the magnitude of negative pressure and polishing suitable for fixing the polishing pad are used. If the negative pressure required to obtain an appropriate amount of depression on the pad surface is different, the desired effect may not be obtained.

In addition to the above-described uniformity of the amount of polishing on the wafer surface, there is a problem of film thickness distribution before polishing as a factor that impairs the uniformity of film thickness after polishing. The interlayer insulating film and the metal film after the film formation generally have a film thickness difference of approximately several percent on the inner and outer circumferences of the wafer. When a wafer having such a film thickness distribution is uniformly polished, the difference in film thickness before polishing remains after polishing. In such a case, it is necessary to carry out polishing with the film thickness distribution corrected in the film forming process in the CMP process.

In view of the above problems, the present invention is a polishing apparatus and a semiconductor which are suitable for uniformly polishing the surface of a semiconductor wafer or making the polishing amount different between the outer peripheral portion and the central portion of the semiconductor wafer by an arbitrary amount. An object is to provide a method for manufacturing a device.

[0015]

In order to solve the above problems, the present invention provides a polishing apparatus shown in the following (1) to (2) and a method for manufacturing a semiconductor device shown in the following (3) to (6). I will provide a. (1) A polishing platen having a vent hole communicating with the vacuum suction means and rotating around a rotation axis, a first layer attached to the polishing platen, and a second layer adhered to the first layer A polishing pad having a plurality of grooves formed on the adhesive surface of the first layer to the second layer and communicating with the ventilation holes of the polishing plate, and a pressure for controlling the suction pressure of the vacuum suction means. Control means, semiconductor wafer holding means for applying relative movement between the polishing pad and the semiconductor wafer, semiconductor wafer pressing means for applying a polishing load between the polishing pad and the semiconductor wafer, A polishing apparatus comprising: a slurry supply unit that supplies slurry onto a polishing pad.

(2) A plurality of vent holes communicating with independent vacuum suction means are formed, and a polishing platen rotating around a rotation axis, a first layer attached to the polishing platen, and the first plate Polishing comprising a second layer adhered to a layer, and a plurality of grooves communicating with each vent hole of the polishing platen are formed in each predetermined region on a surface of the first layer that is adhered to the second layer. Pad,
Between the pressure control means for individually controlling the suction pressure of the independent vacuum suction means, the semiconductor wafer holding means for giving relative motion between the polishing pad and the semiconductor wafer, and the polishing pad and the semiconductor wafer. A polishing apparatus comprising: a semiconductor wafer pressing means for applying a polishing load to the polishing pad; and a slurry supply means for supplying a slurry onto the polishing pad.

(3) A step of forming wiring on the semiconductor wafer, a step of forming an interlayer insulating film for covering the wiring, and means for forming a desired recess on the polishing surface of the polishing pad during polishing. And a step of polishing the interlayer insulating film with a polishing apparatus having the same.

(4) A step of forming a groove in a predetermined region on the semiconductor wafer, a step of forming a metal film on the semiconductor wafer including the inside of the groove, and a step of polishing on the polishing surface of the polishing pad. And a step of polishing the metal film with a polishing apparatus having means for forming desired depressions.

(5) A step of forming wirings on a semiconductor wafer, a step of forming an interlayer insulating film for covering the wirings, and a desired recess for each predetermined region on the polishing surface of the polishing pad during polishing. And a step of polishing the interlayer insulating film with a polishing apparatus having a means for forming a semiconductor device.

(6) Forming a groove in a predetermined region on the semiconductor wafer, forming a metal film on the semiconductor wafer including the inside of the groove, and forming an interlayer insulating film for covering the wiring. And a step of polishing the metal film with a polishing apparatus having means for forming a desired depression in each predetermined region on the polishing surface of the polishing pad during polishing.

In the polishing apparatus of the present invention, a recess having an appropriate depth for introducing a slurry can be formed on the surface of the polishing pad during polishing of the wafer, and therefore, as compared with the method of forming a groove on the surface of the polishing pad. Therefore, it becomes possible to carry out polishing while maintaining the uniformity of the polishing amount for a long period of time without being affected by polishing pad consumption. Further, since the polishing amounts of the outer peripheral portion and the central portion of the wafer can be individually controlled, uniform polishing can be performed over the entire surface of the semiconductor wafer. Further, it becomes possible to manufacture a semiconductor device using a semiconductor wafer which is uniformly polished over the entire surface.

[0022]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) FIG. 1 is a schematic view of a polishing apparatus used in the first embodiment. The present polishing apparatus drops a slurry 3 onto a polishing pad 2 attached to a polishing platen 1 and a wafer 5 at an arbitrary polishing pressure via a wafer carrier 4 to the polishing pad 2.
By pressing and rotating the polishing platen 1 to rotate the polishing pad 2
Then, polishing is performed by applying relative motion to the wafer 5.

In addition to the above-described known polishing apparatus, in this embodiment, the polishing pad 2 is composed of a first layer 2a made of soft polyurethane foam and a second layer 2b made of hard polyurethane foam. A plurality of grooves 8 communicating with the ventilation holes 6 provided in the polishing surface plate 1 are formed on the bonding surface with the second layer, and the inside of the grooves 8 is connected by the vacuum pump 7 connected to the ventilation holes 6 during polishing. Is vacuum-sucked to form a recess 9 for introducing slurry in the polishing surface of the second layer 2b of the polishing pad. The negative pressure generated by the vacuum pump 7 can be arbitrarily controlled by the pressure controller 10.

FIG. 3 shows the first polishing pad in this embodiment.
An example of layer 2a is shown. FIG. 3A is a plan view and FIG.
(B) is a sectional view. The plurality of grooves 8 provided in the first layer 2a are circular concentric about the polishing pad center, and the dimensions of the circular grooves 8 are width 5 mm, pitch 10 mm, depth 0.
It is 5 mm. Further, these plural circular grooves are communicated with each other by the groove 31, and all the grooves are equally depressurized during vacuum suction. The form of the grooves provided in the first layer of the polishing pad is not limited to the above-described dimensions. For example, as shown in FIG. 4, the grooves 42 are arranged in a lattice pattern in the first layer 41 of the polishing pad. May be.

Reference numeral 91 in FIG. 9 shows a correlation between the use time of the polishing pad and the uniformity of the polishing amount within the wafer when the SiO ₂ film formed on the wafer having a diameter of 200 mm is polished using the above polishing apparatus. ing. For comparison, the result 92 obtained by the conventional polishing method is also shown. The polishing amount uniformity U
Is a value calculated by the following formula from the maximum value Rmax and the minimum value Rmin of the polishing amount measured at 48 points on the wafer surface. U (%) = (Rmax−Rmin) / (Rmax + Rmin) × 100 (Equation 1) Polishing conditions are a polishing pressure of 280 gf / cm ² , a polishing platen rotation speed of 93 rpm, and a negative pressure for forming a recess on the polishing pad surface. Was -500 gf / cm ² . From the results shown in FIG. 9, it can be seen that according to the present invention, the uniformity of the polishing amount at the beginning of wafer polishing is maintained for a long period of time as compared with the conventional polishing method.

(Embodiment 2) FIG. 2 is a schematic view of a polishing apparatus used in the second embodiment. In this apparatus, a plurality of grooves 212, which are all in communication with each other in the polishing pad shown in the first embodiment, are communicated in every three regions on the radius of the polishing pad, and the ventilation holes 21, 22, which are communicated in each region, The vacuum pumps 24, 25, and 26 are configured to suction via 23.

The negative pressure generated by each vacuum pump is independently controlled by individually provided pressure control devices 27, 28 and 29, and each of the above three regions is provided on the polishing surface of the second layer 210b of the polishing pad 210. It is possible to form the recesses 211 having different depths.

FIG. 5 shows the polishing pad 210 in this embodiment.
The example of the first layer 210a of FIG. FIG. 5A is a plan view and FIG. 5B is a sectional view. The plurality of grooves 212 provided in the first layer 210a are circular concentric with the polishing pad center as an axis, and the circular grooves 212 have dimensions of width 5 mm, pitch 10 mm, and depth 0.5 mm. Further, the plurality of grooves 212 are formed in the region 51 where the central portion of the wafer 15 contacts.
And the groove 5 for each of the inner region 52 and the outer region 53 thereof.
4, 55, 56 communicate with each other.

The width of the region 51 in contact with the central portion of the wafer 5 is preferably about 1/3 of the wafer diameter. In this embodiment, the diameter is 2
It was about 70 mm for polishing a 00 mm wafer.
As in the first embodiment, the form of the grooves provided in the first layer of the polishing pad is not limited to the above-mentioned dimensions, and the grid-like grooves 62 are formed in the first layer of the polishing pad as shown in FIG. Layer 6
1 may be provided.

FIG. 10 shows a diameter of 200 using the above polishing apparatus.
The distribution of the polishing amount in the diameter direction of the wafer when the SiO ₂ film formed on the wafer of mm is polished is shown. Figure 10 (a)
(C) shows the negative pressure in the area 51 where the wafer central portion is in contact.
500 gf / cm ² of constant, as the same negative pressure region 52 and 53, -800gf / ^cm 2 the values, -
300 gf ^/ cm 2, the results obtained when a 0 gf / cm ^2.

From FIG. 10, by increasing the negative pressure in the other regions 52 and 53 to be larger than the negative pressure in the region 51 in contact with the central portion of the wafer, the polishing amount of the outer peripheral portion of the wafer is increased,
It can be seen that the polishing amount on the outer peripheral portion of the wafer is reduced by reducing the size. From the above, the region 51 of the polishing pad 210,
It was confirmed that by controlling the negative pressure applied to 52 and 53, the polishing amount in the central portion and the peripheral portion of the wafer can be controlled individually.

Subsequently, as shown by 111 in FIG. 11, a wafer on which an SiO ₂ film of about 1500 nm having a distribution in which the film thickness of the wafer outer peripheral portion is about 80 nm thicker than the central portion is formed is polished. Figure 10 (a) where the amount increases
When the film was polished under the conditions of No. 1 and No. 112, the film thickness after polishing was about 1200 nm over the entire surface of the wafer, and it was confirmed that the film thickness distribution before polishing could be corrected.

(Embodiment 3) Next, an embodiment of a method for manufacturing a semiconductor device using the flattening of the surface of a semiconductor wafer according to the present invention will be described with reference to FIG. (1) to (6) in FIG. 7 indicate the order of each step. First,
In the step (1), an element (not shown) such as a transistor is formed on the surface layer 71 of the semiconductor wafer, and the interlayer insulating film 72 is formed. Then, a metal film is formed to a thickness of 500 nm and patterned by a dry etching method to form a wiring layer 73. In the step (2), a SiO ₂ film having a thickness of 1000 nm is formed as the interlayer insulating film 74 by the CVD method.

Next, in the step (3), the surface of the interlayer insulating film 74 is polished and flattened by the CMP method using the polishing apparatus of the second embodiment. At this time, the film thickness difference between the outer peripheral portion and the central portion of the interlayer insulating film 74, which is generated during film formation, is corrected, so that the interlayer insulating film 74 after polishing has a uniform thickness over the entire surface of the wafer.

In the step (4), a contact hole 75 is formed to connect the wiring layer 73 and the upper wiring layer to be formed. Subsequently, after forming a titanium nitride film as a barrier film, a tungsten film is formed so as to fill the contact hole 75.

In the step (5), the excess tungsten film outside the contact hole 75 is removed by the CMP method using the polishing apparatus of the second embodiment to form the contact plug 76.

Next, in the step (6), the upper wiring layer 77 is formed by forming and patterning a metal film to complete the semiconductor device.

In the semiconductor device thus completed, the thickness of the interlayer insulating film 74 is made uniform over the entire surface of the wafer by the step (3), so that the wiring is damaged or the connection is defective due to the formation of the contact hole 75. There is no problem. Therefore, product defects are reduced and the reliability of the manufactured semiconductor device is improved. Further, in the step (5), the contact plug 76 is formed over the entire surface of the wafer almost at the same time by adjusting the polishing amount distribution according to the film thickness distribution of the surplus tungsten film in the wafer surface.

Therefore, the contact plugs formed early in the wafer surface are not excessively polished and the height is reduced, and a short circuit between the contact plugs due to the polishing residue of the excess tungsten film is not caused. . Therefore, product defects are reduced and the reliability of the manufactured semiconductor device is improved.

(Embodiment 4) Formation of Embedded Metal Wiring Using the Present Invention An example of a method of manufacturing a semiconductor device by forming embedded metal wiring will be described with reference to FIG. (1) to in FIG.
(7) shows the order of each process. In the step (1), the insulating film 83 is formed on the surface of the insulating film 82 where the lower contact plug 81 is exposed, and the contact plug 81 and the wiring layer to be formed are connected by dry etching or the like. A groove 84 having a wiring pattern is formed in the insulating film 83. In the step (2), a metal film 85 is formed by a sputtering method or the like so as to fill the groove 84 of the wiring pattern.

In the step (3), the surplus metal film on the insulating film 83 is polished and removed by the CMP method using the polishing apparatus of the second embodiment to form the wiring layer 86. In the step (4), the insulating film 87 is formed on the wiring layer 86, and the contact hole 88 is formed to connect the upper wiring layer to be formed. In the step (5), a metal film of tungsten or the like is formed so as to fill the contact hole 88 by a sputtering method or the like. In the process of (6), the contact hole 88
CM for the outer surplus metal film using the polishing apparatus of the second embodiment
The contact plug 89 is formed by removing it by the P method.

In the step (7), the insulating film 810 is formed on the surface of the insulating film 87 where the connection surface of the contact plug 89 is exposed, and the contact plug 89 and the upper wiring layer formed from this are formed by dry etching or the like. A wiring pattern groove 811 is formed in the insulating film 810 so as to be connected. By repeating the above steps (1) to (7), a semiconductor device having a multilayer wiring structure is formed.

In the semiconductor device thus completed, the polishing amount distribution is adjusted in accordance with the film thickness distribution of the surplus tungsten film in the wafer surface in the steps (3) and (6) of FIG. In 3), the metal-embedded wiring is formed almost simultaneously over the entire surface of the wafer. Also, step (6)
Then, the contact plugs 76 are formed over the entire surface of the wafer almost at the same time.

For this reason, excessive polishing occurs in a part of the wafer surface, and the height of the metal-embedded wiring or contact plug is reduced below a desired value, and between the contact plugs due to polishing residue of the excess metal film. It does not cause a short circuit defect. Therefore, product defects are reduced and the reliability of the manufactured semiconductor device is improved.

[0045]

As described above, in the polishing apparatus of the present invention, since a recess having an appropriate depth for introducing a slurry can be formed on the polishing pad surface at the time of polishing a wafer, a groove is formed on the polishing pad surface. As compared with the method of forming a polishing pad, it becomes possible to carry out polishing while maintaining the uniformity of the polishing amount for a long period of time without being affected by the wear of the polishing pad. Further, since the polishing amounts of the outer peripheral portion and the central portion of the wafer can be individually controlled, uniform polishing can be performed over the entire surface of the semiconductor wafer. Therefore, product defects due to non-uniformity of the film thickness or the polishing amount on the wafer surface in the manufacturing process of the semiconductor device are reduced, and the reliability of the manufactured semiconductor device is improved.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a polishing apparatus according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a polishing apparatus according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a polishing pad first layer according to the first embodiment of the present invention.

FIG. 4 is a view showing a configuration of a polishing pad first layer according to the first embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a polishing pad first layer according to a second embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a polishing pad first layer according to a second embodiment of the present invention.

FIG. 7 is a diagram showing an example of a method of manufacturing a semiconductor device using planarization of a wafer surface.

FIG. 8 is a diagram showing an example of a method for manufacturing a semiconductor device by forming a metal-embedded wiring.

FIG. 9 is a diagram showing a correlation between a polishing pad usage time and polishing amount uniformity.

FIG. 10 is a diagram showing a polishing amount distribution when the polishing apparatus according to the embodiment of the present invention is used.

FIG. 11 is a diagram showing a film thickness distribution before and after polishing.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Polishing surface plate, 2 ... Polishing pad, 2a ... 1st layer of polishing pad, 2b ... 2nd layer of polishing pad, 3 ... Slurry, 4 ... Wafer carrier, 5 ... Wafer, 6 ... Vent hole, 7 ... Vacuum Pump, 8 ... Groove of polishing pad first layer, 9 ... Depression of polishing pad second layer surface, 10 ... Pressure controller, 21, 22, 23 ... Vent hole, 24, 25, 26 ... Vacuum pump, 27, 28 Two
9 ... Pressure controller, 210 ... Polishing pad, 210a ... 1st layer of polishing pad, 210b ... 2nd layer of polishing pad, 21
1 ... Recess of polishing pad second layer surface, 212, 31, 42
... groove of polishing pad first layer, 41 ... first layer of polishing pad,
51, 52, 53 ... areas on the polishing pad, 54, 55,
56, 61 ... First layer of polishing pad, 62 ... Groove of polishing pad first layer, 71 ... Wafer surface layer, 72, 74 ... Interlayer insulating film, 73, 77, 86 ... Wiring layer, 75, 88 ... Contact Hole, 76, 81, 89 ... Contact plug, 8
2, 83, 87, 810 ... Insulating film, 84 ... Wiring pattern groove, 85 ... Metal film, 811 ... Wiring pattern groove, 91
... polishing amount uniformity property in the present invention, 92 ... polishing amount uniformity property by a conventional method, 111 ... film thickness distribution curve before polishing, 112 ... film thickness distribution curve after polishing

Claims (6)

[Claims] 1. A polishing platen having a vent hole communicating with the vacuum suction means and rotating about a rotation axis, a first layer attached to the polishing platen, and a first layer adhered to the first layer. Two
A polishing pad having a plurality of grooves formed on the adhesive surface of the first layer to the second layer and communicating with the ventilation holes of the polishing platen; and controlling the suction pressure of the vacuum suction means. Pressure control means, semiconductor wafer holding means for applying relative motion between the polishing pad and the semiconductor wafer, and semiconductor wafer pressing means for applying a polishing load between the polishing pad and the semiconductor wafer And a slurry supply means for supplying a slurry onto the polishing pad. 2. A polishing platen having a plurality of vent holes communicating with independent vacuum suction means and rotating around a rotation axis, a first layer attached to the polishing platen, and the first plate.
Polishing comprising a second layer adhered to a layer, and a plurality of grooves communicating with each vent hole of the polishing platen are formed in each predetermined region on a surface of the first layer that is adhered to the second layer. A pad, pressure control means for individually controlling the suction pressure of the independent vacuum suction means, semiconductor wafer holding means for providing relative movement between the polishing pad and the semiconductor wafer, the polishing pad and the semiconductor A polishing apparatus comprising: a semiconductor wafer pressurizing unit for applying a polishing load to a wafer; and a slurry supplying unit for supplying slurry onto the polishing pad. 3. A step of forming wiring on a semiconductor wafer,
A semiconductor device comprising: a step of forming an interlayer insulating film covering the wiring; and a step of polishing the interlayer insulating film with a polishing apparatus having means for forming a desired recess on a polishing surface of a polishing pad during polishing. Manufacturing method. 4. A step of forming a groove in a predetermined region on a semiconductor wafer, a step of forming a metal film on the semiconductor wafer including the inside of the groove, and a step of polishing on a polishing surface of a polishing pad. And a step of polishing the metal film with a polishing apparatus having means for forming a desired depression. 5. A step of forming wiring on a semiconductor wafer,
A step of forming an interlayer insulating film for covering the wiring, and a step of polishing the interlayer insulating film by a polishing device having means for forming a desired depression in each predetermined region on the polishing surface of the polishing pad A method for manufacturing a semiconductor device having: 6. A step of forming a groove in a predetermined region on a semiconductor wafer, a step of forming a metal film on the semiconductor wafer including the inside of the groove, and an interlayer insulating film for covering the wiring. A method of manufacturing a semiconductor device, comprising: a step of polishing the metal film with a polishing apparatus having a means for forming a desired recess in each predetermined region on the polishing surface of the polishing pad.