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CN113539952B - Process control method for copper CMP - Google Patents

Process control method for copper CMP Download PDF

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Publication number
CN113539952B
CN113539952B CN202110723556.3A CN202110723556A CN113539952B CN 113539952 B CN113539952 B CN 113539952B CN 202110723556 A CN202110723556 A CN 202110723556A CN 113539952 B CN113539952 B CN 113539952B
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China
Prior art keywords
copper
copper cmp
dielectric layer
process control
cmp
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CN202110723556.3A
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Chinese (zh)
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CN113539952A (en
Inventor
黄景山
裴雷洪
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Shanghai Huali Integrated Circuit Manufacturing Co Ltd
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Priority to CN202110723556.3A priority Critical patent/CN113539952B/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/04—Lapping machines or devices; Accessories designed for working plane surfaces
    • B24B37/07—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool
    • B24B37/10—Lapping machines or devices; Accessories designed for working plane surfaces characterised by the movement of the work or lapping tool for single side lapping
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/11—Lapping tools
    • B24B37/20—Lapping pads for working plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/27—Work carriers
    • B24B37/30—Work carriers for single side lapping of plane surfaces
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B37/00—Lapping machines or devices; Accessories
    • B24B37/34—Accessories
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B24—GRINDING; POLISHING
    • B24B—MACHINES, DEVICES, OR PROCESSES FOR GRINDING OR POLISHING; DRESSING OR CONDITIONING OF ABRADING SURFACES; FEEDING OF GRINDING, POLISHING, OR LAPPING AGENTS
    • B24B57/00—Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents
    • B24B57/02—Devices for feeding, applying, grading or recovering grinding, polishing or lapping agents for feeding of fluid, sprayed, pulverised, or liquefied grinding, polishing or lapping agents
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76831—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches, e.g. non-conductive sidewall liners
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H01L21/76879—Filling of holes, grooves or trenches, e.g. vias, with conductive material by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating

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  • Engineering & Computer Science (AREA)
  • Mechanical Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)

Abstract

The invention discloses a copper CMP process control method, which comprises the following steps: etching the first dielectric layer to form a groove; measuring the residual thickness of the first dielectric layer at the bottom of the groove; forming a copper layer to completely fill the groove and extend the groove to the surface of the first dielectric layer outside the groove; step four, copper CMP is carried out to remove a copper layer outside the groove and form a copper wire by the copper layer filled in the groove; and (3) adjusting the polishing time of the copper CMP according to the residual thickness of the first dielectric layer measured in the second step so as to enable the thickness of the copper wire to reach a first target value. The method can eliminate the adverse effect of the dielectric layer etching process before copper CMP on the thickness of the copper wire and can improve the yield of products.

Description

Process control method for copper CMP
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a process control method for copper Chemical Mechanical Polishing (CMP).
Background
In semiconductor integrated circuit fabrication, the formation process of copper lines often requires the use of a damascene process, which is to first form trenches, then refill the copper layer, then perform copper CMP to remove the copper layer outside the trenches and grind the copper layer inside the trenches to the desired thickness and form the copper lines. Copper CMP is often required in the damascene process.
As shown in fig. 1, a schematic structural diagram of a conventional CMP apparatus is shown, where the conventional CMP apparatus includes a chassis device, i.e., a polishing table 101, and the polishing table 101 is driven to rotate by a rotating device, and in fig. 1, the polishing table 101 is shown to rotate by a rotating line.
The polishing table 101 is provided with a polishing pad 102.
A wafer 103 is held on the polishing head 104, the polishing head 104 is rotated, and the polishing head 104 is further provided with a means for applying pressure so that the wafer 103 is pressed against the polishing pad 102.
The Slurry 106 including the abrasive particles and the Slurry (Slurry) is supplied from the Slurry pipe to the Slurry nozzle 105 and flows onto the polishing pad 102 through the Slurry nozzle 105.
During polishing, the polishing head 104 contacts the wafer 104 with the polishing pad 102, applies pressure and rotates, and then polishes the film layer of the wafer 104. During polishing, the polishing liquid 106 is mainly used for increasing the hydrogen bonding capability of the surface materials and water of various wafers 103 such as silicon wafers, increasing the molecular affinity of the materials to be polished and the polishing pad, and simultaneously, the polished particles can also carry away the polished material particles.
The diamond 108 is arranged on the diamond disc 107, and the diamond disc 107 can also be selected; the masonry disk 107 can sweep over the polishing pad 102 to remove polishing residue from the polishing pad 102 and to maintain the surface of the polishing pad 102 rough.
In copper CMP, since the process of performing trench etching, i.e., front layer etching, is included before copper CMP, the thickness of the dielectric layer remaining at the bottom of the trench after front layer etching affects the thickness of the copper line after copper CMP, and finally affects the electrical parameters of the resistivity (Rs) of the device, thereby affecting the yield of the product.
Disclosure of Invention
The invention aims to solve the technical problem of providing a process control method of copper CMP, which can eliminate the adverse effect of a dielectric layer etching process before copper CMP on the thickness of a copper wire and can improve the yield of products.
In order to solve the technical problems, the process control method of copper CMP provided by the invention comprises the following steps:
Step one, providing a first dielectric layer, and etching the first dielectric layer to form a groove, wherein the groove is positioned in a copper wire forming area.
And step two, measuring the residual thickness of the first dielectric layer at the bottom of the groove.
And thirdly, forming a copper layer, wherein the groove is completely filled by the copper layer and extends to the surface of the first dielectric layer outside the groove.
Step four, performing copper CMP, wherein the copper CMP removes the copper layer outside the groove, and levels the top surface of the copper layer in the groove and the top surface of the first dielectric layer outside the groove, and the copper wire is formed by the copper layer filled in the groove; and (3) the polishing time of the copper CMP is also adjusted according to the residual thickness of the first dielectric layer measured in the second step, so that the thickness of the copper wire reaches a first target value.
In the fourth step, the relation between the adjustment value of the polishing time of the copper CMP and the residual thickness of the first dielectric layer is:
Wherein Δt represents an adjustment value of the polishing time of the copper CMP, rox represents a remaining thickness of the first dielectric layer, TARGET2 represents a second TARGET value of the remaining thickness of the first dielectric layer, and RR represents a polishing rate of the copper CMP.
A further improvement is that the polishing time of the copper CMP is the initial set value of the polishing time of the copper CMP minus the adjustment value.
Further, the initial set value of the polishing time of the copper CMP is an average value of polishing times required for the thickness of the copper wire to reach the first target value among the plurality of copper CMP.
A further improvement is that RR takes the maximum value of the polishing rate of the last copper CMP.
In a further improvement, the first dielectric layer is an interlayer film formed on the semiconductor substrate.
In the first step, a through hole opening is formed at the same time, and the through hole opening completely penetrates through the first dielectric layer and exposes the surface of the bottom metal wire;
And thirdly, filling the through hole opening by the copper layer and forming the through hole.
Further improvement is that the underlying metal line is formed in an underlying interlayer film.
In a further improvement, the semiconductor substrate and the first dielectric layer are preceded by more than one layer of interlayer films and bottom metal wires, and the bottom metal wires are connected through bottom through holes.
Further improvement is that the material of the bottom metal wire comprises copper, and the process control step of copper CMP of the bottom metal wire composed of copper material is the same as the process control step of copper CMP of the copper wire.
A further improvement is that the semiconductor substrate comprises a silicon substrate.
A further improvement is that the material of the first dielectric layer comprises a low dielectric constant layer.
Further improvements are that the material of the underlying interlayer film includes a low dielectric constant layer.
A further improvement is that the low dielectric constant layer comprises SiCOH.
A further improvement is that a SiCN layer is also spaced between the first dielectric layer and the underlying interlayer film of the next layer.
The method is further improved in that after the second step is completed, the residual thickness of the first dielectric layer is directly calculated to obtain an adjustment value of the copper CMP polishing time, then the adjustment value of the copper CMP polishing time is imported to a running (R2R) system, and then the running system feeds back the adjustment value of the copper CMP polishing time to a copper CMP polishing machine table to achieve automatic adjustment of the copper CMP polishing time.
The method is further improved in that after the second step is completed, the residual thickness of the first dielectric layer is directly calculated to be an adjustment value of the copper CMP grinding time, and then the copper CMP grinding time is directly adjusted on a copper CMP grinding machine in a manual mode.
In copper CMP, the copper CMP and the previous dielectric layer etching process have relevance, namely the previous dielectric layer etching process before copper CMP influences the copper CMP.
Drawings
The invention is described in further detail below with reference to the attached drawings and detailed description:
FIG. 1 is a schematic view of a conventional chemical mechanical polishing apparatus;
FIG. 2 is a flow chart of a process control method for copper CMP in accordance with an embodiment of the present invention;
Fig. 3A-3D are schematic views of device structures at each step of a process control method for copper CMP according to an embodiment of the present invention.
Detailed Description
FIG. 2 is a flow chart of a process control method for copper CMP according to an embodiment of the invention; as shown in fig. 3A to 3D, a schematic device structure of each step of the process control method of copper CMP according to an embodiment of the present invention is shown; the process control method of the copper CMP comprises the following steps:
step one, as shown in fig. 3A, a first dielectric layer 204 is provided. The top surface of the first dielectric layer 204 is marked with a mark 2041.
As shown in fig. 3B, the first dielectric layer 204 is etched to form a trench 205, where the trench 205 is located in a copper line 208 forming region.
In the embodiment of the present invention, taking copper CMP in a dual damascene process as an example, the trench 205 is formed and the via opening 206 is formed at the same time, and the via opening 206 completely penetrates the first dielectric layer 204 and exposes the surface of the underlying metal line 202.
In the embodiment of the present invention, the first dielectric layer 204 is an interlayer film formed on a semiconductor substrate.
The underlying metal line 202 is formed in the underlying interlayer film 201.
The semiconductor substrate and the first dielectric layer 204 previously include more than one layer of the bottom interlayer film 201 and the bottom metal lines 202, and the bottom metal lines 202 are connected through bottom through holes 209.
The semiconductor substrate includes a silicon substrate.
The material of the first dielectric layer 204 includes a low dielectric constant layer.
The material of the underlayer interlayer film 201 includes a low dielectric constant layer.
Preferably, the low dielectric constant layer comprises SiCOH.
A SiCN layer 203 is further interposed between the first dielectric layer 204 and the underlying interlayer film 201 of the next layer.
Step two, as shown in fig. 3B, the remaining thickness d1 of the first dielectric layer 204 at the bottom of the trench 205 is measured.
Step three, as shown in fig. 3C, a copper layer 207 is formed, and the copper layer 207 completely fills the trench 205 and extends to the surface of the first dielectric layer 204 outside the trench 205.
Step four, as shown in fig. 3D, performing copper CMP, wherein the copper CMP removes the copper layer 207 outside the trench 205 and levels the top surface of the copper layer 207 inside the trench 205 and the top surface of the first dielectric layer 204 outside the trench 205, and the copper line 208 is formed by the copper layer 207 filled in the trench 205; the polishing time of the copper CMP is further adjusted according to the remaining thickness d1 of the first dielectric layer 204 measured in the second step, so that the thickness d2 of the copper line 208 reaches a first target value.
In the embodiment of the present invention, the relationship between the adjustment value of the polishing time of the copper CMP and the remaining thickness d1 of the first dielectric layer 204 is:
Wherein Δt represents an adjustment value of the polishing time of the copper CMP, rox represents a remaining thickness d1 of the first dielectric layer 204, TARGET2 represents a second TARGET value of the remaining thickness d1 of the first dielectric layer 204, and RR represents a polishing rate of the copper CMP.
The polishing time of the copper CMP is the initial set value of the polishing time of the copper CMP minus the adjustment value.
The initial set value of the polishing time of the copper CMP is an average value of polishing times required to bring the thickness d2 of the copper wire 208 to the first target value among the plurality of the copper CMP. Namely: the method for obtaining the initial set value of the copper CMP polishing time comprises the following steps:
The polishing time required to bring the thickness d2 of the copper wire 208 to the first target value in the most recent copper CMP, for example, 25 times, is generally counted as the polishing time required to bring the thickness d2 of the copper wire 208 to the first target value in the most recent copper CMP of the same product or similar product.
And averaging the counted multiple grinding time to obtain an initial set value of the copper CMP grinding time.
RR is the maximum value of the polishing rate of the last copper CMP.
As can be seen from fig. 3D, the copper CMP lowers the top surface of the first dielectric layer 204 from the position of the dashed line 2041 to the position of the line 2042, and the loss thickness of the first dielectric layer 204 is denoted by D3.
The copper layer 207 completes the filling of the via opening 206 and forms the via 209.
The material of the bottom metal line 202 includes copper, and the process control step of copper CMP of the bottom metal line 202 composed of copper material is the same as the process control step of copper CMP of the copper line 208.
In the embodiment of the present invention, after the second step is completed, the remaining thickness d1 of the first dielectric layer 204 is directly calculated to obtain the adjustment value of the polishing time of the copper CMP, then the adjustment value of the polishing time of the copper CMP is imported into a cargo running system, and then the cargo running system feeds back the adjustment value of the polishing time of the copper CMP to the polishing platform of the copper CMP to realize automatic adjustment of the polishing time of the copper CMP. In other embodiments can also be: and after the second step is completed, directly calculating the adjustment value of the polishing time of the copper CMP by the residual thickness d1 of the first dielectric layer 204, and then directly adjusting the polishing time of the copper CMP on a polishing machine of the copper CMP in a manual mode. The manual adjustment can be performed when the running system is not yet applied, for example, the polishing time of the copper CMP can be adjusted by the manual adjustment in a new product test strip stage.
In copper CMP, there is a correlation between the copper CMP and the previous dielectric layer etching process, that is, the dielectric layer etching process before copper CMP, that is, the previous layer etching process may affect copper CMP, and in the embodiment of the present invention, the remaining thickness d1 of the first dielectric layer 204 at the bottom of the trench 205 is measured after etching the first dielectric layer 204, and the polishing time of copper CMP is adjusted according to the remaining thickness d1 of the first dielectric layer 204, so that the thickness d2 of the copper line 208 after copper CMP can be kept to be the target value, that is, the first target value, so that the adverse effect of the dielectric layer etching process before copper CMP on the thickness of the copper line 208 can be eliminated, and finally, the resistivity of the device can be kept stable, and thus the product yield can be improved.
The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims (15)

1. A process control method for copper CMP, comprising the steps of:
step one, providing a first dielectric layer, and etching the first dielectric layer to form a groove, wherein the groove is positioned in a copper wire forming area;
measuring the residual thickness of the first dielectric layer at the bottom of the groove;
Forming a copper layer, wherein the groove is completely filled by the copper layer and extends to the surface of the first dielectric layer outside the groove;
Step four, performing copper CMP, wherein the copper CMP removes the copper layer outside the groove, and levels the top surface of the copper layer in the groove and the top surface of the first dielectric layer outside the groove, and the copper wire is formed by the copper layer filled in the groove; the polishing time of the copper CMP is also adjusted according to the residual thickness of the first dielectric layer measured in the second step, so that the thickness of the copper wire reaches a first target value;
the relation between the adjustment value of the copper CMP grinding time and the residual thickness of the first dielectric layer is as follows:
Wherein Δt represents an adjustment value of the polishing time of the copper CMP, rox represents a remaining thickness of the first dielectric layer, TARGET2 represents a second TARGET value of the remaining thickness of the first dielectric layer, and RR represents a polishing rate of the copper CMP;
the polishing time of the copper CMP is the initial set value of the polishing time of the copper CMP minus the adjustment value.
2. The process control method for copper CMP according to claim 1, wherein: the initial set value of the polishing time of the copper CMP is an average value of polishing times required to bring the thickness of the copper wire to the first target value in the copper CMP a plurality of times.
3. The process control method for copper CMP according to claim 1, wherein: RR is the maximum value of the polishing rate of the last copper CMP.
4. The process control method for copper CMP according to claim 1, wherein: the first dielectric layer is an interlayer film formed on the semiconductor substrate.
5. The process control method for copper CMP according to claim 4, wherein: simultaneously forming a through hole opening, wherein the through hole opening completely penetrates through the first dielectric layer and exposes the surface of the bottom metal wire;
And thirdly, filling the through hole opening by the copper layer and forming the through hole.
6. The process control method for copper CMP according to claim 5, wherein: the underlying metal line is formed in the underlying interlayer film.
7. The process control method for copper CMP according to claim 6, wherein: the semiconductor substrate and the first dielectric layer are preceded by more than one layer of interlayer films and bottom metal wires, and the bottom metal wires are connected through bottom through holes.
8. The process control method for copper CMP according to claim 7, wherein: the material of the bottom metal wire comprises copper, and the process control step of copper CMP of the bottom metal wire composed of copper material is the same as the process control step of copper CMP of the copper wire.
9. The process control method for copper CMP according to claim 7, wherein: the semiconductor substrate includes a silicon substrate.
10. The process control method for copper CMP according to claim 9, wherein: the material of the first dielectric layer comprises a low dielectric constant layer.
11. The process control method for copper CMP according to claim 10, wherein: the material of the bottom interlayer film comprises a low dielectric constant layer.
12. The process control method for copper CMP according to claim 11, wherein: the low dielectric constant layer includes SiCOH.
13. The process control method for copper CMP according to claim 9, wherein: and a SiCN layer is also arranged between the first dielectric layer and the bottom interlayer film of the next layer.
14. The process control method for copper CMP according to claim 1, wherein: and step two, directly calculating the adjustment value of the polishing time of the copper CMP by the residual thickness of the first dielectric layer after the step two is completed, then guiding the adjustment value of the polishing time of the copper CMP into a running system, and then feeding back the adjustment value of the polishing time of the copper CMP to a polishing machine of the copper CMP by the running system to realize automatic adjustment of the polishing time of the copper CMP.
15. The process control method for copper CMP according to claim 1, wherein: and step two, directly calculating the adjustment value of the polishing time of the copper CMP by the residual thickness of the first dielectric layer after the step two is completed, and then directly adjusting the polishing time of the copper CMP on a polishing machine of the copper CMP in a manual mode.
CN202110723556.3A 2021-06-29 2021-06-29 Process control method for copper CMP Active CN113539952B (en)

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Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200507092A (en) * 2003-08-13 2005-02-16 Promos Technologies Inc Method for controlling cmp process
CN102760684A (en) * 2011-04-26 2012-10-31 中芯国际集成电路制造(上海)有限公司 Metal interconnection method
CN108406575A (en) * 2018-02-05 2018-08-17 上海华虹宏力半导体制造有限公司 CMP grinding method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6881664B2 (en) * 2001-08-28 2005-04-19 Lsi Logic Corporation Process for planarizing upper surface of damascene wiring structure for integrated circuit structures
US7083495B2 (en) * 2003-11-26 2006-08-01 Taiwan Semiconductor Manufacturing Company, Ltd. Advanced process control approach for Cu interconnect wiring sheet resistance control

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200507092A (en) * 2003-08-13 2005-02-16 Promos Technologies Inc Method for controlling cmp process
CN102760684A (en) * 2011-04-26 2012-10-31 中芯国际集成电路制造(上海)有限公司 Metal interconnection method
CN108406575A (en) * 2018-02-05 2018-08-17 上海华虹宏力半导体制造有限公司 CMP grinding method

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