JP2003234378A - Manufacturing method of semiconductor device, and semiconductor mounting equipment - Google Patents
Manufacturing method of semiconductor device, and semiconductor mounting equipmentInfo
- Publication number
- JP2003234378A JP2003234378A JP2002034600A JP2002034600A JP2003234378A JP 2003234378 A JP2003234378 A JP 2003234378A JP 2002034600 A JP2002034600 A JP 2002034600A JP 2002034600 A JP2002034600 A JP 2002034600A JP 2003234378 A JP2003234378 A JP 2003234378A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- semiconductor
- circuit board
- block body
- back surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
- H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
- H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
- H01L2924/3511—Warping
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、フリップチップ実
装技術を用いた半導体装置の製造方法と半導体実装設備
に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device manufacturing method and semiconductor mounting equipment using a flip chip mounting technique.
【０００２】[0002]
【従来の技術】半導体プロセスの微細化技術の進歩に伴
って、半導体パッケージの形態が、ＱＦＰからμＢＧ
Ａ、ＣＳＰへと進化し、さらには半導体ベアチップを直
接回路基板上に接続するフリップチップ実装へと進化し
ている。中でもフリップチップ実装は、半導体素子と回
路基板とが直接実装されているため、高速信号処理を必
要とする機器への応用展開が今後一層加速するものと思
われる。2. Description of the Related Art With the progress of miniaturization technology of semiconductor processes, the form of a semiconductor package is changed from QFP to μBG.
It has evolved to A and CSP, and further to flip chip mounting in which a semiconductor bare chip is directly connected to a circuit board. Among them, the flip-chip mounting is expected to further accelerate the application and development to devices that require high-speed signal processing because the semiconductor element and the circuit board are directly mounted.
【０００３】このフリップチップ実装を実現するために
は、高度な実装プロセス技術が必要不可欠であり、半導
体素子と回路基板との接合を短時間でかつ高い信頼性を
確保できるプロセス技術及び設備が特に重要である。In order to realize this flip-chip mounting, a high-level mounting process technology is indispensable, and a process technology and equipment which can secure a high reliability in a short time for joining a semiconductor element and a circuit board are particularly required. is important.
【０００４】以下、フリップチップ実装技術を用いて実
装を行う場合の一例について、図５、図６を参照して説
明する。図５は従来の半導体実装設備を用いて半導体素
子を回路基板上にフリップチップ実装する工程の模式図
であり、図６は製造される半導体装置の拡大詳細図であ
る。An example of mounting using the flip-chip mounting technique will be described below with reference to FIGS. 5 and 6. FIG. 5 is a schematic view of a process of flip-chip mounting a semiconductor element on a circuit board using a conventional semiconductor mounting equipment, and FIG. 6 is an enlarged detailed view of a manufactured semiconductor device.
【０００５】従来の半導体実装設備を示す図５におい
て、２１は半導体素子２５を実装位置まで搬送して加圧
する加圧ヘッド、２２は加圧ヘッド２１の下部に設けら
れた吸着プレートで半導体素子２５を吸着保持する。２
３は回路基板２４を保持するベース台である。In FIG. 5 showing the conventional semiconductor mounting equipment, 21 is a pressure head for conveying the semiconductor element 25 to a mounting position and pressurizing it, and 22 is a suction plate provided under the pressure head 21 for the semiconductor element 25. Hold by adsorption. Two
Reference numeral 3 is a base table for holding the circuit board 24.
【０００６】次に、半導体装置の製造工程を説明する
と、まず半導体素子２５に形成されている電極パッド２
６上にＡｕ線を溶融した２段突起形状のバンプ２７を形
成した後、この半導体素子２５を加圧ヘッド２１の吸着
プレート２２にてフェースダウンして保持するととも
に、バンプ２７の２段突起部に導電性接着剤２９を転写
し、ベース台２３上の回路基板２４上にフリップチップ
実装し、回路基板２４にパターン形成した端子電極２８
と接合している。このように加圧ヘッド２１にて吸着プ
レート２２を介して半導体素子２５にある一定圧の荷重
を印加した状態で回路基板２４と確実に接合させる方法
を用いている。その後、導電性接着剤２９を加熱硬化さ
せた後、さらに回路基板２４と半導体素子２５との間の
隙間に液状のエポキシ系封止樹脂３０を充填し、硬化さ
せている。Next, the manufacturing process of the semiconductor device will be described. First, the electrode pad 2 formed on the semiconductor element 25.
After the bump 27 having a two-step projection shape in which the Au wire is melted is formed on the semiconductor chip 6, the semiconductor element 25 is held face down by the suction plate 22 of the pressure head 21 and the two-step projection part of the bump 27 is held. A conductive adhesive 29 is transferred onto the circuit board 24, flip-chip mounted on the circuit board 24 on the base 23, and the pattern-formed terminal electrodes 28 are formed on the circuit board 24.
It is joined with. In this way, a method is used in which the pressure head 21 is surely bonded to the circuit board 24 while applying a constant pressure load to the semiconductor element 25 via the suction plate 22. After that, the conductive adhesive 29 is heated and hardened, and then a liquid epoxy-based encapsulating resin 30 is filled in the gap between the circuit board 24 and the semiconductor element 25 and hardened.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、図５で
示した従来例の製造方法では、回路基板２４自体に厚み
があって比較的剛性が高く、半導体素子２５に近い熱膨
張係数で、かつ１個の半導体素子２５をフリップチップ
実装する場合に関しては特に問題はないと思われるが、
図７に示すように、実際に複数個の半導体素子２５を回
路基板２４にフリップチップ実装する際には、回路基板
２４の反りや歪みの影響で、実装状態が（Ａ）〜（Ｃ）
に示すような挙動を示すとともに、半導体素子２５自体
においても、図８に示すように、ロット間ばらつきの影
響で（ａ）〜（ｃ）のような高さばらつきが発生する。However, in the manufacturing method of the conventional example shown in FIG. 5, the circuit board 24 itself is thick and has relatively high rigidity, a thermal expansion coefficient close to that of the semiconductor element 25, and 1 It seems that there is no particular problem when flip chip mounting the individual semiconductor elements 25,
As shown in FIG. 7, when a plurality of semiconductor elements 25 are actually flip-chip mounted on the circuit board 24, the mounting states are (A) to (C) due to the influence of the warp or distortion of the circuit board 24.
In addition to the behavior as shown in FIG. 8, in the semiconductor element 25 itself, as shown in FIG. 8, height variations as shown in (a) to (c) occur due to the influence of lot-to-lot variation.
【０００８】このように高さばらつきや反りがある状態
で実装すると、半導体素子２５の平行度も必然的にずれ
る方向へと作用するが、従来の構成では加圧ヘッド２１
と吸着プレート２２が剛性的に固定されているため、半
導体素子２５の高さばらつきや図７の（Ｂ）に示すよう
な傾きを抑制することは極めて困難である。If the semiconductor element 25 is mounted in a state in which there is height variation or warpage, the parallelism of the semiconductor element 25 inevitably shifts. However, in the conventional configuration, the pressure head 21 is used.
Since the suction plate 22 is rigidly fixed, it is extremely difficult to suppress the height variation of the semiconductor element 25 and the inclination as shown in FIG. 7B.
【０００９】また、回路基板２４に発生した反りや歪み
を矯正するために、ベース台２３に吸着用の溝もしくは
孔を設け、回路基板２４の反りを抑制させる方法も考え
られるが、導電性接着剤２９を硬化させるためには、一
旦吸着を解除させる必要性があるため、この影響で反り
が初期状態に戻り、接合部に不具合が発生する。また、
導電性接着剤２９の硬化工程が乾燥機を用いたバッチ処
理であるため、この硬化工程の搬送時に何らかのダメー
ジを接合部に与える可能性があるとともに、生産リード
タイムが長くなり、量産性に課題を有する。In addition, in order to correct the warp or distortion generated in the circuit board 24, a method for suppressing the warp of the circuit board 24 by providing a groove or hole for suction in the base 23 is conceivable. In order to cure the agent 29, it is necessary to once release the adsorption, and this influence causes the warp to return to the initial state, causing a defect in the joint portion. Also,
Since the curing process of the conductive adhesive 29 is a batch process using a dryer, some damage may be caused to the joint portion during the transportation of this curing process, the production lead time becomes long, and mass productivity is a problem. Have.
【００１０】また、半導体素子２５と回路基板２４の隙
間に充填された封止樹脂３０の加熱硬化に対しても従来
は乾燥機を用いたバッチ処理を行っており、複数個の半
導体素子２５を一連のプロセス中で一括処理するために
は、従来の方法では困難を来すという問題がある。Further, in order to heat and cure the sealing resin 30 filled in the gap between the semiconductor element 25 and the circuit board 24, conventionally, batch processing using a dryer is performed, and a plurality of semiconductor elements 25 are There is a problem that conventional methods are difficult to perform batch processing in a series of processes.
【００１１】本発明は、上記従来の問題点に鑑み、回路
基板の反り・歪みや半導体素子の高さ寸法ばらつきがあ
っても確実に信頼性の高い接合を実現でき、さらに回路
基板上に複数個の半導体素子を短時間で一括して接合す
ることができる半導体装置の製造方法及び半導体実装設
備を提供することを目的とする。In view of the above-mentioned conventional problems, the present invention can surely realize highly reliable bonding even if there is warp / distortion of a circuit board or variations in height of semiconductor elements. An object of the present invention is to provide a semiconductor device manufacturing method and semiconductor mounting equipment capable of collectively bonding individual semiconductor elements in a short time.
【００１２】[0012]
【課題を解決するための手段】本発明の半導体装置の製
造方法は、回路基板上に半導体素子をフリップチップ実
装し、半導体素子の裏面を加圧しながら回路基板と半導
体素子の間に介在させた樹脂を加熱硬化させる半導体装
置の製造方法であって、ばね構造を有するブロック体を
半導体素子の裏面に対向配置する第１工程と、半導体素
子の裏面をブロック体を介して加圧しながら樹脂を加熱
硬化する第２工程とを備えたものであり、ばね構造を有
するブロック体にて加圧した状態で半導体素子と回路基
板の間の樹脂を加熱硬化させるので、回路基板の反り・
歪みや半導体素子の高さ寸法ばらつきがあっても確実に
信頼性の高い接合を実現でき、さらに回路基板上に複数
個の半導体素子を接合する場合も一括して短時間で接合
して半導体装置を製造することができる。According to a method of manufacturing a semiconductor device of the present invention, a semiconductor element is flip-chip mounted on a circuit board, and the back surface of the semiconductor element is pressed and interposed between the circuit board and the semiconductor element. A method of manufacturing a semiconductor device, comprising heating and curing a resin, comprising: a first step of arranging a block body having a spring structure opposite to a back surface of a semiconductor element; and heating the resin while pressurizing the back surface of the semiconductor element through the block body. The second step of curing is performed, and the resin between the semiconductor element and the circuit board is heated and cured while being pressed by the block body having the spring structure.
Even if there are distortions or variations in the height of semiconductor elements, reliable bonding can be reliably realized. Furthermore, when a plurality of semiconductor elements are bonded on a circuit board, they can be bonded together in a short time. Can be manufactured.
【００１３】また、第１の工程において、複数のブロッ
ク体が回路基板上に実装された複数の半導体素子の各々
に対向した位置に配置され、各ブロック体で半導体素子
の裏面を一括して加圧加熱硬化すると、複数個の半導体
素子を個々に確実にかつ短時間で一括して接合すること
ができる。Further, in the first step, a plurality of block bodies are arranged at positions facing each of the plurality of semiconductor elements mounted on the circuit board, and the back surface of the semiconductor element is collectively applied by each block body. When pressure-hardened, a plurality of semiconductor elements can be individually and collectively bonded together in a short time.
【００１４】また、半導体素子の電極部に設けた二段突
起バンプの先端に導電性接着剤を付着する工程と、回路
基板に半導体素子をフェースダウンにて実装後導電性接
着剤を熱硬化する工程と、半導体素子と回路基板の隙間
に熱硬化性樹脂から成る封止樹脂を充填する工程と、ブ
ロック体を介して半導体素子の裏面を加圧し、封止樹脂
を加圧加熱硬化する工程とを有すると、導電性接着剤に
よる接合と封止樹脂による固定封止を行うことによって
高い信頼性を持って接合することができる。Further, a step of attaching a conductive adhesive to the tips of the two-step projection bumps provided on the electrode portion of the semiconductor element, and mounting the semiconductor element face down on the circuit board, and then thermosetting the conductive adhesive. A step, a step of filling a gap between the semiconductor element and the circuit board with a sealing resin made of a thermosetting resin, a step of pressing the back surface of the semiconductor element through a block body, and a step of press-heating and curing the sealing resin. By having the above, it is possible to perform the bonding with high reliability by performing the bonding with the conductive adhesive and the fixed sealing with the sealing resin.
【００１５】また、回路基板の端子電極上に、導電性粒
子を充填された樹脂層を形成する工程と、電極パッドに
バンプを形成した半導体素子を回路基板上にフリップチ
ップ実装する工程と、ブロック体を介して半導体素子の
裏面を加圧し、バンプと端子電極間を導電性粒子を介し
て電気的に導通させるとともに樹脂を加熱硬化する工程
とを有すると、短いリードタイムで接合することができ
る。尚、導電性粒子を充填された樹脂層は、ＡＣＦ（異
方導電性フィルム）の貼付けやＡＣＰ（異方導電性ペー
スト）の塗布によって形成できる。Further, a step of forming a resin layer filled with conductive particles on the terminal electrodes of the circuit board, a step of flip-chip mounting a semiconductor element having bumps formed on the electrode pads on the circuit board, and a block. When the back surface of the semiconductor element is pressed through the body, the bumps and the terminal electrodes are electrically connected through the conductive particles and the resin is heat-cured, the bonding can be performed in a short lead time. . The resin layer filled with conductive particles can be formed by sticking ACF (anisotropic conductive film) or applying ACP (anisotropic conductive paste).
【００１６】また、回路基板の端子電極上に樹脂層を形
成する工程と、電極パッドにバンプを形成した半導体素
子を回路基板上にフリップチップ実装する工程と、ブロ
ック体を介して半導体素子の裏面を加圧し、バンプと端
子電極を圧接させて電気的に導通させるとともに樹脂を
加熱硬化する工程とを有すると、短いリードタイムでか
つ低コストにて接合することができる。尚、樹脂層は、
ＮＣＦ（非導電性フィルム）の貼付けやＮＣＰ（非導電
性ペースト）の塗布によって形成できる。Further, a step of forming a resin layer on the terminal electrodes of the circuit board, a step of flip-chip mounting a semiconductor element having bumps formed on the electrode pads on the circuit board, and a back surface of the semiconductor element via a block body. And a step of pressing the bumps and the terminal electrodes to make them electrically conductive and heat-curing the resin, the bonding can be performed at a short lead time and at low cost. The resin layer is
It can be formed by pasting NCF (non-conductive film) or applying NCP (non-conductive paste).
【００１７】また、本発明の半導体実装設備は、回路基
板上に半導体素子をフリップチップ実装し、半導体素子
の裏面を加圧しながら回路基板と半導体素子の間の隙間
に介在させた樹脂を加熱硬化させるようにした半導体実
装設備であって、半導体素子の裏面を加圧する加圧ヘッ
ドに、ばね構造を有するブロック体を設けたものであ
り、上記製造方法を実施して回路基板の反り・歪みや半
導体素子の高さ寸法ばらつきがあっても確実に信頼性の
高い接合を実現でき、さらに回路基板上に複数個の半導
体素子を接合する場合も一括して短時間で接合して半導
体装置を製造することができる。Further, in the semiconductor mounting equipment of the present invention, the semiconductor element is flip-chip mounted on the circuit board, and the resin interposed in the gap between the circuit board and the semiconductor element is heat-cured while pressing the back surface of the semiconductor element. In the semiconductor mounting equipment configured to do so, a pressure head that applies pressure to the back surface of the semiconductor element is provided with a block body having a spring structure. Even if there are variations in the height of semiconductor elements, reliable bonding can be reliably achieved.Furthermore, when a plurality of semiconductor elements are bonded on a circuit board, they can be bonded together in a short time to manufacture semiconductor devices. can do.
【００１８】また、ブロック体のばね構造は、ブロック
体に任意の方向から千鳥状またはストライプ状に形成し
た複数のスリットにて構成するのが好適である。Further, it is preferable that the spring structure of the block body is composed of a plurality of slits formed in the block body in a zigzag or stripe shape from an arbitrary direction.
【００１９】また、ブロック体の下部に、半導体素子の
形状と同等若しくはそれより大きな形状を有する押圧プ
レートを設けると、各半導体素子の全体を安定して加圧
でき、高い信頼性をもって確実に接合することができ
る。Further, if a pressing plate having a shape equal to or larger than the shape of the semiconductor element is provided below the block body, the entire semiconductor elements can be stably pressed, and the semiconductor elements can be bonded reliably with high reliability. can do.
【００２０】また、ブロック体または押圧プレートにお
ける半導体素子の裏面と当接する面に弾性体を設ける
と、半導体素子と当接する際のダメージを最小限に抑え
ることができるとともに、樹脂が押圧プレートやブロッ
ク体に付着するのを防止できて好適である。If an elastic body is provided on the surface of the block body or the pressing plate that contacts the back surface of the semiconductor element, damage when contacting the semiconductor element can be minimized, and the resin can be used to press the pressing plate or block. It is suitable because it can be prevented from adhering to the body.
【００２１】また、封止樹脂を加熱硬化する手段とし
て、押圧プレートまたはブロック体の内部またはブロッ
ク体の上方に配置したプレートの少なくとも一つに熱源
を設け、かつ押圧プレートとブロック体と熱源とは一体
構造とすると、半導体装置の熱容量に応じた制御が可能
となるとともに、構成が簡単でかつ容易に高精度の装置
構成とすることができる。As means for heating and curing the sealing resin, a heat source is provided on at least one of the pressing plate or the block body or the plate arranged above the block body, and the pressing plate, the block body and the heat source are With the integrated structure, control according to the heat capacity of the semiconductor device becomes possible, and the device structure is simple and easy, and a highly accurate device structure can be obtained.
【００２２】また、加圧ヘッドに、回路基板上に実装さ
れた複数の半導体素子の各々に対向するように複数のブ
ロック体を配設すると、複数個の半導体素子を個々に独
立した状態で加圧加熱硬化させることが可能となるた
め、複数個の半導体素子を一括してかつ確実に接合する
ことができ、リードタイムを大幅に短縮して生産性を向
上できる。Further, if a plurality of block bodies are arranged in the pressure head so as to face each of the plurality of semiconductor elements mounted on the circuit board, the plurality of semiconductor elements are individually applied. Since it becomes possible to carry out pressure heating and curing, a plurality of semiconductor elements can be bonded collectively and reliably, and the lead time can be greatly shortened to improve productivity.
【００２３】[0023]
【発明の実施の形態】以下、本発明の半導体装置の製造
方法とそれに用いる半導体実装設備の実施形態につい
て、図１〜図３を参照して説明する。BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of a method for manufacturing a semiconductor device of the present invention and semiconductor mounting equipment used for the same will be described below with reference to FIGS.
【００２４】図１、図２において、１は空気圧もしくは
圧縮ガスを供給することにより加圧力を発生する加圧ヘ
ッドで、その下部に熱源としてのカートリッジヒータや
セラミックヒータなどのヒータ２を内蔵させたプレート
３が配設されている。プレート３の下部には、千鳥状ま
たはストライプ状に複数のスリット４ａを形成してばね
構造としたブロック体４が配設され、さらにブロック体
４の下面に半導体素子５に押圧力を印加する押圧プレー
ト６が配設されている。この押圧プレート６は、半導体
素子５の形状と同等もしくはそれより大きな形状とされ
ている。また、ブロック体４及び押圧プレート６にも熱
源としてのヒータ２が内蔵され、かつプレート３、ブロ
ック体４、押圧プレート６は一体構造とされている。さ
らに、押圧プレート６の下面に、Ｓｉゴムなどの弾性体
７が配設されている。回路基板８は、ベース台９上に保
持されている。In FIGS. 1 and 2, reference numeral 1 is a pressurizing head for generating a pressing force by supplying air pressure or compressed gas, and a heater 2 such as a cartridge heater or a ceramic heater as a heat source is built in the lower part thereof. A plate 3 is arranged. A block body 4 having a spring structure in which a plurality of slits 4a are formed in a zigzag shape or a stripe shape is arranged below the plate 3, and a pressing force for applying a pressing force to the semiconductor element 5 is applied to the lower surface of the block body 4. A plate 6 is arranged. The pressing plate 6 has a shape equal to or larger than the shape of the semiconductor element 5. Further, the heater 2 as a heat source is also built in the block body 4 and the pressing plate 6, and the plate 3, the block body 4, and the pressing plate 6 are integrated. Further, an elastic body 7 such as Si rubber is arranged on the lower surface of the pressing plate 6. The circuit board 8 is held on the base 9.
【００２５】また、製造される半導体装置は、半導体素
子５に形成されている電極パッド１０に２段突起状のバ
ンプ１１を設け、その先端に設けた導電性接着剤１３に
てバンプ１１と回路基板８に形成された端子電極１２を
接合し、さらに半導体素子５と回路基板８の間に封止樹
脂１４を充填・封止して構成されている。In the manufactured semiconductor device, bumps 11 having a two-step protrusion are provided on the electrode pads 10 formed on the semiconductor element 5, and the conductive adhesive 13 provided at the tip of the bumps 11 and the circuit. The terminal electrode 12 formed on the substrate 8 is joined, and a sealing resin 14 is filled and sealed between the semiconductor element 5 and the circuit board 8.
【００２６】次に、以上の構成における半導体装置の製
造工程について説明する。半導体素子５の電極パッド１
０に２段突起状のバンプ１１を形成するとともに、その
バンプ１１の先端に導電性接着剤１３を付着させ、この
半導体素子５をフェースダウンにて回路基板８上にフリ
ップチップ実装し、その導電性接着剤１３を熱硬化さ
せ、バンプ１１と回路基板８に形成された端子電極１２
を導電性接着剤１３にて接合させる。Next, a manufacturing process of the semiconductor device having the above structure will be described. Electrode pad 1 of semiconductor element 5
A bump 11 having a two-step projection shape is formed on the semiconductor chip 0, a conductive adhesive 13 is attached to the tip of the bump 11, and the semiconductor element 5 is flip-chip mounted on the circuit board 8 face down. Electrodes 12 formed on the bumps 11 and the circuit board 8 by thermosetting the conductive adhesive 13
Are bonded with a conductive adhesive 13.
【００２７】次に、半導体素子５と回路基板８の隙間に
熱硬化性の封止樹脂１４を充填した後、図１に示すよう
に、この半導体素子５の裏面の上方に、プレート３とば
ね構造のブロック体４と押圧プレート６を一体構造とし
た加圧ヘッド１を対向配置する。Next, after filling the gap between the semiconductor element 5 and the circuit board 8 with the thermosetting sealing resin 14, as shown in FIG. 1, the plate 3 and the spring are provided above the back surface of the semiconductor element 5. The pressure head 1 in which the block body 4 having the structure and the pressing plate 6 are integrated is arranged to face each other.
【００２８】次に、加圧ヘッド１に空気圧もしくは圧縮
ガスを供給して押圧力を発生させ、図２に示すように、
その押圧力をばね構造のブロック体４を介して押圧プレ
ート６に伝達し、半導体素子５の裏面を均一に加圧す
る。その際、ブロック体４は、例えば半導体素子５と押
圧プレート６が当接した時の位置を基準（ｂ）として、
＋ａ側と−ａの上下変位及び傾きに対して伸縮自在に作
用するため、半導体素子５の高さばらつきや押圧を加え
た場合の傾きに対して追従した補正の動きが可能とな
り、半導体素子５を均一に加圧することができる。その
結果、安定した接合が維持されるとともに、接続の信頼
性も大幅に向上させることができる。Next, air pressure or compressed gas is supplied to the pressure head 1 to generate a pressing force, and as shown in FIG.
The pressing force is transmitted to the pressing plate 6 via the block body 4 having the spring structure, and the back surface of the semiconductor element 5 is uniformly pressed. At this time, the block body 4 uses, for example, the position when the semiconductor element 5 and the pressing plate 6 are in contact as a reference (b),
Since it acts flexibly with respect to the vertical displacement and inclination of the + a side and −a, it is possible to perform a correction movement that follows the height variation of the semiconductor element 5 and the inclination when pressure is applied. Can be uniformly pressed. As a result, stable joining can be maintained and the reliability of connection can be greatly improved.
【００２９】その状態で、プレート３、ブロック体４及
び押圧プレート６に内蔵させたヒータ２による熱が、ブ
ロック体４、押圧プレート６を介して半導体素子５に伝
達され、回路基板８と半導体素子５との隙間に介在させ
た封止樹脂１４を加熱硬化させる。その際、ヒータ２が
ブロック体４及び押圧プレート６にも内蔵され、さらに
押圧プレート６とブロック体４とプレート３とが一体構
造となっているため、回路基板８または半導体素子５の
熱容量や昇温速度に対して、安定した温度プロファイル
を容易に実現することができる。In this state, heat from the heater 2 built in the plate 3, the block body 4 and the pressing plate 6 is transferred to the semiconductor element 5 through the block body 4 and the pressing plate 6, and the circuit board 8 and the semiconductor element. The sealing resin 14 that is interposed in the gap between the resin and the resin 5 is cured by heating. At that time, since the heater 2 is also built in the block body 4 and the pressing plate 6, and the pressing plate 6, the block body 4, and the plate 3 have an integral structure, the heat capacity and the temperature of the circuit board 8 or the semiconductor element 5 are increased. It is possible to easily realize a stable temperature profile with respect to the temperature rate.
【００３０】かくして、ばね構造のブロック体４を介し
て半導体素子５の裏面を加圧しつつ加熱硬化すること
で、フリップチップ実装時に生じた半導体素子５の高さ
ばらつきや回路基板８の反りの影響を解消した状態で封
止樹脂１４を加熱硬化させるため、安定した接続信頼性
を得ることができる。Thus, the back surface of the semiconductor element 5 is heated and hardened while being pressed through the block body 4 having the spring structure, so that the height variation of the semiconductor element 5 and the warp of the circuit board 8 which occur during flip-chip mounting are affected. Since the sealing resin 14 is heated and cured in a state where the above problem is solved, stable connection reliability can be obtained.
【００３１】また、ブロック体４の下方に設けられた押
圧プレート６は、半導体素子５の形状と同等もしくはそ
れより大きな形状であるため、半導体素子５の全体を安
定して押圧することができ、さらに押圧プレート６の底
面にＳｉゴムなどの弾性体７が配設されているので、半
導体素子５と当接する際のダメージを最小限に抑えると
ともに、封止樹脂１４が押圧プレート６に付着するのを
抑制できる。Further, since the pressing plate 6 provided below the block body 4 has a shape equal to or larger than the shape of the semiconductor element 5, the entire semiconductor element 5 can be pressed stably. Further, since the elastic body 7 such as Si rubber is disposed on the bottom surface of the pressing plate 6, the damage at the time of contact with the semiconductor element 5 is minimized, and the sealing resin 14 is attached to the pressing plate 6. Can be suppressed.
【００３２】また、本実施形態によれば、従来のオーブ
ン乾燥によるバッチ処理に対して、一連のプロセスの流
れの中で加圧加熱処理を行うことができるため、生産性
を大幅に向上させるとともに、搬送時における何らかの
外部圧力における半導体素子５と回路基板８の接合部の
ダメージの影響を最小限に抑制することができるため、
接続信頼性をより向上させることができる。Further, according to the present embodiment, the pressure heating treatment can be carried out in a series of process flow as compared with the conventional batch treatment by oven drying, so that the productivity is greatly improved. Since it is possible to minimize the influence of damage to the joint portion between the semiconductor element 5 and the circuit board 8 due to some external pressure during transportation,
The connection reliability can be further improved.
【００３３】上記実施形態の説明では、回路基板８に単
一の半導体素子５を接合する例を説明したが、複数個の
半導体素子５を回路基板８に一括して接合する場合に
は、図３に示すように、加圧ヘッド１に対して、回路基
板８上に実装された複数個の半導体素子５（Ａ）〜
（Ｃ）にそれぞれ対向させて複数のブロック体４を配設
する。これにより、各半導体素子５を個々に独立した状
態で加圧した状態でそれぞれの封止樹脂１４を加熱硬化
させることが可能となるため、多数個の半導体素子５の
実装を一括で加圧加熱硬化することができる。その結
果、従来のバッチ処理が解消され、リードタイムの大幅
な短縮を図るとともに、生産性を向上させることができ
る。In the description of the above embodiment, an example in which a single semiconductor element 5 is bonded to the circuit board 8 has been described. However, when a plurality of semiconductor elements 5 are bonded to the circuit board 8 at once, As shown in FIG. 3, a plurality of semiconductor elements 5 (A) mounted on the circuit board 8 are attached to the pressure head 1.
A plurality of block bodies 4 are arranged so as to face (C). This makes it possible to heat and cure each sealing resin 14 in a state where each semiconductor element 5 is individually pressurized and pressed, so that mounting of a large number of semiconductor elements 5 is collectively performed by pressure heating. Can be cured. As a result, the conventional batch processing is eliminated, the lead time can be greatly shortened, and the productivity can be improved.
【００３４】以上の実施形態の説明では、図４（ａ）に
示すように、半導体素子５の電極パッド１０に設けた２
段突起バンプ１１の先端に導電性接着剤１３を付着し、
回路基板８に半導体素子５をフェースダウンにて実装後
導電性接着剤１３を熱硬化し、半導体素子５と回路基板
８の隙間に封止樹脂１４を充填し、半導体素子５の裏面
を加圧し、封止樹脂１４を加圧加熱硬化して半導体装置
を製造する工程について説明したが、図４（ｂ）に示す
ように、回路基板８の端子電極１２上に導電性粒子１５
ａを充填された樹脂フィルムであるＡＣＦ（異方導電性
フィルム）１５を貼付け、電極パッド１０にバンプ１１
を形成した半導体素子５を回路基板８上にフリップチッ
プ実装し、この半導体素子５の裏面をブロック体４を介
して加圧加熱し、バンプ１１と端子電極１２間で樹脂フ
ィルムを溶解させて導電性粒子１５ａを介して電気的に
導通させるとともに樹脂フィルムを加熱硬化させて半導
体装置を製造する工程においても、ブロック体４を介し
て加圧加熱することにより上記作用効果を奏することが
できる。なお、ＡＣＦ（異方導電性フィルム）に代えて
ＡＣＰ（異方導電性ペースト）を用いてもよい。In the above description of the embodiment, as shown in FIG. 4A, the two electrodes provided on the electrode pad 10 of the semiconductor element 5 are provided.
Attach the conductive adhesive 13 to the tip of the step protrusion bump 11,
After mounting the semiconductor element 5 on the circuit board 8 face down, the conductive adhesive 13 is thermoset, the gap between the semiconductor element 5 and the circuit board 8 is filled with the sealing resin 14, and the back surface of the semiconductor element 5 is pressed. Although the process of manufacturing the semiconductor device by pressurizing and heating the sealing resin 14 has been described, the conductive particles 15 are formed on the terminal electrodes 12 of the circuit board 8 as shown in FIG. 4B.
ACF (anisotropic conductive film) 15, which is a resin film filled with a, is attached, and bumps 11 are formed on the electrode pads 10.
The semiconductor element 5 on which the semiconductor element 5 is formed is flip-chip mounted on the circuit board 8, and the back surface of the semiconductor element 5 is pressed and heated through the block body 4 to melt the resin film between the bump 11 and the terminal electrode 12 and conduct the electric conduction. Even in the step of electrically conducting through the conductive particles 15a and heating and curing the resin film to manufacture a semiconductor device, the above-described effects can be obtained by pressurizing and heating through the block body 4. Note that ACP (anisotropic conductive paste) may be used instead of ACF (anisotropic conductive film).
【００３５】また、図４（ｃ）に示すように、回路基板
８の端子電極１２上に熱硬化性の樹脂フィルムからなる
ＮＣＦ（非導電性フィルム）１６を貼付け、電極パッド
１０にバンプ１１を形成した半導体素子５を回路基板８
上にフリップチップ実装し、この半導体素子５の裏面を
ブロック体４を介して加圧加熱し、バンプ１１と端子電
極１２間で樹脂フィルムを溶解させてバンプ１１と端子
電極１２を圧接させて電気的に導通させるとともに樹脂
フィルムを加熱硬化させて半導体装置を製造する工程に
おいても、ブロック体４を介して加圧加熱することによ
り上記作用効果を奏することができる。なお、ＮＣＦ
（非導電性フィルム）に代えてＮＣＰ（非導電性ペース
ト）を用いてもよい。As shown in FIG. 4C, an NCF (non-conductive film) 16 made of a thermosetting resin film is attached on the terminal electrodes 12 of the circuit board 8 and the bumps 11 are formed on the electrode pads 10. The formed semiconductor element 5 is connected to the circuit board 8
It is flip-chip mounted on top, and the back surface of this semiconductor element 5 is pressed and heated through the block body 4, and the resin film is melted between the bump 11 and the terminal electrode 12 to bring the bump 11 and the terminal electrode 12 into pressure contact with each other for electrical Also in the process of manufacturing a semiconductor device by electrically conducting the resin film and heating and curing the resin film, it is possible to achieve the above-described effects by pressurizing and heating via the block body 4. In addition, NCF
NCP (non-conductive paste) may be used instead of (non-conductive film).
【００３６】[0036]
【発明の効果】本発明の半導体装置の製造方法及び半導
体実装設備によれば、以上の説明から明らかなように、
加圧ヘッドにばね構造のブロック体と熱源を設けた構成
とすることにより、半導体素子と回路基板との安定した
接合が実現できるとともに、多数個のフリップチップ実
装を一括で処理することができ、生産性を大きく向上す
ることができる。According to the method of manufacturing the semiconductor device and the semiconductor mounting equipment of the present invention, as is clear from the above description,
By providing the pressure head with a block body having a spring structure and a heat source, stable bonding between the semiconductor element and the circuit board can be realized, and a large number of flip-chip mountings can be collectively processed. The productivity can be greatly improved.
【図１】本発明の半導体装置の製造方法及び半導体実装
設備の一実施形態の全体構成を示す断面図である。FIG. 1 is a cross-sectional view showing an overall configuration of an embodiment of a semiconductor device manufacturing method and semiconductor mounting equipment of the present invention.
【図２】同実施形態の要部の拡大断面図である。FIG. 2 is an enlarged cross-sectional view of a main part of the same embodiment.
【図３】同実施形態の半導体装置の製造方法における別
の好適な実施態様の全体構成を示す断面図である。FIG. 3 is a cross-sectional view showing the overall configuration of another preferred embodiment of the method for manufacturing a semiconductor device of the same embodiment.
【図４】本発明の半導体装置の製造方法の他の実装方式
への適用例の説明図である。FIG. 4 is an explanatory diagram of an application example of the semiconductor device manufacturing method of the present invention to another mounting method.
【図５】従来例の半導体装置の製造工程を示す断面図で
ある。FIG. 5 is a cross-sectional view showing a manufacturing process of a conventional semiconductor device.
【図６】同従来例で製造される半導体装置の拡大断面図
である。FIG. 6 is an enlarged cross-sectional view of a semiconductor device manufactured in the conventional example.
【図７】回路基板に複数の半導体素子をフリップチップ
実装する際の回路基板の反りの状態の説明図である。FIG. 7 is an explanatory diagram of a warped state of the circuit board when a plurality of semiconductor elements are flip-chip mounted on the circuit board.
【図８】回路基板に複数の半導体素子をフリップチップ
実装する際の半導体素子の高さのばらつきの状態の説明
図である。FIG. 8 is an explanatory diagram of a state in which heights of semiconductor elements are varied when a plurality of semiconductor elements are flip-chip mounted on a circuit board.
１ 加圧ヘッド ２ ヒータ ３ プレート ４ ブロック体 ５ 半導体素子 ６ 押圧プレート ７ 弾性体 ８ 回路基板 １０ 電極パッド １１ バンプ １２ 端子電極 １３ 導電性接着剤 １４ 封止樹脂 １５ ＡＣＦ（異方導電性フィルム） １６ ＮＣＦ（非導電性フィルム） 1 pressure head 2 heater 3 plates 4 block body 5 Semiconductor element 6 Pressing plate 7 elastic body 8 circuit board 10 electrode pad 11 bumps 12 terminal electrode 13 Conductive adhesive 14 Sealing resin 15 ACF (anisotropic conductive film) 16 NCF (Non-conductive film)
───────────────────────────────────────────────────── フロントページの続き (72)発明者 小山 雅義 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 砂川 義隆 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 Ｆターム(参考） 5F044 KK01 PP16 ─────────────────────────────────────────────────── ─── Continued front page (72) Inventor Masayoshi Koyama 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. (72) Inventor Yoshitaka Sunagawa 1006 Kadoma, Kadoma-shi, Osaka Matsushita Electric Sangyo Co., Ltd. F term (reference) 5F044 KK01 PP16
Claims (11)
プ実装し、半導体素子の裏面を加圧しながら回路基板と
半導体素子の間に介在させた樹脂を加熱硬化させる半導
体装置の製造方法であって、ばね構造を有するブロック
体を半導体素子の裏面に対向配置する第１工程と、半導
体素子の裏面をブロック体を介して加圧しながら樹脂を
加熱硬化する第２工程とを備えたことを特徴とする半導
体装置の製造方法。1. A method of manufacturing a semiconductor device, wherein a semiconductor element is flip-chip mounted on a circuit board, and a resin interposed between the circuit board and the semiconductor element is heat-cured while pressing the back surface of the semiconductor element. The method further comprises a first step of disposing a block body having a spring structure so as to face the back surface of the semiconductor element, and a second step of heating and curing the resin while pressurizing the back surface of the semiconductor element through the block body. Manufacturing method of semiconductor device.
が回路基板上に実装された複数の半導体素子の各々に対
向した位置に配置され、各ブロック体で半導体素子の裏
面を一括して加圧加熱硬化することを特徴とする請求項
１記載の半導体装置の製造方法。2. In the first step, a plurality of block bodies are arranged at positions facing a plurality of semiconductor elements mounted on a circuit board, and the back surfaces of the semiconductor elements are collectively applied by each block body. The method of manufacturing a semiconductor device according to claim 1, wherein the method is pressure heating and curing.
起バンプの先端に導電性接着剤を付着する工程と、回路
基板に半導体素子をフェースダウンにて実装後導電性接
着剤を熱硬化する工程と、半導体素子と回路基板の隙間
に熱硬化性樹脂から成る封止樹脂を充填する工程と、ブ
ロック体を介して半導体素子の裏面を加圧し、封止樹脂
を加圧加熱硬化する工程とを有することを特徴とする請
求項１又は２記載の半導体装置の製造方法。3. A step of adhering a conductive adhesive to the tip of a two-step protruding bump provided on an electrode pad of the semiconductor element, and a step of mounting the semiconductor element face down on the circuit board, followed by thermosetting the conductive adhesive. A step, a step of filling a gap between the semiconductor element and the circuit board with a sealing resin made of a thermosetting resin, a step of pressing the back surface of the semiconductor element through a block body, and a step of press-heating and curing the sealing resin. The method for manufacturing a semiconductor device according to claim 1, further comprising:
充填された樹脂層を形成する工程と、電極パッドにバン
プを形成した半導体素子を回路基板上にフリップチップ
実装する工程と、ブロック体を介して半導体素子の裏面
を加圧し、バンプと端子電極間を導電性粒子を介して電
気的に導通させるとともに樹脂を加熱硬化する工程とを
有することを特徴とする請求項１又は２記載の半導体装
置の製造方法。4. A step of forming a resin layer filled with conductive particles on a terminal electrode of a circuit board, a step of flip-chip mounting a semiconductor element having bumps formed on electrode pads on the circuit board, and a block. 3. The step of pressurizing the back surface of the semiconductor element through the body to electrically connect the bump and the terminal electrode with each other through the conductive particles, and heating and curing the resin. Of manufacturing a semiconductor device of.
る工程と、電極パッドにバンプを形成した半導体素子を
回路基板上にフリップチップ実装する工程と、ブロック
体を介して半導体素子の裏面を加圧し、バンプと端子電
極を圧接させて電気的に導通させるとともに樹脂を加熱
硬化する工程とを有することを特徴とする請求項１又は
２記載の半導体装置の製造方法。5. A step of forming a resin layer on a terminal electrode of a circuit board, a step of flip-chip mounting a semiconductor element having bumps formed on electrode pads on the circuit board, and a back surface of the semiconductor element via a block body. 3. The method for manufacturing a semiconductor device according to claim 1, further comprising the step of: pressurizing the bump to bring the bump and the terminal electrode into pressure contact so as to be electrically connected to each other and heat-curing the resin.
プ実装し、半導体素子の裏面を加圧しながら回路基板と
半導体素子の間の隙間に介在させた樹脂を加熱硬化させ
るようにした半導体実装設備であって、半導体素子の裏
面を加圧する加圧ヘッドに、ばね構造を有するブロック
体を設けたことを特徴とする半導体実装設備。6. A semiconductor mounting facility in which a semiconductor element is flip-chip mounted on a circuit board, and a resin interposed in a gap between the circuit board and the semiconductor element is heat-cured while pressing the back surface of the semiconductor element. A semiconductor mounting facility characterized in that a block body having a spring structure is provided on a pressure head for pressing the back surface of a semiconductor element.
任意の方向から千鳥状またはストライプ状に形成した複
数のスリットにて構成したことを特徴とする請求項６記
載の半導体実装設備。7. The semiconductor mounting equipment according to claim 6, wherein the spring structure of the block body is constituted by a plurality of slits formed in the block body in a zigzag or stripe shape from an arbitrary direction.
と同等若しくはそれより大きな形状を有する押圧プレー
トを設けたことを特徴とする請求項６又は７記載の半導
体実装設備。8. The semiconductor mounting equipment according to claim 6, wherein a pressing plate having a shape equal to or larger than the shape of the semiconductor element is provided below the block body.
半導体素子の裏面と当接する面に弾性体を設けたことを
特徴とする請求項６〜８の何れかに記載の半導体実装設
備。9. The semiconductor mounting equipment according to claim 6, wherein an elastic body is provided on a surface of the block body or the pressing plate that comes into contact with the back surface of the semiconductor element.
押圧プレートまたはブロック体の内部またはブロック体
の上方に配置したプレートの少なくとも一つに熱源を設
け、かつ押圧プレートとブロック体と熱源とは一体構造
としたことを特徴とする請求項６〜９の何れかに記載の
半導体実装設備。10. A means for heating and curing a sealing resin,
10. The heat source is provided in at least one of the pressing plate or the plate arranged inside the block body or above the block body, and the pressing plate, the block body and the heat source are integrally structured. Semiconductor mounting equipment according to any one of the above.
た複数の半導体素子の各々に対向するように複数のブロ
ック体を配設したことを特徴とする請求項６〜１０の何
れかに記載の半導体実装設備。11. The pressing head is provided with a plurality of block bodies so as to face each of a plurality of semiconductor elements mounted on a circuit board. Semiconductor mounting equipment described.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002034600A JP2003234378A (en) | 2002-02-12 | 2002-02-12 | Manufacturing method of semiconductor device, and semiconductor mounting equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2002034600A JP2003234378A (en) | 2002-02-12 | 2002-02-12 | Manufacturing method of semiconductor device, and semiconductor mounting equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JP2003234378A true JP2003234378A (en) | 2003-08-22 |
Family
ID=27777052
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002034600A Pending JP2003234378A (en) | 2002-02-12 | 2002-02-12 | Manufacturing method of semiconductor device, and semiconductor mounting equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2003234378A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100962225B1 (en) | 2007-12-12 | 2010-06-11 | (주)에이에스티 | Chip Bonding Method Applied to Multi Chip Bonding |
| CN112333932A (en) * | 2020-11-23 | 2021-02-05 | 深圳远芯光路科技有限公司 | A multi-head hot-pressing reflow device and its operation method |
| CN113539883A (en) * | 2020-04-13 | 2021-10-22 | Jmj韩国株式会社 | Semiconductor device mounting apparatus |
-
2002
- 2002-02-12 JP JP2002034600A patent/JP2003234378A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100962225B1 (en) | 2007-12-12 | 2010-06-11 | (주)에이에스티 | Chip Bonding Method Applied to Multi Chip Bonding |
| CN113539883A (en) * | 2020-04-13 | 2021-10-22 | Jmj韩国株式会社 | Semiconductor device mounting apparatus |
| CN113539883B (en) * | 2020-04-13 | 2024-06-07 | Jmj韩国株式会社 | Semiconductor device mounting apparatus |
| CN112333932A (en) * | 2020-11-23 | 2021-02-05 | 深圳远芯光路科技有限公司 | A multi-head hot-pressing reflow device and its operation method |
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