JP2003142659A - Semiconductor storage device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent generation of voltage offset in ferroelectric hysteresis characteristic in an initial state and also prevent generation of fluctuation of reading out charges in polarization reversal repetition, when film formation of a ferroelectric material film is performed at a temperature of at most 450 deg.C. SOLUTION: A PTO growth nucleus layer 102, three PZT layers 103, 104, 105 which are different in Zr/Ti ratio, an upper electrode side PTO layer 106 and an upper electrode 107 are laminated on a lower electrode 101. Zr/Ti ratios of the three PZT layer 103, 104, 105 are about 0.2, 0.35 and 0.55. In this device, the PZT layer 103 which relieves difference of lattice constant to the PTO growth nucleus layer is formed on the PTO growth nucleus layer 102 (1), the PZT layer 105 whose coercive electric field is small is arranged on an interface between the upper electrode 107 and the PZT layer, and domain rotation of 90 deg. is facilitated (2), and a PTO layer which is the same as the growth nucleus layer 102 is formed between the upper electrode and the PZT layer 105 (3), so that reversal nucleus formation which becomes opportunity of polarization reversal is generated by the same condition in an upper and a lower interface.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device having a ferroelectric capacitor element, and in particular, lead zirconate titanate (Pb (Zr, Ti) O ₃ as a ferroelectric substance, hereinafter referred to as "PZ."
(Referred to as “T”).

[0002]

2. Description of the Related Art In recent years, research and development of a non-volatile memory device using a ferroelectric capacitor has become active. This non-volatile memory device includes a selection transistor, and has a mechanism for storing information by using a ferroelectric capacitor connected to one diffusion layer of the selection transistor as a memory cell. A ferroelectric thin film such as lead zirconate titanate (PZT) is used as the material of the ferroelectric capacitor, and nonvolatile information is stored by polarization of the ferroelectric thin film.

As a method of depositing a ferroelectric thin film, a chemical vapor deposition method (CVD method) is excellent in uniformity in a large-diameter wafer and coverage with a surface step, and is promising as a mass-production technique when applied to ULSI. Is believed to be. In general, metal hydrides and chlorides, which are constituent elements of ceramics such as PZT, have a low vapor pressure. Therefore, among the CVD methods, metal-organic vapor phase epitaxy (M
The OCVD method) is often used as a method for depositing these ferroelectric thin films. Since many organic metal raw materials used in the MOCVD method are solid or liquid at room temperature, they are usually heated and vaporized, mixed with a carrier gas, transported to a growth tank in which the substrate is installed, and deposited on the substrate. How to do it.

For example, Japanese Patent Laid-Open No. 11-317500 discloses a device structure of a semiconductor memory device in which a ferroelectric thin film is formed by MOCVD. In this device structure, since the ferroelectric capacitance element is installed at the top of the device after the formation of the multilayer metal wiring, the formation of the multilayer metal wiring is hindered due to the height difference of the ferroelectric capacitance element. Without a situation happening
Excellent compatibility with CMOS processes is maintained. However, in order to realize this device structure, in order to avoid disconnection and increase in resistance of the metal wiring formed prior to the formation of the ferroelectric capacitor element, the ferroelectric thin film is used as a thin film.
It is necessary to form at a low temperature of ℃ or less. A technique for forming a ferroelectric thin film by the MOCVD method at such a low temperature is disclosed in Japanese Patent Laid-Open No. 2000-58525. According to the publication, first, only the Pb organometallic raw material is flowed on the surface of the lower electrode, and then a PZT growth nucleus layer having a small Zr / Ti ratio is formed, and thereafter, growth nuclei are grown on the growth nucleus layer. A PZT thin film having a larger Zr / Ti ratio than the layer is deposited as a ferroelectric layer. By such a method, it becomes possible to grow a PZT thin film having a controlled orientation and good crystallinity at a low temperature.

[0005]

In the conventional film forming method described above, the PZT ferroelectric layer having a larger Zr / Ti ratio than the growth nucleus layer is formed on the PZT growth nucleus layer having a small Zr / Ti ratio. However, if the Zr / Ti ratio is made too large, distortion due to the difference in lattice constant is likely to occur near the interface. This strain rapidly attenuates as the distance from the interface increases. Since a charged layer is likely to be generated at the interface where strain exists, the charged layer is formed only near the interface. This charge layer causes a voltage offset in the ferroelectric hysteresis characteristic in the initial state when an electrode is formed on the ferroelectric layer to manufacture a ferroelectric capacitor.
The voltage offset in the ferroelectric hysteresis characteristic of the ferroelectric capacitor causes an imbalance in the retention characteristic due to the write polarity, which is not preferable.

In order to avoid such a phenomenon, Zr /
The Ti ratio should be reduced, but the coercive electric field increases when the Zr / Ti ratio is reduced. In general, damage and strain accompanying the upper electrode formation process are introduced at the interface between the upper surface of the ferroelectric thin film and the upper electrode, so that movement of atoms at the interface is hindered, but if the coercive electric field of the PZT thin film is large, The influence of such strain is promoted, and in the vicinity of this interface, polarization inversion hardly occurs. Further, the 90 ° domain rotation in which the region that was oriented to the a-axis immediately after the PZT thin film was oriented to the c-axis, which is the polarization axis, is also blocked by the application of the electric field, and it cannot be completed in the first writing operation. However, it will gradually occur by the subsequent application of the electric field. These results synergistically cause a change in the read charge during repeated polarization inversion. In a non-volatile memory device using a ferroelectric capacitor element, this fluctuation of the read charge directly causes the fluctuation of the signal voltage inside the memory device, which lowers the operational reliability of the device.

The present invention has been made in view of this point, and an object thereof is to generate a voltage offset in the ferroelectric hysteresis characteristics in the initial state even when a film is formed at a temperature of 450 ° C. or lower. In addition, there is no fluctuation in the read charge due to repeated polarization inversion, and at the same time, the remanent polarization value in the initial state is large, and the ferroelectric hysteresis shape is good. It is to provide a semiconductor memory device having high cost.

[0008]

To achieve the above object, according to the present invention, in a semiconductor memory device having a ferroelectric capacitor having a structure in which a PZT layer is sandwiched between upper and lower electrodes, a PZT layer There is provided a semiconductor memory device characterized in that the Zr / Ti ratio is changed from the lower electrode side to the upper electrode side. And, preferably, Zr / Ti
The ratio is monotonically increased from the lower electrode side to the upper electrode side. Further, more preferably, a lead titanate (PTO) layer is formed at the interface between the lower electrode and the upper electrode and the PZT layer.

Further, according to the present invention, in a semiconductor memory device having a ferroelectric capacitor having a structure in which a PZT layer is sandwiched between upper and lower electrodes, an interface between the lower electrode and the PZT layer and an upper electrode. A PTO layer is formed at each interface between the PZT layer and the PZT layer. And, preferably, the PTO layer formed on the lower electrode side and the PTO layer formed on the upper electrode side have substantially the same film thickness.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. [First Embodiment] FIG. 1 is a sectional view [(a)] of a ferroelectric device according to a first embodiment of the present invention and a composition ratio distribution diagram [(b)] in the film thickness direction. is there. 2 is a ferroelectric hysteresis characteristic diagram [(a)] in the initial state of the ferroelectric device of FIG. 1, a fatigue characteristic diagram [(b)], and a ferroelectric hysteresis characteristic diagram [(c) after the fatigue characteristic measurement. )]. As shown in FIG. 1A, in the ferroelectric device of the present embodiment, a lead titanate (PTO) growth nucleus layer 102 and first and second Zr / Ti ratios different from each other are formed on a lower electrode 101. , The third PZT layers 103, 104 and 105 and the PTO layer 106 on the upper electrode side are laminated, and the upper electrode 107 is formed on the PTO layer 106.

In the growth of a PZT thin film, particularly in the low temperature film formation at 450 ° C. or lower using the MOCVD method, it is important to form growth nuclei having crystallinity as good as possible at the initial stage of film formation. The growth nucleus layer is the basis for forming growth nuclei in the initial stage of film formation. The reactivity between Pb and Ti is P
Since the reactivity between b and Zr is higher, if a growth nucleus layer having a large amount of Ti is used, good quality crystal nuclei can be formed even at a low temperature.
A PZT film having a [Zr] / ([Zr] + [Ti]) ratio of 0.15 or less acts as a crystal nucleus layer, but a PTO film containing no Zr has the best crystallinity, so that the growth As the nucleus layer, a PTO grown nucleus layer of PTO alone is most preferable. Here, [A] represents the mol% concentration of the component A in PZT. The mol% concentration of Pb, Zr or Ti corresponding to A can be determined by fluorescent X-ray analysis or secondary ion mass spectrometry (S
It can be easily measured by means such as IMS).
The growth nucleus layer may be a continuous film that covers the entire lower electrode, but it is more preferable that the growth nucleus layer has an island shape. This is because when the growth nucleus layer is a continuous film, two dielectric layers having different compositions and different dielectric constants are formed at the interface with the lower electrode, which causes bias of the electric field and lowering of the dielectric constant. In addition, when the growth nucleus layer has an island shape, it becomes easier to control the orientation and the crystal grain size.

As shown in FIG. 1B, the first PZT layer 103, the second PZT layer 104, and the third PZT layer 105.
[Zr] / ([Zr] + [Ti]) ratio of
It is about 0.2, 0.35, and 0.55. The film thickness of the first, second and third PZT layers 103, 104 and 105 is
20-30 nm, 200 nm, 10-20 n, respectively
It is adjusted to be in the order of m. The film thickness of the PTO layer 106 is about 5 nm.

Next, the ferroelectric device of the present embodiment will be described in more detail together with its manufacturing method. In the present embodiment, ruthenium (R
u) was used. As MOCVD raw materials, for Pb, bisdipivaloyl methanate lead [Pb (DPM) ₂ ], Ti
Titanium isopropoxide [Ti (OiPr) ₄ ],
Zirconium butoxide [Zr (OtB
u) ₄ ], and nitrogen dioxide (NO ₂ ) was used as an oxidant. During the formation of the PTO layer and the PZT layer, the total gas pressure in the vacuum chamber is 100 mTorr (13.33P).
a), the substrate temperature was kept at 430 ° C. First, Pb (D
PM) ₂ is supplied for 2 seconds at a flow rate of 0.2 SCCM, then NO ₂ is supplied for 10 seconds at a flow rate of 3.0 SCCM while Pb (DPM) ₂ is being flown, and then Ti The supply of (OiPr) ₄ is started. Pb
(DPM) ₂ flow rate 0.2 SCCM, Ti (OiPr)
₄ flow rate 0.25SCCM, NO ₂ flow rate 3.0SCC
The film formation condition of M is maintained for 30 seconds and the island-shaped PTO
The growth nucleus layer 102 is formed. Next, the source gas supply conditions were changed, and the flow rate of Pb (DPM) ₂ was 0.25 SCCM, Z.
Flow rate of r (OtBu) ₄ 0.2SCCM, Ti (OiP)
r) ₄ flow rate 0.4SCCM, NO ₂ flow rate 3.0SC
The film forming condition of CM is maintained for 200 seconds and the film thickness is 30 nm.
With a [Zr] / ([Zr] + [Ti]) ratio of about 0.
2 to obtain the first PZT layer 103. Next, Pb (DP
M) ₂ flow rate 0.25 SCCM, Zr (OtBu) ₄ flow rate 0.3 SCCM, Ti (OiPr) ₄ flow rate 0.3
The film formation condition of ₂ SCCM and NO ₂ flow rate of 3.0 SCCM is maintained for 1100 seconds, and the [Zr] / ([Zr] + [Ti]) ratio having a film thickness of 200 nm at the film central portion is about 0.3.
The second PZT layer 104 of No. 5 is formed. Then Pb
(DPM) ₂ flow rate 0.25 SCCM, Zr (OtB
u) ₄ flow rate 0.4 SCCM, Ti (OiPr) ₄ flow rate 0.2 SCCM, NO ₂ flow rate 3.0 SCCM are held for 100 seconds, and the film thickness is 20 nm. [Zr] / ([Zr] A third PZT layer 105 having a + [Ti]) ratio of about 0.55 is formed. Furthermore, Pb (DP
M) ₂ flow rate 0.2 SCCM, Ti (OiPr) ₄ flow rate 0.25 SCCM, and NO ₂ flow rate 3.0 SCCM are held for 30 seconds to form the PTO layer 106. Lastly, as the upper electrode 107, in order to avoid a heating effect on the film structure during the formation of the upper electrode, A is formed by vacuum evaporation.
After depositing u, the manufacturing process of the ferroelectric capacitor according to the present embodiment is completed. When Au is used as the electrode,
It is a well-known fact that the change in the inversion charge appears early in repeated polarization inversion, but in order to eliminate the effect of the heating effect on the film structure during the formation of the upper electrode, vacuum deposition is used as the upper electrode. Au by the method was intentionally used.

As shown in FIG. 2A, the ferroelectric capacitor element of the present embodiment manufactured as described above is bilaterally symmetric in the ferroelectric hysteresis characteristics in its initial state, and does not show a voltage shift. . In addition, FIG.
It is shown by superimposing the initial-state hysteresis (single-shot hysteresis) obtained by a single-shot voltage sweep of bipolar voltages of 2V, ± 3V, ± 4V, and ± 5V. Figure 2
As shown in (b), the ferroelectric device of the present embodiment is
When polarization reversal is performed by repeatedly applying bipolar voltage pulses of ± 3 V, the change in the inversion charge appears earlier as expected as compared with the case where Ru, which is well known as the upper electrode, is used. . However, the inversion charges and the non-inversion charges show almost no change until the number of polarization inversions of about 10 ⁶ to 10 ⁷ . In addition, FIG.
The single shot hysteresis measured after the fatigue characteristic experiment at each point shown in (b) is shown in an overlapping manner. Remanent polarization has hardly changed from the beginning of inversion,
Also, the hysteresis shapes are completely overlapped. In FIG. 2C, the residual charge when the applied voltage is zero is zero.

[Comparative Example] FIG. 3 is a sectional view [(a)] of a ferroelectric capacitor element of a comparative example and a composition ratio distribution diagram [(b)] in the film thickness direction. FIG. 4 is a ferroelectric hysteresis characteristic diagram [(a)] of the ferroelectric capacitor of FIG. 3 in an initial state.
FIG. 4 is a fatigue characteristic diagram [(b)] and a ferroelectric hysteresis characteristic diagram [(c)] after the fatigue characteristic measurement. Figure 3
As shown in (a), the ferroelectric capacitor of the present embodiment has a PTO growth nucleus layer 202 and a PTO growth nucleus layer 202 on the lower electrode 201.
The ZT layer 204 and the upper electrode side PTO layer 206 are laminated, and the upper electrode 207 is formed on the PTO layer 206. As shown in FIG. 3B, the PZT layer 204 is
It is a single ferroelectric thin film layer having a [Zr] / ([Zr] + [Ti]) ratio of about 0.35. PZT layer 204
Has a thickness of 250 nm, and the PTO layer 206 has a thickness of about 5 nm.

Next, the ferroelectric capacitor of this comparative example was prepared.
The manufacturing method will be described in more detail. In this comparative example
The lower electrode, MOCVD raw material, and oxidizer in the first
It is the same as the embodiment. Formation of PTO and PZT layers
Throughout the membrane, the total pressure of the gas in the vacuum vessel is 100 mTo
rr (13.33 Pa), substrate temperature kept at 430 ° C
It was First Pb (DPM)_Two2 at a flow rate of 0.2 SCCM
Seconds, then Pb (DPM)_TwoIn the condition
No NO_TwoIs supplied for 10 seconds at a flow rate of 3.0 SCCM
Then, as it is, Ti (OiPr)_FourSupply of
To start. Pb (DPM)_TwoFlow rate of 0.2 SCCM, T
i (OiPr)_FourFlow rate of 0.25 SCCM, NO_TwoFlow of
The film formation condition of 3.0 SCCM was maintained for 30 seconds
A PTO growth nucleus layer 202 having a layered structure is formed. Next, the raw material
Change the gas supply condition, Pb (DPM) _TwoFlow rate of 0.2
5SCCM, Zr (OtBu)_FourFlow rate of 0.3 SCC
M, Ti (OiPr)_FourFlow rate of 0.32 SCCM, NO
_TwoFlow rate of 3.0 SCCM for 1500 seconds
[Zr] / ([Zr] which holds and has a film thickness of 250 nm
Forming a PZT layer 204 having a + [Ti] ratio of about 0.35
It Furthermore, Pb (DPM) _TwoFlow rate of 0.2 SCCM,
Ti (OiPr)_FourFlow rate of 0.25 SCCM, NO_Twoof
Hold the film forming condition of flow rate 3.0 SCCM for 30 seconds,
A PTO layer 206 having a film thickness of 5 nm is formed. last
Then, Au is deposited as the upper electrode 207 by a vacuum evaporation method.
Complete the manufacturing process of the ferroelectric capacitor of this comparative example.
It

As shown in FIG. 4A, the ferroelectric memory element of this comparative example manufactured as described above is asymmetric in left and right in the ferroelectric hysteresis (single shot hysteresis) in its initial state, which is obvious. Indicates voltage shift. FIG. 4A is a diagram of FIG. 2A of the first embodiment.
In the same manner as the above, the hysteresis in the initial state (single shot hysteresis) obtained by the single-shot voltage sweep of both polarities of ± 2V, ± 3V, ± 4V, and ± 5V is superimposed and shown. In addition, as shown in FIG. 4B, the ferroelectric capacitor of this comparative example is already subjected to polarization reversal by repeatedly applying a bipolar voltage pulse of ± 3 V, and in particular, in the initial polarization reversal, The charge shows a large fluctuation. Further, as shown in FIG. 4C, in the ferroelectric capacitor of this comparative example, the remanent polarization is already largely changed at the beginning of inversion, and the hysteresis shape is also greatly changed. Similarly to FIG. 2C of the first embodiment, FIG. 4C shows the single shot hysteresis measured after the fatigue characteristic experiment at each point shown in FIG. is there.

Ferroelectric hysteresis characteristics and fatigue characteristics of the ferroelectric capacitor according to the first embodiment shown in FIGS. 2A to 2C and the comparative example shown in FIGS. 4A to 4C. A significant difference between the ferroelectric hysteresis characteristic and the fatigue characteristic of the ferroelectric capacitor is that the PTO grown nucleus layer 102 and the second PZT layer 104 in the ferroelectric capacitor of the first embodiment are different. The first PZT layer 103 and the second P that are present between
This shows the effect of the third PZT layer 105 existing between the ZT layer 104 and the upper electrode side PTO layer 106.

Below, the first PZT layer 103 and the third PZT layer 103
The effect with the ZT layer 105 will be considered. As described in the prior art, PZ having a small Zr / Ti ratio or a large Zr / Ti ratio on the growth nucleus layer made of PTO.
When the T ferroelectric layer is grown, strain is generated at the interface due to the difference in lattice constant. This strain is rapidly attenuated as the distance from the interface is increased, so that the charged layer is formed only near the interface. This charged layer causes a voltage offset in the ferroelectric hysteresis characteristics in the initial state of the manufactured ferroelectric capacitor.

On the other hand, in the first embodiment, the PTO grown nucleus layer 102 and the [Zr] / ([Zr] + [Ti]) ratio having a relatively large Zr / Ti ratio are about 0. .3
5 between the second PZT layer 104 and [Zr] / ([Z
By forming the first PZT layer 103 having a ratio of [r] + [Ti] of 0.2 smaller than 0.35 of 20 to 30 nm, the first PZT layer 103 acts as a strain buffer layer and is generated. This has the effect of suppressing the amount of interfacial charge that occurs.
However, [Zr] / ([Zr of the first PZT layer 103
r] + [Ti]) ratio is smaller than 0.15, P
It has been confirmed that the coercive electric field of the entire ZT layer becomes too large and the polarization value decreases. On the other hand, [Z
When the r] / ([Zr] + [Ti]) ratio is larger than 0.25, the second P deposited on the first PZT layer 103 is deposited.
Since the difference in the Zr / Ti ratio from the ZT layer 104 becomes small,
It has also been confirmed that the effect of the first PZT layer 103 as a buffer layer does not appear. Therefore, the [Zr] / ([Zr] + [Ti]) ratio of the first PZT layer 103 is 0.
It is preferably not less than 15 and not more than 0.25, and is about 0.
Most preferably, it is 2. Also, the first PZT layer 1
The film thickness of 03 is preferably 20 to 30 nm.
When the film thickness of the first PZT layer 103 is thinner than 20 nm, the effect of the first PZT layer 103 as a buffer layer cannot be seen. On the other hand, the film thickness of the first PZT layer 103 is set to 30
If it is thicker than nm, Zr / of the first PZT layer 103
The effect as a ferroelectric layer with a small Ti ratio becomes large,
It works to increase the coercive voltage of the PZT layer as a whole.

Next, the effect of the third PZT film 105 will be described. Damage and strain are introduced into the interface between the upper surface of the PZT layer and the upper electrode by the upper electrode forming process. In addition to the charge generated by damage, PZ
The stress applied to the T layer also affects the behavior of the ferroelectric domain. Due to such an action, the PZT layer near the interface with the upper electrode is less likely to undergo polarization reversal, and a voltage offset occurs in the ferroelectric hysteresis in the initial state. Furthermore, in a tetragonal structure PZT exhibiting ferroelectricity, when a 90 ° domain rotation in which the a axis and the c axis, which is the polarization axis, are switched by application of an electric field occurs during polarization reversal,
The read charge fluctuates. When strain is introduced near the interface with the upper electrode, it is difficult for the 90 ° domain rotation to be completed at the time of the first writing operation due to the strain effect, and gradually occurs by the subsequent application of an electric field. Is likely to occur. In particular, the coercive electric field of the PZT layer existing near the interface with the upper electrode is large, that is,
In the composition having a small Zr / Ti ratio, the difference between the a-axis length and the c-axis length is large, and therefore the 90 ° domain rotation works in the direction of increasing the strain, and this tendency becomes remarkable.

It is generally accepted that the coercive electric field tends to decrease with increasing Zr / Ti ratio in PZT. This is because Zr having a large ionic radius randomly occupies B sites, that is, sites containing Zr and Ti, so that the B site space is expanded and Ti having a small ionic radius occupying the same B site can move relatively freely. It is understood that this is because When the Ti ions are allowed to move freely, polarization inversion occurs with the movement of Ti ions, and therefore polarization inversion easily occurs. As in the first embodiment, [Zr] / ([Zr] + [T
i]) on the second PZT layer 104 having a ratio of about 0.35,
The growth of the third PZT layer 105 having a [Zr] / ([Zr] + [Ti]) ratio of 0.55, which is larger than 0.35, means that the PZT having a small coercive electric field is formed near the interface with the upper electrode.
As a layer is formed, it has the effect of facilitating polarization reversal near the interface with the upper electrode. In addition to that, [Z
r] / ([Zr] + [Ti]) ratio, thus Zr /
When the Ti ratio is increased, the ratio of the a-axis length and the c-axis length in the tetragonal PZT molecule approaches 1, so that the strain in the film generated by the 90 ° domain rotation becomes small, and the 90 ° domain rotation becomes easy. Become. Due to this effect, the 90 ° domain rotation can be completed in the first write operation, and the read charge fluctuation due to the repetition of polarization inversion thereafter can be suppressed.

Such an effect is obtained by the third PZT layer 105.
If the [Zr] / ([Zr] + [Ti]) ratio of is smaller than 0.43, it becomes thin. Also, the third PZT
The [Zr] / ([Zr] + [Ti]) ratio of the layer 105 is 0.
When it is larger than 58, the crystal phase changes from tetragonal to rhombohedral and the polarization axis changes, so that a desired polarization value cannot be obtained. Therefore, the [Zr] / ([Zr] + [Ti]) ratio of the third PZT layer 105 is preferably 0.43 or more and 0.58 or less. Also, the third PZ
The thickness of the T layer 105 is preferably 10 to 20 nm. When the film thickness of the third PZT layer 105 is made thicker than 20 nm, the paraelectric component is increased in the ferroelectric capacitor element as a whole, and its hysteresis shape is deteriorated. on the other hand,
If the film thickness of the third PZT layer 105 is made thinner than 10 nm, the above-mentioned effect does not appear. In addition, through the above experiment, [Zr] / ([Zr] + of the second PZT layer 104 is obtained.
It has been found that the [Ti] ratio is preferably 0.3 or more and 0.4 or less, and most preferably 0.35. The film thickness is preferably 100 to 200 nm.

[Confirmation Experiment 1] FIGS. 5A and 5B are composition ratio distribution diagrams [(a) and (b)] in the film thickness direction of the ferroelectric capacitor element of confirmation experiment 1 for confirming the effect of the present invention. FIG. 3 is a ferroelectric hysteresis characteristic diagram [(c) and (d)] of each ferroelectric capacitor. In this experiment, the effect of the PTO layer on the upper electrode side provided at the interface between the upper electrode and the ferroelectric layer was examined. First, the substrate temperature is set to 430
After setting the temperature to 50 ° C. and forming an island-shaped PTO growth nucleus layer of 5 nm under the same conditions as in the first embodiment, a PZT layer of the same composition as the second PZT layer 104 in the first embodiment of 220 nm is formed. Then, a PTO layer having a thickness of 15 nm is formed, and then a PZT layer having the same composition is formed to have a thickness of 15 nm.
Sample A was prepared. Next, a PTO growth nucleus layer, a PZT layer, a PTO layer, and a PZT layer having an island structure were formed under the same conditions as the sample A, and then the PTO layer was formed to a thickness of 15 nm to prepare a sample B. However, the thickness of the first PZT layer is 205 nm.
And a thickness different from that of the sample A. Further, in any of the samples, the upper electrode was finally manufactured, but Au was deposited by the vacuum deposition method to form the upper electrode so that the heat treatment effect did not occur during the manufacture of the upper electrode.

5 (a) and 5 (b) show the composition ratio distributions in the film thickness direction of Sample A and Sample B, respectively. The total film thickness of sample A and sample B is the same. Sample A has a higher ratio of the PZT layer to the total film thickness. FIG. 5 (c),
FIG. 5D shows ± 2 V and ± for sample A and sample B, respectively.
It is shown by superimposing ferroelectric hysteresis (single shot hysteresis) in an initial state obtained when sweeping a single-shot voltage of both polarities of 3 V, ± 4 V, and ± 5 V. Comparing FIG. 5 (c) and FIG. 5 (d), the size of remanent polarization, the squareness of ferroelectric hysteresis, etc.
The sample B shown in FIG. 5D has better characteristics. Sample B having a lower proportion of the PZT layer to the total film thickness exhibits better ferroelectric hysteresis than sample A having a higher proportion of the PZT layer to the total film thickness means that the interface of the sample B with the upper electrode is higher. It is shown that the formed PTO layer has a great effect on the improvement of the ferroelectric hysteresis characteristic.

[Confirmation Experiment 2] FIG. 6 is a composition ratio distribution diagram [(a)] in the film thickness direction of the ferroelectric capacitor element of Confirmation Experiment 2 used for confirming the effect of the present invention. It is a ferroelectric hysteresis characteristic figure [(b)]. In this experiment,
The effect of the film thickness of the PTO layer provided at the interface between the upper electrode and the ferroelectric layer on the ferroelectric hysteresis characteristics was investigated.
First, after setting the substrate temperature to 430 ° C. and forming the island-shaped PTO growth nucleus layer of 5 nm under the same conditions as in the first embodiment, the second PZT layer 104 in the first embodiment is formed.
After forming a PZT layer having the same composition as that of 220 nm and then forming PTO layers of various thicknesses, Au was deposited by a vacuum deposition method to form an upper electrode, and the ferroelectric capacitor element of this example was formed. The manufacturing process is completed.

FIG. 6A shows the composition ratio distribution in the film thickness direction of the ferroelectric memory element of the present experiment manufactured in this way. The value of the film thickness x of the PTO layer formed at the interface between the upper electrode and PZT is 0, 5, 10, 20, 33 nm. FIG. 6B is a ferroelectric hysteresis in an initial state obtained when sweeping a single-shot voltage of both polarities of ± 2 V, ± 3 V, ± 4 V, and ± 5 V to a sample having the film thickness x. (Single shot hysteresis) is shown in an overlapping manner. x = 0 nm, that is, when the PTO layer is not formed at the interface between the upper electrode and PZT, x
= 5 nm, the ferroelectric hysteresis characteristic in the case of x = 5 nm is superior in view of the magnitude of the residual polarization and the squareness of the ferroelectric hysteresis characteristic. Especially, when the sweep voltage is small, the difference is remarkable. On the other hand, when the film thickness of the PTO layer is increased as x = 10, 20, 33 nm, the coercive voltage value increases and the remanent polarization value decreases. This is because as the thickness of the PTO layer increases,
This is because the voltage applied to the PTO layer, which has a lower dielectric constant than that of the PZT layer, increases and the ratio of the voltage applied to the PZT layer decreases. The present inventor has found from the detailed evaluation that the film thickness of this PTO layer may be as thin as 3 to 7 nm, and is most preferably about 5 nm. That is, this PT
When the film thickness of the O layer is the same as the film thickness of the PTO growth nucleus layer, the most excellent ferroelectric hysteresis characteristic is obtained. From this result, it was confirmed that the obtained effect is not the effect of the PTO crystal itself (bulk effect) but the effect of the electrode interface. By forming the same PTO layer at the interfaces with the upper and lower electrodes, the PZTs at both interfaces will also be in the same state, and inversion nucleation that triggers polarization reversal will occur under the same conditions on both the upper and lower interfaces. To be judged. In this example, the case where the Zr / Ti ratio of the PZT layer was constant in the film thickness direction of the PZT layer was described, but as in the first embodiment, the Zr / Ti ratio of the PZT layer is changed in the film thickness direction. Similar effects are obtained even when the Ti ratio changes.

As described above, in the ferroelectric capacitor of the present invention, (1) PTO is formed on the PTO growth nucleus layer.
By forming a PZT layer having a small Zr / Ti ratio for relaxing the lattice constant difference from the growth nucleus layer, the PTO growth nucleus layer and P
Prevents the formation of a charge layer at the interface with the ZT ferroelectric layer,
(2) By forming a PZT layer having a large Zr / Ti ratio at the interface between the upper electrode and the PZT layer and disposing a PZT layer having a small coercive electric field, polarization reversal near the interface with the upper electrode and 90 ° domain rotation are achieved. (3) upper electrode and Z
By forming the same PTO layer as the PTO growth nucleus layer between the PZT layer having a large r / Ti ratio, the inversion nucleation that triggers the polarization inversion occurs under the same conditions on the upper and lower interfaces. Due to the structural improvement inside the PZT film and the effect of improving the interface state, the voltage shift of the ferroelectric hysteresis in the initial state and the fluctuation of the read charge during repeated polarization inversion are significantly suppressed.

[Second Embodiment] FIG. 7 is a sectional view of a ferroelectric capacitor according to a second embodiment of the present invention [(a)].
And (b) of the composition ratio distribution in the film thickness direction. Figure 7
As shown in (a), the ferroelectric capacitor of the present embodiment has a PTO growth nucleus layer 302 and a Z
Five layers of PZT layers 308, 309, 3 having different r / Ti ratios
04, 310, 311 and the PTO layer 306 on the upper electrode side
And are stacked, and the upper electrode 307 is formed on the PTO layer 306.
Are formed. First P of the first embodiment
The ZT layer 103 is formed of two PZT layers 308 and 309, the third PZT layer 105 is formed of two PZT layers 310 and 311 and
Each is a replacement. The ferroelectric capacitance element of the present embodiment has a larger number of interfaces of PZT layers having different Zr / Ti ratios than the ferroelectric capacitance element of the first embodiment, but the lattice constant difference between adjacent PZT layers is large. Has a merit that the interface strain can be further suppressed.

As a result of earnest research, the present inventor has found that the PZT layer 3
The [Zr] / ([Zr] + [Ti]) ratio of 08 is 0.1 or more and 0.2 or less, and the [Zr] / ([Z
It has been found that the ratio [r] + [Ti]) is preferably about 0.2. Further, the respective film thicknesses are the same as the PZT layer 30
8 is thinner than that of the PZT layer 309, and
The sum of the film thicknesses of the T layer 308 and the PZT layer 309 is 20 to 4
The thickness is preferably 0 nm, more preferably 30 nm, and the film thickness of the PZT layer 308 is 10 n.
Most preferably, the thickness of the PZT layer 309 is 20 nm. By making the PZT layer 308 thinner than the PZT layer 309, a layer having a small Zr / Ti ratio can be thinned and an increase in coercive voltage of the entire PZT layer can be suppressed. [Zr] / ([Zr of the PZT layer 310
r] + [Ti]) ratio is 0.4 or more and 0.55 or less, PZ
The [Zr] / ([Zr] + [Ti]) ratio of the T layer 311 is preferably about 0.55. [Z of the PZT layer 310
Unless the r] / ([Zr] + [Ti]) ratio is 0.4 or more, the effect of facilitating polarization reversal and 90 ° domain rotation near the interface with the upper electrode becomes weak. The film thickness of the PZT layer 310 is smaller than the film thickness of the PZT layer 311, and the sum of the film thicknesses of the PZT layer 310 and the PZT layer 311 is preferably 15 to 30 nm, and is 20 nm. Is more preferable, and the film thickness of the PZT layer 310 is 8n.
Most preferably, the thickness of the PZT layer 311 is 12 nm. Unless the PZT layer 310 is made thinner than the PZT layer 311, polarization inversion near the interface with the upper electrode and 9
The effect of facilitating 0 ° domain rotation is weakened.

[Third Embodiment] FIG. 8 is a sectional view of a ferroelectric capacitor according to a third embodiment of the present invention [(a)].
And (b) of the composition ratio distribution in the film thickness direction. Figure 8
As shown in (a), the ferroelectric capacitor of the present embodiment has a PTO growth nucleus layer 402 and a Z layer on the lower electrode 401.
The PZT layer 412 in which the r / Ti ratio continuously changes and the PTO layer 406 on the upper electrode side are stacked to form the PTO layer 40.
6 has an upper electrode 407 formed thereon. The first PZT layer 103 and the second PZT layer 1 of the first embodiment
04 and the interface between the second PZT layer 104 and the third PZT layer 105 are such that the Zr / Ti ratio changes continuously and smoothly. When the MOCVD method is used as the film forming method, the MOCVD method is used.
It is possible to realize such an interface in which the Zr / Ti ratio changes continuously by controlling the supply amount of the raw material in fine steps. Compared with the interface where the Zr / Ti ratio changes stepwise as shown in FIGS. 1 and 7, such an interface is less likely to generate a crystal grain boundary that is more likely to be a charge trap site, and the voltage to the ferroelectric hysteresis is increased. The effect of suppressing the occurrence of offset is increased. The thicknesses of the regions to be composition-modulated are 20 to 30 nm on the lower electrode side and 10 to 20 nm on the upper electrode side, and are the same as those of the first PZT layer 103 and the third PZT layer 105 of the first embodiment, respectively. It is preferable that they have the same thickness. In addition, Z in the central portion of the PZT film
[Zr] / ([Zr] + in the region where the r / Ti ratio does not change
[Ti]) ratio is about 0.35, and its film thickness is 100-200.
nm is preferable. In addition, from the first embodiment to the third embodiment, the film forming temperature is 450.
It was confirmed that the effect of the ferroelectric structure of the present invention described above is maintained even at a temperature of not less than ° C. Further, in the first to third embodiments, P is used as the ferroelectric substance.
Although ZT is used, the semiconductor memory device of the present invention is
It is not limited to T, but can be configured using a ferroelectric having at least Zr and Ti as negative elements. As such a ferroelectric, (Pb, La) (Zr, Ti) O ₃ ,
(Pb, Nb) (Zr, Ti) O ₃ , La ₂ (Zr, T
i) O ₇ , (Pr, Ce) Pb _n (Zr, Ti) _n O
Ferroelectric materials having a simple perovskite crystal structure or a layered perovskite crystal structure, such as _{3n + 1} , can be given. Further, as the means for supplying the raw material in the MOCVD method, carrier gas transportation or liquid material transportation may be used, and the film formation method may be the sol-gel method, the sputtering method, or the laser ablation method. I was able to reproduce the effect.

[Fourth Embodiment] FIGS. 9A to 9C are cross-sectional views in order of the processes, for explaining the method for manufacturing the ferroelectric memory device according to the fourth embodiment of the present invention. First, an isolation oxide film 606 is formed on a silicon substrate by the LOCOS method to define an element formation region, and then, if necessary, phosphorus, boron or the like is ion-implanted as impurities to form an n-well (not shown), Alternatively and / or form a p-well (not shown). Next, a gate oxide film 601 is formed by wet oxidation, a polysilicon film is formed on the entire surface, and the formed polysilicon film is etched by a normal photoetching technique to form a gate polysilicon layer 602. To do. After forming a silicon oxide film around the gate polysilicon layer 602, etching is performed to form a sidewall oxide film 603. Next, the diffusion layer 605 is formed by ion-implanting impurities. n
For example, arsenic is used as an impurity for forming the type diffusion layer, and boron is used as an impurity for forming the p type diffusion layer. Further, after forming a Ti film on the entire surface and performing a heat treatment, the Ti film that has not reacted with silicon is removed by etching, so that the Ti silicide film is formed on the gate polysilicon layer 602 and the diffusion layer 605, respectively. 60
4 is formed. Through the above steps, as shown in FIG. 9A, an n-channel or p-channel MOS transistor is formed in the region defined by the isolation oxide film 606 on the silicon substrate.

Next, after a silicon oxide film or a silicon oxide film (BPSG film) to which a boron oxide and a phosphorus oxide are added is formed on the entire surface as the first interlayer insulating film 607a,
The surface is flattened by using a chemical mechanical polishing method (CMP method) or an etch back method. Next, a contact hole for forming a connection to the diffusion layer 605 is formed in the first interlayer insulating film 607a by etching, and then the diffusion layer 60 is formed.
Injecting n-type or p-type impurities into 5 at 750 ° C.
Heat treatment for 10 seconds. After that, a Ti film and a TiN film, which will be a barrier layer to the diffusion layer 605, are continuously formed.
Further, after depositing tungsten by the CVD method, C
The surface is flattened by the MP method to form the first plug 608a. A Ti film 609, a TiN film 610, and a Ti film 611, which will be a barrier layer of the lower electrode, are successively formed thereon by a sputtering method, and further, in order to form a lower electrode of the ferroelectric capacitor, Ru film 61 having a film thickness of 100 nm
2 is deposited (FIG. 9B).

Next, a laminated film composed of the PTO growth nucleus layer, the PZT layer, and the upper electrode side PTO layer having the structure described in any of the first to third embodiments is formed into a film. It is formed to have a thickness of 200 nm. Then, a Ru film is formed by a sputtering method in order to form an upper electrode of the ferroelectric capacitor. Further, a Ru film for forming an upper electrode of the ferroelectric capacitor by dry etching, a laminated film including a PTO growth nucleus layer, a PZT layer, and an upper electrode side PTO layer, and Ru films 614 and T.
By patterning the i film 611, the TiN film 610, and the Ti film 609, the upper electrodes 614 and P are respectively formed.
A ferroelectric thin film structure layer 613 including a TO growth nucleus layer, a PZT layer, and an upper electrode side PTO layer, and a lower electrode 615 including a Ru film 612 and barrier metal layers (609 to 611) are formed. Through the above steps, as shown in FIG.
A PZT ferroelectric capacitor element including the upper electrode 614, the ferroelectric thin film structure layer 613 and the lower electrode 615 is formed.

Next, as shown in FIG. 9D, a silicon oxide film is formed by plasma CVD as a second interlayer insulating film 607b.
After being formed on the entire surface by the method, an opening is provided on the PZT ferroelectric capacitor element, and the second plug 608b is formed by the same method as the first plug. Then, WSi, TiN, Al,
After depositing Cu and TiN by sputtering in this order,
By processing by etching, a metal wiring 616 extending from the front side to the rear side of the drawing is formed on the second plug 608b. The metal wiring 616 becomes a plate line of the memory cell. Furthermore, a passivation film 61 made of a silicon oxide film and a silicon oxynitride film (SiO _x N _y film).
7 is formed, and the process of manufacturing the ferroelectric memory device by the first manufacturing method of the present embodiment is completed. The plate line of the memory cell is usually connected to the inverter of the plate line driving circuit at the end of the cell array.

Next, the electrical characteristics of the ferroelectric memory device manufactured by the above manufacturing method were evaluated. First, the inversion charge amount and the non-inversion charge amount were calculated from the ferroelectric hysteresis characteristics in the initial state. A value of 30 μC / cm ² or more was obtained as the difference between the calculated inversion charge amount and non-inversion charge amount, and it was concluded that there is no voltage offset in the initial state. In addition, fluctuations in the read charge due to repeated polarization inversion were suppressed, and fatigue characteristics and retention characteristics were good. The leak current is 10 ⁻⁴ A when 10 V is applied.
/ Cm ² or less was good. In addition, when the characteristics of the MOS type FET formed under the ferroelectric capacitance element were evaluated, when the gate was formed to have a gate length of 0.26 μm,
In both the p-channel FET and the n-channel FET, the variation in the threshold voltage Vt was 10% or less over the entire surface of the wafer, which was good. Furthermore, when the resistance of the 0.4 μm square first plug 608a was measured by a plug chain, the resistance per plug was 10 Ωcm or less, which was good.

[Fifth Embodiment] FIGS. 10A to 10D are cross-sectional views in order of the processes, for illustrating a method for manufacturing a ferroelectric memory device according to a fifth embodiment of the present invention. In the manufacturing method of the present embodiment, the steps up to the step of forming the Ru film for forming the lower electrode are the same as those in the manufacturing method of the fourth embodiment. That is, first, as shown in FIG. 10A, the gate oxide film 701 is formed in the element formation region defined by the isolation oxide film 706 of the silicon substrate 701.
And the gate polysilicon layer 7 on the gate oxide film 701.
02, a sidewall oxide film 703 on the sidewall of the gate polysilicon layer 702, a diffusion layer 705, and a gate polysilicon layer 7
02 and the diffusion layer 705, a Ti silicide film 704 is formed on each of the surfaces. Next, similar to the manufacturing method according to the fourth embodiment, the first interlayer insulating film 707a, the first plug 708a on the diffusion layer 705, the Ti film 709, and T film.
an iN film 710 and a Ti film 711, a Ru film 712,
Is formed. Then, by dry etching, R
The lower electrode 715 is formed by processing the u film, the Ti film, the TiN film, and the Ti film. Through the above steps, as shown in FIG. 10B, the first plug 70
8a and the lower electrode 715 are formed.

Next, a strong layer composed of a PTO growth nucleus layer, a PZT layer and an upper electrode side PTO layer having the structure described in any of the first to third embodiments. The dielectric thin film structure layer 713 is formed to have a film thickness of 200 nm. Through the above steps, FIG.
A ferroelectric thin film structure layer 713 is formed as shown in FIG.

Next, as shown in FIG. 10D, in order to form the upper electrode, a Ru film is formed by a sputtering method, and the Ru film is patterned by dry etching to form the Ru film. Upper electrode 71
4 is formed. Then, similarly to the first manufacturing method, the second interlayer insulating film 707b, the second plug 708b on the PZT ferroelectric capacitor, and the front side of the paper which becomes the plate line of the memory cell on the second plug 708b. After that, a metal wiring 716 extending rearward from and a passivation film 717 are formed, and the process of manufacturing the ferroelectric memory device of the present embodiment is completed.

In the manufacturing method of the present embodiment, the layer thickness of the layer that is etched in one dry etching is thin, so that a finer pattern can be formed as compared with the manufacturing method of the fourth embodiment. It is possible. Further, the ferroelectric thin film structure layer 713 is not etched, and therefore, the side surface of the ferroelectric thin film structure layer 713 is not exposed to plasma during any dry etching. The introduction of defects into the structure layer 713 is also reduced. The ferroelectric memory device manufactured by the manufacturing method of the present embodiment also showed excellent electrical characteristics similar to those of the ferroelectric memory device manufactured by the manufacturing method of the fourth embodiment.

[Sixth Embodiment] FIGS. 11A to 11D are cross-sectional views in order of the processes, for illustrating a method for manufacturing a part of the ferroelectric memory device according to the fifth embodiment of the present invention. In the ferroelectric memory device of this embodiment, the memory section and the logic circuit section are integrated on the same substrate. Using FIG. 11,
A method of manufacturing the memory portion of the ferroelectric thin film device of this embodiment will be described. In the manufacturing method of the present embodiment, the steps up to the step of manufacturing the first plug 808a made of tungsten are the same as those in the manufacturing methods of the fourth and fifth embodiments. Next, the first interlayer insulating film 807
barrier metal composed of Ti and TiN on the entire surface of a,
AlCu alloys are used for sputtering and CVD
After being formed by the method, it is processed by dry etching, and the first metal wiring 81 is formed on the first plug 808a.
6a and 816a 'are formed. First metal wiring 81
6a 'extends in the left-right direction of the paper and is formed in the back of the first metal wiring 816a on the left-right of the paper, and forms the bit line of the memory cell.

Next, a silicon oxide film or a BPSG film is formed on the entire surface as a second interlayer insulating film 807b, and then CMP is performed.
Method is used to planarize the surface. Then, after forming a via hole by etching, Ti that becomes a barrier layer is formed.
A film and a TiN film are continuously formed. After that, a tungsten film is formed by the CVD method, and then the surface is flattened by the CMP method to form the second plug 808b. As a planarization method, an etch back method may be used instead of the CMP method. Next, the first metal wirings 816a and 81
The second metal wiring 816b is formed by the same step as the step of forming 6a '. At this time, at the same time, a wiring (not shown) is formed behind the illustrated second metal wiring 816b and extends in the left-right direction of the paper. The second metal wiring, which is deep inside the second metal wiring 816b and extends in the left-right direction of the paper, is used as a wiring in the logic circuit. The first metal wiring can be used only as the bit wiring of the memory cell, and the cell area can be reduced.

Next, a silicon oxide film or a BPSG film is formed as a third interlayer insulating film 807c, planarized by a CMP method, and then a via hole is opened, and a first plug 808a is formed.
Similarly, the third plug 808c is formed on the second metal wiring 816b by using a tungsten plug or the like. Hereinafter, the interlayer insulating film and the metal wiring may be further formed by using the same method. Then, a Ti film 809, a TiN film 810, and a Ti film 811 are formed on the third interlayer insulating film 807c.
Is continuously sputtered to form a film with a thickness of 100 nm.
A thick Ru film 812 is formed. Through the above steps, as shown in FIG. 9B, the Ru film 812 and the barrier metal (809-) for forming the plurality of plugs and the lower electrodes are formed.
811) is formed.

Next, similarly to the first manufacturing method of the fourth embodiment, the PTO grown nucleus layer having the structure described in any of the first to third embodiments. And P
A laminated film including a ZT layer and a PTO layer on the upper electrode side is formed to have a film thickness of 200 nm, and subsequently, a Ru film is formed by a sputtering method to form an upper electrode. Further, by dry etching, a Ru film for forming an upper electrode, a laminated film including a PTO growth nucleus layer, a PZT layer, and an upper electrode side PTO layer, a Ru film 812, and a Ti film 811, a TiN film 810, and a Ti film. By processing the film 809 and the upper electrode 814, P respectively.
A ferroelectric thin film structure layer 813 including a TO growth nucleus layer, a PZT layer, and a PTO layer on the upper electrode side, and a lower electrode 815 are formed. Through the above steps, as shown in FIG. 11C, a PZT ferroelectric capacitor element including the upper electrode 814, the ferroelectric thin film structure layer 813 and the lower electrode 815 is formed.

Next, as shown in FIG. 9D, a silicon oxide film is plasma-enhanced as the fourth interlayer insulating film 807d.
Then, an opening is provided on the PZT ferroelectric capacitor element, and a fourth plug 808d is formed by the same method as the first plug 808a. Then WSi, Ti
N, Al, Cu, and TiN are formed in this order by a sputtering method and then processed by etching to form a fourth plug 80.
A third metal wiring 816c extending from the front to the rear of the drawing is formed on 8d. The third metal wiring 816c is
It becomes the plate line of the memory cell. Further, the passivation film 8 made of a silicon oxide film and a SiO _x N _y film.
17 is formed, and the process of manufacturing the ferroelectric memory device by the manufacturing method of the present embodiment is completed.

Next, the electrical characteristics of the ferroelectric memory device manufactured by the above manufacturing method were evaluated. First, the inversion charge amount and the non-inversion charge amount were calculated from the ferroelectric hysteresis characteristic in the initial state and the ferroelectric hysteresis characteristic in the initial state. A value of 30 μC / cm ² or more was obtained as the difference between the calculated inversion charge amount and non-inversion charge amount, and it was concluded that there is no voltage offset in the initial state. In addition, fluctuations in the read charge due to repeated polarization inversion were suppressed, and fatigue characteristics and retention characteristics were good. Leak current is 10 ⁻⁴ A / cm when 10 V is applied
It was as good as ² or less. In addition, when the characteristics of the MOSFET formed under the ferroelectric capacitance element were evaluated, when the gate was formed to have a gate length of 0.26 μm, there was a variation in the threshold voltage Vt of both the p-channel FET and the n-channel FET. It was 10% or less on the entire surface of the wafer, which was good. Furthermore, when the resistance of the 0.4 μm square third plug 808c was measured by a contact chain, the specific resistance per contact was 10 Ωcm or less, which was good.

Also in the manufacturing method of the present embodiment, FIG.
Similarly to the manufacturing method of the fifth embodiment shown in FIG. 0, in manufacturing the ferroelectric capacitor, the Ru film 812 and Ti are used.
The film 811, the TiN film 810, and the Ti film 809 are processed to form a lower electrode, a dielectric thin film structure layer is formed on the entire surface, and the Ru film formed thereon is processed to form a ferroelectric film. You may form a capacitive element upper electrode. In this case, the layer thickness of the layer etched in one dry etching is small, and a finer pattern can be formed. In addition, since the dielectric thin film structure layer is not etched, and therefore the side surface of the dielectric thin film structure layer is not exposed to plasma during any dry etching, the dielectric thin film structure layer is not exposed to the plasma. The introduction of defects is also reduced.

Although the present invention has been described based on the preferred embodiments thereof, the ferroelectric capacitor element of the present invention is not limited to the above-mentioned embodiments, and the gist of the present invention is not limited thereto. Ferroelectric capacitance elements that have undergone various changes within the range not changed are also included in the scope of the present invention. For example, the lower electrode and the upper electrode are not limited to Ru, but Ru, Pt,
It may be formed using a pure metal such as Ir, an oxide thereof, or a laminated structure including them. Further, the plug is not limited to the tungsten plug and may be formed using polysilicon.

[0049]

As described above, the semiconductor memory device of the present invention relaxes the strain in the PZT ferroelectric thin film by changing the Zr / Ti ratio of the PZT ferroelectric thin film in the film thickness direction, Moreover, since the generation of the internal electric field is prevented, it is possible to suppress the voltage offset in the initial state, which directly affects the performance of the nonvolatile memory device using the ferroelectric thin film. In addition, the semiconductor memory device of the present invention can reduce strain at the interface between the growth nucleus layer and the PZT ferroelectric thin film,
Further, since the strain effect due to the formation of the upper electrode can be relaxed, it is possible to improve the ferroelectric hysteresis characteristic in the initial state and suppress the fluctuation of the read charge due to repeated polarization inversion (switching).

[Brief description of drawings]

FIG. 1 is a sectional view [(a)] of a ferroelectric capacitor according to a first embodiment of the present invention and a composition ratio distribution diagram [(b)] in a film thickness direction.

FIG. 2 is a ferroelectric hysteresis characteristic diagram [(a)] in the initial state of the ferroelectric capacitor of FIG. 1, a fatigue characteristic diagram [(b)], and a ferroelectric hysteresis characteristic diagram after the fatigue characteristic measurement [( c)].

3A and 3B are a sectional view [(a)] and a composition ratio distribution diagram [(b)] of a ferroelectric capacitor of a comparative example.

4 is a ferroelectric hysteresis characteristic diagram [(a)] in an initial state of the ferroelectric capacitor of FIG. 3, a fatigue characteristic diagram [(b)], and a ferroelectric hysteresis characteristic diagram after the fatigue characteristic measurement [( c)].

FIG. 5 is a composition ratio distribution diagram [(a) and (b)] in the film thickness direction of a ferroelectric capacitor manufactured to confirm the effect of the present invention, and a ferroelectric capacitor of each ferroelectric capacitor. Dielectric hysteresis characteristic diagram [(c) and (d)].

FIG. 6 is a composition ratio distribution diagram [(a)] in the film thickness direction of a ferroelectric capacitor manufactured to confirm the effect of the present invention.
And a ferroelectric hysteresis characteristic diagram [(b)].

FIG. 7 is a sectional view [(a)] of a ferroelectric capacitor according to a second embodiment of the present invention and a composition ratio distribution diagram [(b)] in a film thickness direction.

FIG. 8 is a sectional view [(a)] of a ferroelectric capacitor according to a third embodiment of the present invention and a composition ratio distribution diagram [(b)] in a film thickness direction.

9A to 9C are sectional views in order of the steps, for explaining the manufacturing method of the ferroelectric memory device according to the fourth embodiment of the present invention.

FIG. 10 is a sectional view in order of the steps, for explaining the manufacturing method of the ferroelectric memory device according to the fifth embodiment of the present invention.

11A to 11D are sectional views in order of the processes, for explaining the method for manufacturing the part of the ferroelectric memory device according to the sixth embodiment of the present invention.

[Explanation of symbols]

101, 201, 301, 401 Lower electrode 102, 202, 302, 402 PTO growth nucleus layer 103 First PZT layer 104 Second PZT layer 105 Third PZT layer 106, 206, 306, 406 PTO layer 107, 207 , 307, 407 upper electrodes 204, 304, 308, 309, 310, 311, 4
12 PZT layers 601, 701 Gate oxide films 602, 702 Gate polysilicon layers 603, 703 Side wall oxide films 604, 704 Ti silicide films 605, 705 Diffusion layers 606, 706 Separation oxide films 607a, 707a, 807a First interlayer insulating film Films 607b, 707b, 807b Second interlayer insulating film 807c Third interlayer insulating film 807d Fourth interlayer insulating film 608a, 708a, 808a First plug 608b, 708b, 808b Second plug 808c Third plug 808d Fourth plug 609, 611 , 709, 711, 809, 811 T
i film 610, 710, 810 TiN film 612, 712, 812 Ru film 613, 713, 813 ferroelectric thin film structure layer 614, 714, 814 upper electrode 615, 715, 815 lower electrode 616, 716 metal wiring 816a, 816a ' First metal wiring 816b Second metal wiring 816c Third metal wiring 617, 717, 817 Passivation film

   ─────────────────────────────────────────────────── ─── Continued front page    F term (reference) 5F058 BA11 BD02 BD05 BF06                 5F083 FR01 FR02 GA21 GA29 JA15                       JA35 JA36 JA37 JA38 JA39                       JA40 JA53 JA56 MA06 MA16                       MA17 PR21 PR40

Claims (20)

[Claims] 1. A ferroelectric capacitor having a structure in which a ferroelectric having a simple perovskite crystal structure or a layered perovskite crystal structure containing zirconium (Zr) and titanium (Ti) as negative elements is sandwiched between upper and lower electrodes. Z of a ferroelectric layer in a semiconductor memory device having an element
A semiconductor memory device characterized in that a growth nucleus layer is formed at an interface between the ferroelectric layer and the lower electrode by changing an r / Ti ratio between the lower electrode side and the upper electrode side. 2. The semiconductor memory device according to claim 1, wherein the growth nucleus layer is formed by removing a part of the negative element of the ferroelectric layer. 3. Zirconium (Zr) as a negative element
In a semiconductor memory device having a ferroelectric capacitor having a structure in which a ferroelectric having a simple perovskite type crystal structure containing titanium and titanium (Ti) or a layered perovskite type crystal structure is sandwiched between upper and lower electrodes, A semiconductor memory device, wherein a layer formed by removing a part of a negative element of the layer is formed with a film thickness substantially equal to an interface between the ferroelectric layer and the upper and lower electrodes. 4. A ferroelectric having a simple perovskite type crystal structure is lead zirconate titanate (Pb (Zr, T
i) O ₃ , hereinafter referred to as “PZT”), The semiconductor memory device according to claim 1. 5. The layer formed by removing a part of the negative element of the growth nucleus layer or the ferroelectric layer is lead titanate (hereinafter referred to as “PTO”). 5. The semiconductor memory device according to any one of 1 to 4. 6. The semiconductor memory device according to claim 5, wherein the PTO layer is formed in an island shape on the lower electrode or the upper electrode. 7. The Zr / Ti ratio monotonically increases from the lower electrode side to the upper electrode side.
The semiconductor memory device according to any one of 1. 8. The semiconductor memory device according to claim 7, wherein the Zr / Ti ratio changes stepwise. 9. A PZT layer of three layers having different Zr / Ti ratios, and the Zr / Ti ratio of the lowermost PZT layer is 0.17 to 0.17.
0.33, the Zr / Ti ratio of the intermediate PZT layer is 0.43 to
0.67, the Zr / Ti ratio of the uppermost PZT layer is 0.75
9. The semiconductor memory device according to claim 8, wherein: 10. The film thickness of the lowermost PZT layer is 20 to
30 nm, the thickness of the intermediate PZT layer is 100 to 200
10. The semiconductor memory device according to claim 9, wherein the uppermost PZT layer has a thickness of 10 to 20 nm. 11. A PZT layer having five layers having different Zr / Ti ratios, and the Zr / Ti ratio of the lowermost PZT layer is 0.11 to 0.11.
0.25, the Zr / Ti ratio of the intermediate PZT layer is 0.43 to
9. The semiconductor memory device according to claim 8, wherein the Zr / Ti ratio of the PZT layer from the bottom to the fourth layer is 0.67 to 1.22. 12. The film thickness of the lowermost PZT layer is smaller than the film thickness of the second to second PZT layers, and the film thickness of the lower to fourth PZT layers is the film thickness of the uppermost PZT layer. The semiconductor memory device according to claim 11, wherein the semiconductor memory device is thinner. 13. The total thickness of the lowermost PZT layer and the lowermost second PZT layer is 20 to 40 nm, and the thickness of the lowermost fourth PZT layer and the uppermost PZT layer. 13. The semiconductor memory device according to claim 11 or 12, wherein the total is 15 to 30 nm. 14. The semiconductor memory device according to claim 7, wherein the Zr / Ti ratio continuously changes. 15. A PZT having a constant Zr / Ti ratio in the middle portion.
15. The semiconductor memory device according to claim 14, which has a layer. 16. A Pr having a constant Zr / Ti ratio in the intermediate portion.
16. The semiconductor memory device according to claim 15, wherein the ZT layer has a thickness of 100 to 200 nm. 17. The Zr / Ti ratio of the PZT layer in the middle portion is 0.43 to 0.67.
17. The semiconductor memory device according to 5 or 16. 18. P at the interface between the upper electrode and the PZT layer
A TO layer is formed, and the TO layer is formed.
7. The semiconductor memory device according to any one of 7. 19. The semiconductor memory device according to claim 18, wherein the PTO layer formed on the lower electrode side and the PTO layer formed on the upper electrode side have substantially the same film thickness. 20. The semiconductor memory device according to claim 1, wherein at least the ferroelectric layer is formed by a metal organic chemical vapor deposition method.