JP5561300B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a method of manufacturing a semiconductor device having a capacitor structure in which a capacitor film made of a dielectric material is sandwiched between a lower electrode and an upper electrode, and in particular, a ferroelectric capacitor in which the capacitor film is made of a ferroelectric material. It is suitable to apply to the structure.

In recent years, development of a ferroelectric memory (FeRAM: Ferro-electric Random Access Memory) that holds information in a ferroelectric capacitor structure by using polarization inversion of the ferroelectric has been advanced. A ferroelectric memory is a non-volatile memory in which retained information is not lost even when the power is turned off, and is attracting particular attention because it can be expected to realize high integration, high speed driving, high durability, and low power consumption.

  As described in Patent Documents 1 to 3 below, the capacitor structure used in the FeRAM memory cell uses, for example, an SBT film or a PZT film as the ferroelectric film, and the ferroelectric film is used as the lower electrode. And the upper electrode. For example, a platinum film is used as the lower electrode, and a platinum film, an iridium oxide film, or the like is used as the upper electrode.

In Patent Document 1, in order to suppress the separation and mutual diffusion of the constituent elements of the ferroelectric film, a period from the process of completely crystallizing the ferroelectric film to the process of forming the protective film of the capacitor structure is disclosed. A method that does not perform high-temperature heat treatment is disclosed. Specifically, first, a capacitor film is formed using PZT, which is a ferroelectric material, and then crystallized by an RTA (Rapid Thermal Annealing) method. Subsequently, an upper electrode is formed using IrO _x (0 <x <2) as a material, and further the RTA method is performed to completely crystallize the capacitor film, and at the same time, iridium (Ir) of the upper electrode is diffused into PZT. Let According to this method, mutual diffusion between the electrode and the ferroelectric film and separation of constituent elements of the ferroelectric film can be prevented.

  In Patent Document 2, in order to improve the crystallinity of the ferroelectric film having a stacked capacitor structure, an iridium film and an iridium oxide film are stacked to form a lower electrode, and then a first PZT film is formed. Further, a method for forming a second PZT film thicker than the first PZT film is disclosed.

  Patent Document 3 discloses a method of adding a heteropolyacid to an organometallic compound coating solution such as SBT or PZT in order to form a ferroelectric film that promotes crystallization at a low temperature of 650 ° C. or lower.

JP 2005-183841 A JP 2003-68991 A JP 2003-128419 A

As specifically disclosed in Patent Document 1, in the conventional FeRAM manufacturing method, after forming an upper electrode from IrO _x (0 <x <2) on a capacitor film made of a ferroelectric material, annealing is performed. A technique has been proposed in which iridium is diffused into the capacitor film.

When iridium diffuses into the capacitor film, it binds into the ferroelectric crystal grains (in the case of ABO ₃ type perovskite structure, A site and B site), the reverse charge of the capacitor structure increases, and the leakage current slightly increases. It becomes a state. However, when iridium is not bonded to the ferroelectric crystal grains, the iridium accumulates at the crystal grain boundary to form a leak path, and the leak current of the capacitor increases rapidly. At the same time, the interface portion (no ferroelectricity) between the upper electrode and the capacitor film becomes thicker, the inversion charge amount decreases, and the coercive electric field increases. Furthermore, when many crystal defects (vacancies) are generated in the capacitor film, iridium fills the crystal defects and the leakage current increases drastically. As a result, there is a problem that the yield of FeRAM is significantly reduced.

  The present invention has been made in view of the above-described problems, and is a highly reliable semiconductor that can secure a high yield without increasing the leakage current, although improving the inversion electrification amount of the capacitor structure. An object is to provide a method for manufacturing a device.

A method of manufacturing a semiconductor device of the present invention is a method of manufacturing a semiconductor device having a capacitor structure in which a capacitor film made of a dielectric material is sandwiched between a lower electrode and an upper electrode above a semiconductor substrate, In forming the capacitor structure, a step of forming a lower electrode layer, a step of forming a dielectric film containing amorphous PZT on the lower electrode layer to a thickness in the range of 120 nm to 150 nm, and an oxidizing property Performing a first heat treatment by RTA method on the dielectric film in an atmosphere at a temperature within a range of 548 ° C. to 553 ° C., crystallizing a lower layer portion of the dielectric film, and maintaining an upper layer portion in an amorphous state; Forming a top electrode layer containing iridium on the dielectric film; and subjecting the top electrode layer to a second heat treatment in an oxidizing atmosphere; And a step of diffusing um inside the dielectric layer, the upper electrode layer, the dielectric layer, and said lower electrode layer were processed, respectively, and forming the capacitor structure.

According to the present invention, it is possible to secure a high yield without increasing the leakage current, although the amount of inversion electrification of the capacitor structure is improved, and a highly reliable semiconductor device is realized.

FIG. 1A is a schematic cross-sectional view showing the configuration of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 1B is a schematic cross-sectional view showing the configuration of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 1C is a schematic cross-sectional view showing the configuration of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 1D is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 2A is a schematic sectional view showing the configuration of the FeRAM according to the first embodiment in the order of steps together with the manufacturing method thereof. FIG. 2B is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 2C is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 2D is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 3A is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 3B is a schematic cross-sectional view showing the configuration of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 3C is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 4A is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 4B is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 4C is a schematic cross-sectional view showing the configuration of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 5A is a schematic cross-sectional view showing the configuration of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 5B is a schematic cross-sectional view showing the structure of the FeRAM according to the first embodiment along with its manufacturing method in the order of steps. FIG. 6 is a schematic cross-sectional view illustrating the capacitor configuration of the FeRAM according to the first embodiment. FIG. 7A is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with its manufacturing method. FIG. 7B is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 7C is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 7D is a schematic cross-sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with its manufacturing method. FIG. 8A is a schematic sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with its manufacturing method. FIG. 8B is a schematic sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 8C is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 8D is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 9A is a schematic sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 9B is a schematic cross-sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with its manufacturing method. FIG. 9C is a schematic sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 10A is a schematic cross-sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with its manufacturing method. FIG. 10B is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 11A is a schematic cross-sectional view showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 11B is a schematic sectional view showing the structure of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof. FIG. 12 is a schematic cross-sectional view illustrating the capacitor configuration of the FeRAM according to the second embodiment. FIG. 13A is a schematic cross-sectional view showing only a configuration corresponding to FIG. 1D as a main configuration of Example 1 according to the third embodiment. FIG. 13B is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of Example 2 according to the third embodiment. FIG. 13C is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of Example 3 according to the third embodiment. FIG. 14A is a schematic cross-sectional view showing only a configuration corresponding to FIG. 1D as a main configuration of Example 4 according to the third embodiment. FIG. 14B is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of Example 5 according to the third embodiment. FIG. 14C is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of Example 6 according to the third embodiment. FIG. 15 is a characteristic diagram showing the results of examining the dependence of the PZT (111) orientation intensity peak on the X-ray incident energy. FIG. 16 is a schematic cross-sectional view showing the FeRAM capacitor configuration of Example 6 according to the third embodiment. FIG. 17A is a cross-sectional photograph showing a state after a PZT film having a thickness of 140 nm formed on the lower electrode layer made of Pt is subjected to heat treatment at 553 ° C. for 90 seconds by the RTA method. FIG. 17B is a cross-sectional photograph showing a state after a PZT film having a thickness of 140 nm formed on the lower electrode layer made of Pt is subjected to heat treatment at 573 ° C. for 90 seconds by the RTA method. FIG. 18A is a schematic cross-sectional view showing the influence on the cross-sectional view of the capacitor due to the temperature of each heat treatment. FIG. 18B is a schematic cross-sectional view showing the influence on the cross-sectional view of the capacitor due to the temperature of each heat treatment. FIG. 18C is a schematic cross-sectional view showing the influence on the cross-sectional view of the capacitor due to the temperature of each heat treatment. FIG. 19A is a characteristic diagram showing the results of measuring the crystallinity of the heat-treated CSPLZT film. FIG. 19B is a characteristic diagram showing the results of measuring the crystallinity of the heat-treated CSPLZT film. FIG. 20A is a characteristic diagram showing the results of measuring the crystallinity of the heat-treated CSPLZT film. FIG. 20B is a characteristic diagram showing the results of measuring the crystallinity of the heat-treated CSPLZT film. FIG. 21A is a characteristic diagram showing the influence of the heat treatment temperature on the crystallinity of the CSPLZT film when the film thickness of CSPLZT is 120 nm. FIG. 21B is a characteristic diagram showing the influence of the heat treatment temperature on the crystallinity of the CSPLZT film when the film thickness of CSPLZT is 120 nm. FIG. 22A is a characteristic diagram showing the results of measuring the inversion charge amount QSW with an applied voltage of 3.0V. FIG. 22B is a characteristic diagram showing a result of measuring the inversion charge amount QSW with an applied voltage of 3.0V. FIG. 23A is a characteristic diagram showing the dependence of the applied voltage on the cell capacitor. FIG. 23B is a characteristic diagram showing a coercive voltage Vc of polarization reversal in the cell capacitor. FIG. 24A is a characteristic diagram showing a result of measuring a leakage current of a ferroelectric capacitor structure (discrete). FIG. 24B is a characteristic diagram showing the result of measuring the leakage current of the ferroelectric capacitor structure (cell array). FIG. 25A is a characteristic diagram showing yield measurement results in a ferroelectric capacitor structure (1T1C type cell array). FIG. 25B is a characteristic diagram showing yield measurement results in the ferroelectric capacitor structure (1T1C type cell array). FIG. 26 is a characteristic diagram showing a result of RET failure (SS & OS) in PT yield.

-Specific embodiments to which the present invention is applied-
Hereinafter, specific embodiments to which the present invention is applied will be described in detail with reference to the drawings. In the following embodiments, the case where the present invention is applied to FeRAM will be exemplified, but the present invention can also be applied to a semiconductor memory using a normal dielectric film as a capacitor structure.

(First embodiment)
In this embodiment, a so-called planar type FeRAM in which the conduction between the lower electrode and the upper electrode of the ferroelectric capacitor structure is taken above the ferroelectric capacitor structure is exemplified. For convenience of explanation, the structure of the FeRAM will be described together with its manufacturing method.
1A to 5B are schematic cross-sectional views showing the configuration of the FeRAM according to the first embodiment in the order of steps together with the manufacturing method thereof.

First, as shown in FIG. 1A, a MOS transistor 20 that functions as a selection transistor is formed on a silicon semiconductor substrate 10.
Specifically, the element isolation structure 11 is formed on the surface layer of the silicon semiconductor substrate 10 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
Next, an impurity, here B, is ion-implanted into the element active region under the conditions of a dose amount of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV to form the well 12.

  Next, a thin gate insulating film 13 having a thickness of about 3.0 nm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film having a thickness of about 180 nm and a thickness of about 29 nm are formed on the gate insulating film 13 by a CVD method. For example, a silicon nitride film is deposited, and the gate electrode 14 is patterned on the gate insulating film 13 by processing the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 13 into an electrode shape by lithography and subsequent dry etching. Form. At the same time, a cap film 15 made of a silicon nitride film is patterned on the gate electrode 14.

Next, using the cap film 15 as a mask, impurities, here As, are ion-implanted under the conditions of a dose of 5.0 × 10 ¹⁴ / cm ² and an acceleration energy of 10 keV to form a so-called LDD region 16.

  Next, for example, a silicon oxide film is deposited on the entire surface by the CVD method, and this silicon oxide film is so-called etched back, thereby leaving the silicon oxide film only on the side surfaces of the gate electrode 14 and the cap film 15 to form the sidewall insulating film 17. Form.

  Next, using the cap film 15 and the sidewall insulating film 17 as a mask, an impurity, here P, is ion-implanted under the condition that the impurity concentration is higher than that of the LDD region 16, and the source / A drain region 18 is formed to complete the MOS transistor 20.

Subsequently, as shown in FIG. 1B, a protective film 21 and an interlayer insulating film 22a of the MOS transistor 20 are sequentially formed.
Specifically, a protective film 21 and an interlayer insulating film 22 a are sequentially deposited so as to cover the MOS transistor 20. Here, as the protective film 21, a silicon oxide film is used as a material, and is deposited to a film thickness of about 20 nm by a CVD method. As the interlayer insulating film 22a, for example, a laminated structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm) and a plasma TEOS film (film thickness of about 1000 nm) are sequentially formed is formed. Polishing is performed by CMP until the film thickness reaches about 700 nm.

Subsequently, as shown in FIG. 1C, an interlayer insulating film 22b and a protective film 23 are sequentially formed. 1C and subsequent figures, for convenience of illustration, only the structure above the interlayer insulating film 22a is shown, and illustration of the silicon semiconductor substrate 10, the MOS transistor 20, and the like is omitted.
More specifically, first, a silicon oxide film is deposited to a thickness of about 100 nm on the interlayer insulating film 22a by, for example, a plasma CVD method using TEOS to form an interlayer insulating film 22b. Thereafter, the interlayer insulating film 22b is annealed. As conditions for the annealing treatment, for example, the annealing is performed at 650 ° C. for 20 minutes to 45 minutes while supplying N ₂ gas at a flow rate of 20 liters / minute.

Next, a protective film 23 is formed on the interlayer insulating film 22b to function as an adhesion film of a ferroelectric capacitor structure described later and to prevent hydrogen / water from entering the ferroelectric film. As the protective film 23, alumina (Al ₂ O ₃ ) is used as a material and is deposited to a thickness of about 20 nm to 50 nm by sputtering. As the protective film 23, instead of alumina, a film of aluminum nitride, tantalum oxide, titanium oxide, zirconium oxide, or the like, or a laminated structure thereof may be used. Thereafter, the protective film 23 is annealed in order to improve the crystallinity of the lower electrode of the ferroelectric capacitor structure. As the conditions for this annealing treatment, for example, the annealing is performed at 650 ° C. for 30 seconds to 120 seconds, for example, 60 seconds, while supplying O ₂ gas at a flow rate of 2 liters / minute.

Subsequently, as shown in FIG. 1D, a lower electrode layer 24, a ferroelectric film 25, and an upper electrode layer 26 are sequentially formed.
Specifically, first, a Pt film is deposited to a thickness of, for example, about 150 nm to 200 nm, here about 150 nm, by sputtering, and the lower electrode layer 24 is formed. In order to improve the crystallinity of Pt (111), it is desirable to form a film at a substrate temperature of 350 ° C. or higher and a high temperature and low power of 0.3 kW, for example. The material of the lower electrode layer 24 may be Ir, Ru, Rh, Re, Os, Pd, oxides thereof, SrRuO ₃ , other conductive oxides, or a laminated structure thereof instead of Pt. .

Next, a first ferroelectric film 25a is formed on the entire surface of the lower electrode layer 24 by, eg, sputtering. The first ferroelectric film 25a has an ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr, Ca, Na, K, and at least one selected from rare earth elements, B = Ti, Zr, Nb. , Ta, W, Mn, Fe, Co, Cr), and a ferroelectric material such as PZT, for example, is formed to a thickness of about 70 nm to 250 nm, here about 120 nm. In addition, although a plurality of A atoms exist in one unit of perovskite structure, they are not necessarily the same in each unit, and the same applies to the case of B atoms.

As the material of the first ferroelectric film 25a, PZT, PLZT, BLT, SBT, and Bi layered structure doped with at least one selected from La, Ca, Sr, and Si instead of PZT ( For example, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element: 0 <x <1), SrBi ₂ Ta ₂ O ₉ , and SrBi ₄ Ti ₄ O ₁₅ One kind selected from may be used. These dielectric materials have an ABO ₃ type perovskite structure as a unit.
In addition to the ferroelectric material, a high dielectric material such as an oxide Zr or Pb-based material may be deposited.

Next, an amorphous second ferroelectric film 25b is formed on the entire surface of the first ferroelectric film 25a by, for example, sputtering. The second ferroelectric film 25b is selected from an ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr, Ca, Na, K, and rare earth elements) containing an Ir element in at least one of the A site and the B site. And at least one selected from the group consisting of B = Ti, Zr, Nb, Ta, W, Mn, Fe, Co, and Cr), for example, PZT. About 20 nm in this case. In addition, although a plurality of A atoms exist in one unit of perovskite structure, they are not necessarily the same in each unit, and the same applies to the case of B atoms.

  If the film thickness of the ferroelectric film 25b is too large, the switching charge amount of the capacitor structure tends to decrease. The content of Ir element is preferably about 0.01 to 3.00%. When the content of Ir element increases, it is accumulated at the crystal grain boundary in the second ferroelectric film 25b by the subsequent heat treatment, and a leak path of the capacitor structure is formed. Here, it is desirable to form the second ferroelectric film 25b using a PZT target to which about 1% of Ir is added.

As a material of the second ferroelectric film 25b to which Ir is added, PZT, PLZT, BLT, SBT doped with at least one selected from La, Ca, Sr, and Si instead of PZT, and Bi layered structure (for example, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element: 0 <x <1), SrBi ₂ Ta ₂ O ₉ , and SrBi ₄ Ti ₄ O ₁₅ are selected. 1 type) may be used. These dielectric materials have an ABO ₃ type perovskite structure as a unit.

  Next, the second ferroelectric film 25b is heat treated. Here, heat treatment is performed by an RTA (Rapid Thermal Annealing) method in an oxidizing atmosphere, here an atmosphere containing oxygen (a mixed atmosphere of an inert gas and oxygen). For example, the heat treatment temperature is 550 ° C. to 800 ° C., for example, 580 ° C., and the heat treatment time is 30 seconds to 120 seconds, here 60 seconds in an atmosphere of oxygen at a flow rate of 50 sccm and Ar at a flow rate of 2000 sccm. The appropriate heat treatment temperature varies depending on the type of ferroelectric material. For example, the heat treatment temperature of PZT or PZT added in a small amount is preferably 600 ° C. or lower, BLT is 700 ° C. or lower, and SBT is 800 ° C. or lower.

  By this heat treatment, the second ferroelectric film 25b is crystallized, and Ir in the second ferroelectric film 25b is bonded to the A site and B site of the crystal grains in the first ferroelectric film 25a. To do. Here, a ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 25a and the second ferroelectric film 25b.

Next, for example, by sputtering or MOCVD, for example, an IrO _x film (0 <x <2) 26a with a thickness of about 10 nm to 100 nm, here about 50 nm, and an IrO _y film with a thickness of about 100 nm to 300 nm ( 0 <y ≦ 2) 26b is sequentially deposited to form the upper electrode layer 26. At this time, the oxygen composition ratio Y of the IrO _y film 26b is set to be higher than the oxygen composition ratio X of the IrO _x film 26a in order to suppress deterioration of the capacitor structure due to the following processes. By forming the IrO _y film 26b to have a composition close to the stoichiometric composition of IrO ₂ , the problem of the ferroelectric film being reduced by hydrogen radicals without causing a catalytic action on hydrogen is suppressed. The hydrogen resistance of the capacitor structure is improved. The material of the upper electrode layer 26 is Ir, Ru, Rh, Re, Os, Pd, these oxides, and conductive oxides such as SrRuO ₃ or their laminated structure instead of iridium oxide. Also good.

Subsequently, as shown in FIG. 2A, the upper electrode 31 is patterned.
Specifically, after the semiconductor substrate 10 is cleaned on the back surface, the upper electrode layer 26 is processed into a plurality of electrode shapes by lithography and subsequent dry etching, and the upper electrode 31 is patterned.

Subsequently, as shown in FIG. 2B, the ferroelectric film 25 is processed.
Specifically, the ferroelectric film 25 is aligned with the upper electrode 31 and processed by lithography and subsequent dry etching. After the patterning of the ferroelectric film 25, the ferroelectric film 25 is annealed to restore the function of the ferroelectric film 25.

Subsequently, as shown in FIG. 2C, a protective film 27 for preventing the entry of hydrogen / water into the ferroelectric film 25 is formed.
Specifically, on the lower electrode layer 24 so as to cover the ferroelectric film 25 and the upper electrode 31, alumina (Al ₂ O ₃ ) is used as a material and is deposited to a thickness of about 50 nm by a sputtering method, and the protective film 27 is formed. Form. Thereafter, the protective film 27 is annealed.

Subsequently, as shown in FIG. 2D, the lower electrode layer 24 is processed together with the protective film 27 to complete the ferroelectric capacitor structure 30.
Specifically, lithography and subsequent drying are performed so that the protective film 27 and the lower electrode layer 24 are aligned with the processed ferroelectric film 25 so that the lower electrode layer 24 remains larger in size than the ferroelectric film 25. The lower electrode 32 is patterned by processing by etching. Thus, the ferroelectric film 25 and the upper electrode 31 are sequentially stacked on the lower electrode 32, and the ferroelectric capacitor structure 30 in which the lower electrode 32 and the upper electrode 31 are capacitively coupled through the ferroelectric film 25 is completed. Let At the same time, the protective film 27 remains so as to cover from the upper surface of the upper electrode 31 to the side surfaces of the upper electrode 31 and the ferroelectric film 25 and the upper surface of the lower electrode layer 24. Thereafter, the protective film 27 is annealed.

In the ferroelectric capacitor structure 30 according to the present embodiment, the ferroelectric film 25 contains iridium therein, and has an iridium concentration distribution in which the iridium concentration decreases from the upper layer region toward the lower layer region. .
Specifically, as shown in FIG. 6, the upper layer region of the ferroelectric film 25, that is, the portion of the second ferroelectric film 25b has a uniform high iridium concentration, and the lower layer region of the ferroelectric film 25, That is, an iridium concentration distribution is formed in which the iridium concentration decreases as the portion of the first ferroelectric film 25a moves downward.

Subsequently, as shown in FIG. 3A, a protective film 28 is formed.
More specifically, the protective film 28 is formed by depositing a film of about 20 nm to 50 nm by sputtering using alumina (Al ₂ O ₃ ) as a material so as to cover the entire surface of the ferroelectric capacitor structure 30. Thereafter, the protective film 28 is annealed.

Subsequently, as shown in FIG. 3B, an interlayer insulating film 33 is formed.
Specifically, the interlayer insulating film 33 is formed so as to cover the ferroelectric capacitor structure 30 via the protective films 27 and 28. Here, the interlayer insulating film 33 is formed by depositing a silicon oxide film to a film thickness of about 1500 nm to 2500 nm by, for example, a plasma CVD method using TEOS, and then polishing the film to a film thickness of, for example, about 1000 nm by CMP. To do. After CMP, for example, N ₂ O plasma annealing is performed for the purpose of dehydrating the interlayer insulating film 33.

Subsequently, as shown in FIG. 3C, a plug 36 connected to the source / drain region 18 of the transistor structure 20 is formed.
Specifically, first, using the source / drain region 18 as an etching stopper, the interlayer insulating film 33, the protective films 28, 27, the interlayer insulating films 22b, 22a, and the like until the surface of the source / drain region 18 is partially exposed. The protective film 21 is processed by lithography and subsequent dry etching to form a via hole 36a having a diameter of about 0.3 μm, for example.

Next, for example, a Ti film and a TiN film are sequentially deposited to a thickness of about 20 nm and a thickness of about 50 nm so as to cover the wall surface of the via hole 36a, thereby forming a base film (glue film) 36b. Then, for example, a W film is formed by the CVD method so as to fill the via hole 36a through the glue film 36b. Thereafter, the W film and the glue film 36b are polished by CMP using the interlayer insulating film 33 as a stopper to form a plug 36 filling the via hole 36a with W through the glue film 36b. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

4A, after forming a hard mask 37 and a resist mask 38, via holes 34a and 35a to the ferroelectric capacitor structure 30 are formed.
Specifically, first, a silicon nitride film is deposited to a thickness of about 100 nm on the interlayer insulating film 33 by a CVD method, and a hard mask 37 is formed. Next, a resist is applied on the hard mask 37, and the resist is processed by lithography to form a resist mask 38 having openings 38a and 38b.

Next, the hard mask 37 is dry-etched using the resist mask 38, and openings 37a and 37b are formed at portions matching the openings 38a and 38b of the hard mask 37.
Then, mainly using the hard mask 37, the interlayer insulating film 33 and the protective films 28 and 27 are dry-etched using the upper electrode 31 and the lower electrode 32 as etching stoppers, respectively. In this dry etching, processing performed on the interlayer insulating film 33 and the protective films 28 and 27 until a part of the surface of the upper electrode 31 is exposed, and the interlayer insulating film 33 and the protection until a part of the surface of the lower electrode 32 is exposed. The processing applied to the films 28 and 27 is performed at the same time, and via holes 34a and 35a having a diameter of, for example, about 0.5 μm are simultaneously formed at the respective portions.

Subsequently, as shown in FIG. 4B, the resist mask 38 and the hard mask 37 are removed.
Specifically, first, the remaining resist mask 38 is removed by ashing or the like. Thereafter, an annealing process is performed to recover the damage received by the ferroelectric capacitor structure 30 through various steps after the formation of the ferroelectric capacitor structure 30. Then, the hard mask 37 is removed by whole surface anisotropic etching, so-called etch back.

Subsequently, as shown in FIG. 4C, plugs 34 and 35 connected to the ferroelectric capacitor structure 30 are formed.
Specifically, first, base films (glue films) 34b and 35b are formed so as to cover the wall surfaces of the via holes 34a and 35a, and then the via holes 34a and 35a are embedded via the glue films 34b and 35b by a CVD method. A W film is formed. Then, for example, the W film and the glue films 34b and 35b are polished by CMP using the interlayer insulating film 33 as a stopper to form plugs 34 and 35 that fill the via holes 34a and 35a with W via the glue films 34b and 35b. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

Subsequently, as shown in FIG. 5A, first wirings 45 connected to the plugs 34, 35, and 36, respectively, are formed.
Specifically, first, the barrier metal film 42, the wiring film 43, and the barrier metal film 44 are deposited on the entire surface of the interlayer insulating film 33 by sputtering or the like. As the barrier metal film 42, for example, a Ti film is formed to a thickness of about 5 nm and a TiN film is formed to a thickness of about 150 nm by sputtering. As the wiring film 43, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 44, for example, a Ti film and a TiN film having a thickness of about 5 nm and a thickness of about 150 nm are formed by sputtering. Here, since the structure of the wiring film 43 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing of the wiring and reliability.

  Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 44, the wiring film 43, and the barrier metal film 42 are wired by lithography and subsequent dry etching. The first wiring 45 connected to the plugs 34, 35, and 36 is patterned by processing into a shape. Instead of forming an Al alloy film as the wiring film 43, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 45.

Subsequently, as shown in FIG. 5B, a second wiring 54 connected to the first wiring 45 is formed.
Specifically, first, an interlayer insulating film 46 is formed so as to cover the first wiring 45. As the interlayer insulating film 46, a silicon oxide film is formed to a thickness of about 700 nm, a plasma TEOS film is formed to a total thickness of about 1100 nm, and then the surface is polished by CMP to a thickness of 750 nm. Form to the extent.

Next, a plug 47 connected to the first wiring 45 is formed.
First, the interlayer insulating film 46 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 45 is exposed to form, for example, a via hole 47a having a diameter of about 0.25 μm.
Next, after forming a base film (glue film) 48 so as to cover the wall surface of the via hole 47a, a W film is formed by the CVD method so as to fill the via hole 47a via the glue film 48. Then, for example, the W film and the glue film 48 are polished using the interlayer insulating film 46 as a stopper to form a plug 47 that fills the via hole 47 a with W via the glue film 48.

Next, the second wiring 54 connected to the plug 47 is formed.
First, a barrier metal film 51, a wiring film 52, and a barrier metal film 53 are deposited on the entire surface by sputtering or the like. As the barrier metal film 51, for example, a Ti film and a TiN film are stacked to form a film having a thickness of about 5 nm and a thickness of about 150 nm by sputtering. As the wiring film 52, for example, an Al alloy film (here, Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 53, for example, a Ti film and a TiN film are stacked to form a film having a thickness of about 5 nm and a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 52 is the same as that of the logic part other than the FeRAM of the same rule, there is no problem in processing of the wiring and reliability.

  Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 53, the wiring film 52, and the barrier metal film 51 are wired by lithography and subsequent dry etching. The second wiring 54 is patterned by processing into a shape. Instead of forming an Al alloy film as the wiring film 52, a Cu film (or Cu alloy film) may be formed by using a so-called damascene method or the like, and a Cu wiring may be formed as the second wiring 54.

  Thereafter, the planar type FeRAM according to the present embodiment is completed through various processes such as formation of an interlayer insulating film and further upper layer wiring.

  As described above, according to the present embodiment, although the amount of inversion electrification of the ferroelectric capacitor structure 30 is improved, a high yield can be ensured without increasing the leakage current. A high planar type FeRAM can be realized.

(Second Embodiment)
In the present embodiment, a so-called stack type FeRAM in which the conduction of the lower electrode of the ferroelectric capacitor structure is taken below the ferroelectric capacitor structure and the conduction of the upper electrode is taken above the ferroelectric capacitor structure is exemplified. For convenience of explanation, the structure of the FeRAM will be described together with its manufacturing method.
7A to 11B are schematic cross-sectional views showing the configuration of the FeRAM according to the second embodiment in the order of steps together with the manufacturing method thereof.

First, as shown in FIG. 7A, a MOS transistor 120 that functions as a selection transistor is formed on a silicon semiconductor substrate 110.
Specifically, the element isolation structure 111 is formed on the surface layer of the silicon semiconductor substrate 110 by, for example, the STI (Shallow Trench Isolation) method to determine the element active region.
Next, an impurity, here B, is ion-implanted into the element active region under conditions of a dose amount of 3.0 × 10 ¹³ / cm ² and an acceleration energy of 300 keV to form the well 112.

  Next, a thin gate insulating film 113 having a thickness of about 3.0 nm is formed in the element active region by thermal oxidation or the like, and a polycrystalline silicon film having a thickness of about 180 nm and a thickness of about 29 nm are formed on the gate insulating film 113 by a CVD method. For example, a silicon nitride film is deposited, and the gate electrode 114 is patterned on the gate insulating film 113 by processing the silicon nitride film, the polycrystalline silicon film, and the gate insulating film 113 into an electrode shape by lithography and subsequent dry etching. Form. At the same time, a cap film 115 made of a silicon nitride film is patterned on the gate electrode 114.

Next, using the cap film 115 as a mask, an impurity, in this case, As is ion-implanted into the element active region under the conditions of a dose amount of 5.0 × 10 ¹⁴ / cm ² and an acceleration energy of 10 keV to form a so-called LDD region.

  Next, for example, a silicon oxide film is deposited on the entire surface by a CVD method, and this silicon oxide film is so-called etched back to leave the silicon oxide film only on the side surfaces of the gate electrode 114 and the cap film 115, and the sidewall insulating film 117. Form.

  Next, using the cap film 115 and the sidewall insulating film 117 as a mask, an impurity, here P, is ion-implanted under the condition that the impurity concentration is higher than that of the LDD region 116, and the source / A drain region 118 is formed to complete the MOS transistor 120.

Subsequently, as shown in FIG. 7B, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123 of the MOS transistor 120 are sequentially formed.
Specifically, a protective film 121, an interlayer insulating film 122, and an upper insulating film 123a are sequentially formed so as to cover the MOS transistor 120. Here, as the protective film 121, a silicon oxide film is used as a material, and is deposited to a thickness of about 20 nm by a CVD method. As the interlayer insulating film 122, for example, a stacked structure in which a plasma SiO film (film thickness of about 20 nm), a plasma SiN film (film thickness of about 80 nm) and a plasma TEOS film (film thickness of about 1000 nm) are sequentially formed is formed. Polishing is performed by CMP until the film thickness reaches about 700 nm. As the upper insulating film 123a, a silicon nitride film is used as a material, and is deposited to a thickness of about 100 nm by a CVD method.

Subsequently, as shown in FIG. 7C, a plug 119 connected to the source / drain region 118 of the transistor structure 120 is formed. 8C and subsequent figures, for convenience of illustration, only the structure above the interlayer insulating film 122 is shown, and illustration of the silicon semiconductor substrate 110, the MOS transistor 120, and the like is omitted.
Specifically, first, using the source / drain region 118 as an etching stopper, lithography is performed on the upper insulating film 123a, the interlayer insulating film 122, and the protective film 121 until the surface of the source / drain region 118 is partially exposed. For example, a via hole 119a having a diameter of about 0.3 μm is formed by dry etching.

Next, a base film (glue film) 119b is formed by sequentially depositing, for example, a Ti film and a TiN film to a film thickness of about 20 nm and a film thickness of about 50 nm so as to cover the wall surface of the via hole 119a. Then, for example, a W film is formed by the CVD method so as to fill the via hole 119a through the glue film 119b. Thereafter, the W film and the glue film 119b are polished by CMP using the upper insulating film 123a as a stopper to form a plug 119 filling the via hole 119a with W via the glue film 119b. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

  Subsequently, as shown in FIG. 7D, an orientation improving film 123b, an oxygen barrier film 123c, a lower electrode layer 124, a ferroelectric film 125, and an upper electrode layer 126 are sequentially formed.

More specifically, first, in order to improve the orientation of the ferroelectric capacitor structure, for example, Ti is deposited to a thickness of about 20 nm, and then Ti is nitrided by rapid annealing (RTA) treatment at 650 ° C. in an N ₂ atmosphere. TiN is used to form a conductive orientation improving film 123b.
Specifically, a sputtering DC power of 2.6 kW is supplied for 7 seconds at a substrate temperature of 20 ° C. in an Ar atmosphere of 0.15 Pa in a sputtering apparatus in which the distance between the semiconductor substrate 110 and the target is set to 60 mm. As a result, a Ti film having a strong Ti (002) orientation can be obtained. Then, this Ti film is heat-treated at 650 ° C. for 60 seconds in a nitrogen atmosphere by the RTA method to obtain a (111) -oriented TiN film.

Next, for example, TiAlN is deposited to a film thickness of about 100 nm to form a conductive oxygen barrier film 123c.
Specifically, by reactive sputtering using an alloyed target of Ti and Al, in a mixed atmosphere of Ar at a flow rate of 40 sccm and nitrogen at a flow rate of 10 sccm, at a substrate temperature of 400 ° C. under a pressure of 253.3 Pa, TiAlN is formed to a thickness of 100 nm with a sputtering power of 1.0 kW.

Next, an Ir film is deposited to a thickness of, for example, about 100 nm by sputtering, and the lower electrode layer 124 is formed.
Specifically, an Ir film is formed in an Ar atmosphere at a substrate temperature of 500 ° C. under a pressure of 0.11 Pa and a sputtering power of 0.5 kW. As the lower electrode layer 124, a platinum group metal such as Pt or a conductive oxide such as PtO, IrO _x , SrRuO ₃ may be used instead of the Ir film. Moreover, it can also be set as the laminated film of said metal or a metal oxide.

Next, the first ferroelectric film 25a is formed on the entire surface of the lower electrode layer 124 by, eg, MOCVD. The first ferroelectric film 25a has an ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr, Ca, Na, K, and at least one selected from rare earth elements, B = Ti, Zr, Nb. , Ta, W, Mn, Fe, Co, Cr), and a ferroelectric material such as PZT, for example, is formed to a thickness of about 70 nm to 250 nm, here about 120 nm. In addition, although a plurality of A atoms exist in one unit of perovskite structure, they are not necessarily the same in each unit, and the same applies to the case of B atoms.

As a specific example of the MOCVD method, Pb (DPM) ₂ , Zr (dmhd) ₄ , and Ti (O—iOr) ₂ (DPM) ₂ are all dissolved in a THF solvent at a concentration of 0.3 mol / l. , Pb, Zr, and Ti liquid raw materials are formed. Furthermore, these liquid raw materials are supplied to the vaporizer of the MOCVD apparatus at a flow rate of 0.326 ml / min, 0.200 ml / min, and 0.200 ml / min together with THF solvent at a flow rate of 0.474 ml / min. By vaporizing, a source gas of Pb, Zr, and Ti is formed.

Further, the MOB apparatus is maintained at a substrate temperature of 620 ° C. under a pressure of 665 Pa (5 Torr), and the Pb, Zr, and Ti source gases formed in this manner act on the MOCVD apparatus for 620 seconds. Let As a result, a desired PZT film is formed on the lower electrode layer 124 to a thickness of about 100 nm, for example.
Note that the first ferroelectric film 25a may be formed by sputtering, for example, instead of the MOCVD method.

As the material of the first ferroelectric film 25a, PZT, PLZT, BLT, SBT, and Bi layered structure doped with at least one selected from La, Ca, Sr, and Si instead of PZT ( For example, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element: 0 <x <1), SrBi ₂ Ta ₂ O ₉ , and SrBi ₄ Ti ₄ O ₁₅ One kind selected from may be used. These dielectric materials have an ABO ₃ type perovskite structure as a unit.
In addition to the ferroelectric material, a high dielectric material such as an oxide Zr or Pb-based material may be deposited.

Next, an amorphous second ferroelectric film 125b is formed on the entire surface of the first ferroelectric film 125a by, eg, MOCVD. The second ferroelectric film 125b is selected from an ABO ₃ type perovskite structure (A = Bi, Pb, Ba, Sr, Ca, Na, K, and rare earth elements) containing Ir element in at least one of the A site and the B site. And at least one selected from the group consisting of B = Ti, Zr, Nb, Ta, W, Mn, Fe, Co, and Cr), for example, PZT. About 20 nm in this case. In addition, although a plurality of A atoms exist in one unit of perovskite structure, they are not necessarily the same in each unit, and the same applies to the case of B atoms.

As a specific example of the MOCVD method, as an organic source for supplying lead (Pb), Pb (DPM) ₂ (Pb (C ₁₁ H ₁₉ O ₂ ) ₂ ) is dissolved in THF (Tetra Hydro Furan: C ₄ H ₈ O). The material dissolved in is used. As an organic source for supplying zirconium (Zr), a material in which Zr (DMHD) ₄ (Zr ((C ₉ H ₁₅ O ₂ ) ₄ ) is dissolved in a THF solution is used.Organic for supplying titanium (Ti) As a source, a material in which Ti (O—iPr) ₂ (DPM) ₂ (Ti (C ₃ H ₇ O) ₂ (C ₁₁ H ₁₉ O ₂ ) ₂ ) is dissolved in a THF solution is used.Iridium (Ir) supply As an organic source, a material in which Ir (DMP) ₃ (Ir (C ₁₁ H ₁₉ O ₂ ) ₃ ) is dissolved in a THF solution is used.

If the film thickness of the ferroelectric film 125b is too large, the switching charge amount of the capacitor structure is likely to be reduced. The content of Ir element is preferably about 0.01 to 3.00%. When the content of Ir element increases, it is accumulated at the crystal grain boundary in the second ferroelectric film 125b by the subsequent heat treatment, and a leak path of the capacitor structure is formed. Here, it is desirable to form the second ferroelectric film 125b using a raw material containing about 1% of Ir.
Note that the second ferroelectric film 125b may be formed by sputtering, for example, instead of the MOCVD method.

As the material of the second ferroelectric film 125b to which Ir is added, PZT, PLZT, BLT, SBT doped with at least one selected from La, Ca, Sr, and Si instead of PZT, and Bi layered structure (for example, (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element: 0 <x <1), SrBi ₂ Ta ₂ O ₉ , and SrBi ₄ Ti ₄ O ₁₅ are selected. 1 type) may be used. These dielectric materials have an ABO ₃ type perovskite structure as a unit.

  Next, the second ferroelectric film 125b is heat-treated. Here, heat treatment is performed by an RTA (Rapid Thermal Annealing) method in an oxidizing atmosphere, here an atmosphere containing oxygen (a mixed atmosphere of an inert gas and oxygen). For example, the heat treatment temperature is 550 ° C. to 800 ° C., for example, 580 ° C., and the heat treatment time is 30 seconds to 120 seconds, here 60 seconds in an atmosphere of oxygen at a flow rate of 50 sccm and Ar at a flow rate of 2000 sccm. The appropriate heat treatment temperature varies depending on the type of ferroelectric material. For example, the heat treatment temperature of PZT or PZT added in a small amount is preferably 600 ° C. or lower, BLT is 700 ° C. or lower, and SBT is 800 ° C. or lower.

  By this heat treatment, the second ferroelectric film 125b is crystallized, and Ir in the second ferroelectric film 125b is bonded to the A site and B site of the crystal grains in the first ferroelectric film 125a. To do. Here, a ferroelectric film 125 serving as a capacitor film is formed by the first ferroelectric film 125a and the second ferroelectric film 125b.

Next, an IrO _x film (0 <x <2) 126a having a film thickness of, for example, about 10 nm to 100 nm, here about 50 nm is formed by, for example, sputtering or MOCVD. A Pt film may be formed instead of the IrO _x film.

Next, with the IrO _x film 126a formed, the second ferroelectric film 125b is heat treated,
Here, heat treatment is performed in a mixed atmosphere of an inert gas and oxygen by RTA (Rapid Thermal Annealing). For example, the heat treatment temperature is 725 ° C., and the heat treatment time is 60 seconds in an atmosphere of oxygen at a flow rate of 20 sccm and Ar at a flow rate of 2000 sccm.

By this heat treatment, the second ferroelectric film 125b is completely crystallized and the plasma damage of the IrO _x film 126a can be recovered, and oxygen vacancies in the second ferroelectric film 125b are compensated. .

Next, an IrO _y film (0 <y ≦ 2) 126b having a film thickness of about 100 nm to 300 nm is deposited on the IrO _x film 126a (in an Ar atmosphere at a pressure of 0.8 Pa and a sputtering power of 1.0 kW). When deposited for 79 seconds, it becomes 200 nm). At this time, the oxygen composition ratio Y of the IrO _y film 126b is set to be higher than the oxygen composition ratio X of the IrO _x film 126a in order to suppress deterioration of the capacitor structure due to the subsequent processes. By forming the IrO _y film 126b to have a composition close to the stoichiometric composition of IrO ₂ , there is no catalytic effect on hydrogen, and the problem that the ferroelectric film is reduced by hydrogen radicals is suppressed. The hydrogen resistance of the capacitor structure is improved. Instead of the IrO ^x film 126a and the IrO _y film 126b, a conductive oxide such as Ir, Ru, Rh, Re, Os, Pd, an oxide thereof, and SrRuO ₃ or a stacked structure thereof may be used. .

Next, an Ir film 126c that functions as a hydrogen barrier film is deposited on the IrO _y film 126b by sputtering, for example, in an Ar atmosphere to a thickness of 100 nm under a pressure of 1 Pa and a sputtering power of 1.0 kW. At this time, the upper electrode layer 126 formed by stacking the IrO _x film 126a, the IrO _y film 126b, and the Ir film 126c is formed. Instead of the Ir film 126c, a Pt film or a SrRuO3 film may be formed.

Subsequently, after the back surface of the semiconductor substrate 110 is cleaned, a TiN film 128 and a silicon oxide film 129 are formed as shown in FIG. 8A.
Specifically, the TiN film 128 is deposited on the upper electrode layer 126 to a thickness of about 200 nm by sputtering or the like. The silicon oxide film 129 is deposited on the TiN film 128 to a thickness of about 1000 nm by, for example, a CVD method using TEOS. Here, an HDP film may be formed instead of the TEOS film. A silicon nitride film may be further formed on the silicon oxide film 129.

Subsequently, as shown in FIG. 8B, a resist mask 101 is formed.
Specifically, a resist is applied on the silicon oxide film 129, and this resist is processed into an electrode shape by lithography to form a resist mask 101.

Subsequently, as shown in FIG. 8C, the silicon oxide film 129 is processed.
Specifically, the silicon oxide film 129 is dry etched using the resist mask 101 as a mask. At this time, the silicon oxide film 129 is patterned following the electrode shape of the resist mask 101 to form a hard mask 129a. Further, the resist mask 101 is etched to reduce the thickness.

Subsequently, as shown in FIG. 8D, the TiN film 128 is processed.
Specifically, the TiN film 128 is dry etched using the resist mask 101 and the hard mask 129a as a mask. At this time, the TiN film 128 is patterned according to the electrode shape of the hard mask 129a to form the hard mask 128a. Further, the resist mask 101 is thinned by being etched during the etching. Thereafter, the resist mask 101 is removed by ashing or the like.

Subsequently, as shown in FIG. 9A, the upper electrode layer 126, the capacitor film 125, the lower electrode layer 124, the oxygen barrier film 123c, and the orientation improving film 123b are processed.
Specifically, the upper electrode layer 126, the capacitor film 125, the lower electrode layer 124, the oxygen barrier film 123c, and the orientation enhancement film 123b are dry-etched using the hard masks 128a and 129a as a mask and the upper insulating film 123 as an etching stopper. To do. At this time, the upper electrode layer 126, the capacitor film 125, the lower electrode layer 124, the oxygen barrier film 123c, and the orientation improving film 123b are patterned following the electrode shape of the hard mask 128a. Further, the hard mask 129a is thinned by being etched during the etching. Thereafter, the hard mask 129a is removed by dry etching (etchback) on the entire surface.

Subsequently, as shown in FIG. 9B, the ferroelectric capacitor structure 130 is completed.
Specifically, the hard mask 128a used as a mask is removed by wet etching. At this time, the capacitor film 125 and the upper electrode 132 are sequentially stacked on the lower electrode 131, and the ferroelectric capacitor structure 130 in which the lower electrode 131 and the upper electrode 132 are capacitively coupled through the capacitor film 125 is completed. In the ferroelectric capacitor structure 130, the lower electrode 131 is connected to the plug 119 through the conductive orientation improving film 123b and the oxygen barrier film 123c, and the plug 119, the orientation improving film 123b, and the oxygen barrier film are connected. The source / drain 118 and the lower electrode 131 are electrically connected through 123c.

In the ferroelectric capacitor structure 130 according to the present embodiment, the ferroelectric film 125 contains iridium therein, and has an iridium concentration distribution in which the iridium concentration decreases from the upper layer region toward the lower layer region. .
Specifically, as shown in FIG. 12, the upper layer region of the ferroelectric film 125, that is, the portion of the second ferroelectric film 125b has a uniform high iridium concentration, and the lower layer region of the ferroelectric film 125, That is, an iridium concentration distribution is formed in which the iridium concentration decreases as the portion of the first ferroelectric film 125a moves downward.

Subsequently, as shown in FIG. 9C, a protective film 133 and an interlayer insulating film 134 are formed.
Specifically, first, the protective film 1 is deposited to a thickness of about 20 nm to 50 nm by sputtering using alumina (Al ₂ O ₃ ) as a material so as to cover the entire surface of the ferroelectric capacitor structure 130.
33 is formed. Thereafter, the protective film 133 is annealed.

Next, an interlayer insulating film 234 is formed so as to cover the ferroelectric capacitor structure 130 via the protective film 133. Here, the interlayer insulating film 134 is formed by depositing a silicon oxide film to a film thickness of about 1500 nm to 2500 nm by a plasma CVD method using TEOS, for example, and then polishing the film to a film thickness of about 1000 nm by CMP. To do. For example, N ₂ O plasma annealing is performed after CMP for the purpose of dehydrating the interlayer insulating film 134.

Subsequently, as shown in FIG. 10A, a via hole 135a to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.
Specifically, the interlayer insulating film 134 and the protective film 133 are patterned by lithography and subsequent dry etching to form a via hole 135a that exposes a part of the surface of the upper electrode 132.

Subsequently, as shown in FIG. 10B, a plug 135 connected to the upper electrode 132 of the ferroelectric capacitor structure 130 is formed.
Specifically, first, a base film (glue film) 135b is formed so as to cover the wall surface of the via hole 135a, and then a W film is formed by the CVD method so as to fill the via hole 135a via the glue film 135b. Then, for example, the W film and the glue film 135b are polished by CMP using the interlayer insulating film 134 as a stopper, thereby forming a plug 135 filling the via hole 135a with W via the glue film 135b. After the CMP, for example, a plasma annealing process of N ₂ O is performed.

Subsequently, as shown in FIG. 11A, first wirings 145 respectively connected to the plugs 135 are formed.
Specifically, first, the barrier metal film 142, the wiring film 143, and the barrier metal film 144 are deposited on the entire surface of the interlayer insulating film 134 by sputtering or the like. As the barrier metal film 142, for example, a Ti film and a TiN film having a thickness of about 5 nm and a thickness of about 150 nm are formed by sputtering. As the wiring film 143, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 144, for example, a Ti film is deposited to a thickness of about 5 nm and a TiN film is deposited to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 143 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing or reliability of the wiring.

  Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 144, the wiring film 143, and the barrier metal film 142 are wired by lithography and subsequent dry etching. The first wiring 145 connected to the plug 135 is patterned by processing into a shape. Instead of forming an Al alloy film as the wiring film 143, a Cu film (or Cu alloy film) may be formed by using a so-called damascene method or the like, and a Cu wiring may be formed as the first wiring 145.

Subsequently, as illustrated in FIG. 11B, a second wiring 154 connected to the first wiring 145 is formed.
Specifically, first, an interlayer insulating film 146 is formed so as to cover the first wiring 145. As the interlayer insulating film 146, a silicon oxide film is formed to a thickness of about 700 nm, a plasma TEOS film is formed to a total thickness of about 1100 nm, and then the surface is polished by CMP to a thickness of 750 nm. Form to the extent.

Next, a plug 147 connected to the first wiring 145 is formed.
The interlayer insulating film 146 is processed by lithography and subsequent dry etching until a part of the surface of the first wiring 145 is exposed to form a via hole 147a having a diameter of about 0.25 μm, for example. Next, after forming a base film (glue film) 148 so as to cover the wall surface of the via hole 147a, a W film is formed by the CVD method so as to fill the via hole 147a via the glue film 148. Then, for example, the W film and the glue film 148 are polished using the interlayer insulating film 146 as a stopper to form a plug 147 that fills the via hole 147a with W via the glue film 148.

Next, second wirings 154 connected to the plugs 147 are formed.
First, a barrier metal film 151, a wiring film 152, and a barrier metal film 153 are deposited on the entire surface by sputtering or the like. As the barrier metal film 151, for example, a Ti film and a TiN film are stacked to form a film having a thickness of about 5 nm and a thickness of about 150 nm by sputtering. As the wiring film 152, for example, an Al alloy film (here, an Al—Cu film) is formed to a thickness of about 350 nm. As the barrier metal film 153, for example, a Ti film is deposited to a thickness of about 5 nm and a TiN film is deposited to a thickness of about 150 nm by sputtering. Here, since the structure of the wiring film 152 is the same as that of the logic part other than the FeRAM having the same rule, there is no problem in processing or reliability of the wiring.

  Next, after forming, for example, a SiON film or an antireflection film (not shown) as an antireflection film, the antireflection film, the barrier metal film 153, the wiring film 152, and the barrier metal film 151 are wired by lithography and subsequent dry etching. The second wiring 154 is patterned by processing into a shape. Instead of forming an Al alloy film as the wiring film 152, a Cu film (or Cu alloy film) may be formed using a so-called damascene method or the like, and a Cu wiring may be formed as the second wiring 154.

  Thereafter, the stack type FeRAM according to the present embodiment is completed through various processes such as formation of an interlayer insulating film and a further upper layer wiring.

  As described above, according to the present embodiment, it is possible to improve the inversion electrification amount of the ferroelectric capacitor structure 130, but it is possible to ensure a high yield without increasing the leakage current. A high stack type FeRAM can be realized.

(Third embodiment)
In this embodiment, other examples applicable to the first embodiment will be described. Here, the description is based on the first embodiment, but the present invention can be similarly applied to the second embodiment. In addition, in each figure of FIG. 13A-FIG. 13C and FIG. 14A-FIG. 14C, only the structure corresponded to FIG. 1D is shown.

[Example 1]
FIG. 13A is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of the first embodiment.
In this example, first, in the first embodiment, the first ferroelectric film is formed on the lower electrode layer 24 by a sputtering method at a low temperature, for example, 10 ° C. to 100 ° C., here, 50 ° C. The first ferroelectric film 61 is formed. The film thickness and the like are the same as those of the first ferroelectric film 25a.

Subsequently, as in the first embodiment, the second ferroelectric film 25b is formed by sputtering using a target to which Ir is added.
Thereafter, the first ferroelectric film 61 and the second ferroelectric film 25b are crystallized by the RTA method. When the first ferroelectric film 61 and the second ferroelectric film 25b are PZT films, when the total thickness of the PZT films is about 150 nm, the flow rate is 2 slm at 560 ° C. to 580 ° C. And a heat treatment for 90 seconds in an O ₂ mixed atmosphere with a flow rate of 25 sccm. In addition to this heat treatment, it is desirable to perform a heat treatment for 60 seconds in an oxygen atmosphere at 700 ° C. to 750 ° C.

By this heat treatment, the first ferroelectric film 61 and the second ferroelectric film 25 b are completely crystallized, and Ir in the second ferroelectric film 25 b is changed into the first ferroelectric film 61. It binds to the A site and B site of the crystal grains. Here, the ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 61 and the second ferroelectric film 25b.
Thereafter, the upper electrode layer 26 is formed and patterned in the same manner as in the first embodiment, whereby the ferroelectric capacitor structure 30 is formed.

[Example 2]
FIG. 13B is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of the second embodiment.
In this example, first, as in the first embodiment, an amorphous first ferroelectric film 61 is formed on the lower electrode layer 24 as a first ferroelectric film. The film thickness and the like are the same as those of the first ferroelectric film 25a. Thereafter, the first ferroelectric film 61 is crystallized by the RTA method. When the first ferroelectric film 61 is a PZT film, heat treatment is performed for 90 seconds in a mixed atmosphere of Ar at a flow rate of 2 slm and O ₂ at a flow rate of 25 sccm at 560 ° C. to 580 ° C.

Subsequently, as in the first embodiment, the second ferroelectric film 25b is formed by sputtering using a target to which Ir is added.
Thereafter, the first ferroelectric film 61 and the second ferroelectric film 25b are crystallized by the RTA method. When the first ferroelectric film 61 and the second ferroelectric film 25b are PZT films, when the total thickness of the PZT films is about 150 nm, the flow rate is 2 slm at 560 ° C. to 580 ° C. And a heat treatment for 90 seconds in an O ₂ mixed atmosphere with a flow rate of 25 sccm. In addition to this heat treatment, it is desirable to perform a heat treatment for 60 seconds in an oxygen atmosphere at 700 ° C. to 750 ° C.

By this heat treatment, the second ferroelectric film 25b is completely crystallized, and Ir in the second ferroelectric film 25b is converted to an A site or a B site of crystal grains in the first ferroelectric film 61. To join. Here, the ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 61 and the second ferroelectric film 25b.
Thereafter, the upper electrode layer 26 is formed and patterned in the same manner as in the first embodiment, whereby the ferroelectric capacitor structure 30 is formed.

  Here, it was confirmed that Ir was doped in the crystal lattice of PZT by using the anomalous dispersion method. Anomalous dispersion is a phenomenon in which the refractive index and scattering power change greatly due to the resonance effect in a state where the frequency of X-rays is close to the frequency of the absorption edge of atoms. That is, when the X-ray diffraction intensity of a certain substance is measured, if the substance is irradiated with energy close to the absorption edge of the constituent element of the substance, the X-ray diffraction intensity changes greatly. By utilizing this phenomenon and examining the energy dependence of the diffraction intensity of a specific peak, the constituent elements of that peak can be clarified.

  In order to investigate the doping of Ir into the PZT film, the energy near the LIII absorption edge of Ir was used. Note that LIII is an electron orbit in an Ir atom.

FIG. 15 shows the result of examining the dependency of the PZT (111) orientation intensity on the X-ray incident energy after annealing PZT deposited on the lower electrode layer made of Pt.
The wavelength near the LIII absorption edge of Ir was used as the X-ray. When the Ir LIII absorption edge energy is 11.21 eV, the decrease in strength is large. This clearly shows that Ir is contained in the crystal lattice of Ir-doped PZT, and Ir-doped PZT is not simply diffused into the PZT film. , Ir is contained as a crystal constituent element of PZT. That is, the PZT has a crystal structure containing an Ir element at at least one of the A site and the B site of the ABO ₃ type perovskite structure.

[Example 3]
FIG. 13C is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of the third embodiment.
In this example, first, as in the first embodiment, an amorphous first ferroelectric film 61 is formed on the lower electrode layer 24 as a first ferroelectric film. The film thickness and the like are the same as those of the first ferroelectric film 25a. Thereafter, the first ferroelectric film 61 is crystallized by the RTA method. When the first ferroelectric film 61 is a PZT film, heat treatment is performed for 90 seconds in a mixed atmosphere of Ar at a flow rate of 2 slm and O ₂ at a flow rate of 25 sccm at 560 ° C. to 580 ° C.

Subsequently, as in the first embodiment, the second ferroelectric film 25b is formed by sputtering using a target to which Ir is added.
Subsequently, as in the first embodiment, an IrO _x film (0 <x <2) 26a having a thickness of about 50 nm is formed. A Pt film may be formed instead of the IrO _x film.

  Thereafter, the second ferroelectric film 25b is crystallized by the RTA method. When the second ferroelectric film 25b is a PZT film, the heat treatment temperature is 725 ° C., and the heat treatment time is 60 seconds in a mixed atmosphere of oxygen at a flow rate of 20 sccm and Ar at a flow rate of 2000 sccm.

By this heat treatment, the second ferroelectric film 25b is completely crystallized, and Ir in the second ferroelectric film 25b is converted to an A site or a B site of crystal grains in the first ferroelectric film 61. To join. Further, the plasma damage of the IrO _x film 26a can be recovered, and oxygen vacancies in the second ferroelectric film 25b are compensated. Here, the ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 61 and the second ferroelectric film 25b.
Thereafter, the IrO _y film 26b is formed and patterned in the same manner as in the first embodiment, thereby forming the ferroelectric capacitor structure 30.

[Example 4]
FIG. 14A is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of the fourth embodiment.
In this example, first, as in the first embodiment, a first ferroelectric film 25a is formed on the lower electrode layer 24 as a first ferroelectric film.

Subsequently, as in the first embodiment, the second ferroelectric film 25b is formed by sputtering using a target to which Ir is added.
Subsequently, as in the first embodiment, an IrO _x film (0 <x <2) 26a having a thickness of about 50 nm is formed. A Pt film may be formed instead of the IrO _x film.

  Thereafter, the second ferroelectric film 25b is crystallized by the RTA method. When the second ferroelectric film 25b is a PZT film, the heat treatment temperature is 725 ° C., and the heat treatment time is 60 seconds in an atmosphere of oxygen at a flow rate of 20 sccm and Ar at a flow rate of 2000 sccm.

By this heat treatment, the second ferroelectric film 25b is completely crystallized, and Ir in the second ferroelectric film 25b is converted into an A site or a B site of crystal grains in the first ferroelectric film 25a. To join. Further, the plasma damage of the IrO _x film 26a can be recovered, and oxygen vacancies in the second ferroelectric film 25b are compensated. Here, a ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 25a and the second ferroelectric film 25b.
Thereafter, the IrO _y film 26b is formed and patterned in the same manner as in the first embodiment, thereby forming the ferroelectric capacitor structure 30.

[Example 5]
FIG. 14B is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of the fifth embodiment.
In this example, first, the first ferroelectric film 61 in an amorphous state is formed on the lower electrode layer 24 as in the first embodiment. The film thickness and the like are the same as those of the first ferroelectric film 25a. Note that the first ferroelectric film 25a may be formed as in the first embodiment.

Subsequently, as in the first embodiment, the second ferroelectric film 25b is formed by sputtering using a target to which Ir is added.
Thereafter, the first ferroelectric film 61 and the second ferroelectric film 25b are crystallized by the RTA method. When the first ferroelectric film 61 and the second ferroelectric film 25b are PZT films, when the total thickness of the PZT films is about 150 nm, the flow rate is 2 slm at 560 ° C. to 580 ° C. And a heat treatment for 90 seconds in an O ₂ mixed atmosphere with a flow rate of 25 sccm.

  By this heat treatment, the first ferroelectric film 61 and the second ferroelectric film 25 b are completely crystallized, and Ir in the second ferroelectric film 25 b is changed into the first ferroelectric film 61. It binds to the A site and B site of the crystal grains. Here, the ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 61 and the second ferroelectric film 25b.

Subsequently, as in the first embodiment, an IrO _x film (0 <x <2) 26a having a thickness of about 50 nm is formed. A Pt film may be formed instead of the IrO _x film.

  Thereafter, the RTA method is performed. When the second ferroelectric film 25b is a PZT film, the heat treatment temperature is 725 ° C., and the heat treatment time is 120 seconds in an atmosphere of oxygen at a flow rate of 20 sccm and Ar at a flow rate of 2000 sccm.

By this heat treatment, the second ferroelectric film 25b is completely crystallized, and Ir in the second ferroelectric film 25b is converted to an A site or a B site of crystal grains in the first ferroelectric film 61. To join. Further, the plasma damage of the IrO _x film 26a can be recovered, and oxygen vacancies in the second ferroelectric film 25b are compensated. Here, the ferroelectric film 25 serving as a capacitor film is formed by the first ferroelectric film 61 and the second ferroelectric film 25b.
Thereafter, the IrO _y film 26b is formed and patterned in the same manner as in the first embodiment, thereby forming the ferroelectric capacitor structure 30.

[Example 6]
FIG. 14C is a schematic cross-sectional view showing only the configuration corresponding to FIG. 1D as the main configuration of the sixth embodiment.
In this example, first, a ferroelectric film serving as a capacitor film is formed on the lower electrode layer 24 by sputtering at a low temperature, for example, 20 ° C. to 100 ° C., here 50 ° C., and the amorphous ferroelectric film 62 is formed. Is formed to a thickness of about 140 nm.

Subsequently, heat treatment is performed by the RTA method. The temperature of this heat treatment is controlled so that the ferroelectric film 62 is completely crystallized in the portion on the lower electrode layer 24 (the lower layer portion of the ferroelectric film 62) so that the surface layer becomes amorphous. At this time, the film thickness of the ferroelectric film 62 affects the crystal state.

  In general, the crystallization of the ferroelectric film proceeds from the portion on the lower electrode. When the heat treatment temperature is high, the crystallization speed is increased. FIGS. 17A and 17B are cross-sectional photographs showing a state after a PZT film having a thickness of 140 nm formed on the lower electrode layer made of Pt is subjected to heat treatment at 553 ° C. and 573 ° C. for 90 seconds by the RTA method. is there. When the annealing temperature is low, the grain boundaries of the columnar crystals are not visible near the surface, and it seems that they are not crystals. On the other hand, when the annealing temperature is high, the grain boundaries of the columnar crystals appear to be clear (in the case of a 120 nm-thick PZT film, if a heat treatment is performed at 568 ° C. for 90 seconds, the grain boundaries of the columnar crystals are near the surface. Can be seen.)

Subsequently, an IrO _x film (0 <x <2) 26c having a film thickness of about 20 nm to 80 nm, here, about 50 nm is formed on the ferroelectric film 62 by, for example, sputtering or MOCVD. Here, in order to control the value of x of the IrO _x film 26c, the power applied to the semiconductor substrate 10 is set to 2.0 kW in an atmosphere of oxygen having a flow rate of 50 to 58 sccm and Ar having a flow rate of 100 sccm. The value of x of the formed IrO _x film 26c is, for example, about 1.4.

  Subsequently, heat treatment is performed by the RTA method. Specifically, the heat treatment time is 120 seconds in a treatment temperature of 725 ° C. and an oxidizing atmosphere, here an atmosphere containing oxygen (mixed atmosphere of oxygen at a flow rate of 20 sccm and Ar at a flow rate of 2000 sccm).

By this heat treatment, the ferroelectric film 62 is completely crystallized, and Ir in the IrO _x film 26 c is diffused into the ferroelectric film 62. Further, the plasma damage of the IrO _x film 26c is recovered, and oxygen vacancies in the ferroelectric film 62 are compensated. In addition, the interface between the ferroelectric film 62 and the IrO _x film 26c becomes flat (very advantageous for low voltage operation).
Thereafter, the IrO _y film 26b is formed and patterned in the same manner as in the first embodiment, thereby forming the ferroelectric capacitor structure 30.

  In the ferroelectric capacitor structure 30 according to this example, as shown in FIG. 16, the ferroelectric film 62 contains iridium inside, and has an iridium concentration distribution in which the iridium concentration decreases from the upper surface toward the lower surface. Have.

Hereinafter, a structure including a Pt layer serving as a lower electrode, an amorphous PZT film serving as a capacitor film, and an IrO _x film serving as a part of the upper electrode (x = 1.4: hereinafter referred to as an IrO _1.4 film) is used. The mechanism of the present invention will be described.

  The Pt lower electrode layer is oriented in the (111) plane. On top of this, an amorphous PZT film is deposited to 150 nm. Thereafter, heat treatment is performed by an RTA method in an atmosphere of oxygen at a flow rate of 25 sccm and Ar at a flow rate of 2000 sccm for 90 seconds.

FIG. 18A, FIG. 18B, and FIG. 18C show the influence on the cross-sectional view of the capacitor due to the temperature of each heat treatment.
Crystal growth of the PZT film grows from between (111) crystal grains of the Pt lower electrode layer. When the temperature of the heat treatment is low, the crystal growth of the PZT film has a large variation, and the size of the columnar PZT crystal particles is also very large. The surface of the PZT film is amorphous.

Thereafter, an IrO _1.4 film is formed, and further heat treatment is performed by an RTA method in an atmosphere of 725 ° C., oxygen at a flow rate of 20 sccm, and Ar at a flow rate of 2000 sccm for 20 seconds. At this time, since the IrO _1.4 film is an unsaturated film, Ir in the IrO _1.4 film diffuses into the PZT film, and Pb in the PZT film diffuses into the IrO _1.4 film. At this time, since the crystal grains in the PZT film vary widely, Ir is doped into the crystal grains (A site and B site) of the PZT film, and Ir is also present in the gaps between the crystal grains of the PZT film. It will remain. It can be determined that these Irs form a capacitor leak path. However, the interface layer (paraelectric layer) between the PZT film and the IrO _1.4 film becomes thin due to the influence of mutual diffusion between Pb and Ir. That is, it is advantageous for low voltage operation of the capacitor structure.

On the other hand, if the heat treatment temperature after the formation of the PZT film is appropriate, the crystal grains of the PZT film are substantially uniform and the surface layer of the PZT film is in an amorphous state. Thereafter, when the IrO _1.4 film is formed and heat-treated, the diffusion of Pb and Ir can be controlled, and the interface layer between the PZT film and the IrO _1.4 film can also be thinned. At the same time, since the crystal grains of the PZT film are almost uniform, Ir hardly accumulates at the crystal grain boundary of the PZT film, and the leakage current of the capacitor structure is also reduced.

Further, when the heat treatment after the PZT film formation is increased, the crystal growth of PZT becomes faster, and some variation occurs in the crystal growth. At this time, the surface layer of the PZT film is not in an amorphous state, and the PZT film is completely crystallized. Thereafter, when an IrO _1.4 film is formed and heat-treated, mutual diffusion of Pb and Ir occurs. However, since the PZT film is crystallized, Ir hardly diffuses into the crystal grains of the PZT film, and Ir accumulates between the crystal grains and between the PZT film and the IrO _1.4 film. The interface layer between the PZT film and the IrO _1.4 film is also thickened.

  In each of the above embodiments, the invention has been devised based on the above basic idea. That is, by doping a small amount of Ir in the ferroelectric film, the defects in the ferroelectric film are compensated, the crystallinity of the ferroelectric film becomes uniform, and the inter-grain size of the ferroelectric film becomes uniform. In this method, the interface layer between the ferroelectric film and the upper electrode can be thinned without causing Ir to accumulate.

Here, the following experiment is performed by the method of Example 6.
The lower electrode of the capacitor structure is Pt (film thickness 150 nm, 350 ° C., film formation with 0.3 kW film formation power). As the ferroelectric film, an amorphous CSPLZT film having a thickness of 150 nm is formed on the lower electrode by RF sputtering using a PZT target to which a small amount of Ca, Sr, and La is added. This amorphous CSPLZT film is heat-treated by the RTA method. The heat treatment time is 90 seconds in a mixed atmosphere of oxygen at a flow rate of 25 sccm and Ar at a flow rate of 2000 sccm. The heat treatment temperature was investigated from 533 ° C to 588 ° C. The IrO _1.4 film is formed for 8 seconds at a power applied to the semiconductor substrate of 2.0 kW and a substrate temperature of 20 ° C. in a mixed atmosphere of oxygen at a flow rate of 50 to 58 sccm and Ar at a flow rate of 100 sccm. Thereby, an IrO _1.4 film having a thickness of about 47 nm is formed. Thereafter, heat treatment is performed for 20 seconds in a mixed atmosphere of 725 ° C., oxygen at a flow rate of 20 sccm, and Ar at a flow rate of 2000 sccm by the RTA method.

The results of measuring the crystallinity of the CSPLZT film heat-treated as described above are shown in FIGS. 19A, 19B, 20A, and 20B.
As shown in the figure, the (101) plane of the CSPLZT film under each condition is hardly oriented (influence of the background level). When the heat treatment temperature is low, the orientation of the (100) plane is strong, and when the heat treatment temperature is high, the orientation strength of the (222) plane is strong. On the other hand, when the heat treatment temperature is low, the orientation rate (= (222) / [(222) + (100) + (101)]) of the (222) plane of the CSPLZT film is low. When the heat treatment temperature is 548 ° C. or higher, the orientation ratio of the (222) plane is almost saturated. From the above results, it can be seen that the crystallinity of the CSPLZT film almost depends on the heat treatment conditions after the ferroelectric film is formed. That is, when the heat treatment temperature is lowered, the crystallinity of the CSPLZT film is poor and the size of the crystal particles varies. When the heat treatment temperature is 548 ° C. or higher, the crystal grain size of the CSPLZT film becomes substantially uniform.

  On the other hand, the crystallinity of the CSPLZT film depends on the film thickness and the heat treatment temperature. FIG. 21A and FIG. 21B show the influence of the heat treatment temperature when the CSPLZT film thickness is 120 nm on the crystallinity of the CSPLZT film. When the heat treatment temperature is low, the orientation strength of the (100) plane increases and the orientation ratio of the (222) plane decreases. When the temperature is about 543 ° C. or higher, the orientation rate is almost saturated. From this result, the optimum heat treatment temperature of the ferroelectric film decreases as the film thickness decreases. That is, when the surface layer of the ferroelectric film is in an amorphous state, the heat treatment conditions for aligning the size and orientation of the ferroelectric crystal grains also depend on the thickness of the PZT.

A ferroelectric capacitor structure using a CSPLZT film as a capacitor film, an IrO _1.4 film, and an IrO ₂ film (thickness of about 200 nm) as an upper electrode is formed, and wiring is formed up to three layers, and one transistor-one capacitor (1T1C) Complete the FeRAM. Next, the monitoring characteristics and PT yield of the completed 1T1C FeRAM were investigated.

  First, the planar shape is a square ferroelectric capacitor (discrete) having a side length of 50 μm, and the planar shape is a long side length of 1.50 μm and a short side length of 1.15 μm. 1,428 rectangular ferroelectric capacitors (cell capacitors) were formed, and the inversion charge amount QSW was measured.

The results of measuring the inversion charge amount QSW with the applied voltage being 3.0 V are shown in FIGS. 22A and 22B.
This result is an average value at 56 points in the substrate plane. As shown in the figure, when the heat treatment temperature of the CSPLZT film is 538 ° C. or lower, the QSW of the discrete is lowered. It is almost the maximum value from 543 to 558 ° C., and further when the heat treatment temperature becomes higher, the QSW becomes lower. The same trend is seen in cell capacitors.

On the other hand, the dependence of the applied voltage on the cell capacitor is shown in FIG.
For this Vc, the applied voltage having the largest rate of change of the value P relative to the change of the applied voltage was taken as the coercive voltage Vc. Note that ◆ indicates the coercive voltage Vc (−) when the rate of change is negative, and ▲ indicates the coercive voltage Vc (+) when the rate of change is positive. When Vc was low, a high inversion charge amount QSW was obtained from a low voltage to a saturation voltage, and the gradient increased. This means that it is extremely suitable for a ferroelectric memory operating at a low voltage.

  As shown in FIGS. 23A and 23B, the cell capacitors at 543 ° C. and 558 ° C. rise quickly to a low voltage, the saturation QSW increases, and Vc decreases. When the heat treatment temperature is increased, the rise to the low voltage is delayed, the saturation QSW is decreased, and Vc is increased.

When the heat treatment temperature is 560 ° C. or lower, the surface of the CSPLZT film is amorphous, and after the IrO _1.4 film is formed, if heat treatment is performed, Ir diffuses into the CSPLZT film, and the CSPLZT film and the IrO _1.4 film The interface is flat and a thin interface layer is produced. On the other hand, when the heat treatment temperature is 563 ° C. or higher, the surface layer of the CSPLZT film is crystallized. At higher temperatures, the CSPLZT film crystallizes more completely. In this case, in the heat treatment after the formation of the IrO _1.4 film, Ir diffuses into the CSPLZT film, but hardly enters the crystal grains of the CSPLZT film and hits the crystal grain boundary. Moreover, the interface layer between the CSPLZT film and the IrO _1.4 film is also thickened. In this situation, the polarization inversion charge amount is reduced and the coercive voltage is also increased.

Next, the leakage current of the above ferroelectric capacitor structure (discrete and cell array) was measured. The results are shown in FIGS. 24A and 24B.
The applied voltage corresponds to the potential of the lower electrode with respect to the upper electrode, and was set to ± 5V. L-CAPF is a discrete leak current, and L-CAP is a cell array leak current. L-CAPF-2 is a leakage current of discretely applied voltage + 5V. As shown in the figure, when the heat treatment temperature of PZT becomes 543 ° C. or less, each leakage current increases rapidly. The leakage current between 548-558 ° C. is the lowest. Furthermore, the result that the leakage current increases as the heat treatment temperature increases was obtained. This phenomenon can be explained as follows.

  When the heat treatment temperature is low, the crystal grain size of PZT varies widely, and there are many grain boundary defects. Therefore, when Ir diffuses into PZT, these vacancies are filled first. The filled vacant Ir forms a leakage path of the capacitor structure, and the leakage current of the capacitor structure also increases rapidly. When the heat treatment temperature is appropriate, there are few defects in the crystal grain boundaries of the CSPLZT film, and Ir diffuses into the crystal grains, so that no capacitor leak path is formed. When the heat treatment temperature is increased, PZT crystal grains are completely formed, and Ir hardly enters the crystal grains, so that they accumulate in the crystal grain boundaries as they are, and a leak path is formed.

25A and 25B are characteristic diagrams showing measurement results of yield in a ferroelectric capacitor structure (1T1C type cell array).
In the measurement of yield, the operating voltage was 3V. PT1 indicates the yield when reading is performed after writing. PT2 indicates the yield when heat treatment at 250 ° C. is performed before reading. PT3 indicates the yield when data is inverted after heat treatment with respect to PT2. PT indicates the total yield of PT1, PT2, and PT3. The PT ratio is PT / PT1.

  As shown in the figure, the heat treatment temperature of PZT (CSPLZT) greatly affects the device yield. When the heat treatment temperature of PZT is low, the leakage current of the capacitor is large, so that a high voltage cannot be applied to the capacitor structure, and the yield of PT1 becomes very low. On the other hand, when the heat treatment temperature of PZT becomes high, the capacitor structure becomes difficult to operate at a low voltage, it becomes easy to retain (SS: Same State failure) and imprint (OS: Opposite State failure), and PT becomes low. Similarly, the PT ratio is lowered. FIG. 26 shows the result of RET failure (SS & OS) in PT yield.

From the above results, it is desirable that the heat treatment temperature of the PZT (CSPLZT) film be 543 ° C. to 573 ° C. The optimum temperature is 553 ° C. Further, in the heat treatment at 548 ° C. to 558 ° C., a device yield of 90% and a yield rate of 98% or more can be obtained.
On the other hand, when the film thickness of PZT is 120 nm, the optimum heat treatment temperature is considered to be 543 ° C to 553 ° C.

Claims (2)

A method of manufacturing a semiconductor device having a capacitor structure in which a capacitor film made of a dielectric material is sandwiched between a lower electrode and an upper electrode above a semiconductor substrate,
In forming the capacitor structure,
Forming a lower electrode layer;
Forming a dielectric film containing amorphous PZT on the lower electrode layer to a thickness in the range of 120 nm to 150 nm ;
A step of subjecting the dielectric film to a first heat treatment by an RTA method in an oxidizing atmosphere at a temperature within a range of 548 ° C. to 553 ° C., crystallizing a lower layer portion of the dielectric film, and maintaining an upper layer portion in an amorphous state When,
Forming an upper electrode layer containing iridium on the dielectric film;
Applying a second heat treatment to the upper electrode layer in an oxidizing atmosphere to diffuse iridium in the upper electrode layer into the dielectric film;
Processing the upper electrode layer, the dielectric film, and the lower electrode layer to form the capacitor structure, respectively. The upper electrode layer has a multi-layer structure,
On the dielectric film, a lowermost layer of the upper electrode layer is formed with a composition of IrO _x (0 <x <2),
After performing the second heat treatment on the lowermost layer and diffusing iridium in the lowermost layer into the dielectric film,
Wherein the remaining layers of the upper electrode layer is formed on the lowermost layer, a method of manufacturing a semiconductor device according to claim 1, characterized in that to complete the upper electrode layer.

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