JP2003110241A - Wiring board and electronic device using the same - Google Patents
Wiring board and electronic device using the sameInfo
- Publication number
- JP2003110241A JP2003110241A JP2001300759A JP2001300759A JP2003110241A JP 2003110241 A JP2003110241 A JP 2003110241A JP 2001300759 A JP2001300759 A JP 2001300759A JP 2001300759 A JP2001300759 A JP 2001300759A JP 2003110241 A JP2003110241 A JP 2003110241A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- layer
- wiring board
- wiring
- thickness
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
Abstract
(57)【要約】
【課題】 貫通孔を銅導体で良好に充填でき、貫通導体
表面の平滑性に優れ、電子部品が確実に強固に接続でき
る配線基板および電子装置を提供する。
【解決手段】 複数の絶縁層1および配線導体2が交互
に積層されるとともに上下の配線導体2間を絶縁層1に
形成された貫通孔3を電解めっき法による銅導体で充填
して成る貫通導体4により電気的に接続して成る配線基
板5において、銅導体は、電流密度が0.3〜0.8A/dm
2の電解めっきによる2/3〜3/4の厚みを占める第
1層4aと、電流密度が1.0〜3.0A/dm2の電解めっ
きによる残りの厚みを占める第2層4bとから成るとと
もに、第2層4bの表面の結晶粒径が0.1〜2μmであ
る。
(57) [Problem] To provide a wiring board and an electronic device capable of filling a through hole with a copper conductor satisfactorily, having excellent smoothness on the surface of the through conductor, and securely and firmly connecting electronic components. SOLUTION: A plurality of insulating layers 1 and wiring conductors 2 are alternately laminated, and a through hole formed between upper and lower wiring conductors 2 by filling a through hole 3 formed in the insulating layer 1 with a copper conductor formed by electrolytic plating. In the wiring board 5 electrically connected by the conductor 4, the copper conductor has a current density of 0.3 to 0.8 A / dm.
A first layer 4a occupying a thickness of 2/3 to 3/4 by electrolytic plating 2 and a second layer 4b occupying the remaining thickness by electrolytic plating having a current density of 1.0 to 3.0 A / dm 2 ; The crystal grain size on the surface of the second layer 4b is 0.1 to 2 μm.
Description
【0001】[0001]
【発明の属する技術分野】本発明は、半導体集積回路素
子などの電子部品を収容するための電子部品収納用配線
基板およびこれを用いた電子装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for accommodating electronic parts such as semiconductor integrated circuit elements and an electronic device using the same.
【0002】[0002]
【従来の技術】一般に、現在の電子機器は、移動体通信
機器に代表されるように小型・薄型・軽量・高性能・高
機能・高品質・高信頼性が要求されてきており、このよ
うな電子機器に搭載される電子装置も小型・高密度化が
要求されるようになってきている。そのため、電子装置
を構成する配線基板にも小型・薄型・多端子化が求めら
れてきており、それを実現するために信号導体等の配線
導体の幅を細くするとともにその間隔を狭くし、さらに
配線導体の多層化により高密度配線化が図られている。2. Description of the Related Art Generally, current electronic devices are required to be small, thin, lightweight, high-performance, high-performance, high-quality and highly reliable as represented by mobile communication devices. Electronic devices mounted on various electronic devices are also required to be small and have high density. Therefore, wiring boards that make up electronic devices are also required to be small, thin, and have multiple terminals. To achieve this, the widths of wiring conductors such as signal conductors are made narrower and the intervals between them are reduced. High-density wiring is achieved by multilayering wiring conductors.
【0003】このような高密度配線が可能な配線基板と
して、ビルドアップ法を採用して製作された配線基板が
知られている。ビルドアップ法とは、例えば、ガラスク
ロスやアラミド不布織等の補強材に耐熱性や耐薬品性を
有するエポキシ樹脂に代表される熱硬化性樹脂を含浸さ
せて硬化した芯体上に配線導体を被着形成するととも
に、この配線導体上を含む芯体上にエポキシ樹脂等の熱
硬化性樹脂から成るワニスを塗布して加熱硬化させて絶
縁層を形成した後、配線導体上の絶縁層にレーザで径が
50〜200μm程度の貫通孔を穿設し、しかる後、絶縁層
表面に銅の導体膜を被着させるとともに貫通孔内部に銅
の導体膜を被着充填して配線導体および貫通導体を形成
し、その上に絶縁層や貫通導体・配線導体の形成を複数
回繰り返す配線基板の製造方法である。A wiring board manufactured by adopting a build-up method is known as a wiring board capable of such high-density wiring. The build-up method is, for example, a wiring conductor on a core body obtained by impregnating a reinforcing material such as glass cloth or aramid non-woven fabric with a thermosetting resin typified by an epoxy resin having heat resistance and chemical resistance and curing the same. After depositing and forming the insulating layer on the wiring conductor by applying a varnish made of a thermosetting resin such as an epoxy resin on the core body including the wiring conductor and heating and curing it. Laser diameter
A through hole of about 50 to 200 μm is bored, and then a copper conductor film is deposited on the surface of the insulating layer and a copper conductor film is deposited and filled inside the through hole to form a wiring conductor and a through conductor. A method of manufacturing a wiring board in which the formation of an insulating layer and a through conductor / wiring conductor is repeated a plurality of times thereon.
【0004】このような配線導体および貫通導体を形成
する方法としては、無電解めっきと電解めっきとを組合
せたセミアディティブ法や無電解めっきのみのフルアデ
ィティブ法がある。しかしながら、フルアディティブ法
は無電解めっきのみで配線導体および貫通導体の形成を
行うことから、配線導体および貫通導体を形成するのに
長時間を要してしまい生産性に劣るという問題点を有し
ている。このため、配線導体および貫通導体は、一般的
には無電解めっきと電解めっきとを組合せたセミアディ
ティブ法を用いて形成されている。As a method for forming such a wiring conductor and a through conductor, there are a semi-additive method in which electroless plating and electrolytic plating are combined, and a full additive method only with electroless plating. However, since the full-additive method forms the wiring conductor and the through conductor only by electroless plating, it takes a long time to form the wiring conductor and the through conductor, and thus has a problem of poor productivity. ing. Therefore, the wiring conductor and the through conductor are generally formed by using a semi-additive method that combines electroless plating and electrolytic plating.
【0005】このようなセミアディティブ法は、絶縁層
表面および貫通孔内部に、厚みが1〜2μmの無電解銅
めっき層を被着後、その上にドライフィルムレジストで
配線パターンに対応した開口部を有するめっきレジスト
層を形成するとともに、その開口部から露出する無電解
銅めっき層上に電解銅めっき層を被着形成し、その後め
っきレジスト層を剥離し、しかる後、電解銅めっき層と
めっきレジスト層を剥離したことにより表面に露出した
無電解銅めっき層とをエッチングして配線導体および貫
通導体を形成する方法である。In such a semi-additive method, an electroless copper plating layer having a thickness of 1 to 2 μm is deposited on the surface of the insulating layer and the inside of the through hole, and an opening corresponding to the wiring pattern is formed thereon by a dry film resist. While forming a plating resist layer having, the electrolytic copper plating layer is formed by depositing on the electroless copper plating layer exposed from the opening, and then the plating resist layer is peeled off, and then the electrolytic copper plating layer and plating are performed. This is a method of forming a wiring conductor and a through conductor by etching the electroless copper plating layer exposed on the surface by peeling the resist layer.
【0006】なお、ビルドアップ法により製作された配
線基板は、その表面の配線導体の一部が電子部品を実装
するための実装用電極として形成され、半田バンプを介
して実装用電極と電子部品の端子とが接続されている。
また、実装用電極の表面には、半田バンプとの密着性に
優れるニッケル−金めっき層が被着されている。In the wiring board manufactured by the build-up method, a part of the wiring conductor on the surface is formed as a mounting electrode for mounting an electronic component, and the mounting electrode and the electronic component are connected via solder bumps. Is connected to the terminal.
In addition, a nickel-gold plating layer having excellent adhesion to the solder bumps is deposited on the surface of the mounting electrode.
【0007】[0007]
【発明が解決しようとする課題】しかしながら、上記の
配線基板によれば、貫通孔に電解銅めっき層を充填する
場合、1.0A/dm2以上の高い電流密度で電解銅めっき
層を形成すると、貫通孔の開口部近傍での電解銅めっき
層の成長が、貫通孔の内部での電解銅めっき層の成長に
比較して極めて大きく促進され、その結果、貫通孔の開
口近傍で大きく成長した電解銅めっき層により貫通孔の
開口部付近が先に塞がれて貫通導体の内部に空洞が形成
されてしまい、配線基板へ電子部品を実装する際の熱で
貫通導体内部の空洞の閉塞された液体が急激に膨張し、
配線基板に膨れが生じ、電子部品が確実に実装できない
という問題点を有していた。However, according to the above wiring board, when the through-hole is filled with the electrolytic copper plating layer, if the electrolytic copper plating layer is formed at a high current density of 1.0 A / dm 2 or more, The growth of the electrolytic copper plating layer in the vicinity of the opening of the through hole is greatly promoted as compared with the growth of the electrolytic copper plating layer in the inside of the through hole. The copper plating layer first closes the opening of the through hole to form a cavity inside the through conductor, and the heat inside the electronic component mounted on the wiring board blocked the cavity inside the through conductor. The liquid expands rapidly,
There is a problem in that the wiring board swells and the electronic component cannot be reliably mounted.
【0008】また、上記の配線基板によれば、貫通孔の
径よりも絶縁層の厚みが大きくなると、電解銅めっき液
が貫通孔に浸透し難くなり、貫通孔内へ電解銅めっき層
を良好に被着充填できなくなってしまうという問題点も
有していた。Further, according to the above wiring board, when the thickness of the insulating layer is larger than the diameter of the through hole, the electrolytic copper plating solution hardly penetrates into the through hole, and the electrolytic copper plating layer is well formed in the through hole. However, there is also a problem in that it becomes impossible to adhere and fill.
【0009】さらに、上記の配線基板によれば、0.8A
/dm2以下の低い電流密度で電解銅めっき層を形成す
ると、貫通孔内への電解銅めっき層の被着充填は良好と
なるが、めっき時間が長くかかり生産性が低下するだけ
でなく、電解銅めっき層の結晶粒径が大きくなり、エッ
チング後に電解銅めっき層表面に2〜10μmの粒状の突
起が形成されてしまい、その結果、配線基板の実装用電
極表面に形成されるニッケル−金めっき層の厚みが不均
一となってしまい、実装用電極と半田バンプとの接続強
度が低下して、電子部品を配線基板に強固に接続できな
いという問題点を有していた。Further, according to the above wiring board, 0.8 A
When the electrolytic copper plating layer is formed at a low current density of / dm 2 or less, the deposition of the electrolytic copper plating layer in the through holes is good, but the plating time is long and not only the productivity decreases, but also The crystal grain size of the electrolytic copper plating layer becomes large, and granular projections of 2 to 10 μm are formed on the surface of the electrolytic copper plating layer after etching. As a result, nickel-gold formed on the surface of the mounting electrode of the wiring board. There is a problem that the thickness of the plating layer becomes non-uniform, the connection strength between the mounting electrode and the solder bump is reduced, and the electronic component cannot be firmly connected to the wiring board.
【0010】本発明は、かかる従来技術の問題点に鑑み
完成されたものであり、その目的は貫通孔を銅導体で良
好に充填でき、貫通導体表面の平滑性に優れ、電子部品
が確実に強固に接続できる配線基板およびこれを用いた
電子装置を提供することにある。The present invention has been completed in view of the above problems of the prior art, and its purpose is to be able to satisfactorily fill a through hole with a copper conductor, to provide an excellent smoothness of the surface of the through conductor, and to ensure that an electronic component can be manufactured. An object of the present invention is to provide a wiring board that can be firmly connected and an electronic device using the same.
【0011】[0011]
【課題を解決するための手段】本発明の配線基板は、複
数の絶縁層および配線導体が交互に積層されるとともに
上下の配線導体間を絶縁層に形成された貫通孔を電解め
っき法による銅導体で充填して成る貫通導体により電気
的に接続して成る配線基板において、銅導体は、電流密
度が0.3〜0.8A/dm2の電解めっきによる2/3〜3
/4の厚みを占める第1層と、電流密度が1.0〜3.0A/
dm2の電解めっきによる残りの厚みを占める第2層と
から成るとともに、第2層の表面の結晶粒径が0.1〜2
μmであることを特徴とするものである。In the wiring board of the present invention, a plurality of insulating layers and wiring conductors are alternately laminated and a through hole formed between the upper and lower wiring conductors in the insulating layer is formed by electrolytic plating. In a wiring board electrically connected by a through conductor formed by filling with a conductor, the copper conductor has a current density of 0.3 to 0.8 A / dm 2 and is 2/3 to 3 by electrolytic plating.
The first layer occupying a thickness of / 4 and the current density is 1.0 to 3.0 A /
The second layer occupies the remaining thickness of the dm 2 electrolytic plating, and the crystal grain size of the surface of the second layer is 0.1 to 2
It is characterized by being μm.
【0012】また、本発明の配線基板は、上記構成にお
いて、絶縁層の厚みが15〜50μmであるとともに、貫通
孔の径が30〜200μmであることを特徴とするものであ
る。Further, the wiring board of the present invention is characterized in that, in the above-mentioned constitution, the thickness of the insulating layer is 15 to 50 μm and the diameter of the through hole is 30 to 200 μm.
【0013】本発明の電子装置は、上記の配線基板の表
面に電子部品を実装するとともに、電子部品の電極を配
線導体または貫通導体に電気的に接続して成ることを特
徴とするものである。The electronic device of the present invention is characterized in that an electronic component is mounted on the surface of the above-mentioned wiring board, and an electrode of the electronic component is electrically connected to a wiring conductor or a through conductor. .
【0014】本発明の配線基板によれば、貫通導体を形
成する銅導体を電流密度が0.3〜0.8A/dm2の電解め
っきによる2/3〜3/4の厚みを占める第1層と、電
流密度が1.0〜3.0A/dm2の電解めっきによる残りの
厚みを占める第2層とから形成するとともに、第2層の
表面の結晶粒径を0.1〜2μmとしたことから、銅導体
の形成を短時間で行なうことができ、生産性に優れた配
線基板とすることができ、また、第2層の表面にニッケ
ル−金めっき層を均一に形成することができ、半田バン
プとの接続強度が高く、搭載する電子部品と強固に接続
できる配線基板とすることができる。According to the wiring board of the present invention, the copper conductor forming the penetrating conductor is electrolytically plated at a current density of 0.3 to 0.8 A / dm 2 , and the first layer occupies a thickness of 2/3 to 3/4; The formation of the copper conductor was made from the second layer occupying the remaining thickness of the electrolytic plating having a current density of 1.0 to 3.0 A / dm 2 and the crystal grain size of the surface of the second layer was 0.1 to 2 μm. Can be performed in a short time, a wiring board with excellent productivity can be obtained, and a nickel-gold plating layer can be uniformly formed on the surface of the second layer, so that the connection strength with solder bumps can be improved. Therefore, it is possible to provide a wiring board which has a high cost and can be firmly connected to the mounted electronic components.
【0015】また、本発明の配線基板によれば、上記構
成において、絶縁層の厚みを15〜50μmとするととも
に、貫通孔の径を30〜200μmとしたことから、電解銅
めっき液が貫通孔に容易に浸透し、貫通孔内への電解銅
めっき層の被着充填を良好とすることができ、その結
果、貫通導体内部に空洞が形成されることはなく、配線
基板へ電子部品を実装する際の熱で配線基板に膨れが生
じることはない。Further, according to the wiring board of the present invention, in the above structure, the thickness of the insulating layer is set to 15 to 50 μm, and the diameter of the through hole is set to 30 to 200 μm. Can be easily penetrated into the through hole, and the electrolytic copper plating layer can be well deposited and filled in the through hole. As a result, a cavity is not formed inside the through conductor and the electronic component is mounted on the wiring board. The wiring board does not bulge due to the heat generated during the process.
【0016】本発明の電子装置によれば、上記の配線基
板の表面に電子部品を実装するとともに、電子部品の電
極を配線導体または貫通導体に電気的に接続して成るこ
とから、電子部品と配線基板との接続が強固な電子装置
とすることができる。According to the electronic device of the present invention, the electronic component is mounted on the surface of the wiring board, and the electrode of the electronic component is electrically connected to the wiring conductor or the through conductor. An electronic device having a strong connection with the wiring board can be provided.
【0017】[0017]
【発明の実施の形態】次に、本発明の配線基板およびこ
れを用いた電子装置を添付の図面に基づいて詳細に説明
する。図1は、本発明の配線基板およびこれを用いた電
子装置の実施の形態の一例を示す断面図であり、図2
は、図1の要部拡大断面図である。DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a wiring board of the present invention and an electronic device using the same will be described in detail with reference to the accompanying drawings. 1 is a sectional view showing an example of an embodiment of a wiring board of the present invention and an electronic device using the same.
FIG. 2 is an enlarged cross-sectional view of the main part of FIG.
【0018】これらの図において、1は絶縁層、2は配
線導体、3は貫通孔、4は貫通導体で、主にこれらで本
発明の配線基板5が構成される。また、配線導体2の一
部から成る実装用電極2aに半導体素子等の電子部品6
を搭載することにより本発明の電子装置7が製作され
る。In these figures, 1 is an insulating layer, 2 is a wiring conductor, 3 is a through hole, and 4 is a through conductor, and these mainly constitute the wiring board 5 of the present invention. In addition, an electronic component 6 such as a semiconductor element is mounted on the mounting electrode 2a formed of a part of the wiring conductor 2.
The electronic device 7 of the present invention is manufactured by mounting the.
【0019】配線基板5は、電子部品6を搭載する機能
を有し、例えばガラス繊維を縦横に織り込んだガラスク
ロスにエポキシ樹脂やビスマレイミドトリアジン樹脂等
の熱硬化性樹脂を含浸させて成る板状の芯体絶縁層1a
の上下面に、エポキシ樹脂や変性ポリフェニレンエーテ
ル樹脂等の熱硬化性樹脂から成る絶縁層1bと銅めっき
膜からなる配線導体2とをそれぞれ複数層、交互に積層
して成る多層板である。The wiring board 5 has a function of mounting the electronic component 6, and is, for example, a plate-shape formed by impregnating a glass cloth in which glass fibers are woven vertically and horizontally with a thermosetting resin such as epoxy resin or bismaleimide triazine resin. Core insulation layer 1a
It is a multi-layer board in which a plurality of insulating layers 1b made of a thermosetting resin such as an epoxy resin or a modified polyphenylene ether resin and a wiring conductor 2 made of a copper plating film are alternately laminated on the upper and lower surfaces.
【0020】芯体絶縁層1aは、配線基板5に強度を持
たせる機能を有し、厚みが0.3〜1.5mmであり、その上
面から下面にかけて直径が0.1〜1.0mmの複数のスルー
ホール9を有している。そして、各スルーホール9の内
壁には銅めっき膜が被着されており、上下面に形成され
た配線導体層8がスルーホール9の銅めっき膜を介して
電気的に接続されている。The core insulating layer 1a has a function of giving strength to the wiring board 5, has a thickness of 0.3 to 1.5 mm, and has a plurality of through holes 9 having a diameter of 0.1 to 1.0 mm from its upper surface to its lower surface. Have A copper plating film is deposited on the inner wall of each through hole 9, and the wiring conductor layers 8 formed on the upper and lower surfaces are electrically connected via the copper plating film of the through hole 9.
【0021】このような芯体絶縁層1aは、ガラスクロ
スに未硬化の熱硬化性樹脂を含浸させたシートを熱硬化
させた後、これに上面から下面にかけてドリル加工を施
すことにより製作される。なお、芯体絶縁層1a上下面
の配線導体層8は、芯体絶縁層1a用のシートの上下全
面に厚みが3〜50μmの銅膜を被着しておくとともにこ
の銅膜をシートの硬化後にエッチング加工することによ
り所定のパターンに形成される。また、スルーホール9
内壁の銅めっき膜は、芯体絶縁層1aにスルーホール9
を設けた後に、このスルーホール9にめっき法により厚
みが3〜50μm程度の銅めっき膜を析出させることによ
り形成される。なお、配線導体層8は、スルーホール9
内壁に銅めっき膜を形成する際に、めっき法により同時
に形成してもよい。Such a core insulating layer 1a is manufactured by thermosetting a sheet in which glass cloth is impregnated with an uncured thermosetting resin, and then drilling the sheet from the upper surface to the lower surface. . For the wiring conductor layers 8 on the upper and lower surfaces of the core insulating layer 1a, a copper film having a thickness of 3 to 50 μm is deposited on the entire upper and lower surfaces of the sheet for the core insulating layer 1a, and the copper film is cured. After that, it is formed into a predetermined pattern by etching. Also, through hole 9
The copper plating film on the inner wall has a through hole 9 in the core insulating layer 1a.
Is formed, and then a copper plating film having a thickness of about 3 to 50 μm is deposited in the through hole 9 by a plating method. The wiring conductor layer 8 has through holes 9
When the copper plating film is formed on the inner wall, it may be simultaneously formed by a plating method.
【0022】さらに、芯体絶縁層1aは、スルーホール
9の内部にエポキシ樹脂やビスマレイミドトリアジン樹
脂等の熱硬化性樹脂から成る樹脂柱10が充填されてい
る。樹脂柱10は、スルーホール9を塞ぐことによりスル
ーホール9の直上および直下に絶縁層1bを形成可能と
するためのものであり、未硬化のペースト状の熱硬化性
樹脂をスルーホール9内にスクリーン印刷法により充填
し、これを熱硬化させた後、その上下面を略平坦に研磨
することにより形成される。そして、この樹脂柱10を含
む芯体絶縁層1aの上下面に絶縁層1bおよび配線導体
2が積層されている。Further, in the core insulating layer 1a, resin columns 10 made of a thermosetting resin such as epoxy resin or bismaleimide triazine resin are filled in the through holes 9. The resin pillar 10 is for closing the through hole 9 so that the insulating layer 1b can be formed directly above and directly below the through hole 9, and an uncured paste-like thermosetting resin is placed in the through hole 9. It is formed by filling by a screen printing method, thermally curing it, and polishing the upper and lower surfaces thereof to be substantially flat. The insulating layer 1b and the wiring conductor 2 are laminated on the upper and lower surfaces of the core insulating layer 1a including the resin columns 10.
【0023】絶縁層1bは、配線導体2を高密度に配線
するための絶縁間隔を提供するためのものである。そし
て、上下に位置する配線導体2間を貫通孔3内部に形成
された銅導体から成る貫通導体4を介して電気的に接続
することにより高密度配線を立体的に形成可能としてい
る。The insulating layer 1b is provided to provide an insulating space for wiring the wiring conductors 2 at high density. Then, high-density wiring can be three-dimensionally formed by electrically connecting the wiring conductors 2 located above and below through the penetrating conductor 4 made of a copper conductor formed inside the through hole 3.
【0024】このような絶縁層1bは、エポキシ樹脂や
ビスマレイミドトリアジン樹脂・変性ポリフェニレンエ
ーテル樹脂等の熱硬化性樹脂とシリカ等の無機フィラー
とから成り、絶縁層1bの厚み方向の熱膨張係数を20〜
60×10-6/℃としておくことが好ましい。なお、熱膨張
係数が20×10-6/℃未満であると、絶縁層1bが硬く脆
くなりクラックが発生し易くなる傾向があり、60×10-6
/℃を超えると、熱膨張差により貫通導体4と絶縁層1
bとが剥離し易くなる傾向がある。また、絶縁層1bの
熱膨張係数を20〜60×10-6/℃とするには、シリカ等の
無機フィラーを熱硬化性樹脂に対して50〜80重量%充填
すればよい。The insulating layer 1b is made of a thermosetting resin such as an epoxy resin, a bismaleimide triazine resin or a modified polyphenylene ether resin, and an inorganic filler such as silica, and has a coefficient of thermal expansion in the thickness direction of the insulating layer 1b. 20 ~
It is preferably set at 60 × 10 −6 / ° C. Incidentally, the thermal expansion coefficient is less than 20 × 10 -6 / ℃, tend to crack becomes hard and brittle insulating layer 1b is is likely to occur, 60 × 10 -6
If the temperature exceeds / ° C, the through conductor 4 and the insulating layer 1
b tends to peel off easily. Further, in order to set the thermal expansion coefficient of the insulating layer 1b to 20 to 60 × 10 −6 / ° C., 50 to 80% by weight of an inorganic filler such as silica may be filled in the thermosetting resin.
【0025】そして、このような配線基板5は、次に述
べる工程により製作される。まず、熱硬化性樹脂と無機
フィラーとから成るフィルムを芯体絶縁層1aおよび配
線導体層8表面に積層するとともに熱硬化させて一層目
の絶縁層1bを形成する。次に、レーザにより配線導体
層8上の絶縁層1bに貫通孔4を形成し、その後、絶縁
層1bと貫通孔3内部とを過マンガン酸塩類水溶液等の
粗化液に浸漬し粗化する。次に、絶縁層1bと貫通孔3
内部とに、パラジウム等の無電解めっき触媒を被着した
後、配線基板5を硫酸銅・ロッセル塩・ホルマリン・E
DTAナトリウム塩・安定剤等から成る無電解めっき液
に約30分間浸漬して絶縁層1b表面および貫通孔3内部
に1〜2μmの無電解銅めっきを析出させる。そして、
絶縁層1b上の無電解銅めっきを耐めっき樹脂層で被覆
するとともに耐めっき樹脂層に露光・現像により配線パ
ターンとなる開口部を形成する。さらに、配線基板5を
硫酸・硫酸銅5水和物・塩素・光沢剤等から成る電解銅
めっき液に浸漬し、0.3〜0.8A/dm2の電流密度で数
分間電解銅めっきすることにより貫通孔3の深さ方向で
2/3〜3/4 の厚みに貫通導体4を形成する銅導体
の第1層4aを形成し、その後、1.0〜3.0A/dm2の
電流密度で数分間電解銅めっきすることにより銅導体の
第2層4bを形成して貫通孔3を銅導体で充填する。な
お、この時、絶縁層1b表面の配線導体2となる耐めっ
き樹脂層の開口部にも電解銅めっき層が被着される。し
かる後、耐めっき樹脂層を剥離し、耐めっき樹脂層下の
無電解めっきをエッチング除去することにより配線導体
2を形成する。その後、二層目以降の絶縁層1bおよび
貫通導体4・配線導体2を上記と同様の方法で繰返し形
成することにより配線基板5が製作される。Then, such a wiring board 5 is manufactured by the following steps. First, a film made of a thermosetting resin and an inorganic filler is laminated on the surfaces of the core insulating layer 1a and the wiring conductor layer 8 and thermoset to form the first insulating layer 1b. Next, a through hole 4 is formed in the insulating layer 1b on the wiring conductor layer 8 by a laser, and then the insulating layer 1b and the inside of the through hole 3 are immersed in a roughening solution such as a permanganate aqueous solution to roughen. . Next, the insulating layer 1b and the through hole 3
After depositing an electroless plating catalyst such as palladium on the inside, the wiring board 5 is covered with copper sulfate, Rossell salt, formalin, E
It is dipped in an electroless plating solution containing DTA sodium salt / stabilizer for about 30 minutes to deposit 1-2 μm of electroless copper plating on the surface of the insulating layer 1b and inside the through holes 3. And
The electroless copper plating on the insulating layer 1b is covered with a plating resistant resin layer, and an opening to be a wiring pattern is formed in the plating resistant resin layer by exposure and development. Further, the wiring board 5 is immersed in an electrolytic copper plating solution containing sulfuric acid, copper sulfate pentahydrate, chlorine, a brightener, etc., and electrolytic copper plating is performed at a current density of 0.3 to 0.8 A / dm 2 for several minutes to penetrate the wiring board 5. The first layer 4a of the copper conductor forming the through conductor 4 is formed to a thickness of 2/3 to 3/4 in the depth direction of the hole 3, and then electrolysis is performed for several minutes at a current density of 1.0 to 3.0 A / dm 2. The second layer 4b of the copper conductor is formed by copper plating, and the through hole 3 is filled with the copper conductor. At this time, the electrolytic copper plating layer is also deposited on the opening of the anti-plating resin layer which becomes the wiring conductor 2 on the surface of the insulating layer 1b. Thereafter, the plating resistant resin layer is peeled off, and the electroless plating under the plating resistant resin layer is removed by etching to form the wiring conductor 2. After that, the wiring board 5 is manufactured by repeatedly forming the second and subsequent insulating layers 1b and the penetrating conductors 4 and the wiring conductors 2 in the same manner as described above.
【0026】なお、ここで貫通孔3を充填する銅導体の
厚みは、図2のAに示すように貫通孔3の実質的な深さ
に対応する厚みをさす。また、銅導体の第1層4aの厚
みとは、図2のXに示すように第1層4aの下面から上
面の一番低い個所までの厚みをさし、銅導体の第2層4
bの厚みとは、図2のYに示すように銅導体の厚みAか
ら銅導体の第1層4aの厚みXを引いた厚みをさす。Here, the thickness of the copper conductor filling the through hole 3 refers to the thickness corresponding to the substantial depth of the through hole 3 as shown in FIG. In addition, the thickness of the first layer 4a of the copper conductor refers to the thickness from the lower surface of the first layer 4a to the lowest portion of the upper surface thereof, as shown by X in FIG.
The thickness b is the thickness obtained by subtracting the thickness X of the first layer 4a of the copper conductor from the thickness A of the copper conductor as shown in Y of FIG.
【0027】さらに、銅導体の第1層4aの厚みは、貫
通孔3の深さ方向で銅導体の厚みの2/3〜3/4とす
ることが好ましい。厚みが2/3未満であると、1.0〜
3.0A/dm2と高い電流密度で形成される銅導体が多く
なり、貫通孔3の開口部付近が先に塞がれて貫通導体4
の中央部に空洞が形成され易くなる傾向があり、厚みが
3/4を超えると電解めっき時間が長くなり生産性が低
下する傾向にある。したがって、第1層4aの厚みを、
貫通孔3の深さ方向で銅導体の2/3〜3/4とするこ
とが好ましい。Further, the thickness of the first layer 4a of the copper conductor is preferably set to 2/3 to 3/4 of the thickness of the copper conductor in the depth direction of the through hole 3. If the thickness is less than 2/3, 1.0-
The number of copper conductors formed at a high current density of 3.0 A / dm 2 increases, and the vicinity of the opening of the through hole 3 is closed first and the through conductor 4
There is a tendency that a cavity is easily formed in the central part of the above, and if the thickness exceeds 3/4, the electrolytic plating time becomes longer and the productivity tends to decrease. Therefore, the thickness of the first layer 4a is
It is preferable that the depth of the through hole 3 is set to 2/3 to 3/4 of that of the copper conductor.
【0028】また、第1層4aを形成する電解めっきの
電流密度は0.3〜0.8A/dm2が好ましく、0.3A/dm
2未満であると電解めっきの被着に時間がかかり生産性
が低下する傾向にあり、0.8A/dm2を超えると貫通孔
3の開口部付近が先に塞がれて貫通導体4の中央部に空
洞が形成され易くなる傾向がある。したがって、第1層
4aの電解めっきの電流密度は0.3〜0.8A/dm2とす
ることが好ましい。The current density of the electroplating for forming the first layer 4a is preferably 0.3 to 0.8 A / dm 2 , and 0.3 A / dm 2.
If it is less than 2, it takes a long time to deposit the electrolytic plating and the productivity tends to decrease, and if it exceeds 0.8 A / dm 2 , the vicinity of the opening of the through hole 3 is closed first and the center of the through conductor 4 is closed. There is a tendency that a cavity is easily formed in the part. Therefore, the current density of the electroplating of the first layer 4a is preferably 0.3 to 0.8 A / dm 2 .
【0029】さらに、第2層4bを形成する電解めっき
の電流密度は1.0〜3.0A/dm2が好ましく、1.0A/d
m2未満であると、電解銅めっき層の結晶粒径が大きく
なってしまい、電解銅めっき層表面に2〜10μmの粒状
の突起が形成されてしまう傾向があり、3.0A/dm2を
超えると電解銅めっきの成長速度が速過ぎて厚みの制御
が困難になる傾向がある。したがって、第2層4bの電
解めっきの電流密度は1.0〜3.0A/dm2であることが
好ましい形。Further, the current density of the electrolytic plating forming the second layer 4b is preferably 1.0 to 3.0 A / dm 2 , and 1.0 A / d.
If it is less than m 2 , the crystal grain size of the electrolytic copper plating layer tends to be large, and granular projections of 2 to 10 μm tend to be formed on the surface of the electrolytic copper plating layer, which exceeds 3.0 A / dm 2 . And the growth rate of electrolytic copper plating tends to be too fast, making it difficult to control the thickness. Therefore, it is preferable that the current density of electrolytic plating of the second layer 4b is 1.0 to 3.0 A / dm 2 .
【0030】また、絶縁層1bの厚みは15〜50μmであ
ることが好ましく、厚みが15μmより薄くなると絶縁層
1bの絶縁性が低下してしまう傾向があり、50μmを超
えると貫通孔3が深くなりめっき液が浸透し難くなり、
貫通孔3を電解銅めっきによる貫通導体4で充填するこ
とが困難となる傾向にある。したがって、絶縁層1bの
厚みは15〜50μmであることが好ましい。また、絶縁層
1bに形成される貫通孔3の径は、30〜200μmである
ことが好ましく、径が30μm未満であるとめっき液が浸
透し難くなり、貫通孔3を電解銅めっきによる貫通導体
4で充填することが困難となる傾向があり、200μmを
超えると高密度配線が難しくなる傾向がある。したがっ
て、貫通孔3の径は30〜200μmであることが好まし
い。The thickness of the insulating layer 1b is preferably 15 to 50 μm, and if the thickness is less than 15 μm, the insulating property of the insulating layer 1b tends to deteriorate, and if it exceeds 50 μm, the through hole 3 becomes deep. It becomes difficult for the plating solution to penetrate,
It tends to be difficult to fill the through holes 3 with the through conductors 4 formed by electrolytic copper plating. Therefore, the thickness of the insulating layer 1b is preferably 15 to 50 μm. Further, the diameter of the through hole 3 formed in the insulating layer 1b is preferably 30 to 200 μm, and if the diameter is less than 30 μm, it is difficult for the plating solution to penetrate, and the through hole 3 is a through conductor formed by electrolytic copper plating. 4 tends to be difficult to fill, and if it exceeds 200 μm, high-density wiring tends to be difficult. Therefore, the diameter of the through hole 3 is preferably 30 to 200 μm.
【0031】また、配線導体2は、搭載される半導体素
子等の電子部品6の各電極を外部電気回路基板(図示せ
ず)に接続するための導電路としての機能を有し、高速
の信号を伝達させるという観点からは5μm以上である
ことが好ましく、配線導体2と絶縁層1bとの熱膨張差
による剥離を防止するという観点からは50μm以下であ
ることが好ましい。したがって、配線導体2の厚みを5
〜50μmとすることが好ましい。The wiring conductor 2 has a function as a conductive path for connecting each electrode of the electronic component 6 such as a semiconductor element to be mounted to an external electric circuit board (not shown), and a high-speed signal is transmitted. Is preferably 5 μm or more from the viewpoint of transmitting the heat conductivity, and is preferably 50 μm or less from the viewpoint of preventing peeling due to a difference in thermal expansion between the wiring conductor 2 and the insulating layer 1b. Therefore, the thickness of the wiring conductor 2 is 5
It is preferable that the thickness is -50 μm.
【0032】また、本発明の配線基板5は、貫通導体4
の第2層4bの結晶粒径の大きさが0.1〜2μmである
こと重要である。結晶粒径の大きさが0.1μm未満であ
るとエッチングされ易く厚みの制御が困難となる傾向が
あり、2μmを超えると電解銅めっき層表面に2〜10μ
mの粒状の突起が形成されてしまい、配線基板5の実装
用電極2a表面にニッケル−金めっき層を形成した際に
ニッケル−金めっき層の厚みが不均一となり、実装用電
極2aと電子部品6を接続する導体バンプ11との接合強
度が低下し、電子部品6が確実に実装できなくなる傾向
がある。したがって、第2層4bの結晶粒径の大きさを
0.1〜2μmにすることが重要である。なお、結晶粒径
を0.1〜2μmとするには、第2層4bを形成する電流
密度を1.0〜3.0A/dm2とすればよい。Further, the wiring board 5 of the present invention includes the through conductor 4
It is important that the crystal grain size of the second layer 4b is 0.1 to 2 μm. If the crystal grain size is less than 0.1 μm, it tends to be easily etched, and it is difficult to control the thickness. If it exceeds 2 μm, the electrolytic copper plating layer surface has 2 to 10 μm.
When the nickel-gold plated layer is formed on the surface of the mounting electrode 2a of the wiring board 5, the thickness of the nickel-gold plated layer becomes non-uniform, and the mounting electrode 2a and the electronic component are formed. There is a tendency that the bonding strength with the conductor bumps 11 that connect 6 to each other is reduced, and the electronic component 6 cannot be reliably mounted. Therefore, the crystal grain size of the second layer 4b
It is important to set the thickness to 0.1 to 2 μm. In order to set the crystal grain size to 0.1 to 2 μm, the current density for forming the second layer 4b may be set to 1.0 to 3.0 A / dm 2 .
【0033】さらに、絶縁層1bの一方の最外層表面に
形成された配線導体2の一部は、電子部品7の各電極に
導体バンプ11を介して接合される電子部品6接続用の実
装用電極2aを形成し、また、絶縁層1bの他方の最外
層表面に形成された配線導体2の一部は、外部電気回路
基板(図示せず)の各電極に導体バンプ11を介して接続
される外部接続用の実装用電極2aを形成している。Further, a part of the wiring conductor 2 formed on the surface of one of the outermost layers of the insulating layer 1b is connected to each electrode of the electronic component 7 through the conductor bump 11 for mounting the electronic component 6 for mounting. A part of the wiring conductor 2 forming the electrode 2a and formed on the surface of the other outermost layer of the insulating layer 1b is connected to each electrode of the external electric circuit board (not shown) through the conductor bump 11. A mounting electrode 2a for external connection is formed.
【0034】実装用電極2aの表面には、その酸化腐蝕
を防止するとともに導体バンプ11の接続を良好とするた
めに、半田との濡れ性が良好で耐腐蝕性に優れたニッケ
ル−金等のめっき層が被着されている。The surface of the mounting electrode 2a is made of nickel-gold or the like which has good wettability with solder and excellent corrosion resistance in order to prevent its oxidation and corrosion and to make the connection of the conductor bump 11 good. The plating layer is applied.
【0035】また、最外層の絶縁層1bおよび実装用電
極2aには、実装用電極2aの中央部を露出させる開口
を有する耐半田樹脂層12が被着されている。耐半田樹脂
層12は、その厚みが10〜50μmであり、例えばアクリル
変性エポキシ樹脂等の感光性樹脂と光開始剤等とから成
る混合物に30〜70重量%のシリカやタルク等の無機粉末
フィラーを含有させた絶縁材料から成り、隣接する実装
用電極2a同士が導体バンプ11により電気的に短絡する
ことを防止するとともに、実装用電極2aと絶縁層1b
との接合強度を向上させる機能を有する。The outermost insulating layer 1b and the mounting electrode 2a are covered with a solder-resistant resin layer 12 having an opening for exposing the central portion of the mounting electrode 2a. The solder-resistant resin layer 12 has a thickness of 10 to 50 μm. For example, 30 to 70% by weight of inorganic powder filler such as silica or talc is added to a mixture of a photosensitive resin such as an acrylic modified epoxy resin and a photoinitiator. Which is made of an insulating material, prevents the adjacent mounting electrodes 2a from being electrically short-circuited by the conductor bumps 11, and the mounting electrode 2a and the insulating layer 1b.
It has a function of improving the bonding strength with.
【0036】このような耐半田樹脂層12は、感光性樹脂
と光開始剤と無機粉末フィラーとから成る未硬化樹脂フ
ィルムを最外層の絶縁層1b表面に被着させる、あるい
は、熱硬化性樹脂と無機粉末フィラーとから成る未硬化
樹脂ワニスを最外層の絶縁層1b表面に塗布するととも
に乾燥し、しかる後、露光・現像により開口部を形成
し、これをUV硬化および熱硬化させることにより形成
される。Such a solder-resistant resin layer 12 is formed by applying an uncured resin film composed of a photosensitive resin, a photoinitiator, and an inorganic powder filler to the surface of the outermost insulating layer 1b, or a thermosetting resin. An uncured resin varnish composed of an inorganic powder filler and an uncured resin varnish is applied to the surface of the outermost insulating layer 1b and dried, and then an opening is formed by exposure / development, which is UV-cured and heat-cured. To be done.
【0037】かくして、本発明の配線基板5によれば、
貫通導体4を形成する銅導体を、電流密度が0.3〜0.8A
/dm2の電解めっきによる2/3〜3/4の厚みを占
める第1層4aと、電流密度が1.0〜3.0A/dm2の電
解めっきによる残りの厚みを占める第2層4bとから形
成するとともに、第2層4bの表面の結晶粒径を0.1〜
2μmとしたことから、貫通導体4の中央部に空洞が形
成されることなく、銅導体で確実に充填された貫通導体
4とすることができ、実装時に膨れや剥がれがなく、ま
た、配線導体2の一部から成る実装用電極2a表面にニ
ッケル−金めっき層を均一に形成することができ、半田
バンプ11との接続強度が高く、搭載する電子部品6と強
固に接続できる配線基板5とすることができる。Thus, according to the wiring board 5 of the present invention,
The current density of the copper conductor forming the through conductor 4 is 0.3 to 0.8 A.
Formed from / to the first layer 4a occupying the thickness of 2/3 to 3/4 by electrolytic plating dm 2, and the second layer 4b current density occupies the remaining thickness by electrolytic plating 1.0~3.0A / dm 2 And the crystal grain size on the surface of the second layer 4b is 0.1 to
Since the thickness is 2 μm, the through conductor 4 reliably filled with the copper conductor can be formed without forming a cavity in the central portion of the through conductor 4, there is no swelling or peeling at the time of mounting, and the wiring conductor is A wiring board 5 capable of uniformly forming a nickel-gold plating layer on the surface of the mounting electrode 2a consisting of a part of the wiring 2 and having a high connection strength with the solder bump 11 and capable of firmly connecting with the mounted electronic component 6. can do.
【0038】また、本発明の配線基板5によれば、絶縁
層1の厚みを15μm〜50μmとするとともに、貫通孔3
の径を30〜200μmとしたことから、電解銅めっき液が
容易に貫通孔3に浸透し、貫通孔3内を電解銅めっき層
で完全に被着充填でき、貫通導体4に欠陥のない配線基
板5とすることができる。According to the wiring board 5 of the present invention, the thickness of the insulating layer 1 is set to 15 μm to 50 μm and the through hole 3 is formed.
Since the diameter of the electrolytic copper plating solution is 30 to 200 μm, the electrolytic copper plating solution can easily penetrate into the through holes 3, and the inside of the through holes 3 can be completely adhered and filled with the electrolytic copper plating layer, so that the through conductors 4 have no defect wiring. It can be the substrate 5.
【0039】なお、導体バンプ11は、鉛−錫・錫−亜鉛
・錫−銀−ビスマス等の合金の導電材料から成り、例え
ば、鉛−錫から成る半田の場合、鉛−錫から成る半田ペ
ーストを耐半田樹脂層12の開口の露出した実装用電極2
a上にスクリーン印刷で充填し、リフロー炉を通すこと
により実装用電極2a上に半球状に固着形成される。し
かる後、実装用電極2aに電子部品6の各電極を導体バ
ンプ11を介して接合して電子部品6を搭載するとともに
配線基板5と電子部品6とをアンダーフィル材Fで接着
し、さらに、この電子部品6を図示しない蓋体やポッテ
ィング樹脂により封止することによって電子装置7と成
り、この電子装置7における実装用電極2aを導体バン
プ11を介して外部電気回路基板(図示せず)の配線導体
に接続することにより本発明の電子装置7が外部電気回
路基板(図示せず)に実装されることとなる。The conductive bumps 11 are made of a conductive material of an alloy such as lead-tin, tin-zinc, tin-silver-bismuth. For example, in the case of solder made of lead-tin, a solder paste made of lead-tin is used. Is the mounting electrode 2 in which the opening of the solder-resistant resin layer 12 is exposed.
It is filled by screen printing on a and is passed through a reflow oven to be fixedly formed in a hemispherical shape on the mounting electrode 2a. Then, each electrode of the electronic component 6 is bonded to the mounting electrode 2a through the conductor bump 11 to mount the electronic component 6, and the wiring board 5 and the electronic component 6 are adhered with the underfill material F. An electronic device 7 is obtained by sealing the electronic component 6 with a lid or potting resin (not shown), and the mounting electrodes 2a in the electronic device 7 are connected to the external electric circuit board (not shown) via the conductor bumps 11. By connecting to the wiring conductor, the electronic device 7 of the present invention is mounted on an external electric circuit board (not shown).
【0040】かくして、本発明の電子装置7によれば、
上記の配線基板5の表面に電子部品6を実装するととも
に、電子部品6の電極を配線導体2または貫通導体4に
電気的に接続して成ることから、電解銅めっきの結晶粒
径が小さいので、エッチング後の電解銅めっき層表面が
平滑になり、配線基板5の実装用電極2a表面のニッケ
ル−金めっき層が均一な厚みとなり、実装用電極2aと
半田バンプ11とで充分な接続強度が得られ、電子部品6
が配線基板5に強固に接続できる電子装置7とすること
ができる。Thus, according to the electronic device 7 of the present invention,
Since the electronic component 6 is mounted on the surface of the wiring board 5 and the electrode of the electronic component 6 is electrically connected to the wiring conductor 2 or the through conductor 4, the crystal grain size of the electrolytic copper plating is small. The surface of the electrolytic copper plating layer after etching becomes smooth, the nickel-gold plating layer on the surface of the mounting electrode 2a of the wiring board 5 has a uniform thickness, and the mounting electrode 2a and the solder bump 11 have sufficient connection strength. Obtained, electronic component 6
The electronic device 7 can be firmly connected to the wiring board 5.
【0041】なお、本発明は、上述の実施の形態の一例
に限定されるものではなく、本発明の要旨を逸脱しない
範囲であれば種々の変更が可能であることはいうまでも
ない。It is needless to say that the present invention is not limited to the above-mentioned example of the embodiment, and various modifications can be made without departing from the scope of the present invention.
【0042】[0042]
【実施例】(実施例1)熱硬化性樹脂と無機フィラーと
から成るフィルムを配線導体層8および芯体絶縁層1a
表面に積層するとともに熱硬化して厚みが30μmの絶縁
層1bを形成した後、レーザにより配線導体層8上の絶
縁層1bに直径が50μmの貫通孔3を形成した。次に、
絶縁層1bと貫通孔3内部を過マンガン酸塩類水溶液等
の粗化液に浸漬し粗化するとともにパラジウム等の無電
解めっき触媒を被着した後、硫酸銅・ロッセル塩・ホル
マリン・EDTAナトリウム塩・安定剤等から成る無電
解めっき液に約30分間浸漬して絶縁層1b表面および貫
通孔3内部に1〜2μmの無電解銅めっきを析出させ
た。その後、絶縁層1b上の無電解銅めっきを耐めっき
樹脂層で被覆し露光・現像により配線パターンとなる開
口部を形成した後、硫酸・硫酸銅5水和物・塩素・光沢
剤等から成る電解銅めっき液に浸漬し、0.5A/dm2の
電流密度で30分間電解めっきすることにより貫通孔3の
深さ30μmの2/3の厚みである20μmに電解めっき層
の第1層4aを形成し、さらに、1.5A/dm2の電流密
度で10分間電解めっきすることにより10μmの厚さの第
2層4bを形成して貫通孔3を銅導体で充填した。しか
る後、5%水酸化ナトリウム水溶液を用いて耐めっき樹
脂層を剥離した後、硫酸過水系または塩化銅系のエッチ
ング液を用いて耐めっき樹脂層下の無電解めっきをエッ
チング除去することにより貫通導体4および配線導体2
を形成した。EXAMPLES Example 1 A film made of a thermosetting resin and an inorganic filler is used as a wiring conductor layer 8 and a core insulating layer 1a.
After being laminated on the surface and thermally cured to form an insulating layer 1b having a thickness of 30 μm, a through hole 3 having a diameter of 50 μm was formed in the insulating layer 1b on the wiring conductor layer 8 by laser. next,
The insulating layer 1b and the inside of the through-hole 3 are immersed in a roughening solution such as an aqueous solution of permanganates to be roughened, and an electroless plating catalyst such as palladium is deposited, and then copper sulfate, Rossell salt, formalin, EDTA sodium salt It was immersed in an electroless plating solution containing a stabilizer or the like for about 30 minutes to deposit 1-2 μm of electroless copper plating on the surface of the insulating layer 1b and inside the through holes 3. After that, the electroless copper plating on the insulating layer 1b is covered with a plating resistant resin layer, and an opening to be a wiring pattern is formed by exposure and development, and thereafter, it is made of sulfuric acid, copper sulfate pentahydrate, chlorine, a brightener, etc. The first layer 4a of the electroplating layer is immersed in an electrolytic copper plating solution and electrolytically plated at a current density of 0.5 A / dm 2 for 30 minutes to a depth of 20 μm, which is 2/3 of the depth of the through hole 3 of 30 μm. Then, the second layer 4b having a thickness of 10 μm was formed by electrolytic plating at a current density of 1.5 A / dm 2 for 10 minutes, and the through hole 3 was filled with a copper conductor. Then, the anti-plating resin layer is peeled off using a 5% sodium hydroxide aqueous solution, and then the electroless plating under the anti-plating resin layer is removed by etching using a sulfuric acid / hydrogen peroxide-based or copper chloride-based etching solution. Conductor 4 and wiring conductor 2
Was formed.
【0043】上記の本発明の条件範囲で製作した配線基
板5は、貫通孔3が銅導体で良好に充填されるとともに
貫通導体4表面の平滑性に優れ、電子部品6が確実・強
固に接続できる配線基板5であった。In the wiring board 5 manufactured within the above condition range of the present invention, the through hole 3 is well filled with the copper conductor and the surface of the through conductor 4 is excellent in smoothness, so that the electronic component 6 is securely and firmly connected. It was a wiring board 5 that could be formed.
【0044】(比較例1)電解銅めっきを2.5A/dm2
の電流密度で15分間行なう以外は、上記と同様にして製
作した配線基板は、貫通導体の中央部に微細な空洞が形
成されていることが貫通導体の断面の電子顕微鏡観察で
確認され、実装時に配線基板が膨れて電子部品が実装で
きなかった。(Comparative Example 1) Electrolytic copper plating was performed at 2.5 A / dm 2
It was confirmed by electron microscope observation of the cross section of the through conductor that the wiring board manufactured in the same manner as above except that the current density of 15 minutes was used, and a fine cavity was formed in the center of the through conductor. Sometimes the wiring board swelled and electronic parts could not be mounted.
【0045】また、電解銅めっきを0.5A/dm2の電流
密度で60分間行なう以外は、上記と同様にして製作した
配線基板は、貫通孔へのめっき性は良好であったが、エ
ッチング後の銅導体の表面は、金属顕微鏡×400で確認
したところ、径5μmφ程度、高さ2〜4μmの微細な
突起が無数に確認され、実装用電極のニッケル−金めっ
きの厚みが不均一となり、実装用電極と導体バンプとの
接続強度が、2/3に低下した。The wiring board produced in the same manner as above except that the electrolytic copper plating was carried out at a current density of 0.5 A / dm 2 for 60 minutes had good plating properties for the through holes, but after etching. When the surface of the copper conductor of No. 4 was confirmed with a metallurgical microscope × 400, countless minute protrusions with a diameter of about 5 μmφ and a height of 2 to 4 μm were confirmed, and the thickness of the nickel-gold plating of the mounting electrodes became uneven, The connection strength between the mounting electrode and the conductor bump was reduced to 2/3.
【0046】[0046]
【発明の効果】本発明の配線基板によれば、貫通導体を
形成する銅導体を電流密度が0.3〜0.8A/dm2の電解
めっきによる2/3〜3/4の厚みを占める第1層と、
電流密度が1.0〜3.0A/dm2の電解めっきによる残り
の厚みを占める第2層とから形成するとともに、第2層
の表面の結晶粒径を0.1〜2μmとしたことから、銅導
体の形成を短時間で行なうことができ、生産性に優れた
配線基板とすることができ、また、第2層の表面にニッ
ケル−金めっき層を均一に形成することができ、半田バ
ンプとの接続強度が高く、搭載する電子部品と強固に接
続できる配線基板とすることができる。According to the wiring board of the present invention, the copper conductor forming the through conductor is electrolytically plated with a current density of 0.3 to 0.8 A / dm 2 and the first layer occupies a thickness of 2/3 to 3/4. When,
The formation of the copper conductor was made from the second layer occupying the remaining thickness of the electrolytic plating having a current density of 1.0 to 3.0 A / dm 2 and the crystal grain size of the surface of the second layer was 0.1 to 2 μm. Can be performed in a short time, a wiring board with excellent productivity can be obtained, and a nickel-gold plating layer can be uniformly formed on the surface of the second layer, so that the connection strength with solder bumps can be improved. Therefore, it is possible to provide a wiring board which has a high cost and can be firmly connected to the mounted electronic components.
【0047】また、本発明の配線基板によれば、絶縁層
の厚みを15〜50μmとするとともに、貫通孔の径を30〜
200μmとしたことから、電解銅めっき液が貫通孔に容
易に浸透し、貫通孔内への電解銅めっき層の被着充填を
良好とすることができ、その結果、貫通導体内部に空洞
が形成されることはなく、配線基板へ電子部品を実装す
る際の熱で配線基板に膨れが生じることはない。According to the wiring board of the present invention, the thickness of the insulating layer is 15 to 50 μm, and the diameter of the through hole is 30 to 50 μm.
Since the thickness is set to 200 μm, the electrolytic copper plating solution can easily penetrate into the through holes, and the deposition of the electrolytic copper plating layer into the through holes can be favorably performed. As a result, cavities are formed inside the through conductors. Therefore, the wiring board will not be swollen by the heat when the electronic component is mounted on the wiring board.
【0048】本発明の電子装置によれば、上記の配線基
板の表面に電子部品を実装するとともに、電子部品の電
極を配線導体または貫通導体に電気的に接続して成るこ
とから、電子部品と配線基板との接続が強固な電子装置
とすることができる。According to the electronic device of the present invention, the electronic component is mounted on the surface of the wiring board, and the electrode of the electronic component is electrically connected to the wiring conductor or the through conductor. An electronic device having a strong connection with the wiring board can be provided.
【図1】図1は本発明の配線基板に電子部品を搭載して
成る電子装置の実施の形態の一例を示す断面図である。FIG. 1 is a cross-sectional view showing an example of an embodiment of an electronic device in which an electronic component is mounted on a wiring board of the present invention.
【図2】図2は、本発明の配線基板の要部拡大断面図で
ある。FIG. 2 is an enlarged sectional view of an essential part of the wiring board of the present invention.
1・・・・・・・・絶縁層 1a・・・・・・・芯体絶縁層 1b・・・・・・・絶縁層 2・・・・・・・・配線導体 2a・・・・・・・実装用電極 3・・・・・・・・貫通孔 4・・・・・・・・貫通導体 4a・・・・・・銅導体の第1層 4b・・・・・・銅導体の第2層 5・・・・・・・・配線基板 6・・・・・・・・電子部品 7・・・・・・・・電子装置 A・・・・・・・・銅導体の厚み X・・・・・・・・銅導体の第1層の厚み Y・・・・・・・・銅導体の第2層の厚み 1 ... Insulation layer 1a .... Insulating layer of core 1b ... Insulating layer 2 ... Wiring conductor 2a ...- Mounting electrodes 3 ... through-hole 4 ... Penetration conductor 4a ... First layer of copper conductor 4b .... Second layer of copper conductor 5 ... Wiring board 6 ... Electronic parts 7 ... Electronic device A ・ ・ ・ ・ ・ ・ Copper conductor thickness X ... Thickness of the first layer of the copper conductor Y ... Thickness of second layer of copper conductor
Claims (3)
層されるとともに上下の前記配線導体間を前記絶縁層に
形成された貫通孔を電解めっき法による銅導体で充填し
て成る貫通導体により電気的に接続して成る配線基板に
おいて、前記銅導体は、電流密度が0.3〜0.8A/
dm2の電解めっきによる2/3〜3/4の厚みを占め
る第1層と、電流密度が1.0〜3.0A/dm2の電
解めっきによる残りの厚みを占める第2層とから成ると
ともに、該第2層の表面の結晶粒径が0.1〜2μmで
あることを特徴とする配線基板。1. A through conductor formed by alternately stacking a plurality of insulating layers and wiring conductors and filling a through hole formed in the insulating layer between upper and lower wiring conductors with a copper conductor by electrolytic plating. In the wiring board electrically connected, the copper conductor has a current density of 0.3 to 0.8 A /
It is composed of a first layer occupying a thickness of 2/3 to 3/4 by electrolytic plating of dm 2 , and a second layer occupying the remaining thickness of electrolytic plating having a current density of 1.0 to 3.0 A / dm 2. In addition, the crystal grain size of the surface of the second layer is 0.1 to 2 μm.
るとともに、前記貫通孔の径が30〜200μmである
ことを特徴とする請求項1記載の配線基板。2. The wiring board according to claim 1, wherein the insulating layer has a thickness of 15 to 50 μm, and the through hole has a diameter of 30 to 200 μm.
の表面に電子部品を実装するとともに、該電子部品の電
極を前記配線導体または前記貫通導体に電気的に接続し
て成ることを特徴とする電子装置。3. An electronic component is mounted on the surface of the wiring board according to claim 1 or 2, and an electrode of the electronic component is electrically connected to the wiring conductor or the through conductor. And electronic device.
Priority Applications (1)
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JP2001300759A JP2003110241A (en) | 2001-09-28 | 2001-09-28 | Wiring board and electronic device using the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001300759A JP2003110241A (en) | 2001-09-28 | 2001-09-28 | Wiring board and electronic device using the same |
Publications (1)
Publication Number | Publication Date |
---|---|
JP2003110241A true JP2003110241A (en) | 2003-04-11 |
Family
ID=19121287
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Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2001300759A Withdrawn JP2003110241A (en) | 2001-09-28 | 2001-09-28 | Wiring board and electronic device using the same |
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JP (1) | JP2003110241A (en) |
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