JP2007273896A - Wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a wiring board capable of increasing the adhesion strength between an insulating layer and a wiring conductor without forming irregularities on the surface.
A wiring substrate 3 includes a core substrate 4, a plurality of wiring conductors 2, an insulating layer 5 and a via conductor 9, and a material including an alloy of copper and tin in a predetermined region of the surface portion of the wiring conductor 2. Therefore, the surface portion of the wiring conductor 2 can be made smooth, and the adhesion strength between the wiring conductor 2 and the insulating layer 5 can be increased.
[Selection] Figure 1

Description

  The present invention relates to a wiring board, and more particularly to a wiring board capable of increasing the adhesion strength between a wiring conductor and an insulating layer.

  As represented by mobile communication devices, electronic devices are required to be smaller, thinner, lighter, higher performance, higher functionality, higher quality, and higher reliability. There is an increasing demand for smaller and higher density electrical devices. Therefore, miniaturization, thinning, and multi-terminals have also been demanded for wiring boards constituting electrical devices. To achieve this, the width of the wiring conductor is narrowed and the interval between the wiring conductors is narrowed. High-density wiring is achieved by multilayering.

  In the first conventional technique, a wiring board manufactured by adopting a build-up method is disclosed as a wiring board capable of such high-density wiring. The build-up wiring board is formed by impregnating a reinforcing material such as glass cloth and aramid non-woven fabric with a thermosetting resin typified by an epoxy resin having heat resistance and chemical resistance to form a cured core. On this core, a varnish made of a thermosetting resin such as an epoxy resin is applied and heat-cured to form an insulating layer, and then a through-hole having a diameter of about 200 μm is drilled in the insulating layer with a laser. Next, the inner wall of the through hole and the surface of the insulating layer are chemically roughened with a roughening solution such as a potassium permanganate solution, and copper is applied to the inner wall of the through hole and the surface of the insulating layer using an electroless copper plating method and an electrolytic copper plating method. A conductor film is deposited to form a through conductor and a wiring conductor. In this way, the entire surface of the wiring conductor is roughened to ensure adhesion between the epoxy resin of the insulating layer and the copper wiring by a physical anchor effect. A wiring board is manufactured by forming a plurality of insulating layers, wiring conductors, and through conductors by repeating the same process as described above on this insulating layer (see, for example, Patent Document 1).

  In the second conventional technique, a wiring conductor manufactured by a build-up method using a full additive that forms a wiring conductor by electroless copper plating is disclosed (for example, see Patent Document 2).

JP-A-10-261869 JP-A-9-130050

  In the first conventional technique, there is a possibility that the propagation speed of the electric signal is reduced and noise is generated due to the unevenness of the surface portion formed by the roughening treatment. Therefore, there is a problem that the increase in processing speed is hindered.

  Moreover, the roughening process given to the main surface of a wiring conductor is also given to the side surface side of a wiring conductor, and there also exists a problem that a high frequency characteristic worsens.

  In the second conventional technique, since the adhesion strength between the wiring conductor and the insulating layer is weak, there is a possibility that the wiring conductor and the insulating layer are peeled off, and there is a problem that connection reliability is low. As a technique for solving such a problem, the present applicant has found that the adhesion strength between the wiring conductor and the insulating layer can be increased by plating the wiring conductor made of copper with another metal. However, when tin is plated on copper, there is a problem that electroless copper plating is difficult to adhere.

  Accordingly, an object of the present invention is to provide a wiring board that suppresses noise generation while improving the adhesion strength between the insulating layer and the wiring conductor.

A wiring board formed by laminating a plurality of wiring conductors on a core board through an insulating layer made of resin,
A via conductor that is formed by a copper plating method and penetrates the core substrate or the insulating layer in the substrate thickness direction to electrically connect different wiring conductors;
An alloy portion made of a material containing an alloy of copper and tin is formed on the surface portion of the plurality of wiring conductors, and the alloy portion is separated from a connection portion where the via conductor and the wiring conductor are connected to each other. A wiring board is provided.

  Further, the invention is characterized in that the alloy portion is formed over the entire surface portion of the plurality of wiring conductors in a wiring conductor provided apart from the via conductor.

  Furthermore, the present invention is characterized in that the alloy part has a thickness dimension of 50 nm or more and 1500 nm or less.

  Furthermore, the present invention is characterized in that the alloy portion gradually increases as the tin concentration in the alloy moves toward the surface portion of the wiring conductor.

Furthermore, the present invention is characterized in that the alloy part includes Cu ₆ Sn ₅ and Cu ₃ Sn, and Cu ₆ Sn ₅ is distributed more on the surface side of the wiring conductor than Cu ₃ Sn. .

  Furthermore, the present invention is characterized in that a plurality of concave portions are formed in the surface portion of the alloy portion.

Further, according to the present invention, the alloy portion is formed in a remaining region excluding an annular region around the via conductor,
The via conductor is directly attached to the wiring conductor in the annular region.

  Furthermore, the present invention is characterized in that the thickness dimension of the alloy portion is gradually reduced toward the via conductor.

  According to the present invention, the wiring substrate includes a core substrate, a plurality of wiring conductors, an insulating layer, and a via conductor. In the plurality of wiring conductors, an alloy portion made of a material containing an alloy of copper and tin is formed at least in a predetermined region of the surface portion. The alloy portion is formed away from a connection portion where the via conductor and the wiring conductor are connected to each other. Thus, the region where the alloy portion is formed can increase the adhesion strength with the insulating layer made of resin by an alloy of copper and tin. Further, since the surface portion of the wiring conductor can be smoothed by the alloy portion, it is possible to prevent a decrease in the propagation speed of the electric signal and to suppress the generation of noise due to the shape of the surface portion. By using such a wiring board, the processing speed of the semiconductor device can be increased.

  Further, the region where the alloy portion is formed excludes a connecting portion where the via conductor and the wiring conductor are connected to each other. Since the via conductor is formed by a copper plating method, when the via conductor is formed in the alloy portion by tin contained in the alloy portion, the adhesive strength between the alloy portion and the via conductor is low, and thus repeated stress, etc. However, by removing the aforementioned connection region, the adhesion strength between the wiring conductor and the insulating layer can be increased without deteriorating the connection reliability between the via conductor and the wiring conductor. Further, by forming the alloy portion, the adhesion between the wiring conductor and the insulating layer is improved, and the substrate can be prevented from swelling during heating such as solder reflow after moisture absorption. As described above, since the adhesion between the wiring conductor and the insulating layer can be ensured, even when a temperature change is applied to the wiring board, delamination (delamination) between the insulating layers is suppressed, and the insulating layer and the wiring conductor are suppressed. No cracks are generated at the interface between the wiring conductor and the disconnection of the wiring conductor caused by the extension of the cracks.

  According to the invention, among the plurality of wiring conductors, the alloy portion is formed over the entire surface portion of the wiring conductor provided apart from the via conductor. Since the wiring conductor provided apart from the via conductor has no connection region connected to the via conductor, an alloy portion is formed over the entire surface portion, and the adhesion strength between the wiring conductor and the insulating layer and the entire surface portion are formed. Can be bigger.

  Furthermore, according to the present invention, the alloy portion has a thickness dimension of not less than 50 nm and not more than 1500 nm. If the thickness dimension of the alloy part is less than 50 nm, the adhesion strength between the wiring conductor and the insulating layer is lowered, and problems such as peeling of the wiring conductor and swelling of the substrate in the solder reflow process after moisture absorption occur. On the other hand, when the thickness dimension of the alloy part exceeds 1500 nm, the electromagnetic resistance of the wiring conductor increases and the high-frequency transmission characteristics deteriorate. Therefore, when the thickness of the alloy part is 50 nm or more and 1500 nm or less, the adhesion strength between the wiring conductor and the insulating layer can be ensured, and the high-frequency transmission characteristics can be prevented from deteriorating.

  Furthermore, according to the present invention, the alloy portion gradually increases as the tin concentration in the alloy moves toward the surface portion of the wiring conductor. Thereby, the adhesion strength between the surface portion of the wiring conductor and the insulating layer can be increased.

Further, according to the present invention, the alloy portion includes Cu ₆ Sn ₅ and Cu ₃ Sn, and Cu ₆ Sn ₅ is distributed more on the surface side of the wiring conductor than Cu ₃ Sn. Accordingly, since the tin concentration is higher on the surface side of the wiring conductor, the adhesion strength between the surface portion of the wiring conductor and the insulating layer can be increased.

Furthermore, according to the present invention, since a plurality of recesses are formed on the surface portion of the alloy portion, the adhesion between the conductor and the insulating resin is further improved.
Further, according to the present invention, the alloy portion is formed in a remaining region excluding an annular region around the via conductor, and the via conductor is directly attached to the wiring conductor in the annular region. . Thereby, since the via conductor is formed by a copper plating method, when the via conductor is formed in the alloy portion by tin contained in the alloy portion, the adhesion strength between the alloy portion and the via conductor is small, Although there is a risk of breakage due to repeated stress, etc., the adhesion strength between the via conductor and the wiring conductor can be improved without impairing the connection reliability by directly attaching the via conductor and the wiring conductor in the aforementioned annular region. Can be bigger.

  Furthermore, according to the present invention, the thickness dimension of the alloy portion is gradually reduced toward the via conductor. When a wiring conductor having an alloy part is heated and cooled, the alloy part and the remaining part excluding the alloy part may be peeled off due to thermal stress or the like, but by gradually reducing the thickness dimension of the alloy part, , It is possible to prevent the peeling force from being concentrated on the end of the alloy part. Thereby, the tolerance with respect to the thermal stress of a wiring conductor can be improved.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing an electronic device 1 according to an embodiment of the present invention. FIG. 2 is an enlarged cross-sectional view of section II in FIG. In FIG. 2, the part regarding the wiring conductor 2 which comprises the electronic apparatus 1 is expanded and shown. The electronic device 1 includes a wiring board 3 and an electronic element 16 mounted on the wiring board 3. The wiring substrate 3 includes a core substrate 4, a plurality of insulating layers 5, and a plurality of wiring conductors 2.

  The core substrate 4 is formed by temporarily curing a sheet obtained by impregnating a glass cloth in which glass fibers are woven vertically and horizontally with a thermosetting resin such as an epoxy resin and a bismaleimide triazine resin. The core substrate 4 has a thickness dimension of, for example, not less than 0.3 mm and not more than 1.5 mm. In the core substrate 4, a sheet in which a glass cloth is impregnated with an uncured thermosetting resin is thermally cured, and then a through hole 6 penetrating in the thickness direction is formed by drilling or laser processing.

  A plurality of through holes 6 are formed and have a diameter of, for example, about 0.1 mm to 1.0 mm. A through-hole conductor 7 made of a copper film is deposited on the inner wall of the through-hole 6. The through-hole conductors 7 electrically connect different wiring conductors 2 formed on both side portions of the through-hole conductor 7 in the axial direction. The through-hole conductor 7 is formed by forming a through-hole 6 in the core substrate 4 and then depositing a copper plating film having a thickness dimension of, for example, 3 μm to 50 μm in the through-hole 6 by a plating method. The through-hole conductor 7 is configured in a cylindrical shape, for example.

  The inside of the through-hole conductor 7 is filled with a thermosetting resin such as an epoxy resin or a bismaleimide triazine resin, and a resin material 22 is provided. The resin material 22 is for making it possible to form the insulating layer 5 or the wiring conductor 2 immediately above and below the through hole 6 by closing the through hole 6. The resin material 22 is formed by filling an uncured paste-like thermosetting resin into the through hole 6 by screen printing, thermally curing it, and then polishing both end surfaces in the thickness direction substantially flatly. Is done. Further, in order to reduce the resistance of the through-hole conductor 7, a conductor paste may be filled instead of the resin material 22.

  The insulating layer 5 is made of a thermosetting resin such as an epoxy resin and a modified polyphenylene ether resin. The insulating layer 5 is formed by being adhered to one surface portion in the thickness direction of the temporarily cured core substrate 4 and thermally cured. The insulating layer 5 is formed by sticking an uncured thermosetting resin film to both end surfaces of the thickness of the core substrate 4 and thermally curing the film, and via holes 8 are formed by laser processing. The insulating layer 5 is laminated on both end surfaces in the thickness direction of the core substrate 4, and each thickness dimension is, for example, about 10 μm to 80 μm.

  Each insulating layer 5 penetrates in the thickness direction, and a via hole 8 having a diameter of, for example, 20 μm to 100 μm is formed. A via conductor 9 made of a copper film is deposited on the inner wall of the via hole 8 by a copper plating method. The via conductors 9 electrically connect the wiring conductors 2 formed on both sides of the via conductor 9 in the axial direction. Therefore, the insulating layer 5 is for providing an insulation interval for wiring the wiring conductor 2 with high density. Further, by electrically connecting the upper layer wiring conductor 2 and the lower layer wiring conductor 2 via the via conductor 9, a high density wiring can be formed three-dimensionally. After the insulating layer 5 is laminated on the core substrate 4, the wiring conductor 2 is formed on the insulating layer 5. In addition, there is a form in which the wiring conductor 2 is formed directly on the core substrate 4. In such a form, after the insulating layer 5 is laminated on the wiring conductor 2, another wiring conductor 2 is formed. The Thus, the insulating layer 5 having the wiring conductor 2 and the via conductor 9 is formed, and the wiring substrate 3 is formed by sequentially stacking the insulating layers 5 as described above.

  The wiring conductor 2 is formed on the surface portion of the insulating layer 5 except for the wiring conductor 2 formed directly on the core substrate 4 in advance. Among the plurality of wiring conductors 2, at least one wiring conductor 2 is electrically connected by a via conductor 9 that penetrates the insulating layer 5 in the thickness direction that is the substrate thickness direction. The wiring conductor 2 located between different layers via the insulating layer 5 includes a through-hole conductor 7 provided through the core substrate 4 in the thickness direction, and a via conductor 9 provided through the insulating layer 5 in the thickness direction. Thus, a desired wiring circuit is formed.

  In the plurality of wiring conductors 2, an alloy portion 10 made of a material containing an alloy of copper and tin is formed at least in a predetermined region of the surface portion. The region where the alloy portion 10 is formed is the remaining region excluding the connection portion 30 where the via conductor 9 and the wiring conductor 2 are connected to each other. Therefore, the alloy portion 10 is formed in the remaining region excluding the annular region around the via conductor 9. As a result, in the annular region around the via conductor 9, the wiring conductor 2 is formed by the existing copper plating method excluding the alloy portion 10. In the annular region, the via conductor 9 is directly attached to the wiring conductor 2.

  As shown in FIG. 1, among the plurality of wiring conductors 2, the alloy portion 10 is formed over the entire surface portion in the thickness direction of the wiring conductor 2 provided away from the via conductor 9. As shown in FIG. 2, the wiring conductor 2 includes a copper portion 11 and an alloy portion 10. The copper portion 11 is mainly composed of copper, and is laminated on the core substrate 4 and the insulating layer 5 by an electroless plating method and an electrolytic plating method. The alloy part 10 is made of an alloy of copper and tin, and by laminating tin on the copper part 11 by electrolytic plating, the copper and tin react to form an alloy of copper and tin. Therefore, the wiring conductor 2 is configured by laminating the layered alloy portion 10 on the layered copper portion 11. These are etched to form a predetermined pattern.

The thickness dimension of the copper part 11 is 3 micrometers or more and 20 micrometers or less, for example. Moreover, the thickness dimension of the alloy part 10 is 50 nm or more and 1500 nm or less, for example. The alloy portion 10 gradually increases as the tin concentration in the alloy moves toward the surface portion of the wiring conductor 2. Accordingly, the wiring conductor 2 is configured such that the surface portion on one side in the thickness direction has the highest tin concentration compared to the remaining portion. The alloy part 10 includes Cu ₆ Sn ₅ and Cu ₃ Sn, and Cu ₆ Sn ₅ is distributed more on the surface side of the wiring conductor 2 than Cu ₃ Sn. The portion 12 made of Cu ₆ Sn ₅ is configured closer to one surface portion in the thickness direction of the wiring conductor 2 than the portion 13 made of Cu ₃ Sn. For example, the thickness dimension of a portion made of Cu ₆ Sn ₅ is not less than 30 nm and not more than 1400 nm. For example, the thickness dimension of a portion made of Cu ₃ Sn is not less than 20 nm and not more than 1400 nm.

In the present embodiment, alloy portion 10 may include tin oxide 14 on one surface portion in the thickness direction. Specifically, the tin oxide 14 is composed of a layer 15 made of Cu _x Sn _y O _z , a layer 16 made of SnO, and SnO _{2 on} one surface in the thickness direction of a portion made of Cu ₆ Sn _5. Layers 17 are sequentially stacked. The thickness dimension of the layer 15 made of Cu _x Sn _y O _z is, for example, not less than 5 nm and not more than 100 nm. The thickness dimension of the layer 16 made of SnO is, for example, not less than 10 nm and not more than 100 nm. The thickness dimension of the layer 17 made of SnO ₂ is, for example, not less than 10 nm and not more than 100 nm.

  A plurality of recesses are formed in the surface portion of the alloy portion 10. When forming a plurality of recesses, first, a plurality of recesses are formed on the surface of the copper part 11, and the alloy part 10 is formed on the copper part 11 on which the recesses are formed. The shape of the portion 11 is reflected, and a plurality of recesses are formed. When forming a plurality of recesses, for example, substitutional electroless plating is used. In substitutional electroless plating, a plating portion constituting the alloy portion 10 is adhered while melting a part of the surface portion of the copper portion 11. For this reason, the alloy part 10 is formed on the copper part 11 and a plurality of fine recesses are formed at the same time by selecting the conditions of the plating process, for example, the processing time, the pH of the processing solution, and the processing temperature. .

  For the treatment of substitutional electroless plating, for example, a treatment solution having a pH of 4.5 or less is preferably used, a treatment temperature of 50 ° C. or less and a treatment time of 20 minutes or less. When the processing temperature exceeds 50 ° C. or the processing time exceeds 20 minutes, a recess exceeding 3 μm is formed, which adversely affects high-speed digital signal transmission. The optimum treatment temperature is 35 ° C. or less, and the treatment time is within 5 minutes. Under this condition, a plurality of recesses having a depth of 50 nm or more and 1500 nm or less are formed. Moreover, if the pH of the treatment liquid selected for the treatment of substitutional electroless plating is adjusted within the range of 1.0 to 3.0, the treatment time can be further shortened.

  The depth dimension of the recess is set to be equal to or less than the thickness dimension of the alloy portion 10. The depth of the concave portion is preferably a fine dimension of 50 nm to 1500 nm. If the depth of the recess is less than 50 nm, the effect of improving the adhesion strength is small, and if it exceeds 1500 nm, the surface unevenness increases, so that the skin effect of the high-speed digital signal tends to adversely affect signal transmission.

  The diameter of the recess is preferably 50 nm or more and 500 nm or less. If the diameter of the recess is less than 50 nm, the effect of improving the adhesion strength is small, and if it is 500 nm or more, the surface unevenness tends to increase, which tends to adversely affect the transmission of high-speed digital signals.

  When tin is plated on the copper portion 11 by substitutional electroless plating, an alloy portion 10 made of an alloy of copper and tin and having a plurality of recesses is formed.

  The thickness dimension of the alloy portion 10 of the wiring conductor 2 is gradually reduced toward the via conductor 9. The range in which the outer peripheral portion of the alloy portion 10 gradually decreases is preferably 0.2 μm or more and 5 μm or less. If the thickness is less than 0.2 μm, the effect of relaxing the stress concentration is small, and the region in contact with the insulating layer 5 exceeding 5 μm becomes too small, so that the adhesion strength is lowered. In addition, it is necessary to enlarge the connection portion of the via conductor 9, and the wiring density is reduced.

As a method of manufacturing the gradually decreasing portion, a method using a difference in speed between surface diffusion and internal diffusion when the alloy portion 10 is plated on the copper portion 11 is used. That is, the alloy part 10 is formed in the copper part 11 and heated to a temperature of, for example, 60 ° C. or more and 150 ° C. or less to diffuse the plated alloy part 10 to the surface and inside. Since the surface diffusion is faster than the internal diffusion, the alloy portion 10 diffuses to the surface and then gradually diffuses to the inside. By setting the heating temperature after plating the alloy portion 10 within the above-mentioned range, the thickness dimension of the alloy portion 10 is, for example, not less than 50 nm and not more than 1500 nm, and includes Cu ₆ Sn ₅ and Cu ₃ Sn, for example, Cu ₆ Sn ₅ The thickness dimension of the portion consisting of 30 nm or more and 1400 nm or less, for example, the thickness dimension of the portion consisting of Cu ₃ Sn is 20 nm or more and 1400 nm or less, and the gradually decreasing range is 0.2 μm or more and 5 μm or less Can be formed.

  The electronic device 1 is configured by mounting an electronic element 16 such as a semiconductor element on one surface portion in the thickness direction of the wiring board 3 via a solder bump 17. In the present embodiment, a solder ball 18 or the like is formed on the surface of the wiring board 3 opposite to the surface on which the electronic element 16 is mounted, and the solder ball 18 is connected to, for example, a printed circuit board via the solder ball 18. . A solder resist may be formed on the surface of the wiring substrate 3, and an underfill may be formed between the wiring substrate 3 on which the solder resist is formed and the electronic element 16.

  A part of the wiring conductor 2 formed on one outermost surface of the insulating layer 5 is joined to each electrode of the electronic element 16 via a solder bump 17 made of, for example, lead-tin. 19 is formed. Further, a part of the wiring conductor 2 formed on the surface of the other outermost layer of the insulating layer 5 is connected to each electrode of the external printed circuit board via a solder ball 18 made of, for example, lead-tin. A pad 20 is formed.

  The surface portion of the wiring conductor 2 to be the bonding pads 19 and 20 has good wettability with solder and resistance to prevent oxidative corrosion and good connection with the solder bumps 17 and the solder balls 18. A nickel and gold plating layer with excellent corrosion properties is applied.

  A solder resist layer 21 having an opening exposing the bonding pads 19 and 20 is attached to the bonding pads 19 and 20. Such a solder resist layer 21 is applied with an uncured resin film composed of a photosensitive resin, a photoinitiator, and an inorganic powder filler, or an uncured resin varnish composed of a thermosetting resin and an inorganic powder filler, or After laminating the uncured resin film, an opening is formed by exposure and development, and this is applied by UV curing and heat curing.

  The solder bumps 17 are made of a conductive material of an alloy such as lead-tin, tin-zinc and tin-silver-bismuth. For example, in the case of solder made of lead-tin, a solder paste made of lead-tin is used as the solder resist layer 21. The bonding pad 19 exposed with the opening is filled by screen printing and passed through a reflow furnace to be hemispherically fixed on the bonding pad 19. By mounting the electronic element 16 by bonding each electrode of the electronic element 16 to the bonding pad 19 via the solder bump 17, the electronic device 1 of the present invention is obtained.

  Next, a method for manufacturing the electronic device 1 according to the present embodiment will be described. FIG. 3 is a cross-sectional view showing a part of the manufacturing process of the electronic device 1 step by step. FIG. 3 shows a case where the insulating layer 5 and the via conductor 9 are sequentially formed on the wiring conductor 2 laminated on the core substrate 4. FIG. 4 is a flowchart showing a part of the manufacturing method of the electronic device 1. As shown in FIG. 3A (a), the core substrate 4 on which the wiring conductor precursor 33 is formed is prepared, and the process proceeds to step a1. The wiring conductor precursor 33 is a precursor of the wiring conductor 2 and is made of copper, and the alloy portion 10 is not formed.

  In step a1, as shown in FIG. 3A (b), the photosensitive film 31 is attached to one surface portion of the wiring conductor precursor 33, and the process proceeds to step a2. The photosensitive film 31 is made of a photosensitive resin material. In step a2, as shown in FIG. 3A (c), the photosensitive film 31 is etched by a photolithography technique to form a plating mask portion 32, and the process proceeds to step a3. Specifically, a photomask is placed on the photosensitive film 31 for exposure. The exposed portion of the resin is cured, and the remaining uncured portion is dissolved (etched) and removed with a developer. This is called a development process. By this development process, a part of the photosensitive film 31 is etched to reach the wiring conductor precursor 33 to expose a part of the wiring conductor precursor 33. Thereby, the plating mask part 32 is formed. When the plating mask portion 32 is formed, the process proceeds to step a3.

  In step a3, as shown in FIG. 3A (d), the alloy portion 10 which is the alloy layer 26 is formed, the wiring conductor 2 is formed from the wiring conductor precursor 33, and the process proceeds to step a4. First, the wiring conductor precursor 33 exposed by vapor deposition, sputtering, electrolytic plating, electroless plating, or the like is plated with tin, for example, 0.1 μm, and then the plated tin layer and the wiring conductor precursor 33 are heated to 105 ° C. By heating at a temperature for 1 hour, the plated tin is alloyed to form an alloy portion 10 made of an alloy of copper and tin, and the wiring conductor 2 is formed. Therefore, the alloy portion 10 is not formed in the region of the wiring conductor precursor 33 covered with the plating mask portion 32. Further, as described above, at the same time when the alloy portion 10 is formed, a plurality of minute recesses (not shown) are formed on one surface portion of the wiring conductor 2. Such a recess is formed simultaneously with the formation of the alloy portion 10 in step a7 as described above.

  In step a4, as shown in FIG. 3A (e), the plating mask portion 32 is removed from the wiring conductor 2, and the process proceeds to step a5. In step a5, as shown in FIG. 3B (f), the resin film 31 that is a precursor of the insulating layer is pasted so as to cover the entire area of one surface portion of the wiring conductor 2 and the core substrate 4, and the process proceeds to step a6. . The resin film 31 is made of an insulating resin.

  In step a6, as shown in FIG. 3B (g), via holes 8 are formed in the resin film 31, an insulating layer is formed, and the process proceeds to step a7. The via hole 8 is formed by laser processing, for example. The via hole 8 is formed so as to expose the wiring conductor 2, and the exposed region is substantially the same as the region where the plating mask portion 32 is formed.

  In step a7, as shown in FIG. 3B (h), an electroless copper plating layer 35 is formed in a region where one surface portion of the insulating layer 5 and the wiring conductor 2 are exposed by via holes, and the process proceeds to step a8. When the electroless copper plating layer 35 is formed on the insulating layer 5, first, a palladium catalyst for electroless plating is deposited on the insulating layer 5. Specifically, one surface portion of the insulating layer 5 is immersed in a roughening solution such as a 50 ° C. permanganate aqueous solution for 15 minutes for roughening, and then the insulating layer 5 is palladium for electroless plating at 30 ° C. Immerse in an aqueous solution of the catalyst for 5 minutes to allow the palladium catalyst to adhere to one surface of the insulating layer 5.

  Next, the insulating layer 5 is immersed in an electroless plating solution at 60 ° C. made of copper sulfate, Rossell salt, formalin, EDTA sodium salt and a stabilizer for about 30 minutes, so that the insulating layer 5 has a thickness of 0.1 μm or more in a predetermined region. An electroless copper plating layer 35 of about 2 μm or less is deposited.

  In step a8, as shown in FIG. 3B (i), the electrolytic copper plating layer 33 and the via conductor 9 as the wiring conductor precursor 33 are formed, and the process proceeds to step a9. In order to form the electrolytic copper plating layer 33 having a predetermined pattern, for example, a semi-additive method or a subtractive method is used. In the present embodiment, the semi-additive method will be described in detail. First, a plating-resistant resin layer is deposited on the electroless copper plating layer 35. The plating-resistant resin layer is made of, for example, a photosensitive resin having a thickness of 10 μm or more and 30 μm or less, and is deposited by laminating. Next, a part of the plating-resistant resin layer is removed into a pattern shape of the wiring conductor 2 by exposure and development, and an opening for depositing the electrolytic copper plating layer 33 is formed.

Next, sulfuric acid, while applying copper sulfate pentahydrate, the electrolytic copper plating solution 2A / dm ² or more 5A / dm ² or less of the current consisting of a chlorine or brighteners, to the insulating layer 5 is immersed for several hours Thus, the electrolytic copper plating layer 33 having a thickness of 3 μm or more and 20 μm or less and the via conductor 9 filled in the via hole 8 are formed in the opening.

  Next, the plating resistant resin layer is removed with a 30 ° C. aqueous sodium hydroxide solution, and the electroless copper plating layer 35 exposed by removing the plating resistant resin layer 23 is further treated with sulfuric acid, hydrogen peroxide water and 25 ° C. Etching is removed with a sulfuric acid aqueous solution such as copper sulfate for 5 minutes. Thereby, the wiring conductor precursor 33 which is the electrolytic copper plating layer 33 having a predetermined pattern is formed.

  In step a9, it is determined whether or not the build-up process is completed. If the wiring conductor 2 is further laminated via the insulating layer 5, the process returns to step a1, and if the build-up process is completed, this flow is terminated. .

  3B (j), FIG. 3C (k) to FIG. 3C (n), and FIG. 3D (o) to FIG. 3D (q), the insulating layer 5 and the wiring conductor 2 are further formed in the above-described step a9. It is a figure which shows the process in the case. 3B (j) corresponds to the aforementioned step a1, FIG. 3C (k) corresponds to the aforementioned step a2, FIG. 3C (k) corresponds to the aforementioned step a2, and FIG. 3C (l) Corresponds to the aforementioned step a3, FIG. 3C (m) corresponds to the aforementioned step a4, FIG. 3C (n) corresponds to the aforementioned step a5, and FIG. 3D (o) corresponds to the aforementioned step a4. 3D (p) corresponds to step a7 described above, and FIG. 3D (q) corresponds to step a8 described above. In FIG. 3D (q), as described above, a bonding pad 19 for connecting an electronic component is formed on a part of the wiring conductor 2 formed on the surface of one outermost layer of the insulating layer 5. Also, a solder resist layer 21 having an opening for exposing the bonding pad 19 is attached to one outermost layer surface of the insulating layer 5. The wiring board 3 is manufactured by such a manufacturing method.

  In addition, the manufacturing method of this invention is not limited to an example of the above-mentioned embodiment, In the range which does not deviate from the summary of this invention, a various change and improvement are possible. For example, in the wiring substrate 3 described above, the insulating layer 5 is laminated only on one surface in the thickness direction, and the wiring conductor 2 is formed on the insulating layer 5, but the insulating layer 5 is laminated on both sides in the thickness direction. The wiring conductor 2 may be formed on both sides. Further, the wiring conductors 2 formed on the both surface portions may be electrically connected by through-hole conductors 7 formed inside the insulating layer 5.

  As described above, the wiring board 3 of the present embodiment includes the core substrate 4, the plurality of wiring conductors 2, the insulating layer 5, and the via conductor 9. An alloy portion 10 made of a material containing an alloy of copper and tin is formed on the surface portions of the plurality of wiring conductors 2. The alloy portion 10 is formed away from the connection portion 30 where the via conductor 9 and the wiring conductor 4 are connected to each other. Thus, in the region where the alloy portion 10 is formed, the adhesion strength with the insulating layer 5 made of resin can be increased by the alloy portion 10 made of a material containing copper and tin. Further, since the surface portion of the wiring conductor 4 can be smoothed by the alloy portion 10, it is possible to prevent a decrease in the propagation speed of the electric signal caused by the shape of the surface portion and to suppress the generation of noise. it can. If such a wiring board is used, the processing speed of the semiconductor device can be increased.

  According to the electronic device 1 of the present embodiment, the electronic component is mounted on the main surface of the wiring board 3 and the wiring conductor 2 and each electrode of the electronic component are electrically connected. In addition, it is possible to obtain a highly reliable electronic device 1 in which the wiring conductor 2 is not broken while the insulating property is good.

It is sectional drawing which shows the electronic device 1 of one Embodiment of this invention. It is an expanded sectional view of the section II in FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the electronic device 1 in stages. FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the electronic device 1 in stages. FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the electronic device 1 in stages. FIG. 4 is a cross-sectional view showing a part of the manufacturing process of the electronic device 1 in stages. FIG. 4 is a flowchart showing a part of the manufacturing method of the electronic device 1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic device 2 Wiring conductor 3 Wiring board 4 Core board 5 Insulating layer 6 Through hole 7 Through hole conductor 8 Via hole 9 Via conductor 10 Alloy part 11 Copper part

Claims (8)

A wiring board formed by laminating a plurality of wiring conductors on a core board through an insulating layer made of resin,
A via conductor that is formed by a copper plating method and penetrates the core substrate or the insulating layer in the substrate thickness direction to electrically connect different wiring conductors;
An alloy portion made of a material containing an alloy of copper and tin is formed on the surface portion of the plurality of wiring conductors, and the alloy portion is separated from a connection portion where the via conductor and the wiring conductor are connected to each other. A wiring board characterized by being provided.   2. The wiring board according to claim 1, wherein among the plurality of wiring conductors, a wiring conductor provided apart from the via conductor has the alloy portion formed over the entire surface portion.   The wiring board according to claim 1, wherein the alloy part has a thickness dimension of 50 nm or more and 1500 nm or less.   The wiring board according to any one of claims 1 to 3, wherein the alloy portion is gradually increased in a tin concentration in the alloy toward a surface portion of the wiring conductor. The alloy part includes Cu ₆ Sn ₅ and Cu ₃ Sn, and a larger amount of Cu ₆ Sn ₅ is distributed on the surface side of the wiring conductor than Cu ₃ Sn. Wiring board.   The wiring board according to claim 1, wherein a plurality of concave portions are formed on a surface portion of the alloy portion. The alloy portion is formed in the remaining region excluding the annular region around the via conductor,
The wiring board according to claim 1, wherein the via conductor is directly attached to the wiring conductor in the annular region.   The wiring board according to claim 1, wherein a thickness dimension of the alloy portion is gradually reduced toward the via conductor.

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