JP2002297101A - Liquid crystal display, and portable telephone and personal digital assitance provided therewith - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device that can be operated with a low power consumption without damaging the display quality. SOLUTION: The liquid crystal display device according to the embodiment includes two display modes differing in current consumption from each other. A charge pump circuit 51 included in a power source circuit for performing power supply has a charge pump unit 60a of a large current supply capability and self-power consumption, a charge pump unit 60b of a small current supply capability and self-power consumption, and a switch circuit 71 for selectively outputting the output voltage of the charge pump units 60a and 60b. A switching control circuit 50 selectively makes the charge pump units 60a and 60b operate according to setting of display modes.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display device which can operate with low power consumption, and a portable telephone and a portable information terminal device having the same.

[0002]

2. Description of the Related Art In recent years, as a flat panel display (FPD: Flat Panel Display) capable of realizing high definition display, low power consumption operation and space saving, a liquid crystal display (LCD) has been actively used. Is being developed. In particular, a liquid crystal display device is generally mounted as a display device of a portable information terminal device such as a mobile phone or an electronic organizer in terms of power consumption.

FIG. 21 is a schematic block diagram illustrating the configuration of a conventional liquid crystal display device. Referring to FIG. 21, a conventional liquid crystal display device 2000 includes an image signal processing circuit 200.
, A driver control circuit 201, a liquid crystal display unit 202,
A row driver circuit 207 and a column driver circuit 210 are provided.

The image signal processing circuit 200 receives an input image signal and receives R (red) display data R [1..0] and G (green) display data G [1.
0] and B (blue) display data B [1..0] are output to the column driver circuit 210. The R (red) display data R [1.0], G (green) display data G [1..0] and B (blue) display data B [1..0] are also referred to simply as "RGB display data". Collectively.

The driver control circuit 201 generates a row driver control signal and a column driver control signal for controlling the row driver circuit 207 and the column driver circuit 210 based on the input synchronization signal.

[0006] The liquid crystal display section 202 has a plurality of pixels 203 arranged in a matrix. Each pixel 203 has R
(Red), G (Green) and B (Blue) are divided into a plurality of dots for displaying respectively. Therefore, in the liquid crystal display unit 202, a plurality of dots are arranged in a matrix. In the liquid crystal display unit 202, a data line 204 is arranged for each dot column, and a scanning line 205 and a common voltage supply line 206 are arranged for each dot row.

[0007] The data line 204 supplies an image display signal which is an analog signal for displaying an image at each dot. The scanning line 105 is used for line scanning of the pixel 203. The common voltage supply line 206 supplies a common voltage VCOM to each pixel 203 (each dot).

The row driver circuit 207 has a shift register circuit 208 and a buffer circuit 209. The shift register circuit 208 generates a control signal for sequentially activating each scanning line 205 based on a row driver control signal from the driver control circuit 201. Buffer circuit 2
09 drives the voltage of the scanning line 205 that is the target of line scanning to, for example, a high level according to the control signal generated by the shift register circuit. Hereinafter, in the present specification, the high level and the low level of the signal level and the signal line voltage level, which are set in a binary manner, are referred to as “H level” and “L level”, respectively. .

The column driver circuit 210 includes a shift register circuit 211, latch circuits 212 and 213,
An A conversion circuit 214 and a buffer circuit 215 are provided.
The column driver circuit 210 supplies an image display signal based on the display data to each dot included in the scan target line via the data line 204.

Note that each of the RGB display data is 2-bit digital data, and the image display signal supplied to the data line 204 is an analog signal having four voltage levels determined in accordance with the 2-bit RGB display data. It is assumed to be a signal.

The image signal is input to the image signal processing circuit 200, and the display data R [1.
0], G [1..0] and B [1..0] are output to the column driver circuit 110. Driver control circuit 201
Is a row driver circuit 1 based on an input synchronization signal.
07 and column driver control signals STH, CLKH, LP and row driver control signals STV, CLKV for controlling the column driver circuit 110.

In the column driver circuit 210, first,
The shift register circuit 211 is a driver control circuit 201
The shift pulse is generated in response to a column driver control signal provided from the controller. The latch circuit 212 sequentially latches one line of RGB display data in response to a shift pulse from the shift register circuit 211. This allows
One line of RGB display data is developed by the latch circuit 112.

The RGB display data latched by the latch circuit 212 is further latched by the latch circuit 213 based on a common latch pulse LP. The D / A conversion circuit 214 converts the RGB display data latched by the latch circuit 213 into an image display signal which is an analog signal. The image display signal is transmitted to each data line 204 via the buffer circuit 115.

On the other hand, in the row driver circuit 207,
The shift register circuit 208 is a driver control circuit 201
, And sequentially generates shift pulses in response to a row driver control signal given by The shift pulse generated by the shift register circuit 208 is transmitted to each of the scan lines 205 via the buffer circuit 209. Based on this, each scanning line 205 is sequentially scanned at regular intervals and is activated to the H level voltage.

FIG. 22 is a circuit diagram showing a liquid crystal drive circuit arranged for each of the RGB dots forming the pixel 203. As shown in FIG.

Referring to FIG. 22, liquid crystal display element 221
Are arranged for each dot. Liquid crystal display element 221
Is sandwiched between a reflection electrode and a counter electrode (not shown). The reflective electrode is coupled to the pixel electrode node Nlc,
The counter electrode is coupled to a predetermined voltage. Generally, the predetermined voltage applied to the common electrode is set to the same voltage as the common voltage VCOM.

The liquid crystal driving circuit includes a TFT (Thin Film) provided between the pixel electrode node Nlc and the data line 204.
Transistor) 220 and a capacitor 222 for holding the voltage of the pixel electrode node Nlc.

The TFT 220 turns on in response to the activation (H level) of the scanning line 205 to electrically couple the data line 204 to the pixel electrode node Nlc. The capacitor 222 is connected between the pixel electrode node Nlc and the common voltage supply line 20.
6 and holds the voltage difference between the pixel electrode node Nlc and the common voltage VCOM.

The corresponding scanning line 205 is connected to the row driver circuit 2
When scanning is performed by 07, the TFT 220 becomes conductive. On the other hand, an image display signal corresponding to the dot output to each data line 204 by the column driver circuit 210 is applied to the liquid crystal display element 221 and the capacitor 220 via the TFT 220.

Accordingly, the liquid crystal display element 221 includes
A voltage corresponding to the voltage difference between the voltage of the pixel display signal applied via the TFT 220 and the voltage of the counter electrode is applied. The liquid crystal display element 221 exhibits an optical response according to the voltage difference. As a result, the reflectance of the RGB dots of each pixel changes according to the RGB display data based on the image signal input to the image signal processing circuit 200. Thus, the image display based on the image signal is executed in the liquid crystal display unit 102.

[0021]

The power consumption of a liquid crystal display device is expressed by the following equation.

Wt = (Wdc + Wac) where Wt represents the power consumption of the entire liquid crystal display device.
Wdc indicates direct current (static) power consumption that is not proportional to the drive frequency Fd, and Wac indicates alternating current (dynamic) power consumption in proportion to the drive frequency Fd.

The drive frequency Fd increases substantially in proportion to the display frame frequency (display frame rate) when the number of pixels of the liquid crystal display section is constant. From this, in order to reduce power consumption, by lowering the display frame frequency, equivalently lowering the driving frequency,
It is effective to reduce the AC component power consumption Wac.

However, in the conventional liquid crystal display device, when the display frame frequency is reduced in order to reduce power consumption, a voltage is applied to each liquid crystal display element, and a pixel display signal is written and written again. (I.e., one frame period) becomes longer. For this reason, the voltage of the pixel electrode, which should be originally maintained by the finite resistivity existing between the two electrode plates of the liquid crystal display element and the capacitance of the capacitor due to the leakage of the TFT, is reduced. Will change greatly.

As a result, when the liquid crystal display element is of the transmission type, the transmittance changes over time, and when the liquid crystal display element is of the reflection type, the reflectance changes with time, so that the ripple of the display luminance increases. Will be done. In addition, since the average voltage of the pixel electrode is also reduced, there is a problem that the display quality is deteriorated such that a sufficient contrast cannot be obtained.

On the other hand, in a display device for a portable device which requires low power consumption, a charge pump circuit as disclosed in, for example, Japanese Patent Application Laid-Open No. 2000-333444 has been used as a power supply circuit.

FIG. 23 is a circuit diagram illustrating a configuration example of the charge pump circuit. Referring to FIG.
(A) shows a charge pump circuit 300a that generates an output voltage 2 · Vi twice as high as the input voltage Vi. In FIG. 23 (b), the polarity of the input voltage Vi is inverted and the output is output. A charge pump circuit 300b for generating the voltage -Vi is shown.

Referring to FIG. 23A, a charge pump circuit 300a includes a switching control circuit 301 for generating a charge pump clock PCLK and its inverted clock / PCLK, and p-channel transistors 303 to 3.
05, an n-channel transistor 306, clock drivers 307 to 310 arranged corresponding to the transistors 303 to 306, and capacitors 302a and 302b.

P channel transistors 303 and 30
4 is connected in series between the output node No1 and the input node Ni1. P-channel transistor 305 and n-channel transistor 306 are coupled in series between input node Ni1 and ground node Ng.

Clock drivers 307, 309 and 3
Reference numeral 10 designates the charge pump clock PCLK from the switching control circuit 301 to the transistors 303 and 305
And 306 respectively. Clock driver 308 transmits the inverted clock / PCLK to the gate of transistor 304.

Capacitor 302a is coupled in parallel with p-channel transistors 304 and 305. Capacitor 302b is connected to input node Ni1 and output node N
o1.

In the first half of the switching cycle in which charge pump clock PCLK is set to H level and inverted clock / PCLK is set to L level, p-channel transistor 304 and n-channel transistor 3
06 is turned on, and p-channel transistors 303 and 3
05 is turned off. In response, the capacitor 302a
Is charged to the voltage difference between the ground node Ng and the input node Ni1, that is, the input voltage Vi.

In the latter half of the switching cycle in which charge pump clock PCLK is set to L level and inverted clock / PCLK is set to H level, p-channel transistor 304 and n-channel transistor 3
06 is turned off, and p-channel transistors 303 and 305 are turned on. In response, the capacitor 30
The charging voltage of 2a shifts by the input voltage Vi. Then, the electric charge charged in the capacitor 302a moves to the capacitor 302b.

By repeating such a switching operation over a plurality of switching sections, an output voltage 2.Vi approximately twice as large as the voltage difference between input node Ni1 and ground node Ng is output to output node No1.

By connecting such charge pump circuits in multiple stages, the operating power supply voltage required for the driver circuit and the like can be obtained from the input voltage Vi.

Referring to FIG. 23B, charge pump circuit 300b includes a switching control circuit 320 for generating charge pump clock PCLK and its inverted clock / PCLK, a p-channel transistor 323,
n-channel transistors 324 to 326, clock drivers 327 to 330, capacitors 321a and 321
b.

N-channel transistor 323 and p-channel transistor 324 are connected in series between input node Ni2 and ground node Ng. P channel transistors 325 and 326 are coupled in series between ground node Ng and output node No2. Clock drivers 327, 328, and 330 transmit the inverted clock / PCLK from switching control circuit 320 to the gates of transistors 323, 324, and 326, respectively. Clock driver 329 transmits the charge pump clock PCLK from switching control circuit 320 to the gate of transistor 325.

Capacitor 321a is connected in parallel with n-channel transistors 324 and 325. Capacitor 321b is coupled between output node No2 and ground node Ng.

Therefore, in the first half of the switching cycle, p-channel transistor 323 and n-channel transistor 325 are turned on, and n-channel transistors 324 and 326 are turned off. In response,
Capacitor 321a is connected to ground node Ng and input node N
The battery is charged up to the voltage difference from i2, that is, the input voltage Vi.

In the latter half of the switching cycle, p-channel transistor 323 and n-channel transistor 325 are turned off, and n-channel transistors 324 and 326 are turned on. In response, the charging voltage of capacitor 321a is shifted by -Vi. Then, the electric charge charged in the capacitor 321a is
Move to capacitor 321b.

By repeating such an operation over a plurality of switching sections, the input voltage Vi becomes approximately -1.
A double output voltage -Vi is generated at the output node No2.
By combining such a charge pump circuit 300b and the charge pump circuit 300a coupled in series, a negative operating power supply voltage can be obtained from the input voltage Vi.

Here, consider the self-power consumption of the charge pump circuit. For example, Japanese Patent Application Laid-Open No. 2000-3334
As described in Japanese Patent No. 44-44, when the load current of the power supply is large, in order to lower the output impedance of the power supply,
In some cases, the on-resistance of the transistor is made as small as possible. Assuming that the gate width of the MOS transistor is W and the gate length is L, the on-resistance decreases in proportion to a constant (W / L) called the transistor size.

However, if the gate width W is designed to be large in order to reduce the on-resistance, the gate capacitance, which is the capacitance between the gate electrode layer and the lower channel layer, becomes large. For this reason, in each transistor, the amount of charge / discharge at the gate capacitance in response to the switching operation increases, and the self-power consumption of the charge pump circuit increases.

Therefore, in the design of the charge pump circuit, if the load current is not sufficiently taken into consideration, the power consumption efficiency of the charge pump circuit may be reduced due to an increase in self-power consumption, and the power consumption of the device may be increased. In particular, in a power supply circuit of a liquid crystal display device used for a low power consumption device such as a mobile phone, since the power supply is on the order of milliwatts, the influence of the self-power consumption of the charge pump circuit in the power supply circuit on the power supply efficiency. large.

The present invention has been made to solve such problems, and an object of the present invention is to provide a liquid crystal display device capable of reducing power consumption without deteriorating display quality and a liquid crystal display device using the same. To provide a mobile phone and a portable information terminal device.

[0046]

According to a first aspect of the present invention, there is provided a liquid crystal display device capable of updating a screen display for each display frame, wherein a plurality of unit display dot pixels arranged in a matrix are formed. A plurality of unit display dots, each of which has a liquid crystal display element whose optical response changes according to an applied voltage, and a first drive circuit for scanning the plurality of unit display dots. And a second for supplying display data corresponding to the screen to at least one unit display dot scanned by the first drive circuit among the plurality of unit display dots.
And a plurality of unit display dots respectively provided in the first display mode.
When the corresponding unit display dot is scanned,
A plurality of data holding circuits for receiving and holding the display data supplied from the second drive circuit are provided corresponding to the plurality of unit display dots, respectively, at least in the second display mode. And applying one of the first and second predetermined voltages to the corresponding liquid crystal display element in accordance with the display data held in the data holding circuit when the unit display dot to be scanned is to be scanned. A plurality of voltage application circuits, a power supply circuit including a plurality of charge pump units having different current supply capacities for supplying operating voltages to the first and second drive circuits, and a plurality of charge circuits corresponding to display modes. And a power supply control circuit for selectively operating the pump unit. The display frame is composed of a first sub-frame for executing screen display in the first display mode and a second sub-frame for executing screen display in the second display mode. The power increases as the current supply capacity increases.

The liquid crystal display according to the second aspect is the first aspect.
The liquid crystal display device according to claim 1, wherein the power supply control circuit is configured to control at least one of the plurality of charge pump units to be operated based on whether the display mode is the first display mode or the second display mode. In response, an operation clock having a predetermined frequency is supplied.

The liquid crystal display device according to the third aspect is the first aspect.
In the liquid crystal display device described above, the power supply circuit has a first charge pump unit having a current supply capability corresponding to a current consumption in a first display mode, and a current supply corresponding to a current consumption in a second display mode. Second with ability
And a switch circuit for coupling one of the first and second charge pump units to a node for supplying an operating voltage when instructed by the power supply control circuit. In each of the first and second display modes, each of the first and second charge pump units operates complementarily.

The liquid crystal display according to the fourth aspect is the first aspect.
In the liquid crystal display device described above, the power supply circuit has a first charge pump unit having a current supply capability corresponding to a difference in current consumption in each of the first and second display modes, and a power supply circuit in the second display mode. A power supply control circuit including: a second charge pump unit having a current supply capability corresponding to a consumed current; and an output node receiving an output of the first and second charge pump units and supplying an operation voltage. In the first display mode, the first and second
Are operated, and only the second charge pump unit is operated in the second display mode.

The liquid crystal display device according to the fifth aspect is the first aspect.
20. The liquid crystal display device according to claim 19, further comprising a detection unit for detecting an operation voltage output from the power supply circuit. The power supply control circuit supplies an operation clock having a predetermined frequency to at least one of the plurality of charge pump units to be operated based on a detection result by the detection unit.

The liquid crystal display device according to the sixth aspect is the first aspect.
The liquid crystal display device according to any one of the preceding claims, further comprising a detection unit for detecting an operation current supplied from a power supply circuit. The power supply control circuit supplies an operation clock having a predetermined frequency to at least one of the plurality of charge pump units to be operated based on a detection result by the detection unit.

The liquid crystal display device according to the seventh aspect is the fifth aspect.
Or the liquid crystal display device according to 6, wherein the power supply circuit has a first charge pump unit having a current supply capability corresponding to the current consumption in the first display mode, and a power supply circuit corresponding to the current consumption in the second display mode. A second charge pump unit having a current supply capability; and a switch circuit for coupling one of the first and second charge pump units to a node for supplying an operating voltage when instructed by the power supply control circuit. Then, the power supply control circuit supplies an operation clock to one of the first and second charge pump units according to the detection result.

The liquid crystal display device according to the eighth aspect is the fifth aspect.
7. The liquid crystal display device according to 6, wherein the power supply circuit has a first charge pump unit having a current supply capability corresponding to a difference in current consumption in each of the first and second display modes, and a second display. A power supply control circuit, comprising: a second charge pump unit having a current supply capability corresponding to current consumption in a mode; and an output node receiving an output of the first and second charge pump units and supplying an operation voltage. Supplies an operation clock to both the first and second charge pump units or only the second charge pump unit according to the detection result.

The liquid crystal display device according to the ninth aspect is the first aspect.
In the liquid crystal display device described above, the liquid crystal display element displays a maximum luminance and a minimum luminance when the first and second predetermined voltages are respectively applied.

A liquid crystal display device according to a tenth aspect is the liquid crystal display device according to the first aspect, wherein the liquid crystal display units are arranged in a matrix and each include a plurality of unit display dots. Pixels, and each of the plurality of pixels has 3 pixels.
It has three primary color dots for gradation display of each primary color, and each primary color dot is constituted by the same number of unit display dots.

The liquid crystal display device according to the eleventh aspect is the liquid crystal display device according to the tenth aspect, wherein each of the same number of unit display dots has a different display area.

A portable telephone according to a twelfth aspect is a portable telephone having a liquid crystal display screen, which comprises a liquid crystal display device capable of updating the display of the liquid crystal display screen for each display frame. The liquid crystal display device includes a liquid crystal display unit having a plurality of unit display dots arranged in a matrix to form a liquid crystal display screen, and each of the plurality of unit display dots changes an optical response according to an applied voltage. It has a liquid crystal display element. The liquid crystal display device further includes a first drive circuit for scanning the plurality of unit display dots, and at least one unit display of the plurality of unit display dots that has been scanned by the first drive circuit. For the dot,
A second drive circuit for supplying display data corresponding to the screen, and a plurality of unit display dots are provided corresponding to the plurality of unit display dots, respectively. , A plurality of data holding circuits for receiving and holding the display data supplied from the second drive circuit, and a plurality of unit display dots are provided corresponding to the plurality of unit display dots, respectively. In the display mode, when one of the corresponding unit display dots is to be scanned, one of the first and second predetermined voltages is applied to the corresponding liquid crystal display element in accordance with the display data held in the data holding circuit. And a plurality of charge pump units having different current supply capacities for supplying operating voltages to the first and second drive circuits. It includes a power supply circuit including the door, in accordance with the display mode, and a power control circuit for selectively operating a plurality of charge pump unit. The display frame is
It is composed of a first sub-frame for executing screen display in the first display mode and a second sub-frame for executing screen display in the second display mode. The self-power consumption of each charge pump unit increases as the current supply capacity increases.

A portable information terminal device according to a thirteenth aspect is a portable information terminal device having a liquid crystal display screen, and includes a liquid crystal display device capable of updating the display of the liquid crystal display screen for each display frame. The liquid crystal display device includes a liquid crystal display portion having a plurality of unit display dots arranged in a matrix and constituting a liquid crystal display screen, each of the plurality of unit display dots,
It has a liquid crystal display element whose optical response changes according to the applied voltage. The liquid crystal display device further includes a first drive circuit for scanning the plurality of unit display dots, and at least one unit display of the plurality of unit display dots that is scanned by the first drive circuit. A second drive circuit for supplying display data corresponding to the screen to the dots, and a plurality of unit display dots are provided respectively corresponding to the plurality of unit display dots. A plurality of data holding circuits for receiving and holding display data supplied from the second drive circuit when a dot is to be scanned, and a plurality of data holding circuits are provided corresponding to the plurality of unit display dots, respectively. However, when the corresponding unit display dot is to be scanned in the second display mode, the first and second display dots are displayed in accordance with the display data held in the data holding circuit. A plurality of voltage application circuits for applying one of the two predetermined voltages to the corresponding liquid crystal display element, and a plurality of voltage supply circuits for supplying operating voltages to the first and second drive circuits, each having a different current supply capability. And a power supply control circuit for selectively operating the plurality of charge pump units according to the display mode. The display frame is a first frame that performs screen display in the first display mode.
And a second sub-frame for executing screen display in the second display mode. The self-power consumption of each charge pump unit increases as the current supply capacity increases.

[0059]

Embodiments of the present invention will be described below in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference characters.

[First Embodiment] [Configuration for Executing Image Display with Low Power Consumption] FIG. 1
FIG. 1 is a schematic block diagram showing an overall configuration of a liquid crystal display device according to Embodiment 1 of the present invention.

Referring to FIG. 1, a liquid crystal display device 1a according to the first embodiment has an image signal processing circuit 2, a display mode switching circuit 3a, a driver control circuit 3b, a reference voltage generation circuit 4, a liquid crystal display, Unit 5.

The image signal processing circuit 2 includes a liquid crystal display device 1a
, R display data R [1..0], G display data G [1..0] and B display data B which are display data of each of the three primary colors at a predetermined timing. Generate [1..0].

The display mode switching circuit 3a generates a mode identification signal SRH for switching the display mode in the liquid crystal display unit 5 based on the input synchronization signal. The switching of the display mode will be described later in detail. Driver control circuit 3b generates a column driver control signal and a row driver control signal for controlling row driver circuit 13 and column driver circuit 17 based on the synchronization signal.
The row driver control signal includes a start pulse STV supplied to the row driver circuit 13 and a shift clock CLKV.
including. The column driver control signal includes a start pulse STH and a shift clock CLKH supplied to the column driver circuit 17. Driver control circuit 3b further generates internal clock CLK.

The synchronizing signal is a general term for a horizontal synchronizing signal and a vertical synchronizing signal for indicating horizontal and vertical timings of an image signal, an image signal enable signal indicating a valid period of the image signal, and the like. Further, the number of display gradations of the liquid crystal display unit is, for example, 4 gradations for each color, and the bit width of each of the input image signal data, that is, each of the RGB display data is set to 2 bits for each color in accordance with the gradations. I do.

The reference voltage generation circuit 4 generates the write reference voltage VREF according to the timing based on the synchronization signal.

The liquid crystal display section 5 has pixels 6 arranged in a matrix. In the entire liquid crystal display unit 5, m (m: natural number) pixels in the row direction and n (n: natural number) pixels in the column direction are arranged.

FIG. 2 is a conceptual diagram illustrating the configuration of each pixel. Referring to FIG. 2, each of pixels 6 includes R (red), G
(Green) and a plurality of dots for displaying B (blue). Each dot is further divided into a plurality of subdots. That is, the dot for displaying R (red) is composed of subdots 40 and 41, and the dot for displaying G (green) is subdot 4
The dots for displaying B (blue) are composed of sub-dots 44 and 45.

Hereinafter, the sub-dots in the pixel 6 located at the x-th row and the y-th column in the liquid crystal display unit 5 are represented by R (x,
y) a, R (x, y) b, G (x, y) a, G (x,
y) b, B (x, y) a and B (x, y) b. Here, x is a natural number of 1 or more and n or less,
y is a natural number of 1 or more and m or less.

As described above, one pixel 6 has 2 × 3 = 6
It is composed of sub-dots. Further, it is assumed that the area ratio of the two sub dots forming each dot is divided so as to be approximately 2: 1. For example, the area ratio between the sub dots R (x, y) a and R (x, y) b is set to approximately 2: 1. Thus, the subdots R (x, y) a, G (x, y) a and B
The area of each of (x, y) a is represented by subdots R (x, y) b, G (x, y) b and B (x,
y) twice the area of each of b. In the following, when the sub-dots R (x, y) a, G (x, y) a and B (x, y) a are collectively referred to as a sub-dot a, the sub-dot R (x, y) When y) b, G (x, y) b and B (x, y) b are collectively referred to, they are referred to as subdots b.

The number of subdots in each dot is 2
The use of individual pieces is merely an example. That is, each dot can be divided into an arbitrary number of subdots corresponding to the bit width of the RGB display data, and an image can be displayed.

Referring to FIG. 1 again, in the liquid crystal display unit 5, such sub-dots are arranged in (2 × m) rows− (3 × m) rows.
n) They are arranged in a matrix in columns. As will be described in detail later, the liquid crystal display element is arranged for each dot.

In the liquid crystal display section 5, a data line 7 for supplying data to each sub-dot and a write reference voltage VREF for applying to a liquid crystal display element in each sub-dot are provided.
, A first and second scanning lines 9 and 10 for line-scanning each pixel (sub-dot), and a common voltage for supplying a common voltage VCOM to each sub-dot. A voltage supply line 11 is provided.

The data lines 7 are arranged for each sub-dot column, and 3 × n data lines are arranged in the entire liquid crystal display section 5.

The reference voltage supply lines 8 are arranged for each row of the sub dots. Therefore, in the entire liquid crystal display unit 5, the voltage supply lines LVR1a, LVR1b to LVRma,
2 × m LVRmbs are arranged. In the following, the voltage supply lines LVR1a, LVR1b to LVRm
Reference numeral 8 is used when a and LVRmb are collectively referred to.

The first scanning line 9 and the second scanning line 10
Are arranged for each row of subdots. Therefore, in the entire liquid crystal display section 5, the first scanning lines LA1a, LA1
2 × m A1b to LAma and LAmb are arranged.
In the following, the first scanning lines LA1a, LA1
Reference numeral 9 is used to generically refer to b to LAma and LAmb.

Similarly, 2 × m second scanning lines LB1a, LB1b to LBma, LBmb are arranged in the entire liquid crystal display section 5. In the following, the reference numeral 10 is used when the second scanning lines LB1a, LB1b to LBma, LBmb are generically referred to.

A reference voltage generating circuit 4 for generating a write reference voltage VREF, and voltage supply lines LVR1a, LVR1b-L
A switch 12 is provided between each of VRma and LVRmb.
Is arranged.

The row driver circuit 13 controls the voltages of the first and second scanning lines 9 and 10 and the on / off of the switch 12 in order to scan the sub-dots, that is, the lines of the pixels. Row driver circuit 13 includes a shift register circuit 14, a control signal generation circuit 15, and a buffer circuit 16.

The shift register circuit 14 sequentially generates shift pulses based on the start pulse STV and the shift clock CLKV. The control signal generation circuit 15
Based on a shift pulse output from the shift register circuit 14, a control signal for controlling each of the first scanning line 9, the second scanning line 10, and the switch 12 is generated. The buffer circuit 16 controls the first and second scanning lines 9 and 9 based on a control signal generated by the control signal generation circuit 15.
10 and a signal for controlling on / off of the switch 12.

As a result, the first scanning line 9 and the second scanning line 10 correspond to the line scanning by the row driver circuit 13.
Are selectively activated to the H level, and the switch 12 is turned on. As a result, the write reference voltage VREF is supplied to the reference voltage supply line 8 corresponding to the switch 12 that is selectively turned on. The switch 12 is turned on during the activation period of the corresponding second scanning line 10.

The column driver circuit 17 drives the data lines 7 arranged in the liquid crystal display section 5 to supply RGB display data to the sub-dots scanned by the row driver circuit 13. The column driver circuit 17 includes a shift register circuit 18, latch circuits 19 and 20,
It has a serial conversion circuit 21 and a buffer circuit 22.

Shift register circuit 18 generates a shift pulse based on start pulse STH and shift clock CLKH. The latch circuit 19 includes one line of RGB display data R [1..0], G [1..0] and B
By sequentially latching [1..0] based on the shift pulse from the shift register circuit 18, display data for one line is developed.

The latch circuit 20 has a common latch pulse L
RG latched by the latch circuit 19 by P
B display data is further latched. The parallel-serial conversion circuit 21 converts each of the 2-bit RGB display data latched by the latch circuit 20 into serial data of one bit. The buffer circuit 22 converts the RGB display data DR1 and DG converted into bit-by-bit serial data by the parallel / serial conversion circuit.
1, DB1 to DRn, DGn, and DBn are driven to the corresponding data lines 7.

In the present embodiment, a configuration has been described in which scanning is performed line by line and RGB display data for one line is collectively driven to each of the data lines 7. , The row driver circuit 13 and the column driver circuit 17 can be configured.

FIG. 3 is a circuit diagram showing a configuration of a liquid crystal drive circuit provided corresponding to each sub dot.

Referring to FIG. 3, liquid crystal drive circuit 30 has a data holding circuit 31a, a voltage applying circuit 31b, and a capacitor. The liquid crystal display element 37 is arranged for each sub dot. When the liquid crystal display unit 5 is a reflection type liquid crystal display device that performs display by reflected light,
The liquid crystal drive circuit can be provided on the back surface of a reflective electrode (not shown) for reflecting light once transmitted through the liquid crystal display element 37. The liquid crystal display element 37 uses, for example, a TN (Twisted Nematic) liquid crystal having no memory cell.

Data holding circuit 31a is an n-type T electrically connected between data line 7 and data holding node N1.
It has an FT 32 and a capacitor 33 connected between the common voltage supply line 11 for supplying the common voltage VCOM and the data holding node N1. The gate of the n-type TFT 32 is coupled to the first scanning line 9.

The voltage application circuit 31b receives the write reference voltage VR
N-type TFT 34 electrically coupled between reference voltage supply line 8 supplying EF and node N2, and p-type TF electrically coupled between common voltage supply line 11 and node N2
T35 and an n-type TFT 36 electrically coupled between the node N2 and the pixel electrode node Nlc.

The gates of n-type TFT 34 and p-type TFT 35 are connected to data holding node N1. n-type TF
The gate of T36 is coupled to the second scan line 10.

The capacitor 38 is connected to the pixel electrode node Nlc.
Is connected between the pixel electrode node Nlc and the common voltage supply line 11.

The liquid crystal display element 37 exhibits an optical response according to a voltage difference Vlc between the counter electrode node Np coupled to the counter electrode and the pixel electrode node Nlc (hereinafter, also referred to as a liquid crystal voltage Vlc). Therefore, when the liquid crystal display element 37 is a reflection type, the reflectance changes according to the liquid crystal voltage Vlc. When the liquid crystal display element 37 is of a transmission type,
The transmittance changes according to the liquid crystal voltage Vlc.

The data lines 7 are commonly connected to a plurality of liquid crystal driving circuits respectively corresponding to subdots belonging to the same column. In addition, the first scanning line 9, the second scanning line 10, the reference voltage supply line 8, and the common voltage supply line 11 are provided with a plurality of liquid crystal drive lines respectively provided corresponding to subdots belonging to the same row (line). Commonly connected to the circuit.

When the first scanning line 9 is scanned by the row driver circuit 13 and activated to the H level voltage, the n-type TFT 32 is turned on. Conversely, the corresponding first scanning line 9 is deactivated to the L level voltage when it is not a scanning target, so that the n-type TFT 32 is turned off. Therefore, the n-type TFT 32 functions as a switching element that is turned on in response to activation of the first scanning line 9.

When the n-type TFT 32 is turned on, the capacitor 33 is charged and discharged according to the level of the display data supplied to the data line 7 by the column driver circuit 17. on the other hand,
When the n-type TFT 32 is turned off, the data holding node N1
Is maintained.

As a result, the data holding circuit 31a sets the voltage of the data holding node N1 according to the voltage of the data line 7 when the first scanning line 9 is activated. When 9 is deactivated, the voltage is set to the voltage held by the capacitor 33. As described above, the data holding circuit 31a is a kind of DRAM (Dynamic Rand) that holds the data level of the display data supplied to the data line 7.
om Access Memory).

The n-type TFT 34 and the p-type TFT 35
Data holding node N1 set by data holding circuit 31a
Operates as a switching element that turns on and off in a complementary manner in accordance with the voltage. As a result, node N2 is electrically coupled to either reference voltage supply line 8 or common voltage supply line 11 according to the voltage of data holding node N1.

The gate of the n-type TFT 36 is connected to the second scanning line 1
0 and is turned on when the second scanning line 10 is scanned by the row driver circuit 13 and activated to the H level voltage. Conversely, when the second scanning line 10 is not scanned and is deactivated to the L level voltage,
The n-type TFT 36 is turned off. Therefore, the n-type TFT 3
6 operates as a switching element that turns on in response to activation of the second scanning line 10.

When the second scanning line 10 is activated, when the voltage of the data holding node N1 is at the H level corresponding to the display data "1", the n-type TFTs 34 and 36 are activated.
, The pixel electrode node Nlc is connected to the reference voltage supply line 8.
And a write reference voltage VREF is applied. On the other hand, when the voltage of the data holding node N1 is equal to the display data “0”
At the L level corresponding to the pixel electrode node N
lc is coupled to a common voltage supply line 11 to provide a common voltage V
COM is applied.

Counter electrode of liquid crystal display element 37 (not shown)
Is applied with a predetermined counter electrode voltage Vc. Generally, the common electrode voltage Vc corresponds to the common voltage VCOM. Therefore, the liquid crystal voltage Vlc applied to the liquid crystal display element 37 changes according to the voltage level of the data holding node.
Vlc = (VREF−Vc) or Vlc = (VCO
M-Vc).

As described above, the voltage application circuit 31b composed of the n-type TFTs 34 and 36 and the p-type TFT 35
The liquid crystal voltage Vlc corresponding to the data level held in the data holding circuit 31a is applied to the liquid crystal display element 37.

FIG. 4 is a conceptual diagram showing the relationship between the liquid crystal voltage applied to the liquid crystal display element and the intensity of reflected light.

Referring to FIG. 4, it is assumed that liquid crystal display element 37 performs liquid crystal display in a normally black mode. Further, when the liquid crystal voltage Vlc is Vmax = | (VREF−Vc) |, the maximum luminance Lmax is generally displayed so that the display contrast is increased, and Vmin = | (V
COM-Vc) |, the voltages are set so that the minimum luminance Lmin is substantially obtained.

As shown in FIG. 2, by forming dots for displaying each color using two sub-dots having an area ratio of about 2: 1, the reflection luminance at each dot is reduced. Lmin, (1/3) Lmax, (2/3) L, which is a combination of the reflection luminances of the two subdots and corresponds to 2-bit gradation expression by a 2-bit image signal.
It can be set to any of the four levels of max and Lmax.

Further, the upper bits (R1, G1, B1) of the 2-bit image signal input to the column driver circuit 17
The data of the lower bits (R0, G0, B0) correspond to the subdots of the smaller area, respectively, so that 2 bits = four levels of color for each color. By performing tonal display, 64 colors can be displayed for each pixel.

Here, a dot which is a display unit of each color is composed of two sub-dots having an area ratio of about 2: 1. Therefore, for four gradation levels expressed by a 2-bit image signal, , The level of the display luminance is associated with a substantially straight line. However, by appropriately setting the area ratio of the sub dots constituting each dot, the characteristics of the display luminance level with respect to the gradation level specified by the image signal,
That is, the γ characteristic can be set to a desired characteristic.

As described above, when a display is performed by applying a liquid crystal voltage to the liquid crystal display element 37, the display frame of each screen can be composed of two display modes.
The first display mode is a display mode in which the data holding circuit 31a and the voltage applying circuit 31b are scanned by the first scanning line 9 and the second scanning line 10 to update the display state of the liquid crystal display element 37 (hereinafter, referred to as a display mode). Refresh mode).

In the second display mode, only the sub-dot voltage application circuit 31b is scanned by the second scanning line 10 to update the data voltage held in the data holding circuit 31a in the refresh mode. A voltage based on the level of the display data transmitted to the holding circuit 31a is applied to the pixel electrode node Nlc via the voltage applying circuit 31b to change the display state of the liquid crystal display element 37 specified in the refresh mode. Mode for holding without updating (hereinafter also referred to as hold mode)
It is.

Next, the overall operation of liquid crystal display device 1a according to the present embodiment will be described with reference to FIGS.

FIG. 5 is a timing chart for explaining the overall operation of the liquid crystal display device 1a in the refresh mode.

Referring to FIG. 5, the input R, G, and B image signals are sent to image signal processing circuit 2. I-th
The time axis of the image signal input to the (i = natural number) input image frame (i) is compressed by the image signal processing circuit 2 to refresh the display frame (i) corresponding to the input image frame (i). It is input to the column driver circuit 17 at a predetermined timing during the subframe (i).

As described above, the display frame corresponding to the display of one screen of the liquid crystal display unit 5 (unit period of one screen display)
And an input image frame (a unit period of one screen input) corresponding to one screen of the input image signal has the same length. Then, the input image signal is displayed on the liquid crystal display unit 5 in a display frame delayed by one frame from the input image frame.

Further, one display frame includes a refresh sub-frame for refreshing (updating) the display on the liquid crystal display unit 5 in accordance with the input image signal, and a liquid crystal display unit 5.
And a hold sub-frame for holding (holding) the display. In the refresh sub-frame, the liquid crystal drive circuit provided corresponding to each sub-dot of the pixel 6 operates in the above-described refresh mode, and in the hold sub-frame, operates in the above-described hold mode.

As shown in FIG. 5, one display frame is composed of one refresh subframe and one or more hold subframes. Here, it is assumed that one hold frame is included in one display frame.

The display mode switching circuit 3a divides the input image frame period into four sub-frame periods based on the input synchronization signal, and sets the first sub-frame as a refresh sub-frame and the remaining three sub-frames. Is set as a hold subframe, and a mode identification signal SRH indicating a refresh subframe or a hold subframe is output.

The image signal processing circuit 2 outputs the mode identification signal S
When RH indicates a refresh subframe, the image signal of the input image frame (i) compressed in the time axis direction is output at a predetermined timing in the refresh subframe (i) of the display frame (i). The signal is input to the latch circuit 19 in the driver circuit 17.

Driver control circuit 3b outputs a column driver control signal to column driver circuit 17 when mode identification signal SRH indicates a refresh subframe. That is, the shift register circuit 18 of the column driver circuit 17 is provided with the driver control circuit 3b from FIG.
Start pulse ST at the timing shown in (f) and (g)
H and the shift clock CLKH are input.

Each time the shift clock CLKH is input, a shift pulse is sequentially output to the latch circuit 19 as a latch pulse. In the latch circuit 19,
The display data R output from the image signal processing circuit 2 based on the latch pulse from the shift register circuit 18
By latching [1..0], G [1..0] and B [1..0], data for one line is developed in the line direction (horizontal direction of display). The data developed in the line direction is latched at a common timing by the latch pulse 20 (FIG. 5 (h)) output from the driver control circuit 3b in the subsequent latch circuit 20.

The display data latched by the latch circuit 20 is converted by the parallel / serial conversion circuit 21 into a serial signal in the order of upper bits and lower bits. The converted serial signal is input to each data line 7 of the liquid crystal display unit 5 via the buffer circuit 22. Thus, the signals DR1, DG1, and DB1 of each data line
As shown in FIG. 5 (i), the signals latched by the latch circuit 20 are the upper bits (R1, G1, B1) in the first half of the line period and the lower bits (R0, G0) in the second half. , B0) in this order.

A row driver signal is output from driver control circuit 3b to row driver circuit 13 regardless of the content of mode identification signal SRH. That is, for the shift register circuit 14 in the row driver circuit 13,
The start pulse STV and the shift clock CLKV are input at timings as shown in FIGS.

The control signal generation circuit 15 supplies the mode identification signal SRH from the display mode switching circuit 3a with a refresh signal.
When indicating a subframe, the shift register circuit 14
, A control signal for driving the switch 12, the first scanning line 9, and the second scanning line 10 as described below is generated. These control signals are supplied to the switch 1 via the buffer circuit 16.
2. The first scanning line 9 and the second scanning line 10 are driven.

For example, in the first half of the first line period, as shown in FIG. 5 (m), the buffer circuit 16 controls the first scanning line LA1 corresponding to the sub-dot a of the first line.
a, and outputs a driving pulse of an H level voltage to the second scanning line LB1a. Similarly, in the latter half of the first line period, as shown in FIG. 5 (n), the first scanning line LA1b and the second scanning line LB1b corresponding to the sub-dot b of the first line are set to H level. The driving pulse of the level voltage is output from the buffer circuit 16.

Further, in the refresh sub-frame, as described above, data corresponding to the upper bits in the first half of the line period and data corresponding to the lower bits in the second half of the line period are supplied to the column driver circuit 17. Is output from each.

As described above, in the first half of the first line period, the liquid crystal drive circuit provided for the subdot a of the first line operates in the refresh mode described with reference to FIG. That is, the data holding circuit 31a and the voltage generating circuit 31b corresponding to the sub-dot a are scanned by the first scanning line LA1a and the second scanning line LB1a, respectively, and correspond to the upper bits of the image signal corresponding to the first line. The held voltage is held by the data holding circuit 31a. Further, the voltage application circuit 31b outputs the write reference voltage V supplied to the voltage supply line LVR1a according to the voltage held at the data holding node N1 by the data holding circuit 31a (that is, the H level / L level of the display data).
REF or the common voltage VCOM supplied to the common voltage supply line 11 is applied to the liquid crystal display element of the sub-dot a.

Similarly, in the latter half of the first line period, the liquid crystal drive circuit provided for the sub-dot b of the first line operates in the refresh mode to set the data level of the lower bit corresponding to the first line. The corresponding voltage is applied to the liquid crystal display element of sub-dot b.

Similarly, in the second and subsequent lines, data corresponding to the upper bits of the image signal is transmitted to the data line 7 in the first half of each line period. Further, the data holding circuit 31a and the voltage applying circuit 3
1b is scanned by the first scanning line 9 and the second scanning line 10, respectively, the data transmitted to the data line 7 is held in the data holding circuit 31a, and the data is changed to the H level / L level of the data. Accordingly, the write reference voltage VR
EF or the common voltage VCOM is applied to the voltage application circuit 31b.
Is applied to the liquid crystal display element 37 corresponding to the sub-dot a.

In the latter half of each line period, data corresponding to the lower bits of the image signal is transmitted to data line 7. Further, the data holding circuit 31a and the voltage applying circuit 31b provided for the sub-dot b serve as the first scanning line 9
And by the second scan line 10, respectively.
The data transmitted to data line 7 is stored in data holding circuit 31a.
And the write reference voltage VREF or the common voltage VREF depending on the H level / L level of the data.
COM is controlled by the voltage application circuit 31b to generate the sub dot b
Is applied to the liquid crystal display element 37 corresponding to.

As described above, the liquid crystal display elements corresponding to all the sub dots constituting the liquid crystal display section 5 are
A voltage corresponding to the image signal is written.

That is, in the refresh sub-frame, the first scanning line 9 and the second scanning line 10 are sequentially activated, and the data holding circuit 31a and the voltage applying circuit 31b are sequentially scanned to hold data. In addition, since a voltage can be applied to the liquid crystal display element based on the held data (data voltage), the display image can be updated by one sub-dot scan, and when the display image data changes to another image. In addition, the displayed image can be switched immediately.

Next, the operation of the hold subframe will be described. FIG. 6 is a timing chart for explaining the overall operation of the liquid crystal display device 1a in the hold mode.

Referring to FIG. 6, in the hold sub-frame, mode identification signal SRH indicates the hold sub-frame, and based on this, RGB display from image signal processing circuit 2 to column driver circuit 17 is performed. The supply of the data and the column driver control signal from the driver control circuit 3b is stopped as shown in FIG. That is, the column driver circuit 17 is stopped, and the L level voltage is constantly output to each data line 7.

On the other hand, as for the row driver circuit 13, the start pulse S
TV and shift clock CLKV are input. The control signal generating circuit 15 generates a control signal for driving the switch 12, the first scanning line 9 and the second scanning line 10 based on the shift pulse output from the shift register circuit 14, Through the switch 12, the first scanning line 9 and the second scanning line 10, respectively.

In the hold subframe, the first
Scan line LB1a of sub-dot a of line, sub-dot b
, And the second scanning line 10 are sequentially activated, and the sub-dot lines are sequentially scanned.
On the other hand, each of the first scanning lines 9 corresponding to each line is set to the L level voltage. Further, in each activation period of the second scanning line 10, the corresponding switch 12 is turned on, and the writing reference voltage VREF is sequentially supplied to the reference voltage supply line 8 corresponding to the scanned line.

As described above, in the first half of the first line period, the liquid crystal drive circuit provided for the sub-dot a on the first line operates in the hold mode. That is, the data holding circuit 31a is not scanned by the first scanning line 9. On the other hand, the voltage application circuit 31b scans by the second scanning line 10 and holds the data voltage held by the data holding circuit 31a, that is, the H level / L level of the display data corresponding to the upper bit of the image signal of the first line. , The write reference voltage VREF supplied to the reference voltage supply line 8 or the common voltage VCOM supplied to the common voltage supply line 11 is again applied to the liquid crystal display element 37 of the sub-dot a to perform rewriting. Execute

Similarly, in the latter half of the first line period, the liquid crystal driving circuit provided corresponding to subdot b of the first line operates in the hold mode, and the liquid crystal display element of subdot b is operated. And execute rewriting.

Similarly, for the second and subsequent lines, the circuit provided for sub-dot a operates in the hold mode in the first half of each line period. That is, the data application circuit 31b is scanned by the second scanning line 10 without scanning the data holding circuit 31a by the first scanning line 9. The voltage application circuit 31b applies the data voltage held in the data holding circuit 31a, that is, the write reference voltage VREF or the common voltage VCOM to the sub-dot a liquid crystal display device 3 in accordance with the level of the upper bit of the image signal.
8 again to execute rewriting.

In the latter half of each line period, the liquid crystal drive circuit provided corresponding to subdot b operates in the hold mode to execute rewriting on the liquid crystal display element of subdot b. I do.

As described above, in the hold subframe, in the refresh subframe, rewriting is performed on the liquid crystal display element based on the data voltage taken in and held by data holding circuit 31a. Is done. Thereby, the optical state of the liquid crystal display element written in the refresh subframe is held in each hold subframe. In the subsequent hold sub-frame, the above-described operation in the hold sub-frame is similarly repeated.

FIG. 7 is a conceptual diagram illustrating the polarity of write reference voltage VREF. Referring to FIG. 7, the polarity of write reference voltage VREF generated by reference voltage generation circuit 4 is inverted for each display line in each subframe, and the polarity of each line is inverted in the same subframe. Is done. Thereby, the polarity of the voltage of the liquid crystal display element can be dispersed for each line.

Therefore, ripples in display luminance, that is, flickers due to switching of subframes are further reduced. In FIG. 7, the case where the write reference voltage VREF is positive with respect to the voltage Vc of the common electrode is expressed as plus (+), and the case where the write reference voltage VREF is negative is expressed as minus (−). The voltage difference between the write reference voltage VREF and the common electrode voltage Vc is always equal in each of the period indicated by plus (+) and the period indicated by minus (-).

Thus, the polarity of the write reference voltage VREF with respect to the common electrode voltage Vc is inverted for each display line in each subframe, and the polarity between the lines is inverted between subframes. Also, a switch 12 provided corresponding to each reference voltage supply line 8
Are turned on during the period of writing the pixel voltage in each line, that is, before and after the period including the activation period of the second scanning line 10, and supply the writing reference voltage VREF to the reference voltage supply line 8.

As described above, the write reference voltage VREF is supplied to each reference voltage supply line 8 via the switch 12, so that the reference voltage generation circuit 4 supplies each of the reference voltage supply lines 8 without providing the switch 12. Compared with the case where the write reference voltage VREF is supplied, the capacitive load of the reference voltage generation circuit 4 is reduced, and the circuit scale of the reference voltage generation circuit 4 can be reduced. Furthermore, when reversing the polarity of the write reference voltage VREF, power consumption due to charging and discharging of the capacitive load of the reference voltage supply line 8 can be reduced.

FIG. 8 is a conceptual diagram for describing a change in display luminance of liquid crystal display device 1a according to the first embodiment.

FIG. 8A shows the change in display luminance in liquid crystal display device 1a according to the embodiment of the present invention.
(B) shows a change in display luminance in the conventional liquid crystal display device.

Referring to FIG. 8A, in the liquid crystal display device 1a according to the present embodiment, even when the display frame rate is low, the image refreshed (updated) in the refresh subframe is Since rewriting is repeatedly performed in the hold subframe, the ripple (flicker) frequency of the display luminance can be made higher than that of the conventional liquid crystal display device. Thereby, the ripple ΔLa of the display luminance is suppressed. In particular, considering human visual characteristics, the frequency of the sub-frame is set to about 60H.
It is desirable to set about z or more. Also,
Even when the display frame rate is reduced, the average voltage of the liquid crystal display element in each display frame does not decrease, so that the display contrast does not decrease.

On the other hand, in the conventional liquid crystal display device shown in FIG. 8B, if the display frame period is set long to reduce the power consumption and the display frame rate is reduced, the ripple in the display luminance is reduced. ΔLb becomes large. In addition, since the average voltage of the liquid crystal display element decreases during each display frame period, the display contrast also decreases.

FIG. 9 is a conceptual diagram showing the power consumption of the column driver circuit 17 in the liquid crystal display device 1a.

As described above, the rewriting of the liquid crystal voltage in the hold subframe is executed based on the data voltage held by the data holding circuit 31a provided for each subdot. In the frame, the column driver circuit 17 can be stopped.

Referring to FIG. 9, the column driver circuit 17 is intermittently driven to operate only the refresh subframe, and the power of the column driver circuit 17 is dynamically supplied in the hold subframe. The operation of the consuming part can be stopped.

That is, when one display frame is composed of N (N: natural number) subframes, the power consumption War of the column driver circuit is expressed by the following equation.

War = (1 / N) × Wr + ((N−1) / N) × Wh where Wr is the average power consumption during the refresh subframe period, that is, the dynamic power consumption and the static power consumption. It indicates the average of the sum, and Wh indicates the average power consumption in the hold subframe, that is, the average value of the static power consumption.

If the column driver circuit 17 is constituted by a CMOS circuit, the static power consumption can be extremely reduced, and therefore, War ≒ (1 / N) × Wr. That is, the power consumption of the column driver circuit is reduced by almost 1 compared to a conventional liquid crystal display device which does not perform intermittent driving of the column driver circuit 17.
/ N.

The drive frequency of the column driver circuit 17 is much higher than the drive frequency of the row driver circuit 13,
For example, even if the number of horizontal pixels of the liquid crystal display unit is about 100, the former reaches about 100 times the latter. For this reason, the power consumption of the column driver circuit 17 is much higher than that of the row driver circuit 13. According to our experiment, each one
It is known that in the case of about 00 pixels, about 50% of the power consumption of the entire liquid crystal display device is consumed by the column driver circuit.

Therefore, like the liquid crystal display device 1a,
Reducing the power consumption by intermittently driving the column driver circuit 17 has a great effect on reducing the power consumption of the entire liquid crystal display device. In the first embodiment, each display frame is composed of one refresh subframe and three hold subframes, and a total of four (N
= 4), the number of hold sub-frames included in one display frame is determined by the fact that the voltage held at the data holding node N1 in each data holding circuit 31a is n-type TF
It can be arbitrarily set within a range that can be maintained so as not to exceed the threshold voltage of T34 or p-type TFT 35.

[Power Supply in Liquid Crystal Display] FIG. 1
0 is a conceptual diagram showing the current consumption of row driver circuit 13 and column driver circuit 17 in liquid crystal display device 1a according to the first embodiment.

As described above, in the refresh subframe, both the row driver circuit 13 and the column driver circuit 17 perform dynamic, that is, periodic operations, whereas in the hold subframe, The dynamic operation of the column driver circuit 17 can be stopped although the pixel voltage is rewritten to the liquid crystal display element.

The current consumption ir + ic in the refresh subframe is equivalent to the sum of the dynamic and static current consumption of row driver circuit 13 and the sum of the dynamic and static current consumption of column driver circuit 17. I do. On the other hand, in the hold subframe, the column driver circuit 17
, The current consumption ir is equivalent to the sum of the sum of the dynamic current consumption and the static current consumption in the row driver circuit 13 and the sum of the static current consumption of the column driver circuit 17. I do. The operating frequency of the column driver circuit 17 is higher than the operating frequency of the row driver circuit 13, and the number of elements of the column driver circuit 17 is
Therefore, the dynamic current consumption of the column driver circuit is several tens of times that of the row driver. Also, as described above, each driver circuit is connected to the CMO.
With the S circuit, the static current consumption is suppressed to an extremely small value as compared with the dynamic current consumption.

As described above, the total current consumption of the row driver circuit 13 and the column driver circuit 17 fluctuates greatly within the display frame period. Therefore, the design of an operating power supply for these driver circuits, that is, a power supply circuit for supplying an operating current is important in reducing the power consumption of the entire liquid crystal display device.

As described in the background art, for a charge pump circuit used as a power supply for a portable device requiring low power consumption, the capacity is designed in accordance with the current consumption of the driver circuit in the refresh subframe. Also, even in a hold subframe with small current consumption, power is supplied by a charge pump circuit with large self-power consumption, which causes a decrease in power supply efficiency.
The power consumption of the liquid crystal display device increases.

On the other hand, when the capability of the charge pump circuit is set based on the current consumption of the driver circuit in the hold subframe or the average current consumption of the driver circuit in the display frame period, the self-power consumption of the charge pump circuit is suppressed. However, the current consumption in the refresh subframe cannot be sufficiently supplied, and the operation power supply voltage may drop or fluctuate, resulting in unstable operation of the driver circuit.

Therefore, the power supply in liquid crystal display device 1a according to the first embodiment is designed in response to a large change in the current consumption of the driver circuit in each display frame period.

Referring again to FIG. 1, liquid crystal display device 1a
Further includes a power supply control circuit 23 and a power supply circuit 24. The power control circuit 23 receives the mode identification signal SRH from the display mode switching circuit 3a and controls the operation of the power circuit 24. Power supply circuit 24 receives input power supply voltage Vi from an external power supply, and generates operating power supply voltage Vop for row driver circuit 13 and column driver circuit 17 at power supply node 25. The row driver circuit 13 and the column driver circuit 17
It operates by receiving the operation power supply voltage Vop supplied to the power supply node 25. The current consumption in the row driver circuit 13 and the column driver circuit 17, that is, the respective operating currents are indicated by iv and ih.

FIG. 11 is a block diagram showing a configuration of power supply circuit 24. Referring to FIG. Referring to FIG. 11, power supply circuit 24 includes switching control circuit 50 and k for generating a positive voltage.
(K: natural number) charge pump circuits 51-1 to 51-51
−k and regulator circuits 52-1 to 52-k, (k + 1) charge pump circuits 53-0 to 53-k for outputting a negative voltage, and a regulator circuit 54-0.
５４54-k.

Charge pump circuits 51-1 to 51-k
Are cascaded in k stages. Hereinafter, charge pump circuits 51-1 to 51- for generating a positive voltage will be described.
k is also simply referred to as a charge pump circuit 51. Each charge pump circuit 51 outputs a voltage that is approximately twice the input voltage.

The first-stage charge pump circuit 51-1 receives the input power supply voltage Vi and receives an output voltage + 2 · Vi approximately twice as high.
Generate The second-stage charge pump circuit 51-2 includes:
The output voltage output by the charge pump circuit 51-1 + 2 ·
In response to Vi, it outputs + 4 · Vi. The subsequent charge pump circuits operate in the same manner, and the output voltage output from the k-th stage charge pump circuit 51-k becomes 2 ^k · Vi.

The regulator circuits 52-1 to 52-k are
The charge pump circuits are arranged corresponding to the charge pump circuits 51-1 to 51-k. Regulator circuits 52-1 to 52-k
Reduces the output voltage of the corresponding charge pump circuit as necessary, and outputs it as a stable operating power supply voltage. The operating power supply voltages output from the regulator circuits 52-1 to 52-k are indicated by + Vo1 to + Vok, respectively.

Each of the charge pump circuits 51 receives switching pulses Pa and Pb from the switching control circuit 50.
And the respective inversion pulses / Pa and / Pb are given.

FIG. 12 is a circuit diagram showing a configuration of charge pump circuit 51 for outputting a positive voltage.

Referring to FIG. 12, charge pump circuit 5
1 denotes two charge pump units 60a and 60b
And a switch 71.

Charge pump 60a has a configuration similar to that of charge pump circuit 300a described in FIG. 23A, and includes capacitors 61a and 62a, p-channel transistors 63a, 64a and 65a, an n-channel transistor 66a, Pulse drivers 67a, 68a, 6
9a and 70a. The input voltage Vni to the charge pump circuit 51 is the first-stage charge pump circuit 51-1.
Is the input power supply voltage Vi, and corresponds to the output voltage of the preceding charge pump circuit in the subsequent charge pump circuits.

P channel transistors 63a and 64
a is connected in series between a node N3 to which the input voltage Vni is input and a node N4 corresponding to an output node of the charge pump unit 60a.

P-channel transistor 65a and n-channel transistor 66a are connected between node N3 and ground voltage G.
ND is coupled in series with ground node N5. The pulse drivers 67a, 69a and 70a output the switching pulses Pa from the switching control circuit 50.
To the gates of p-channel transistors 63a and 64a and n-channel transistor 66a, respectively.

The pulse driver 68a generates a switching pulse / Pa obtained by inverting the phase of the switching pulse Pa.
To the gate of p-channel transistor 64a.
Capacitor 61a is connected in parallel with p-channel transistors 64a and 65a. The capacitor 62a
Coupled between nodes N3 and N4.

In charge pump unit 60a, switching pulse Pa and its inverted pulse / P
In the first half period of the switching cycle in which the switching pulse Pa is set to the H level based on the signal a, the p-channel transistor 64a and the n-channel transistor 66a are turned on via the pulse drivers 67a to 70a, and the p-channel transistor 63a And 55a are turned off. Accordingly, the capacitor 61a is charged up to the input voltage Vni. The switching pulse P
In the latter half of the switching cycle in which a is set to the L level, p-channel transistors 64a and n
Channel transistor 66a is turned off, and p-channel transistors 63a and 65a are turned on. In response, the voltage charged in capacitor 61a shifts by the input voltage Vni, and the charge charged in capacitor 61a moves to capacitor 62a.

By repeating such a switching operation, an output voltage 2 · Vni is generated at node N4 which is approximately twice the input voltage Vni input to node N3.

Charge pump unit 60b has the same structure as charge pump unit 60a, and includes a transistor 6 corresponding to transistors 63a to 66a, respectively.
3b to 66b, capacitors 61b and 62b corresponding to capacitors 61a and 62a, respectively, and pulse drivers 67b to 70b corresponding to pulse drivers 67a to 70a, respectively.

The charge pump unit 60b performs the same switching operation as the charge pump unit 60a based on the switching pulse Pb from the switching control circuit 50 and its inverted pulse / Pb, and outputs an output approximately twice the input voltage Vni. Voltage 2 · Vni is applied to node N6
Generate and output to

In the charge pump unit 60a, considering the current supply capability corresponding to the large current consumption (ir + ic) in the refresh subframe,
The transistors 63a to 63a
The transistor size of the transistor 66a is designed to be relatively large.
On the other hand, in the charge pump unit 60b, the transistor sizes of the transistors 63b to 66b are set so as to have a relatively high on-resistance sufficient to supply a small current consumption ic in the hold subframe. It is designed to be small compared to. As a result, the charge pump unit 60a
Has a sufficient current supply capability, while its self-consumption is relatively large. On the other hand, although the charge pump unit 60b has a small current supply capability, the self-power consumption is suppressed accordingly.

The switching control circuit 50 determines whether the display mode is the refresh mode or the hold mode based on the mode identification signal SRH, and determines the switching pulses Pa and Pb and the respective inversion pulses / Pa and / Pb.

The switch 71 receives a switch switching signal SCP
, One of nodes N4 and N6 is selectively coupled to output node Np1 of charge pump circuit 51.

FIG. 13 is a timing chart for explaining the generation of switching pulses by the switching control circuit.

In the refresh subframe, the switching control circuit 50 synchronizes with the display timing of the liquid crystal panel based on the mode identification signal SRH.
The switching pulses Pa and / Pa are generated based on the internal clock CLK of about 0 kHz. On the other hand, the generation of the switching pulse Pb and its inverted pulse / Pb is stopped, and the signal levels of these clocks are fixed at H level and L level, respectively. As a result,
The switching operation in charge pump unit 60a is performed, and output voltage 2 · Vni is generated at node N4, while the operation of charge pump unit 60b is stopped.

On the other hand, in the hold subframe, switching control circuit 50 controls internal clock CLK.
, The switching pulses Pb and / Pb are generated. On the other hand, the generation of switching pulse Pa and its inverted pulse / Pa is stopped, and the signal levels of these clocks are fixed at H level and L level, respectively. As a result, the switching operation in charge pump unit 60b is performed, and output voltage 2 · Vni is generated at node N6, while the operation of charge pump unit 60a is stopped.

The switch switching signal SCP output by the power supply control circuit 23 is set to H level in the refresh subframe, and is set to L level in the hold subframe.

Referring again to FIG. 12, switch 71 is
In the refresh subframe in which switch switching signal SCP is set at the H level, node N4 is connected to output node Np1, and in the hold subframe, node N6 is connected to output node Np1.

In the refresh subframe,
By the switching operation of the transistors 63a to 66a having a low on-resistance in the charge pump unit 60a, an output voltage 2 · Vni is generated at the output node Np1. Therefore, a relatively large current consumption in the refresh subframe can be supplied with high power efficiency.

On the other hand, in the hold subframe, the output voltage 2 · Vni is applied to output node Np1 by the switching operation of transistors 63b to 66b in which the transistor size in charge pump unit 60b is small and the gate capacitance is suppressed. Generated. Therefore, the self-consumption of the charge pump unit 60a is almost negligible.

As described above, in each of the refresh sub-frame and the hold sub-frame requiring different operation currents, the operation power is supplied by the switching operation of the transistor having the ON resistance corresponding to the operation current. , The operation power supply voltage Vop is supplied by sufficiently supplying the operation current required in each subframe.
And the power consumption of the entire charge pump circuit 51 can be suppressed.
Thus, the power consumption of the entire liquid crystal display device can be reduced.

Referring again to FIG. 11, power supply circuit 24 includes
A charge pump circuit 53-0 for inverting an input power supply voltage Vi input from an external power supply, and a charge pump for inverting output voltages of the charge pump circuits 51-1 to 51-k to generate negative voltages, respectively. Circuits 53-1 to 5-5
3-k, and regulator circuits 54-0 to 54-0 provided corresponding to the charge pump circuits 53-0 to 53-k, respectively.
54-k. Hereinafter, the charge pump circuits 53-0 to 53-k for generating a negative voltage are collectively referred to simply as a charge pump circuit 53. Each charge pump circuit 51 outputs a voltage that is approximately -1 times the input voltage.

The charge pump circuit 53-1 inverts the output voltage + 2 · Vi of the charge pump circuit 51-1.
−2 · Vi is generated. The charge pump circuit 53
-K inverts 2 ^k · Vi, which is the output voltage of the charge pump circuit 51-k, and outputs −2 ^k · Vi.

The regulator circuits 54-0 to 54-k are
Provided corresponding to charge pump circuits 53-0 to 53-k, respectively, and outputs stable negative operating power supply voltages -Vo0 to -Vok based on the negative voltage output from corresponding charge pump circuit 53, respectively. I do. That is, the regulator circuits 52-1 to 52-k and 54-0 to 5-5
4-k output one of the operating power supply voltages to the row driver circuit 13 and the column driver circuit 17.
Is supplied to the power supply node 25 shown in FIG.

FIG. 14 is a circuit diagram showing a configuration of a charge pump circuit 53 for supplying a negative voltage.

Referring to FIG. 14, charge pump circuit 5
3 includes charge pump units 80a and 80b,
And a switch 91.

The charge pump unit 80a is configured as shown in FIG.
It has the same configuration as the charge pump circuit 300b described in (b), and includes capacitors 81a and 82a, p-channel transistors 83a, n-channel transistors 84a, 85a and 86, and pulse drivers 87a and 88.
a, 89a and 90a. Charge pump circuit 5
The input voltage Vni to the first charge pump circuit 5
In 3-0, the input power supply voltage is Vi, and in the subsequent charge pump circuits 53-1 to 53-k, they correspond to the output voltages of the charge pump circuits 51-1 to 53-k.

P-channel transistor 83a and n-channel transistor 84a are connected in series between node N7 to which input voltage Vni is input and ground node N8. N-channel transistors 85a and 86a
Are connected in series between a ground node N8 and a node N9 corresponding to an output node of charge pump unit 80a.

The pulse drivers 87a and 89a receive the switching pulse Pa from the switching control circuit 50.
Is transmitted to the gates of p-channel transistor 83a and n-channel transistor 85a, respectively. The pulse drivers 88a and 90a output the switching pulse P
The switching pulse / Pa with the phase a inverted is transmitted to the gates of n-channel transistors 84a and 86a, respectively. Capacitor 81a is connected in parallel with n-channel transistors 84a and 85a. Capacitor 62a is coupled between ground node N8 and node N9.

In charge pump unit 80a, switching pulse Pa and its inverted pulse / P
In the first half period of the switching cycle in which the switching pulse Pa is set to the H level based on the current a, the p-channel transistor 83a and the n-channel transistor 85a are turned on via the pulse drivers 87a to 90a, and the n-channel transistor 84a And 86a are turned off. Accordingly, the capacitor 81a is charged up to the input voltage Vni.

In the latter half period of the switching cycle in which switching pulse Pa is set to the L level, p-channel transistor 83a and n-channel transistor 85a are turned off, and n-channel transistors 84a and 86a are turned on. In response, the voltage charged in capacitor 61a shifts by -Vni, and the charge charged in capacitor 81a is shifted to capacitor 8a.
Move to 2a.

By repeating such a switching operation, the output voltage −approximately −1 times the input voltage Vni is obtained.
Vni is generated at the node N9.

The charge pump unit 80b has the same structure as the charge pump unit 80a, and includes transistors 8a to 86a corresponding to the transistors 83a to 86a, respectively.
3b to 86b, capacitors 81b and 82b corresponding to capacitors 81a and 82a, respectively, and pulse drivers 87b to 90b corresponding to pulse drivers 87a to 90a, respectively.

The charge pump unit 80b performs the same switching operation as the charge pump unit 80a based on the switching pulse Pb and its inverted pulse / Pb, and outputs the output voltage -Vni approximately -1 times the input voltage Vni to the node. Generate and output to N10.

Switch 91 operates in the same manner as switch 71, and selectively couples one of nodes N9 and N10 to output node Np2 of charge pump circuit 53 according to the level of switch switching signal SCP.

Since switching pulses Pa and Pb, inversion pulses / Pa and / Pb, and switch switching signal SCP are common to charge pump units 60a and 60b, detailed description will not be repeated.

In charge pump unit 80a, similarly to charge pump unit 60a, transistors 83a to 86a are designed to have relatively large transistor sizes. On the other hand, in the charge pump unit 80b, similarly to the charge pump unit 60b, the transistors 83b to 86b are designed to have smaller transistor sizes than the transistors 83a to 86a. As a result, while the charge pump unit 80a has a sufficient current supply capability, the self-power consumption becomes relatively large accordingly. On the other hand, the charge pump unit 6
In the case of 0b, although the current supply capability is small, the self-power consumption is suppressed correspondingly.

With such a configuration, in each of the refresh sub-frame and the hold sub-frame which require different operation currents, the operation power is supplied by the switching operation of the transistor having the on-resistance according to the operation current. be able to. Therefore,
Regarding the supply of the negative voltage, the operation power supply voltage Vo is supplied by sufficiently supplying the operation current required in each subframe.
p, and the charge pump circuit 53
The overall power consumption can be suppressed.

Thus, the single input power supply voltage Vi
, Various levels of operating voltages can be generated. In addition, refreshing with large operating current
In each of the sub-frame and the hold sub-frame having a small operating current, charge pump units 60a and 80a having high current supply capability and large self-consumption power, and charge pump units having low current supply capability but small self-consumption power By switching and operating between 60b and 80b, the power consumption of the power supply circuit 24 can be suppressed, and the power consumption of the entire liquid crystal display device can be reduced.

FIG. 11 shows a configuration in which regulator circuits 52-1 to 52-k are arranged corresponding to charge pump circuits 51-1 to 51-k connected in cascade in k stages, respectively. However, it is not necessary to provide a regulator circuit for a portion corresponding to a voltage level in a range that does not need to be supplied as an operating voltage to the internal circuit of the liquid crystal display device 1a.

For an internal circuit in which the stability of the operating power supply voltage is not so required, the output of the charge pump circuit can be directly supplied without arranging the regulator circuit. Similarly, the charge pump circuit 53-0
To 53-k and the corresponding regulator circuits 54-0 to 54-k
Regarding the arrangement of 54-k, it is possible to appropriately omit the arrangement according to the level of the operating power supply voltage required in the liquid crystal display device.

Furthermore, if the transistors in the charge pump unit, whose switching operation is stopped, are forcibly pushed in accordance with the type of the subframe, and the leakage current due to these can be set extremely low, the switch 71
Can be deleted. The same applies to the configuration of the charge pump circuit 53 for generating a negative voltage shown in FIG.

In the power supply circuit 24, the configuration in which each regulator circuit is connected to the subsequent stage of the charge pump circuit has been described. However, the configuration may be such that the regulator circuit is connected to the previous stage of the charge pump circuit.

[Modification of First Embodiment] FIG. 15 is a circuit diagram showing a configuration of a charge pump circuit according to a modification of the first embodiment. FIG. 15 representatively shows a configuration of a charge pump circuit for generating a positive voltage.

Referring to FIG. 15, charge pump circuit 51 'according to the modification of the first embodiment differs from charge pump circuit 51 according to the first embodiment shown in FIG. Is omitted. Therefore, output node Np1 is directly connected to both output node N4 of charge pump unit 60a and output node N6 of charge pump unit 60b. Other configurations of charge pump circuit 51 ′ are the same as those of charge pump circuit 51 according to the first embodiment.
Further, in the modification of the first embodiment, the generation of the switching pulse by the switching control circuit 50 is different from that of the first embodiment.

FIG. 16 is a timing chart showing generation of a switching pulse according to the modification of the first embodiment.

Referring to FIG. 16, in the refresh subframe, switching control circuit 50 generates both switching pulses Pa and Pb at a constant period based on internal clock CLK.

On the other hand, in the hold subframe, switching control circuit 50 generates only switching pulse Pb supplied to charge pump unit 60b, and stops generation of switching pulse Pa supplied to charge pump unit 60a. I do.

Therefore, in the refresh sub-frame, charge pump units 60a and 60a
b perform the switching operation and output voltage 2.
Generate Vni. On the other hand, in the hold subframe, only the charge pump unit 60b generates the output voltage 2 · Vni, and the charge pump unit 60a
Is stopped.

The on-resistance of the transistors 63b to 66b constituting the charge pump unit 60b, that is, the transistor size is determined by the current consumption in the hold subframe (current consumption ic of the driver circuit in FIG. 10).
It is designed corresponding to. On the other hand, the on-resistance of the transistors 63a to 66a constituting the charge pump unit 60a, that is, the transistor size corresponds to the difference between the current consumption in the refresh subframe and the current consumption in the hold subframe, that is, the current consumption ir in FIG. Is designed.

In each of the charge pump circuits for outputting a negative voltage, switch 91 is omitted in the configuration of FIG. 14 and charge pump units 80a and 80a are switched using switching pulses Pa and Pb shown in FIG. By operating each of the charge pump circuits 80b, the same operation as each of the charge pump circuits for generating the positive voltage shown in FIG. 15 can be performed.

With such a configuration, as in the first embodiment, in each of the refresh sub-frame and the hold sub-frame having different current consumption, an appropriate amount of operating current according to the current consumption is provided. Supply and self-consumption power in the charge pump circuit,
It can be suppressed according to the required operating current level. Therefore, similarly to the first embodiment, the power consumption of the power supply circuit 24 is suppressed, and the liquid crystal display device 1a
The overall power consumption can be reduced.

[Second Embodiment] In the first embodiment and its modifications, in power supply circuit 24 based on mode identification signal SRH designating a refresh subframe or a hold subframe. The operation of each charge pump circuit was controlled in a feed-forward manner.

In the second embodiment, a description will be given of a configuration in which the operation of power supply circuit 24 is feedback-controlled according to the fluctuation of the operation power supply voltage generated by power supply circuit 24 and the fluctuation of the operation current.

FIG. 17 is a circuit diagram showing a structure of a charge pump circuit according to the second embodiment. FIG. 17 representatively shows a configuration of a charge pump circuit for generating a positive voltage.

Referring to FIG. 17, charge pump circuit 51 ″ according to the second embodiment differs from charge pump circuit 51 according to the first embodiment shown in FIG.
The difference is that a detection unit 95 for detecting the voltage of the output node Np1 is further provided.

Detecting section 95 detects an increase in voltage at output node Np1 from a reference (2 · Vni) at a predetermined level or more and a decrease at a predetermined level or more. For example,
Detector 95 activates detection signal Dr when the voltage level of output node Np1 rises by a predetermined level or more, and activates detection signal Dd when the voltage level of output node Np1 falls by a predetermined level or more. Other configurations of charge pump circuit 51 ″ are similar to those of charge pump circuit 51 according to the first embodiment.

The power supply control circuit 23 sets the switch switching signal SCP based on the detection result of the detection section 95, that is, the detection signals Dr and Dd, and sets the switching pulses Pa and P in the switching control circuit 50.
The switching of the generation pattern of b is instructed.

More specifically, power supply control circuit 23 provides switching signal when detection section 95 activates detection signal Dr indicating that the voltage level of output node Np1 has risen above a predetermined level. An instruction to generate the SCP and generate the switching pulses Pa and Pb is forcibly set to a pattern corresponding to the hold subframe in FIG. This is to avoid a phenomenon in which the output voltage is increased because the current consumption is smaller than the supply current of the charge pump circuit.

On the other hand, the output node N
When the detection signal Dd indicating that the voltage level of p1 has dropped below the predetermined level is activated, the switching signal S
An instruction to generate the CP and generate the switching pulses Pa and Pb is forcibly set to the pattern corresponding to the refresh subframe in FIG. this is,
This is to avoid a phenomenon in which the output voltage drops because the supply current of the charge pump circuit is insufficient compared to the current consumption.

When the detection signals Dr and Dd are not activated, that is, when the output voltage is within a predetermined range, the detection section 95 outputs the current switching signal S
The generation pattern of the CP and the switching pulses Pa and Pb is maintained.

With such a configuration, it is possible to detect whether the supply current of each charge pump circuit is excessively large or small compared with the current consumption of the driver circuit, and thereby determine an appropriate supply current amount. In addition to setting, self-power consumption can be suppressed.

It is to be noted that the detecting section 95 executes only the detection of the output voltage, and the function for judging the activation of the detection signals Dr and Dd is arranged in the switching control circuit 50 and the power supply control circuit 23. It is also possible.

In FIG. 17, the configuration of the charge pump circuit for generating a positive voltage has been described.
The same detection unit 95 is connected to output node Np2 for the charge pump circuit for generating the negative voltage shown in FIG.
And the operation of the power supply control circuit 23 is set in the same manner, it is possible to supply the same current with respect to the supply of the negative voltage.

Also, in the configuration of the charge pump circuit according to the modification of the first embodiment shown in FIG. 16, by providing similar detection section 95, the output voltage of each charge pump circuit is fed back, A configuration in which the operation of the charge pump unit is switched may be employed.

[Modification of Second Embodiment] FIG. 18 is a schematic block diagram showing an overall configuration of a liquid crystal display device 1b according to a modification of the second embodiment.

Referring to FIG. 18, liquid crystal display device 1b according to the modification of the second embodiment differs from liquid crystal display device 1a according to the first embodiment shown in FIG. The difference is that a detection unit 97 for detecting the voltage or current of the power supply node 25 for supplying the operation power supply voltage Vop to the column driver circuit 17 is further provided. The detecting unit 97 includes the detecting unit 95 shown in FIG.
It has the same function as. The structure of the other parts is the same as that of liquid crystal display device 1a, and therefore detailed description will not be repeated.

As described above, by providing detection section 97 for power supply node 25, the current consumption (ih + iv) corresponding to the operation current of the driver circuit or the fluctuation of operation power supply voltage Vop due to the current consumption is directly detected. According to the detection result, the current supply capability and the self-power consumption of the power supply circuit 24 can be appropriately set according to the magnitude of the current consumption according to the first embodiment or its modification.

[Third Embodiment] As described above, the liquid crystal display devices according to the first and second embodiments and the modifications thereof can operate with low power consumption without deteriorating the display quality. Therefore, such a liquid crystal display device is suitable for a battery-driven device such as a mobile phone or a portable information terminal device.

FIG. 19 is a conceptual diagram showing a configuration of mobile phone 100 according to the third embodiment of the present invention.

Referring to FIG. 19, portable telephone 100 has
A liquid crystal display unit 5 of the liquid crystal display device 1a according to the first embodiment is provided as a display screen. Details of the configuration of liquid crystal display device 1a are as described above, and thus will not be repeated.
As a result, it is possible to drive the liquid crystal display device capable of low power consumption operation while preventing the display quality from deteriorating, while suppressing the self-power consumption of the power supply circuit. And a configuration that matches the reduction in power consumption.

FIG. 20 is a conceptual diagram showing a configuration of portable information terminal device 110 according to the third embodiment of the present invention.

Referring to FIG. 20, portable information terminal device 11
0 includes the liquid crystal display unit 5 of the liquid crystal display device 1a according to the first embodiment as a display screen. Thus, the portable information terminal device 110 can achieve high quality display and low power consumption, similarly to the mobile phone 100.

Further, a liquid crystal display device having a configuration according to the modified example of the first embodiment, the second embodiment and the modified example of the second embodiment is applied to the liquid crystal display unit of portable telephone 100 and portable information terminal device 110. It is also possible.

The embodiments disclosed this time are to be considered in all respects as illustrative and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

[0242]

According to the liquid crystal display device of the first, second and ninth aspects, in the second display mode, writing is performed by the potential application circuit based on the display data once taken into and held by the data holding circuit. Since either the reference potential or the common potential can be rewritten to the pixel electrode, the second drive circuit can be intermittently driven to reduce power consumption without lowering display quality. Further, in each of the first and second display modes, the charge pump unit of appropriate current supply capability and self-consumption power according to the operating current required in the first and second driver circuits is selectively operated. Since power can be supplied, the power consumption of the power supply circuit can be suppressed, and the power consumption of the entire liquid crystal display device can be further suppressed.

In the liquid crystal display device according to the third and fourth aspects, the selection of the charge pump unit is controlled in a feed-forward manner in accordance with the switching between the first and second display modes. The effect provided by the device can be enjoyed.

The liquid crystal display device according to any one of claims 5 to 8,
By controlling the selection of the charge pump unit by feeding back the operation power supply voltage or the operation current supplied from the power supply circuit, the effect of the liquid crystal display device according to claim 1 can be enjoyed.

The liquid crystal display device according to the tenth and eleventh aspects can display a color image based on gradation display, in addition to the effect of the liquid crystal display device according to the first aspect.

According to a twelfth aspect of the present invention, in the second display mode, based on the display data once fetched and held by the data holding circuit, the potential application circuit determines whether the writing reference potential or the common potential. Is rewritten to the pixel electrode, thereby performing a screen display by a liquid crystal display device capable of intermittently driving the second drive circuit. Further, in each of the first and second display modes, the charge pump unit having appropriate current supply capability and self-consumption power according to the operating current required by the first and second driver circuits is selectively operated. Since power supply can be performed, the power consumption of the power supply circuit can be suppressed, and the power consumption of the liquid crystal display device can be further suppressed.
High quality display and low power consumption can be achieved.

In the portable information terminal device according to the thirteenth aspect, in the second display mode, the write reference potential or the common potential is applied by the potential application circuit based on the display data once taken into and held by the data holding circuit. Is rewritten to the pixel electrode, thereby performing the screen display by the liquid crystal display device capable of intermittently driving the second drive circuit. Further, in each of the first and second display modes, the charge pump unit having appropriate current supply capability and self-consumption power according to the operating current required by the first and second driver circuits is selectively operated. Since power can be supplied, the self-power consumption of the power supply circuit can be suppressed, and the power consumption of the liquid crystal display device can be further suppressed, so that high-quality display and low power consumption can be achieved.

[Brief description of the drawings]

FIG. 1 is a schematic block diagram showing an overall configuration of a liquid crystal display device according to a first embodiment of the present invention.

FIG. 2 is a conceptual diagram illustrating a configuration of each pixel.

FIG. 3 is a circuit diagram showing a configuration of a liquid crystal drive circuit provided corresponding to each sub dot.

FIG. 4 is a conceptual diagram showing a relationship between a liquid crystal voltage applied to a liquid crystal display element and a reflected light intensity.

FIG. 5 is a timing chart illustrating an overall operation in a refresh mode of the liquid crystal display device according to the first embodiment.

FIG. 6 is a timing chart illustrating an overall operation in the hold mode of the liquid crystal display device according to the first embodiment.

FIG. 7 is a conceptual diagram illustrating the polarity of a write reference voltage VREF.

FIG. 8 is a conceptual diagram for describing a change in display luminance in the liquid crystal display device according to the first embodiment.

FIG. 9 is a conceptual diagram showing power consumption of a column driver circuit in the liquid crystal display device according to the first embodiment.

FIG. 10 is a conceptual diagram showing current consumption of a row driver circuit and a column driver circuit in the liquid crystal display device according to the first embodiment.

FIG. 11 is a block diagram showing a configuration of a power supply circuit shown in FIG.

FIG. 12 is a circuit diagram showing a configuration of a charge pump circuit for outputting a positive voltage.

FIG. 13 is a timing chart illustrating generation of a switching pulse by a switching control circuit.

FIG. 14 is a charge pump circuit 53 that outputs a negative voltage.
FIG. 3 is a circuit diagram showing the configuration of FIG.

FIG. 15 is a circuit diagram showing a configuration of a charge pump circuit according to a modification of the first embodiment.

FIG. 16 is a timing chart showing generation of a switching pulse according to a modification of the first embodiment.

FIG. 17 is a circuit diagram showing a configuration of a charge pump circuit according to a second embodiment.

FIG. 18 is a schematic block diagram showing an overall configuration of a liquid crystal display device according to a modification of the second embodiment.

FIG. 19 is a conceptual diagram showing a configuration of a mobile phone according to a third embodiment of the present invention.

FIG. 20 is a conceptual diagram showing a configuration of a portable information terminal device according to Embodiment 3 of the present invention.

FIG. 21 is a schematic block diagram illustrating a configuration of a conventional liquid crystal display device.

FIG. 22 is a circuit diagram showing a configuration of a liquid crystal drive circuit arranged for each dot shown in FIG. 21;

FIG. 23 is a circuit diagram illustrating a configuration example of a charge pump circuit.

[Explanation of symbols]

3a display mode switching circuit, 3b driver control circuit,
4 Reference voltage generation circuit, 5 liquid crystal display, 6 pixels, 7
Data line, 8 reference voltage supply line, 9 first scan line,
10 second scanning line, 11 common voltage supply line, 12, 7
1,91 switches, 13 row driver circuits, 17 column driver circuits, 23 power supply control circuits, 24 power supply circuits,
25 power supply node, 30 liquid crystal drive circuit, 31a data holding circuit, 31b voltage application circuit, 37 liquid crystal display element, 50 switching control circuit, 51, 51 ', 5
1 ″, 53 charge pump circuit, 52, 54 regulator circuit, 60a, 60b, 80a, 80b charge pump unit, 95, 97 detection unit, Pa, Pb
Switching pulse, Nlc pixel electrode node, Np counter electrode node, SRH mode identification signal, VCOM common voltage, VREF write reference voltage, Vc counter electrode voltage.

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme court ゛ (Reference) G09G 3/20 612 G09G 3/20 612D 624 624B 680 680S 680T (72) Inventor Hiroyuki Murai Marunouchi, Chiyoda-ku, Tokyo 2-3-2, Mitsui Electric Co., Ltd. (72) Inventor Mitsuo Inoue 2-3-2, Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 2H088 EA02 HA07 HA08 HA12 JA05 MA06 2H093 NA16 NA31 NA44 NA51 NA61 NC02 NC03 NC16 NC22 NC23 NC34 NC35 NC58 ND04 ND10 ND39 NE07 5C006 AA12 AA14 AA22 AF44 BB16 BC03 BC12 BF02 BF03 BF04 BF11 BF32 BF34 BF37 BF43 BF46 FA47 5C080 AA10 BF05 JJ05 BF05 JJ

Claims (13)

[Claims] 1. A liquid crystal display device capable of updating the display of a screen for each display frame, comprising: a liquid crystal display unit having a plurality of unit display dot pixels arranged in a matrix; Each has a liquid crystal display element whose optical response changes according to an applied voltage, a first drive circuit for scanning the plurality of unit display dots, and of the plurality of unit display dots, A second drive circuit for supplying display data corresponding to the screen to at least one unit display dot scanned by the first drive circuit; and Each of which is provided from the second drive circuit when a corresponding unit display dot is to be scanned in the first display mode. A plurality of data holding circuits for receiving and holding the display data; and a plurality of data holding circuits provided corresponding to the plurality of unit display dots, respectively corresponding to the first display mode and the second display mode. In order to apply one of the first and second predetermined voltages to the corresponding liquid crystal display element according to the display data held in the data holding circuit when the unit display dot is to be scanned. A plurality of voltage applying circuits; a power supply circuit including a plurality of charge pump units having different current supply capacities for supplying operating voltages to the first and second drive circuits; A power supply control circuit for selectively operating a plurality of charge pump units, wherein the display frame is a screen display in the first display mode. And a second sub-frame for executing a screen display in the second display mode. The self-power consumption of each of the charge pump units increases with the current supply capacity. Liquid crystal display devices that increase accordingly. 2. The power supply control circuit according to claim 1, wherein at least one of the plurality of charge pump units is an operation target based on whether the display mode is the first display mode or the second display mode. 2. The liquid crystal display device according to claim 1, wherein an operation clock having a predetermined frequency is supplied thereto. 3. A power supply circuit comprising: a first charge pump unit having a current supply capability corresponding to a current consumption in the first display mode; and a current supply capability corresponding to a current consumption in the second display mode. And a switch circuit for coupling one of the first and second charge pump units and a node for supplying the operating voltage when instructed by the power supply control circuit. The liquid crystal display device according to claim 1, wherein the power supply control circuit operates each of the first and second charge pump units complementarily in each of the first and second display modes. 4. A power supply circuit comprising: a first charge pump unit having a current supply capability corresponding to a difference between current consumption in each of the first and second display modes; A second charge pump unit having a current supply capability corresponding to a current; and an output node receiving an output of the first and second charge pump units and supplying an operating voltage, the power supply control circuit includes: 2. The liquid crystal according to claim 1, wherein both said first and second charge pump units are operated in said first display mode, and only said second charge pump unit is operated in said second display mode. Display device. 5. The power supply control circuit according to claim 5, further comprising: a detection unit configured to detect the operating voltage output from the power supply circuit, wherein the power supply control circuit is configured to output the operating voltage from the plurality of charge pump units based on a detection result by the detection unit. 2. The liquid crystal display device according to claim 1, wherein an operation clock having a predetermined frequency is supplied to at least one operation target. 6. The power supply control circuit according to claim 6, further comprising: a detection unit configured to detect an operation current supplied from the power supply circuit, wherein the power supply control circuit is configured to detect an operation current of the plurality of charge pump units based on a detection result by the detection unit. 2. The liquid crystal display device according to claim 1, wherein an operation clock having a predetermined frequency is supplied to at least one operation target. 7. A power supply circuit comprising: a first charge pump unit having a current supply capability corresponding to a current consumption in the first display mode; and a current supply capability corresponding to a current consumption in the second display mode. And a switch circuit for coupling one of the first and second charge pump units and a node for supplying the operating voltage when instructed by the power supply control circuit. 7. The liquid crystal display device according to claim 5, wherein the power supply control circuit supplies the operation clock to one of the first and second charge pump units according to the detection result. 8. A power supply circuit comprising: a first charge pump unit having a current supply capability corresponding to a difference in current consumption in each of the first and second display modes; and a power consumption circuit in the second display mode. A second charge pump unit having a current supply capability corresponding to a current; and an output node receiving an output of the first and second charge pump units and supplying an operating voltage, the power supply control circuit includes: , According to the detection result, the first
And / or the second charge pump unit, or
7. The liquid crystal display device according to claim 5, wherein the operation clock is supplied only to the second charge pump unit. 9. The liquid crystal display device according to claim 1, wherein the liquid crystal display element displays a maximum luminance and a minimum luminance when the first and second predetermined voltages are respectively applied. 10. The liquid crystal display section includes a plurality of pixels arranged in a matrix, each including a predetermined number of unit display dots, each of the plurality of pixels being a respective one of three primary colors. 2. The liquid crystal display device according to claim 1, comprising three primary color dots for gradation display, wherein each of said primary color dots is constituted by an equal number of unit display dots. 11. The liquid crystal display device according to claim 10, wherein the same number of unit display dots have different display areas. 12. A mobile phone having a liquid crystal display screen, comprising: a liquid crystal display device capable of updating the display of the liquid crystal display screen for each display frame, wherein the liquid crystal display devices are arranged in a matrix and the liquid crystal is A liquid crystal display unit having a plurality of unit display dots constituting a display screen, wherein each of the plurality of unit display dots has a liquid crystal display element whose optical response changes according to an applied voltage; Further comprising: a first drive circuit for scanning the plurality of unit display dots; and at least one unit display of the plurality of unit display dots which has been scanned by the first drive circuit. A second drive circuit for supplying display data corresponding to the screen to the dots; and a second drive circuit provided for each of the plurality of unit display dots. A plurality of data holding units each receiving and holding the display data supplied from the second drive circuit when a corresponding unit display dot is to be scanned in the first display mode. A circuit, provided corresponding to each of the plurality of unit display dots, respectively, when the corresponding unit display dots are to be scanned in the first display mode and the second display mode, A plurality of voltage applying circuits for applying one of a first and a second predetermined voltage to a corresponding liquid crystal display element in accordance with the display data held in a data holding circuit; And a power supply circuit including a plurality of charge pump units having different current supply capacities for supplying operating voltages to the drive circuits. A power supply control circuit for selectively operating a power pump unit, wherein the display frame includes a first sub-frame for performing a screen display in the first display mode, and a power supply control circuit for performing a screen display in the first display mode. A second sub-frame for executing a screen display, wherein the self-power consumption of each of the charge pump units increases with an increase in the current supply capability. 13. A portable information terminal device having a liquid crystal display screen, comprising: a liquid crystal display device capable of updating the display of the liquid crystal display screen for each display frame, wherein the liquid crystal display devices are arranged in a matrix. A liquid crystal display unit having a plurality of unit display dots constituting the liquid crystal display screen, wherein each of the plurality of unit display dots has a liquid crystal display element whose optical response changes according to an applied voltage; The display device further includes: a first drive circuit for scanning the plurality of unit display dots; and at least one of the plurality of unit display dots scanned by the first drive circuit. A second drive circuit for supplying display data corresponding to the screen to the unit display dots; and a second drive circuit corresponding to the plurality of unit display dots. In the first display mode, when a corresponding unit display dot is to be scanned, each of the plurality of display units receives and holds the display data supplied from the second drive circuit. A data holding circuit provided for each of the plurality of unit display dots, each of which is provided when the corresponding unit display dot is to be scanned in the first display mode and the second display mode; A plurality of voltage applying circuits for applying one of a first and a second predetermined voltage to a corresponding liquid crystal display element in accordance with the display data held in the data holding circuit; A power supply circuit for supplying an operating voltage to the second drive circuit, the power supply circuit including a plurality of charge pump units having respectively different current supply capacities; And a power supply control circuit for selectively operating the charge pump unit. The display frame comprises: a first sub-frame for executing a screen display in the first display mode; And a second sub-frame for performing screen display, wherein the self-power consumption of each of the charge pump units increases in accordance with an increase in the current supply capability.