KR101366851B1 - Liquid crystal display device - Google Patents

Abstract

According to an embodiment of the present invention, a gate driver for supplying a gate signal to a liquid crystal panel of a liquid crystal display includes a pair of gate drivers that are alternately driven at a frame period, thereby reducing the cumulative stress voltage of a transistor as a component to prevent degradation. It's about making technology one. The present invention includes a timing controller that outputs a gate control signal and a data control signal and outputs digital video data to control driving of the gate driver and the data driver; A pair of gate drivers for supplying gate signals to the gate lines of the liquid crystal panel in response to the gate control signals, the gate signals being alternately driven at a frame period; And a data driver for supplying a pixel signal to each data line of the liquid crystal panel in response to the data control signal.

 Gate driver, stress voltage

Description

 [0001] LIQUID CRYSTAL DISPLAY DEVICE [0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technology for driving a liquid crystal panel of a liquid crystal display device, and more particularly, to a driving circuit of a liquid crystal display device capable of preventing degradation by lowering a cumulative stress voltage of a transistor constituting each gate driver that is a component of a gate driver. It is about.

2. Description of the Related Art In recent years, as information technology (IT) has advanced, flat panel displays have become more important as visual information delivery media. In order to secure more competitive power in the future, low power consumption, thinness, lightness and high image quality are required. 2. Description of the Related Art A liquid crystal display (LCD), which is a typical display device of a flat panel display, is an apparatus for displaying an image using the optical anisotropy of a liquid crystal and has advantages such as thinness, small size, low power consumption and high image quality. And is widely applied to a display device of a portable terminal.

Such a liquid crystal display device is a display device capable of displaying a desired image by separately supplying image information to liquid crystal pixels arranged in a matrix form and adjusting the light transmittance of the liquid crystal pixels. Therefore, the liquid crystal display device has a liquid crystal panel in which liquid crystal pixels, which is the minimum unit for realizing an image, are arranged in an active matrix form, and a driving unit for driving the liquid crystal panel. Since the LCD does not emit light by itself, a backlight unit is provided to supply light to the LCD. The driver includes a timing controller and a data driver and a gate driver.

FIG. 1 is a driving block diagram of a conventional liquid crystal display apparatus. As shown in FIG. 1, a gate control signal GDC and a data control signal DDC for controlling the driving of the gate driving unit 12 and the data driving unit 13, A timing controller 11 for sampling digital video data RGB and rearranging the digital video data RGB; A gate driver 12 for supplying a gate signal to each of the gate lines GL0 to GLn of the liquid crystal panel 14 in response to the gate control signal GDC; A data driver 13 for supplying a pixel signal to the data lines DL1 to DLm of the liquid crystal panel 14 in response to the data control signal DDC; The liquid crystal panel 14 includes a liquid crystal cell driven by the gate signal and the pixel signal in a matrix form to display an image. The operation thereof will be described with reference to FIGS. 2 to 8.

The timing controller 11 includes a gate control signal GDC and a data driver 13 for controlling the gate driver 12 by using the vertical / horizontal synchronization signals Hsync / Vsync and the clock signal CLK supplied from the system. Outputs a data control signal (DDC) for controlling. In addition, the timing controller 11 samples digital pixel data (RGB) input from the system, rearranges the sampled pixel data, and supplies the same to the data driver 13.

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock signal GSC and a gate-out enable signal GOE. The data control signal DDC includes a source start pulse SSP, A shift clock signal SSC, a source-out enable signal SOE, a polarity signal POL, and the like.

The gate driver 12 sequentially supplies the gate signal to the gate lines GL1 to GLn in response to the gate control signal GDC input from the timing controller 11, ) Are turned on. Accordingly, pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

To be more specific, the gate driver 12 shifts the gate start pulse GSP according to the gate shift clock GSC to generate a shift pulse. In response to the shift clock, the gate driver 12 supplies a gate signal composed of a gate on / off period (signal) to the corresponding gate line GL in each horizontal period. In this case, the gate driver 12 supplies the gate-on signal only in the enable period in response to the gate-on enable signal GOE, and supplies the gate-off signal (gate-low signal) in the other periods.

The data driver 13 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 11 And supplies the converted pixel signals to the data lines DL1 to DLm on the liquid crystal panel 14. [

The liquid crystal panel 14 is formed in each crossing portion of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC (TFT) connected to each of the TFTs. The thin film transistor TFT is turned on when the gate signal is supplied from the gate line GL, and supplies the pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when the gate off signal is supplied through the gate line GL to maintain the pixel signal charged in the liquid crystal cell C _LC .

The liquid crystal cell C _LC includes a pixel electrode connected to a common electrode and a thin film transistor TFT with a liquid crystal interposed therebetween. The liquid crystal cell C _LC further includes a storage capacitor C _ST so that the charged pixel signal is stably maintained until the next pixel signal is charged. The storage capacitor C _ST is formed between the pixel electrode and the previous gate line. In the liquid crystal cell C _LC , an arrangement state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, and light transmittance is adjusted accordingly to implement gradation.

As shown in FIG. 2, the gate driver 12 includes a series of gate drivers GD1 to GDn operated in a shift register manner, and includes a clock signal CLK and a start signal VST supplied from the timing controller 11. And the reset signal RST to output the gate signals VGOUT [1] to VGOUT [N] by the timing shown in FIG. That is, the gate drivers GD1 to GDn have the gate signals VGOUT [1] to VGOUT [N] in synchronization with the clock signals CLK [1] to CLK [N] after the start signal VST is input. ) Are printed sequentially. The gate lines GL1 to GLn on the liquid crystal panel 14 are driven by the gate signals VGOUT [1] to VGOUT [N] thus output. The operation of generating such gate signals VGOUT [1] to VGOUT [N] is repeated frame by frame.

4 is a detailed circuit diagram showing a first embodiment of the gate drivers GD1 to GDn. The first and gate AD11 supplies the set signal S of the RS flip-flop FF11 by AND combining the control signal CTL supplied from the timing controller 11, and the second and gate AD12 The reset signal R of the RS flip-flop FF11 is supplied by AND combining the control signal CTL. The RS flip-flop FF11 is operated by the set signal S and the reset signal R supplied as described above, so as to output signals of logic opposite to those of the output terminals Q and QB as shown in FIG. Output

In other words, when the gate high voltage V _GH is output to the output terminal Q of the RS flip-flop FF11, the large sized charging transistor T _U is turned on, whereby the RS flip-flop is turned on. The small size discharge transistor T _D is turned off by the gate low voltage V _GL output from the inverting output terminal QB of the flop FF11. In this state, when the clock signal CLK is supplied, the gate high voltage VGH is supplied from the charging transistor T _U to the corresponding gate line GL.

Thereafter, in the discharge mode, the discharge transistor T _D is turned on by the gate high voltage V _GH output from the inverted output terminal QB of the RS flip-flop FF11. Accordingly, the gate high voltage VGH, which is the charging voltage of the gate line GL, is discharged through the discharge transistor T _D to be maintained at the gate low voltage V _GL .

The charging transistor T _U and the discharging transistor T _D are implemented with a-Si: H TFT, and when such a transistor supplies a positive DC voltage between a source and a gate, a threshold voltage is increased. There is a characteristic that the output current is reduced by deteriorating characteristics.

However, as shown in FIG. 5, a high voltage is output from the output terminal Q of the RS flip-flop FF11 to the gate of the charging transistor T _U for a short time corresponding to the charging time of the gate line. It can be seen that. Therefore, the charging transistor T _U receives a stress voltage for the short time.

On the other hand, it can be seen that a high voltage is output from the output terminal QB of the RS flip-flop FF11 to the gate of the discharge transistor T _D for a long time except for the charging time of the gate line. As a result, the discharge transistor T _D is subjected to a stress voltage for a much longer time than the charging transistor T _U.

As described above, in the conventional liquid crystal display device, when the gate driver outputs the gate signal to each gate line of the liquid crystal panel, a high level gate voltage is supplied to the charging transistor for a short time, so that deterioration of characteristics is relatively slow. The discharge transistors in each gate driver receive a high level of gate voltage for a long time as compared with the charging transistors, and thus deteriorate characteristics. Accordingly, there is a problem in that the discharging transistor does not turn off properly even in a section in which the discharging transistor should be kept off, thereby abnormally outputting a voltage.

The conventional technique proposed to solve this problem is shown in FIG. 6. When comparing the prior art of FIG. 6 with the conventional art of FIG. 5, two discharging transistors T _D1 and T _D2 are employed, and two inverting output terminals QB1 are provided on the RS flip-flop FF11. The difference is that the gate high voltage VGH is outputted alternately in a frame period as shown in FIG. 7 so that the discharge transistors T _D1 and T _D2 are alternately driven in a frame period. .

In the case of using two discharge transistors as described above, the degree of deterioration of the discharging transistor can be significantly reduced, but in this case, the deterioration of the charging transistor still has not been solved.

8 is a cumulative stress applied to the charging transistor T _U and the discharge transistors T _D and T _D1 and T _{D2 in} the prior art Type1 of FIG. 4 and the prior art Type2 of FIG. 6. The voltage is shown. In the discharge transistor T _D of FIG. 4, the cumulative stress voltage is continuously increased because a high gate voltage is continuously supplied except for a charging operation section every frame. On the other hand, the discharge transistors T _D1 and T _D2 in FIG. 6 alternately operate in units of frames, and thus the cumulative stress voltage is not increased and is solved in the next frame. However, in FIGS. 4 and 6, the charging transistor T _U is gradually increased, although much lower than the cumulative stress voltages of the discharge transistors T _D and T _D1 and T _D2 . Can be.

As a result, when one discharge transistor is used in a plurality of gate drivers that are components of a gate driver in a conventional liquid crystal display device, a high gate voltage is continuously supplied every frame except for a charging operation period, thereby accumulating a cumulative stress voltage. There is a problem in that it continues to rise, due to the abnormal output of the voltage is not properly turned off even in the section that needs to maintain the off state. In view of this, when two discharge transistors are used, the degree of deterioration of the discharge transistor can be considerably reduced, but the deterioration of the charging transistor still has a problem that is not solved.

Accordingly, an object of the present invention is to provide a pair of gate drivers for one liquid crystal panel and drive them alternately in a frame period to accumulate stress voltages in the charging transistors as well as the discharge transistors of the respective gate drivers constituting the gate driver. It is to block the continuous supply.

The present invention for achieving the above object is a timing controller for outputting a gate control signal and a data control signal, and sampling and rearranging the digital video data; The gate signal is supplied to each gate line of the liquid crystal panel in response to the gate control signal, and includes a pair of gate drivers configured to supply gate signals while driving alternately at frame periods.

The present invention includes a pair of gate drivers for one liquid crystal panel, and drives them alternately at frame periods, thereby driving a cumulative stress voltage at the charging transistors as well as the discharging transistors of the gate drivers constituting the gate drivers. It can be blocked from being supplied to.

As a result, the deterioration of the discharge transistor and the charge transistor is prevented, thereby extending the life of the circuit and improving the reliability.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 9 is a driving block diagram of a liquid crystal display according to the present invention. As shown in FIG. A timing controller 91 for outputting the digital video data RGB and reordering the digital video data RGB; A pair of gate drivers 91 and 92 for supplying gate signals alternately at frame periods to the gate lines GL0 to GLn of the liquid crystal panel 94 in response to the gate control signal GDC; A data driver 93 for supplying a pixel signal to each of the data lines DL1 to DLm of the liquid crystal panel 94 in response to the data control signal DDC; The liquid crystal panel 94 includes a liquid crystal cell driven by the gate signal and the pixel signal in a matrix form to display an image.

FIG. 10 is a detailed block diagram of the gate drivers 91 and 92. As shown therein, a series of gate drivers GD11 to GD1n driven by the gate drivers 91 and 92 by a shift register method are shown. And (GD21 to GD2n), respectively, and are selectively driven alternately in a frame period by the enable signal ENA supplied from the timing controller 91 to output the gate signals VGOUT [1] to VGOUT [N]. Configure to

FIG. 11 is a detailed circuit diagram of the gate drivers GD11 to GD1n and GD21 to GD2n in FIG. 10, and as shown in FIG. 10, is opposite to the two output terminals Q and QB according to the set signal and the reset signal. An RS flip-flop FF21 for outputting a logic signal; An AND gate AD21 for and combining the enable signal ENA to validate the signal output from the inverted output terminal QB of the RS flip-flop FF21 in odd or even frame periods; It is connected in series between the terminal of the clock signal CLK and the ground terminal, and the gate is connected to the output terminal Q and the inverted output terminal QB of the RS flip-flop FF21, respectively. It consists of a charging transistor (T _U ) and a discharge transistor (T _D ) which generate (G [N]).

When described in detail with reference to Figures 12 to 16 attached to the operation of the present invention configured as described above.

In FIG. 9, except for an operation of outputting a gate signal to each gate line GL1 -GLn of the liquid crystal panel 94 while the gate drivers 92A and 92B are alternately driven at a frame period, operations of the remaining parts are generally performed. The same operation as in the liquid crystal display device.

That is, the timing controller 91 uses the vertical / horizontal synchronization signal Hsync / Vsync and the clock signal CLK supplied from the system to control the gate driver 92A, 92B. And a data control signal DDC for controlling the data driver 93. In addition, the timing controller 91 samples the digital pixel data RGB input from the system, rearranges the digital pixel data RGB, and supplies the same to the data driver 93.

The gate control signal GDC includes a gate start pulse GSP, a gate shift clock signal GSC and a gate-out enable signal GOE. The data control signal DDC includes a source start pulse SSP, A shift clock signal SSC, a source-out enable signal SOE, a polarity signal POL, and the like.

The gate driver 92 is alternately driven in a frame period in response to the gate control signal GDC input from the timing controller 91 to supply a gate signal to the gate lines GL1 to GLn of the liquid crystal panel 94 at each time. do. As a result, the thin film transistors TFTs on the horizontal line are turned on. Accordingly, pixel signals supplied through the data lines DL1 to DLm are stored in the respective storage capacitors C _ST through the thin film transistors TFT.

The data driver 93 converts the pixel data RGB into an analog pixel signal (data signal or data voltage) corresponding to the gray scale value in response to the data control signal DDC input from the timing controller 91. The pixel signal thus converted is supplied to the data lines DL1 to DLm on the liquid crystal panel 94.

The liquid crystal panel 94 is formed for each of intersections of the plurality of liquid crystal cells (C _LC) arranged in a matrix, a data line (DL1~DLm) and gate line (GL1~GLn) each of the liquid crystal cell (C _LC And a thin film transistor (TFT) connected to each of them. The thin film transistor TFT is turned on when the gate signal is supplied from the gate line GL, and supplies the pixel signal supplied through the data line DL to the liquid crystal cell C _LC . The thin film transistor TFT is turned off when the gate off signal is supplied through the gate line GL to maintain the pixel signal charged in the liquid crystal cell C _LC . In the liquid crystal cell C _LC , an arrangement state of liquid crystals having dielectric anisotropy varies according to pixel signals charged through the thin film transistor TFT, and light transmittance is adjusted accordingly to implement gradation.

On the other hand, in the present invention, a pair of gate drivers 92A and 92B are provided as in the above description, and they are alternately driven at a frame period so that the gate lines GL1 to GLn of the liquid crystal panel 94 are each time. The gate signal is supplied to the. In the present description, the gate driver 92A operates in the odd frame and the gate driver 92B operates in the even frame.

The pair of gate drivers 92A and 92B are provided with a series of gate drivers GD11 to GD1n and GD21 to GD2n, respectively, which operate in a shift register manner as shown in FIG. 10, and the timing controller 91. Is selectively driven by the enable signal ENA supplied from the control signal, and at each gate line GL1 of the liquid crystal panel 94 by the clock signal CLK, the start signal VST, and the reset signal RST. The gate signals VGOUT [1] to VGOUT [N] are output to ˜GLn.

To this end, the gate drivers GD11 to GD1n and GD21 to GD2n are implemented as shown in FIG. 11, and the operation thereof will be described with reference to the timing diagram of FIG. 12.

The gate driver circuit of FIG. 11 operates alternately in odd frame or even frame period. In the operating frame mode, the enable signal ENA is supplied from the timing controller 91 to 'high' as shown in FIG. 12.

The gate signal G [N-1] is input 'high' to the set terminal S of the RS flip-flop FF21 in the t1 section of the charging mode, and the voltage VM of the intermediate level is applied to the output terminal Q thereof. Is output, whereby the large-sized charging transistor T _U is turned on. The intermediate level voltage VM is a voltage (V _DD -V _TH ) obtained by subtracting the threshold voltage of the input terminal transistor from the supply voltage.

At this time, the reset signal RESET is inputted to the reset terminal R of the RS flip-flop FF21 as 'low', and a 'low' signal is outputted to the inverted output terminal QB thereof. Since the low signal is output to the output terminal Gd of the AD21, the small size discharge transistor T _D is turned off.

Thereafter, the clock signal CLK = CLK [1] is input as 'high' in the t2 section of the charging mode. Accordingly, due to the coupling phenomenon of the parasitic capacitance C _gd between the gate and the drain of the charging transistor T _U , the voltage of the output terminal Q is changed to the intermediate level voltage VM and the clock signal CLK. ) Is bootstrapping to a higher level voltage (VH) plus a voltage (VGH). Therefore, the gate signal G [N] is output from the gate driver at the voltage level VGH of the clock signal CLK during the t2 period.

The gate signal G [N] output from the corresponding gate driver is commonly supplied to the corresponding gate line of the liquid crystal panel 94 and the set terminal S of the RS flip-flop FF21 of the next stage gate driver. .

Thereafter, the clock signal CLK = CLK [1] is lowered to the 'low' level voltage VGL in the period t3 of the discharge mode, and the clock signal CLK = CLK [2] supplied to the next gate driver. ) Rises to the voltage of the 'high' level. In this case, the gate signal G [N-1] is input as 'low' to the set terminal S of the RS flip-flop FF21. Thus, the charging transistor T _U is turned off.

At this time, the reset signal RESET is inputted to the reset terminal R of the RS flip-flop FF21 as 'high', and a 'high' signal is outputted to the inverted output terminal QB thereof. Since the 'high' signal is output to the output terminal Gd of the AD21, the discharge transistor T _D is turned on. Accordingly, the discharge operation of the gate signal G [N] is performed through the discharge transistor T _D so that the potential of the corresponding gate line transitions to a 'low' level.

Thereafter, when the enable signal ENA transitions to 'low', the terminal of the gate signal G [N] is in a floating state, that is, a high impedance state Hi-Z.

FIG. 13 illustrates an operation timing diagram of a gate driver operating as shown in FIG. 11 by dividing an odd frame and an even frame.

That is, in the odd frame, the enable signal ENAO is supplied to the gate drivers GD11 to GD1n of any gate driver, for example, the gate driver 92A, at high, and the gate drivers GD11 to GD1n are supplied. Gate signals G0 [1] to GO [N] are sequentially generated in synchronization with the clock signal CLKO. At this time, the output terminals of the gate drivers GD21 to GDn of the gate driver 92B are in the floating state Hi-Z.

In the even frame, the enable signal ENAO is supplied 'high' to the gate drivers GD21 to GD2n of the gate driver 92B, and the gate drivers GD21 to GD2n are synchronized with the clock signal CLKE. The gate signals G0 [1] to GO [N] are sequentially generated. At this time, the output terminals of the gate drivers GD11 to GD1n of the gate driver 92A are in a floating state Hi-Z.

FIG. 14 is a detailed circuit diagram illustrating an exemplary embodiment of the gate driver illustrated in FIG. 11 and the operation thereof will be described with reference to FIG. 12. Here, the transistors T1-T5 are the components of the RS flip-flop FF21 in FIG. 11, and the transistors T6 and T7 are the components of the AND gate AD21, and the charging transistor T _U and the discharge capacitor are shown in FIG. 11. The transistor T _D is a component of the gate signal output unit 111.

When the gate signal G [N-1] is input as 'high', the diode-type transistor T1 is turned on to output an intermediate level voltage VM to the output terminal Q. The gate signal G [N-1] is a signal input to the set terminal S.

At this time, the reset signal RESET is input to 'low' so that the transistor T3 is maintained in the off state. In this state, the transistor T5 is turned on by the 'high' signal output through the transistor T1, so that the potential of the inversion output terminal QB is maintained at 'low', whereby the transistor T6 is turned on. Since it is turned off, the enable signal ENA is not transmitted to the output terminal Gd through the transistor T6. In this case, since the transistor T7 is turned on by the gate signal G [N-1] of the 'high', the potential of the output terminal Gd of the AND gate AD21 is maintained at 'low'. Therefore, while the charging transistor T _U of the gate signal output unit 111 is turned on, the discharge transistor T _D is turned off.

Thereafter, when the gate signal G [N-1] transitions to 'low' and then the gate of the charging transistor T _U is input when the clock signal CLK = CLK [1] is input to 'high'. Due to the coupling phenomenon of the parasitic capacitance C _gd between the drain and the drain, the voltage of the output terminal Q of the RS flip-flop FF21 is set to the voltage VM and the voltage of the clock signal CLK. VGH) is added to bootstrapping to a higher level of voltage VH. Accordingly, the gate signal G [N] is output from the gate signal output unit 111 at the voltage level VGH of the clock signal CLK.

Thereafter, the clock signal CLK transitions to 'low' and the reset signal RESET is input to 'high'. Accordingly, since the transistor T3 is turned on and the voltage of the output terminal Q is muted to the ground terminal V _SS through the transistor T3, the voltage of the output terminal Q is set to 'low'. Transition. As a result, the charging transistor T _U is turned off.

As described above, when the gate signal G [N-1] transitions to 'low', the diode-type transistor T1 is turned off. Accordingly, the transistor T5 is turned off, and a 'high' signal is output to the inverting output terminal QB through the diode transistor T4.

As a result, the transistor T6 is turned on and the transistor T7 is kept turned off after the gate signal G [N-1] transitions to 'low'. As a result, a 'high' signal is output to the output terminal Gd of the AND gate AD21, whereby the discharge transistor T _D is turned on. Accordingly, the discharge operation of the gate signal G [N] is performed through the discharge transistor T _D.

FIG. 15 is a waveform diagram showing an operation simulation result of the gate drivers 92A and 92B according to the present invention. That is, the potentials of the output node Q node, the inverted output node QB node of the RS flip-flop FF21, and the output node Gd node of the AND gate AD21 are normally generated as described above. When the enable signal ENA transitions to 'low', the output node Gd node of the AND gate AD21 becomes 'low' so that the terminal of the gate signal G [N] is in a high impedance state Hi. -Z).

FIG. 16 shows the charging transistor T _U of the gate signal output unit 111 in the gate drivers GD11 to GD1n and GD21 to GD2n which are components of the gate drivers 92A and 92B according to the present invention. And the cumulative stress voltage of the discharge transistor T _D. As shown therein, the cumulative stress voltage of the charging transistor T _U hardly increases at an initial low value. In addition, the cumulative stress voltage of the discharge transistor T _D is slightly increased and then is completely eliminated in the next frame.

1 is a driving block diagram of a conventional liquid crystal display device.

FIG. 2 is a detailed block diagram of the gate driver of FIG. 1. FIG.

3 is a waveform diagram of each part in Fig.

4 is a circuit diagram of the gate driver in Fig.

5 is an output signal timing diagram of an RS flip-flop in FIG. 4;

6 is another circuit diagram of the gate driver in FIG.

7 is an output signal timing diagram of an RS flip-flop in FIG.

8 is a waveform diagram showing a cumulative stress voltage of a transistor of a gate driver according to the prior art.

9 is a block diagram of a driving circuit of a liquid crystal display device according to the present invention;

FIG. 10 is a detailed block diagram of the gate driver of FIG. 9; FIG.

FIG. 11 is a circuit diagram of a gate driver in FIG. 10.

12 is a waveform diagram of each part in FIG. 11;

FIG. 13 is a frame timing diagram of two gate drivers of FIG. 10; FIG.

14 is a detailed circuit diagram illustrating an implementation of the gate driver of FIG. 11.

15A to 15C are waveform diagrams showing simulation results of a gate driver according to the present invention.

Figure 16 is a waveform diagram showing the cumulative stress voltage of the transistor of the gate driver according to the present invention.

DESCRIPTION OF THE REFERENCE SYMBOLS

91: timing controller 92A, 92B: gate driver

93: data driver 94: liquid crystal panel

SR11-SR1n, SR21-SR2n: Gate Driver FF21: RS Flip-Flop

AD21: AND gate T _U : charging transistor

T _D : Discharge Transistor

Claims (8)

A liquid crystal panel in which a plurality of gate lines and data lines cross each other; First and second gate drivers formed of a plurality of gate drivers, the first and second gate drivers being alternately driven in a frame period in response to the enable signal to supply gate signals to the corresponding gate lines; A data driver supplying a pixel signal to the data line; And A timing controller configured to supply the enable signal to the first and second gate drivers, to control the first and second gate drivers and the data driver, and to output digital video data; The gate driver includes: An RS flip-flop for outputting a signal of logic opposite to the output terminal and the inverted output terminal according to the set signal and the reset signal; An AND gate for performing an AND combination with an enable signal for validating the signal output from the inverted output terminal of the RS flip-flop in odd or even frame periods; A gate signal output unit driven by an output signal of the RS flip-flop and an AND gate to generate a gate signal Liquid crystal display device characterized in that consisting of. delete delete The method of claim 1, The RS flip-flop has a set terminal connected to an output terminal through a diode type first transistor, and its connection point is connected to a ground terminal through second and third transistors connected in parallel, and a power supply terminal V _DD is connected to a diode type fourth transistor. And a connection point connected to the ground terminal through the fifth transistor. The method of claim 1, The AND gate has an enable terminal connected to the inverted output terminal through the sixth transistor, and its connection point is connected to the ground terminal through the seventh transistor, and the gates of the sixth and seventh transistors are respectively connected to the inverted output terminal and the set terminal. A liquid crystal display device, characterized in that the connection is configured. The method of claim 1, The gate signal output unit is connected in series between a clock signal terminal and a ground terminal and a gate is connected to an output terminal and an inverted output terminal of the RS flip-flop to generate a gate signal at a drain and a source common connection point; A liquid crystal display device comprising a discharge transistor. The method according to claim 6, The charging transistor is turned on by the voltage output from the output terminal of the RS flip-flop to output the voltage VM of the intermediate level, and to output the voltage raised to the voltage level VGH of the clock signal input to the source terminal. Liquid crystal display device characterized in that the configuration. The method according to claim 6, And wherein the discharge transistor causes a terminal of an output signal to be in a floating state when the enable signal transitions to 'low'.

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