JP2002222960A - Electro-optic device and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT having high reliability, an electro-optic device using the TFT by efficiently gettering a catalyst element for promoting a crystallization of an amorphous silicon film and a method for manufacturing the same. SOLUTION: The electro-optic device comprises an n-channel TFT and a p-channel TFT having a semiconductor layer including a channel forming region (13), a region (11) containing an n-type impurity element and a p-type impurity element, and a region (12) containing only a p-type impurity element so that wirings for electrically connecting the respective TFTs are connected to the region (12) containing only the p-type impurity element and the region doped with the n-type impurity element is narrowed as compared with the region doped with the n-type impurity element in the semiconductor layer of the n- channel TFT.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an electro-optical device (semiconductor device) including a circuit formed by a thin film transistor (hereinafter, referred to as a TFT) on an insulator, and a method for manufacturing the same. In particular, the present invention provides an electro-optical device (semiconductor device) typified by a liquid crystal display device in which a pixel portion and a driver circuit provided therearound are provided on the same substrate, and the electro-optical device (semiconductor device) as a display portion It relates to the electrical equipment used.

[0002]

2. Description of the Related Art In recent years, a polycrystalline semiconductor film (polysilicon film) obtained by crystallizing an amorphous semiconductor film (amorphous silicon film) formed on an insulating substrate such as glass, especially a crystalline semiconductor film (crystalline silicon film) has been developed. TFTs using a film as an active layer are being actively developed.

Further, research and development have been continued on a process for forming a large-area polysilicon film on a substrate having low heat resistance such as a glass substrate or a plastic substrate. As a so-called low-temperature crystallization technique, there are a crystallization method using a laser beam and a crystallization method in which a catalyst element for promoting crystallization is added and heat-treated.

A technique for adding a catalytic element for promoting crystallization to an amorphous silicon film and performing heat treatment for crystallization is disclosed in Japanese Patent Application Laid-Open No. Hei 7-130652.

According to this technique, the crystallization temperature of the amorphous silicon film can be lowered by 50 to 100 ° C. by the action of a catalytic element, and the time required for crystallization is reduced by 1/100.
Since it can be reduced to 5/10, it is possible to form a large-area crystalline silicon film on the above-mentioned substrate having low heat resistance. It has also been confirmed that a crystalline silicon film obtained by this technique has excellent crystallinity.

[0006]

In the above-described crystallization technique using a catalyst element, a metal element such as Ni or Co is used as the catalyst element. These metal elements form a deep energy level in the silicon film to capture carriers and recombine. Therefore, when a TFT is manufactured using the obtained crystalline silicon film, the electrical characteristics and the properties of the TFT are evaluated. It can be expected to have an adverse effect on reliability.

It has also been confirmed that the catalyst element remaining in the silicon film segregates irregularly, and this segregation is particularly observed at the crystal grain boundaries, and this segregation becomes a weak current escape path (leak path). This is considered to cause a sudden increase in off-state current (current when the TFT is in an off-state).

Therefore, when the crystallization step is completed, it is necessary to remove the catalytic element promptly or reduce the catalytic element to such an extent that no electrical influence is exerted. As this means, a technique utilizing the gettering effect can be used.

As a gettering method, an amorphous silicon film is crystallized with a metal element to form a crystalline silicon film, and then a portion to be a channel formation region of a semiconductor layer of the TFT is covered with a resist mask.
A region other than the channel formation region of the semiconductor layer described above, which is doped with a group 15 element such as P which is effective for gettering at a high concentration to form a region that promotes gettering (hereinafter referred to as a gettering sink) or the like. Next, a region to be a channel forming region of the TFT is covered with a mask made of resist,
15 such as P around the area where the FT semiconductor layer is formed.
A method of providing a gettering sink containing a high concentration of group element and performing gettering has been considered. However, in these methods, a process for forming a mask is required, and the number of masks and the number of processes increase, so that productivity and
There are problems in terms of yield and manufacturing cost.

In a p-channel TFT, after a large amount of phosphorus for gettering is doped, a p-type impurity element (boron (B) in this embodiment) is added to obtain a p-channel TFT. Thus, a source region and a drain region are formed. A significant concentration of boron (B) must be doped in order to reverse the n-type application by pre-doped phosphorus (P).

For this reason, there is a problem that the throughput in the doping process is reduced, or it becomes difficult to improve the crystallinity of the source region and the drain region by the heat treatment.

In order to perform the gettering process,
It is necessary that phosphorus (P) is added to the semiconductor layer. However, in order to form a p-channel TFT, it is necessary to add a p-type impurity element (typically, boron (B)). Before the step of adding boron (B) to the semiconductor layer of the p-channel TFT, there is a step of adding an n-type impurity element (phosphorus (P)). Is added (also called counter doping or cross doping). It is necessary to increase the concentration of boron (B) beyond the concentration of phosphorus (P) to be added. However, if the impurity concentration is too high, the resistance of the source / drain region increases, which causes a decrease in on-current. Would. Further, when the counter doping method is adopted, there is a problem in manufacturing cost and productivity because ions that become acceptors must be excessively doped.

[0013]

A method for manufacturing an electro-optical device (semiconductor device) disclosed in the present invention will be described. When the conductive film (A) and the conductive film (B) formed over the gate insulating film are etched to form a gate electrode, the gate electrode of the n-channel TFT is etched into a predetermined shape. However, the gate electrode (C) of a p-channel TFT
Is used as a mask so that the region where the n-type impurity element is added to the semiconductor layer of the p-channel TFT does not become large in the subsequent n-type impurity element adding step. The conductive films (A) and (B) are etched so that the width in the channel length direction is larger than that of the electrode (B). Using this gate electrode (C) as a mask, the gate electrode (C)
Is doped with phosphorus (P) in a semiconductor layer region which does not overlap with.
The region where phosphorus (P) is implanted functions as a gettering sink.

Next, the gate electrode (D) of the p-channel TFT is etched into a predetermined shape to obtain a gate electrode (E) of a predetermined shape, and then a p-type is applied to the semiconductor layer of the p-channel TFT. Doped with boron (B). Through the steps so far, a channel formation region, a region doped with phosphorus (P) and boron (B), and a region doped only with boron (B) are formed in the semiconductor layer of the p-channel TFT. .

According to the present invention, at the time of gettering, the distance over which the catalytic element moves in the semiconductor layer of the p-channel TFT can be shortened, so that the segregation of the catalytic element at the crystal grain boundaries is reduced, and It is possible to reduce phenomena such as a weak current escape path (leak path) and an off current (a sudden increase in T), thereby improving the characteristics and reliability of the TFT.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention disclosed in this specification is characterized by a method of forming a gate electrode of a p-channel TFT into a predetermined shape. The present invention will be described with reference to FIG.

[0017] In order to solve the above problems, an object of the invention disclosed in this specification is to reduce the amount of phosphorus (P) added to a semiconductor layer of a p-channel TFT.

In order to prevent the catalyst element from segregating at the crystal grain boundaries and causing this to deteriorate TFT characteristics,
At the time of gettering, the movement distance of the catalyst element moving inside the semiconductor layer from the channel formation region to the source region and the drain region is made as short as possible.

Therefore, in the present invention, an n-channel TFT
The etching step of making the gate electrode of the P-type TFT and the gate electrode of the p-channel type TFT into a predetermined shape is a separate step. As shown in FIG. 1A, first, a gate electrode of an n-channel TFT is formed into a predetermined shape by etching, and an n-type impurity element is added. FIG. 1D shows a state of the p-channel TFT at this time as viewed from above. Conductive film (A)
Then, the conductive film (B) is etched to be larger than a predetermined gate electrode shape. The conductive film (A) and the conductive film (B) are referred to as a gate electrode 8. Using this gate electrode 8 as a mask, a region 10 to which n-type impurity element phosphorus is added is formed.

Subsequently, as shown in FIG. 1B, after forming a mask on the n-channel TFT, the p-channel TF
The conductive film of T is etched to form a gate electrode 9 having a predetermined shape.
To form After that, a p-type impurity element is added as shown in FIG. By employing such steps, in the p-channel TFT, only the region 11 to which phosphorus is added as an n-type impurity element and boron is added as a p-type impurity element, and only boron is added, as shown in FIG. Although the region 12 is formed, the region 11 to which phosphorus and boron serving as counter doping are added can be narrowed. Note that the impurity element is not added to the semiconductor layer below the gate electrode etched into a predetermined shape.
It becomes the channel formation region 13.

As described above, in the semiconductor layer of the p-channel TFT, as shown in FIG. 1E, a region to which both phosphorus (P) and boron (B) are added is formed. The object of the present invention is achieved by using 11 as a gettering sink.

In the p-channel TFT, the conductive film (A) and the conductive film (B) are etched to form a gate electrode 18 as shown in FIG.
8 may be used as a mask to add an n-type impurity element. Thus, a region 20 to which only phosphorus is added as shown in FIG. Then, after the gate electrode 18 is etched into a predetermined shape to form the gate electrode 19, a p-type impurity element is added, and the regions 21a and 21b to which the n-type impurity element and the p-type impurity element are added are connected to the p-type impurity element. A region 22 to which only the impurity element is added is formed. As described above, when gettering as shown in FIG.
It is also possible to realize a structure in which the distance over which the catalytic element moves to the gettering sink is reduced.

(Embodiment 1) FIGS. 2 to 5 show an embodiment of the present invention.
This will be described with reference to FIG. Here, a method for manufacturing a pixel TFT in a pixel portion and a TFT of a driver circuit provided in the periphery of the pixel portion over the same substrate will be described in detail according to the process.

In FIG. 3A, a low alkali glass substrate or a quartz substrate can be used as the substrate 100. In this embodiment, a low alkali glass substrate was used. in this case,
Heat treatment may be performed in advance at a temperature lower by about 10 to 20 ° C. than the glass strain point. TF of this substrate 100
A base film 101 such as a silicon oxide film, a silicon nitride film, or a silicon oxynitride film is formed on a surface on which T is formed in order to prevent impurity diffusion from the substrate 100. For example, a silicon oxynitride film made of SiH4, NH3,
A silicon oxynitride film made of H4 and N2O
The layer is formed to a thickness of nm.

Next, 20 to 150 nm (preferably 30 nm)
Semiconductor film having an amorphous structure with a thickness of
It is formed by a known method such as a plasma CVD method or a sputtering method. In this embodiment, an amorphous silicon film is formed to a thickness of 55 nm by a plasma CVD method. Examples of the semiconductor film having an amorphous structure include an amorphous semiconductor film and a microcrystalline semiconductor film. Since the base film 101 and the amorphous silicon film can be formed by the same film formation method, both may be formed continuously. After forming the base film, it is possible to prevent the surface from being contaminated by not once exposing it to the atmosphere, thereby reducing the variation in the characteristics of the TFT to be manufactured and the fluctuation of the threshold voltage (FIG. 3A )).

Then, a semiconductor film having a crystal structure (a crystalline silicon film in this embodiment) is formed according to the technique described in Japanese Patent Application Laid-Open No. 7-130652. The technology described in the publication discloses a catalyst element (Ni, Co, Sn, Pb, Pb) that promotes crystallization during crystallization of an amorphous silicon film.
One or more elements selected from d, Fe, and Cu. Typically, it is Ni. ).

More specifically, heat treatment is performed with the catalytic element held on the surface of the amorphous silicon film to change the amorphous silicon film into a crystalline silicon film. In this embodiment, the method described in Example 1 of the publication is used, but the method described in Example 2 may be used. In addition,
The crystalline silicon film includes a so-called single-crystal silicon film and a polysilicon film. The crystalline silicon film formed in this embodiment is a silicon film having a crystal grain boundary.

As a method for adding the catalyst element to the amorphous silicon film, a gas phase method such as a plasma doping method, an evaporation method or a sputtering method, or a method of applying a solution containing the catalyst element can be adopted. In the method using a solution, it is easy to control the addition amount of the catalyst element, and it is easy to add a very small amount.

Further, by combining the above-described crystallization method and laser crystallization method, the crystallinity of the crystalline semiconductor film can be further enhanced. As a laser used at this time, a pulse transmission type or continuous emission type KrF excimer laser, XeCl excimer laser, YAG laser or YVO ₄ laser can be used.
In the case of using these lasers, it is preferable to use a method in which laser light emitted from a laser transmitter is linearly condensed by an optical system and irradiated on a semiconductor film. The crystallization conditions are
The practitioner may select as appropriate.

When the amorphous silicon film is crystallized, rearrangement of atoms occurs and the film becomes denser. Therefore, the thickness of the crystalline silicon film to be formed is equal to the initial thickness of the amorphous silicon film (in this embodiment, 55 nm).

Then, the crystalline silicon film is divided into islands, and island-like semiconductor layers 102 to 105 are formed.

Here, for the purpose of controlling the threshold voltage over the entire surface of the island-shaped semiconductor layers 102 to 105 forming the n-channel type TFT, the p-type is formed at a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ^3. Boron (B) may be added as an impurity element that imparts the following. Boron (B) may be added by an ion doping method, or may be added simultaneously with the formation of the amorphous silicon film. Although the addition of boron (B) here is not always necessary, it is preferable that the semiconductor layers 102 to 105 to which boron (B) is added be formed in order to keep the threshold voltage of the n-channel TFT within a predetermined range. It was good.

Next, the gate insulating film 106 is
The insulating film containing silicon is formed with a thickness of 10 to 150 nm by a VD method or a sputtering method. For example, 120
A silicon oxynitride film is formed with a thickness of nm. As the gate insulating film 106, another insulating film containing silicon may be used as a single layer or a stacked structure.

Next, a conductive film (A) 107 and a conductive film (B) 108 are formed to form a gate electrode. In this embodiment, a conductive layer (A) 107 made of a conductive nitride metal film and a conductive layer (B) 108 made of a metal film are laminated. The conductive layer (B) 108 is made of tantalum (Ta),
An element selected from titanium (Ti), molybdenum (Mo), and tungsten (W), an alloy containing the above element as a main component, or an alloy film combining the above elements (typically, a Mo-W alloy film, Mo -Ta alloy film), and the conductive layer (A) 107 is formed with a tantalum nitride (TaN), a tungsten nitride (WN), a titanium nitride (TiN) film, and a molybdenum nitride (MoN). As the conductive layer (A) 107, tungsten silicide, titanium silicide, or molybdenum silicide may be used as an alternative material. The conductive layer (B) may have a low impurity concentration in order to reduce the resistance, and it is particularly preferable that the oxygen concentration be 30 ppm or less. For example, when tungsten (W) has an oxygen concentration of 30 ppm or less, a specific resistance of 20 μΩcm or less can be realized.

The conductive layer (A) 107 has a thickness of 10 to 50 nm (preferably 20 to 30 nm), and the conductive layer (B) 108 has a thickness of 200 to 400 nm (preferably 250 to 350 nm).
It is good. In this embodiment, the conductive layer (A) 107 has 3
A tantalum nitride film having a thickness of 0 nm is formed on the conductive layer (B) 108.
Were formed by sputtering using a 350 nm Ta film. In the film formation by the sputtering method, if an appropriate amount of Xe or Kr is added to Ar of the gas for sputtering, the internal stress of the film to be formed can be relaxed and the film can be prevented from peeling. Although not shown, it is effective to form a silicon film doped with phosphorus (P) with a thickness of about 2 to 20 nm under the conductive layer (A) 107. This allows
At the same time as improving the adhesion of the conductive film formed thereon and preventing oxidation, the conductive layer (A) 107 or the conductive layer (B) 1
3 can be prevented from diffusing into the gate insulating film 106 (FIG. 3).
(A)).

Next, a mask 109-
112 are formed, and a first etching process for forming a gate electrode and a capacitor wiring of each TFT is performed. In this embodiment, the first etching condition is ICP
(Inductively Coupled Plasma)
Using an etching method, CF ₄ and Cl ₂ are used as etching gases.
And O ₂ , and the respective gas flow ratios are 25/25 /
10 (sccm) and a pressure of 1 Pa, 50
An RF (13.56 MHz) power of 0 W was supplied to generate plasma to perform etching. A 150 W RF (13.56 MHz) power is also applied to the substrate side (sample stage), and a substantially negative self-bias voltage is applied. The W film is etched under the first etching conditions to form the first film.
Of the conductive layer is tapered.

Thereafter, the second etching condition is changed without removing the masks 109 to 112, and the etching gas is changed to C.
Using F ₄ and Cl ₂ , each gas flow ratio was 30/3.
0 (sccm) and a pressure of 1 Pa is applied to the coil-type electrode for 500
An RF (13.56 MHz) power of W was applied to generate plasma, and etching was performed for about 30 seconds. A 20 W RF (13.56 MHz) power is also applied to the substrate side to apply a substantially negative self-bias voltage. CF ₄
Under the second etching condition in which C ₂ and Cl ₂ are mixed, both the W film and the TaN film are etched to the same extent. In the steps so far, the conductive film (A) 107 and the conductive film (B) 10
A gate electrode (A) 113 of an n-channel TFT, a gate electrode (C) 114 of a p-channel TFT, a gate electrode (F) 115 of a pixel TFT, and a capacitor wiring 116 are formed. . Note that the gate electrode (C) 114 of the p-channel TFT is an n-channel TF
It is designed to be formed to be larger in size than the T gate electrode (A) 113 and the pixel TFT gate electrode (F) 115. In the steps so far, regions of the gate insulating film 106 which are not covered with the masks 109 to 112 are etched and thinned. Note that the gate electrode (A), the gate electrode (C), the gate electrode (F), and the capacitor wiring 116 formed by the first etching treatment are also referred to as a first-shaped gate electrode and a capacitor wiring. Gate electrode (C)
114 indicates that p is added in a later step of adding an n-type impurity element.
The gate electrode (A) 1 in the n-channel TFT is used as a mask so that the region of the semiconductor layer of the channel TFT to which the n-type impurity element is added is not widened.
13 is formed wider.

Then, without removing the masks 109 to 112, a process of adding an n-type impurity element is performed to form an impurity region 118 (FIG. 3B). Phosphorus (P) or arsenic (As) may be used as the n-type impurity element. Here, phosphine (PH ₃ ) is added to add phosphorus (P).
The ion doping method using is applied.

Further, a second etching process is performed without removing the masks 109 to 112. Here, CF ₄ , Cl _2, and O ₂ are used as etching gases, the respective gas flow ratios are 20/20/20 (sccm), and 500 W of RF (13. 56MHz)
Power is applied and a substantially negative self-bias voltage is applied. According to the second etching condition, the W film is selectively etched.

By the second etching process, the conductive films (A) 113a to 116a and the conductive film (B) 113b
To 116b are etched to form the gate electrode (B) 11
9, gate electrode (D) 120, gate electrode (G) 12
1. The capacitance wiring 122 is formed. In this step, the gate electrode (B) 119, the gate electrode (G) 121, and the capacitor wiring 122 of the n-channel TFT are formed in a predetermined shape, and the gate electrode (D) of the p-channel TFT is formed. Reference numeral 120 denotes a predetermined shape (another gate electrode (B) 119, a gate electrode (G) for use as a mask for narrowing a region containing a high concentration of an n-type impurity element in a semiconductor layer of a p-channel TFT. ) 121)
Formed to a larger size. Note that the gate electrode (B) 119, the gate electrode (G) 121, the gate electrode (D) 120, and the capacitor wiring 122 formed by the second etching treatment are also referred to as a gate electrode and a capacitor wiring of a second shape. I do.

Next, a process of adding an n-type impurity element to the semiconductor layer is performed. A gate electrode (B) 119, a gate electrode (D) 120 formed by the second etching process;
Using the gate electrode (G) 121 as a mask, the semiconductor layer below the tapered portion of the conductive film (A) is doped so that the n-type impurity element is also added, so that the n-type impurity regions (A) 123a to 123a are formed. 126a and n-type impurity regions (B) 123b to 126b are formed. The impurity (phosphorus (P)) concentration of the impurity regions 123a to 126a formed at this time may be set to 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ . (In this specification, the concentration of the n-type impurity element contained in the n-type impurity regions 123a to 126a is represented by (n +).) Further, the n-type impurity region (B)
The impurity concentration of 123b to 126b is 5 × 10 ^{17 to} 5 ×
What is necessary is just to set it as 10 ¹⁹ atoms / cm ³ . In this specification, the concentration of the n-type impurity element contained in the n-type impurity regions 123b to 126b is represented by (n-). Although the n-type impurity region 123c overlapping the tapered portion of the conductive layer (A) 119a has a slightly lower impurity concentration,
An impurity region having substantially the same concentration as that of type impurity region 123b is formed (FIG. 4A).

Next, a mask 109-
After removing 112, a mask 127 made of a resist covering the n-channel TFT is newly formed, and a third etching process is performed. SF6 and C are used as etching gases.
l2 and each gas flow ratio is 50/10 (SCC
M) and a pressure of 1.3 Pa is applied to the coil-type electrode at 500
An RF (13.56 MHz) power of W is supplied to generate plasma, and etching is performed for about 30 seconds. A 10 W RF (13.56 MHz) power is applied to the substrate side (sample stage) to apply a substantially negative self-bias voltage. Through the above steps, the gate electrode (D ′) 128 of the p-channel TFT and the gate electrode (H) 1 of the pixel TFT in which the conductive films (A) 120 a and 121 a are etched.
29 are formed. Note that the gate electrode (D ′) 128 and the gate electrode (H) 129 formed by the third etching treatment are also referred to as a third shape gate electrode.

Next, a mask 130 made of a resist for etching to make the gate electrode (D ') 128 of the p-channel TFT a predetermined size and a pixel TFT are formed.
And a mask 131 made of a resist covering the capacitance wiring,
132 is formed. Next, the gate electrode (D ') 128 of the p-channel TFT is etched to obtain the gate electrode (E) 133 of the p-channel TFT (FIG. 4).
(C)). Note that the gate electrode (E) 133 formed by the fourth etching treatment is also referred to as a fourth shape gate electrode.

Next, a p-type impurity element (boron (B) in this embodiment) is added to the semiconductor layer of the p-channel type TFT to form p-type impurity regions 134 to 137. The p-type impurity regions 134 and 136 are added so that the impurity concentration of the p-type impurity element becomes 2 × 10 ²⁰ to 2 × 10 ²¹ atoms / cm ³ . Note that, in this embodiment, before adding boron (B) to the semiconductor layer of the p-channel TFT, the TaN film provided above the region of the semiconductor layer to which boron (B) is added is removed. Boron (B) can be added at low acceleration, and damage to the semiconductor layer at the time of addition can be reduced.

Through the steps so far, an n-type impurity region and a p-type impurity region are formed in each semiconductor region (FIG. 4D).

Next, the masks 130 to 132 are removed, and an inorganic interlayer insulating film 138 is formed. 50 silicon nitride, silicon oxide, or silicon nitride oxide film
It is formed with a thickness of about 500 nm (typically 100 to 300 nm). In this embodiment, a 150-nm-thick silicon oxynitride film is formed by a plasma CVD method. Of course,
The inorganic interlayer insulating film is not limited to a silicon oxynitride film, and may have another insulating film containing silicon in a single layer or a stacked structure.

Next, a step of activating the impurity element added to the semiconductor layer is performed. This activation step is performed using a furnace annealing furnace. As a thermal annealing method, an oxygen concentration is 400 to 700 ° C. in a nitrogen atmosphere of 1 ppm or less, preferably 0.1 ppm or less, typically 500 to 55 ° C.
The activation treatment may be performed at 0 ° C., and in this embodiment, the activation treatment is performed by heating at 550 ° C. for 4 hours. In addition to the thermal annealing method, a laser annealing method or a rapid thermal annealing (RTA) method can be applied.

In this embodiment, simultaneously with the activation treatment, gettering is performed on an n-type impurity region containing a high concentration of phosphorus in order to reduce the remaining amount of the catalyst element used as a catalyst during crystallization. I was letting it. The concentration of phosphorus (P) necessary for gettering is almost the same as that of the impurity region (n +) formed in FIG. 4B, and the heat treatment in the activation step performed here causes the n-channel TFT and The catalyst element could be gettered from the channel formation region of the p-channel TFT. Since the obtained TFT has a low off-current value and high crystallinity, high field-effect mobility can be obtained, and favorable characteristics can be achieved.

An activation treatment may be performed before the formation of the inorganic insulating film 138. However, when the material used for the gate electrode was weak to heat, an interlayer insulating film (an insulating film containing silicon as a main component, for example, a silicon nitride film) was formed for the purpose of protecting the wiring and the like as in this embodiment. It is desirable to perform the activation process later.

Further, a heat treatment is performed at 300 to 550 ° C. for 1 to 12 hours in an atmosphere containing 3 to 100% of hydrogen to perform a step of hydrogenating the semiconductor layer. In this embodiment,
Heat treatment is performed at 410 ° C. for one hour in a nitrogen atmosphere containing about 3% of hydrogen. In this step, dangling bonds in the semiconductor layer are terminated by hydrogen contained in the interlayer insulating film. As another means of hydrogenation, plasma hydrogenation (using hydrogen excited by plasma) may be performed.

When a laser annealing method is used as the activation treatment, it is preferable to irradiate a laser beam such as an excimer laser or a YAG laser after performing the above hydrogenation.

Next, an organic interlayer insulating film 139 made of an organic insulating material is formed on the inorganic interlayer insulating film 138.
In this embodiment, an acrylic resin film having a thickness of 1.6 μm was formed. Next, patterning for forming a contact hole reaching each impurity region is performed.

Thereafter, a transparent conductive film is formed with a thickness of 80 to 120 nm, and the pixel electrode 140 is formed by patterning. For the transparent conductive film, indium oxide zinc oxide alloy (In ₂ O ₃ —ZnO), zinc oxide (ZnO)
Is also a suitable material, and zinc oxide (Z) to which gallium (Ga) is added in order to further increase the transmittance and conductivity of visible light.
nO: Ga) can also be applied.

Then, in the drive circuit portion 205, wirings 141 to 143 electrically connected to the impurity regions are formed. Note that these electrodes are formed by patterning a stacked film of a 50-nm-thick Ti film and a 500-nm-thick alloy film (an alloy film of Al and Ti).

In the pixel portion 206, wirings 144 to 147 in contact with the impurity regions are formed.

The pixel electrode 140 is formed of the semiconductor layer 10 functioning as one electrode forming a storage capacitor by the wiring 146.
5 is electrically connected.

In this embodiment, an example in which a transparent conductive film is used as the pixel electrode 140 has been described. However, if a pixel electrode is formed using a reflective conductive material, a reflective display device can be manufactured. can do. In that case, a pixel electrode can be formed simultaneously in the process of manufacturing the electrode, and a material having excellent reflectivity such as a film mainly composed of Al or Ag or a laminated film thereof is used as a material of the pixel electrode. Is desirable.

As described above, the TFT of the driving circuit is formed on the same substrate.
And a substrate having pixel TFTs in the pixel portion. The driving circuit includes an n-channel TFT 201, p
A channel type TFT 202, and a pixel TFT 20 in a pixel portion.
3. A storage capacitor 204 was formed. In this specification, such a substrate is referred to as an active matrix substrate for convenience.

FIG. 2 is a top view of the active matrix substrate manufactured by the steps described above. Note that the line AA ′ in FIG. 2 corresponds to the line AA ′ in FIG. 5B, and the semiconductor layer 104, the gate electrode 121, the wiring 144, the gate line, and the source line are formed. Similarly, BB 'in FIG.
The line corresponds to the line BB ′ of FIG.
5, a pixel electrode 140 and a wiring 146 are formed.

The n-channel TFT 201 of the driving circuit is
In the island-shaped semiconductor layer 102, a channel formation region, a source or drain region 123a, an impurity region 123b, and an impurity region 123c overlapping with the second shape gate electrode (B) 119 (hereinafter, such an impurity region is referred to as Lov) have. The length of the Lov region in the channel length direction is 0.5 to 3.0 μm, preferably 1.0 to 1.5 μm.
m. Further, a second shape gate electrode (B) 119 formed of a stacked layer of the conductive film (A) 119a and the conductive film (B) 119b is provided.

The p-channel type TFT 202 of the driving circuit is
The island-shaped semiconductor layer 103 includes a channel formation region, a source or drain region 124a, and an impurity region 124b. Further, a fourth shape gate electrode (E) 133 formed of a stacked layer of the conductive film (A) 133a and the conductive film (B) 133b is provided.

The pixel TFT 203 in the pixel portion has a channel forming region, a source or drain region 125a, and impurity regions 125b and 125c in the island-shaped semiconductor layer 104. In addition, a gate electrode (H) 129 having a third shape, which is formed by stacking a conductive film (A) 129a and a conductive film (B) 129b, is provided.

Further, a storage capacitor 204 is formed from the capacitor wiring 122, an insulating film made of the same material as the gate insulating film, and the semiconductor layer 105 to which the p-type impurity element is added. In FIG. 5, the pixel TFT 203 has a double gate structure, but may have a single gate structure or a multi-gate structure provided with a plurality of gate electrodes.

As described above, the present invention makes it possible to optimize the structure of the TFT constituting each circuit according to the specifications required by the pixel portion and the driving circuit, and to improve the operation performance and reliability of the semiconductor device. can do. Further, by forming the gate electrode with a heat-resistant conductive material, the LD
By activating the D region, the source region, and the drain region easily and forming the wiring with a low-resistance material, the wiring resistance can be sufficiently reduced. Therefore, the present invention can be applied to a display device having a pixel portion (screen size) of 4 inch class or more.

(Embodiment 2) In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described below. FIG. 6 is used for the description.

First, according to the first embodiment, after obtaining the active matrix substrate in the state of FIG. 5B, an alignment film 180 is formed on the active matrix substrate of FIG. In this embodiment, before the alignment film 180 is formed, an organic resin film such as an acrylic resin film is patterned to form columnar spacers 181 at predetermined positions for maintaining a substrate interval. Instead of the columnar spacers, spherical spacers may be spread over the entire surface of the substrate.

Next, a counter substrate 182 is prepared. The counter substrate has coloring layers 183 and 184 and a planarizing film 185.
To form Red coloring layer 183 and blue coloring layer 184
Are partially overlapped to form a second light-shielding portion. Although not shown in FIG. 6, a first light-shielding portion is formed by partially overlapping a red coloring layer and a green coloring layer.

Next, a counter electrode 186 was formed in the pixel portion, an alignment film 187 was formed on the entire surface of the counter substrate, and a rubbing process was performed.

Then, the active matrix substrate on which the pixel portion and the driving circuit are formed and the opposing substrate are sealed with a sealing material 188.
Paste in. A filler is mixed in the sealing material 188, and the two substrates are bonded to each other at a uniform interval by the filler and the columnar spacer. afterwards,
A liquid crystal material 189 is injected between the two substrates, and completely sealed with a sealant (not shown). A known liquid crystal material may be used for the liquid crystal material 189. Thus, the active matrix type liquid crystal display device shown in FIG. 6 is completed. Then, if necessary, the active matrix substrate or the opposing substrate is cut into a predetermined shape. Further, a polarizing plate and the like were appropriately provided using a known technique. Then, an FPC was attached using a known technique.

The structure of the liquid crystal display panel thus obtained will be described with reference to the top view of FIG. Note that the same reference numerals are used for portions corresponding to FIG.

The top view shown in FIG.
6. Active matrix including drive circuits 205a and 205b, external input terminal 210 to which an FPC (Flexible Printed Circuit) is attached, connection wiring 211 connecting the external input terminal to the input section of each circuit, and the like. A substrate and an opposite substrate 182 provided with a color filter and the like are attached to each other with a sealant 188 interposed therebetween.

FIG. 7B is a sectional view taken along line ee ′ of the external input terminal 210 shown in FIG. 7A. An FPC including a base film 213 and a wiring 214 is bonded to the external input terminal with an anisotropic conductive resin 215, and a mechanical strength is enhanced by a reinforcing plate. 217
Is a wiring made of a conductive film formed for forming the pixel electrode 140. The outer diameter of the conductive particles 216 is
Since the pitch is smaller than the pitch of 7, when the amount dispersed in the adhesive 215 is made appropriate, it is possible to form an electrical connection with the corresponding wiring on the FPC side without short-circuiting with the adjacent wiring.

The liquid crystal display panel manufactured as described above can be used as a display section of various electric appliances.

(Embodiment 3) In this embodiment, a method for manufacturing a semiconductor device different from that in Embodiment 1 will be described.

After the gate electrode (E) 133 is formed in the third etching step according to the steps shown in Embodiment 1, the gate electrode (B) 119, the gate electrode (E) 133, and the gate electrode (E) 133 formed in the above step are formed. (H) Gate electrodes 119, 129, and 13 using 129 and capacitor wiring 122 as a mask
3 and the gate insulating film 117 in a region not overlapping with the capacitor wiring 122 are removed by etching.

If the gate insulating film is removed by etching, it is highly possible that the thickness of the gate insulating film is likely to vary depending on the position in the gate electrode etching process several times during the impurity doping process. It is not necessary to consider a complicated film thickness.

This embodiment can be applied in combination with the first and second embodiments.

(Embodiment 4) FIG. 8 shows a block diagram of a semiconductor device manufactured by using the present invention. FIG.
1 shows a circuit configuration for performing analog driving. This embodiment shows a semiconductor device having a source side driving circuit 90, a pixel portion 91, and a gate side driving circuit 92. Note that in this specification, a driver circuit is a general term including a source driver circuit and a gate driver circuit.

The source side driving circuit 90 includes a shift register 90a, a buffer 90b, and a sampling circuit (transfer gate) 90c. The gate-side drive circuit 92 includes a shift register 92a, a level shifter 92
b, a buffer 92c is provided. If necessary, a level shifter circuit may be provided between the sampling circuit and the shift register.

In this embodiment, the pixel section 91 is composed of a plurality of pixels, each of which includes a TFT element.

Although not shown, a gate-side drive circuit may be further provided on the opposite side of the gate-side drive circuit 92 across the pixel portion 91.

When digital driving is performed, a latch (A) is used instead of the sampling circuit as shown in FIG.
93b and a latch (B) 93c may be provided. The source side drive circuit 93 includes a shift register 93a, a latch (A)
93b, latch (B) 93c, D / A converter 93
d and a buffer 93e. The gate-side drive circuit 95 includes a shift register 95a, a level shifter 95
b, a buffer 95c is provided. If necessary, a level shifter circuit may be provided between the latch (B) 93c and the D / A converter 93d.

The above configuration can be realized according to the manufacturing process shown in the first embodiment. In this embodiment, only the structure of the pixel portion and the driving circuit is shown. However, according to the manufacturing process of the present invention, a memory or a microprocessor can be formed.

[Embodiment 5] A CMOS circuit and a pixel portion formed by carrying out the present invention can be used for various semiconductor devices (active matrix type liquid crystal displays). That is, the present invention can be applied to all electric appliances in which these semiconductor devices are incorporated in a display portion.

Examples of such electric appliances include a video camera, a digital camera, a projector (rear type or front type), a head mounted display (goggle type display), a personal computer, a portable information terminal (mobile computer, a mobile phone or an electronic book). Etc.). Examples of these are shown in FIGS.
And FIG.

FIG. 10A shows a personal computer, which includes a main body 2001, an image input section 2002, and a display section 20.
03, a keyboard 2004 and the like. The present invention can be applied to the image input unit 2002, the display unit 2003, and other signal control circuits.

FIG. 10B shows a video camera, which includes a main body 2101, a display section 2102, an audio input section 2103, operation switches 2104, a battery 2105, and an image receiving section 210.
6 and so on. The present invention can be applied to the display portion 2102 and other signal control circuits.

FIG. 10C shows a mobile computer (mobile computer) including a main body 2201, a camera section 2202, an image receiving section 2203, operation switches 2204, a display section 2205, and the like. The present invention can be applied to the display portion 2205 and other signal control circuits.

FIG. 10D shows a goggle type display, which includes a main body 2301, a display section 2302, and an arm section 230.
3 and so on. The present invention can be applied to the display portion 2302 and other signal control circuits.

FIG. 10E shows a player using a recording medium (hereinafter, referred to as a recording medium) on which a program is recorded, and includes a main body 2401, a display section 2402, and a speaker section 240.
3, a recording medium 2404, an operation switch 2405, and the like. This player uses a DVD (D
digital Versatile Disc), CD
And the like, it is possible to perform music appreciation, movie appreciation, games, and the Internet. The present invention can be applied to the display portion 2402 and other signal control circuits.

FIG. 10F shows a digital camera, which includes a main body 2501, a display section 2502, an eyepiece section 2503, operation switches 2504, an image receiving section (not shown), and the like. The present invention can be applied to the display portion 2502 and other signal control circuits.

FIG. 11A shows a front type projector, which includes a projection device 2601, a screen 2602, and the like. The present invention can be applied to the liquid crystal display device 2808 forming a part of the projection device 2601 and other signal control circuits.

FIG. 11B shows a rear type projector, which includes a main body 2701, a projection device 2702, and a mirror 270.
3, including a screen 2704 and the like. The present invention relates to a projection device 2
The present invention can be applied to the liquid crystal display device 2808 forming a part of the signal control circuit 702 and other signal control circuits.

FIG. 11C is a diagram showing an example of the structure of the projection devices 2601 and 2702 in FIGS. 11A and 11B. Projection devices 2601, 27
02 denotes a light source optical system 2801, mirrors 2802 and 280
4 to 2806, dichroic mirror 2803, prism 2807, liquid crystal display device 2808, retardation plate 280
9, the projection optical system 2810. Projection optical system 28
Reference numeral 10 denotes an optical system including a projection lens. In this embodiment, an example of a three-plate type is shown, but there is no particular limitation, and for example, a single-plate type may be used. Further, the practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the optical path indicated by the arrow in FIG. Good.

FIG. 11D is a diagram showing an example of the structure of the light source optical system 2801 in FIG. 11C. In this embodiment, the light source optical system 2801 includes a reflector 2811, a light source 2812, a lens array 2813,
814, a polarization conversion element 2815, and a condenser lens 2816. Note that the light source optical system shown in FIG. 11D is an example and is not particularly limited. For example, a practitioner may appropriately provide an optical system such as an optical lens, a film having a polarizing function, a film for adjusting a phase difference, and an IR film in the light source optical system.

However, in the projector shown in FIG. 11, a case where a transmission type semiconductor device is used is shown, and an example of application to a reflection type semiconductor device is not shown.

FIG. 12A shows a mobile phone,
, A display panel; and 3002, an operation panel. The display panel 3001 and the operation panel 3002 are connected to
003. The angle θ between the surface of the connection panel 3003 where the display portion 3004 of the display panel 3001 is provided and the surface of the operation panel 3002 where the operation keys 3006 are provided can be arbitrarily changed. Further, a voice output unit 3005, an operation key 300
6, a power switch 3007, and a voice input unit 3008. The present invention can be applied to the display portion 3004.

FIG. 12B shows a portable book (electronic book), which includes a main body 3101, display portions 3102 and 3103, a storage medium 3104, operation switches 3105, and an antenna 3106.
And so on. The present invention can be applied to the display units 3102 and 3103 and other signal circuits.

FIG. 12C shows a display, which includes a main body 3201, a support 3202, a display portion 3203, and the like.
The invention can be applied to the display portion 3203. The display of the present invention is particularly advantageous when the screen is enlarged, and is advantageous for a display having a diagonal of 10 inches or more (particularly 30 inches or more).

As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electric appliances in various fields. Further, the electric appliance of the present embodiment can be realized by using a configuration composed of any combination of the embodiments 1 to 4.

[0101]

According to the present invention, the gettering of the semiconductor layer of the p-channel TFT can be sufficiently performed without increasing the number of masks and the number of steps, and the resistance of the source region and the drain region can be reduced. In addition, since gettering can be sufficiently performed, an adverse effect due to a catalyst element can be reduced, and a highly reliable p-channel TFT can be relatively easily manufactured with high yield.

[Brief description of the drawings]

FIG. 1 is a diagram showing an embodiment of the present invention.

FIG. 2 is a diagram showing an embodiment of the present invention.

FIG. 3 is a diagram showing an example of an embodiment of the present invention.

FIG. 4 is a diagram showing an example of an embodiment of the present invention.

FIG. 5 is a diagram showing an example of an embodiment of the present invention.

FIG. 6 is a diagram showing an example of an embodiment of the present invention.

FIG. 7 is a diagram showing an example of an embodiment of the present invention.

FIG. 8 is a diagram showing an example of an embodiment of the present invention.

FIG. 9 is a diagram showing an example of an embodiment of the present invention.

FIG. 10 illustrates an example of an electric appliance using a semiconductor device manufactured according to the present invention for a display portion.

FIG. 11 illustrates an example of an electric appliance using a semiconductor device manufactured according to the present invention for a display portion.

FIG. 12 illustrates an example of an electric appliance using a semiconductor device manufactured according to the present invention for a display portion.

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 21/265 604 H01L 29/78 613A 21/322 627Z 21/336 21/265 P 29/43 F 29 / 62G 29/78 617L 627G 617K 612B (72) Naoki Makita 22-22 Nagaike-cho, Abeno-ku, Osaka-shi, Osaka Inside Sharp Corporation F-term within Sharp Corporation (reference) 2H092 JA25 JA28 JA40 JA41 JB44 KA05 KA11 KB25 MA17 MA30 NA13 4M104 AA09 BB25 BB26 BB28 BB30 BB31 BB32 BB33 CC05 FF08 FF13 GG09 5C094 AA42 AA43 BA03 BA43 EA02 GB03 DB07 EA16 FA06 JA01 5F110 AA01 AA06 BB02 BB04 BB05 CC02 DD02 DD03 DD13 DD14 DD15 DD17 DD25 EE01 EE04 EE05 EE06 EE08 EE11 EE14 EE15 EE23 EE28 EE44 FF04 FF09 FF12 FF28 FF30 GG02 GG13 GG24 GG25 GG32 GG34 GG43 GG45 GG51 HJ01 HJ04 HJ12 HJ23 HL02 HL03 HL04 QHL NN06 NN11 NN04 NN06 NN04 NN04 NN04

Claims (18)

[Claims] 1. An electro-optical device having a semiconductor layer on an insulator, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, wherein the semiconductor device comprises an n-channel TFT and a p-channel Wherein the semiconductor layer of the p-channel TFT has a channel formation region, a region containing an n-type impurity element and a p-type impurity element, and a region containing only a p-type impurity element. 2. The electro-optical device according to claim 1, wherein a wiring for electrically connecting each TFT is connected to a region containing only the p-type impurity element. 2. An electro-optical device having a semiconductor layer on an insulator, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film, wherein the semiconductor device comprises an n-channel TFT and a p-channel Wherein the semiconductor layer of the p-channel TFT has a channel formation region, a region containing an n-type impurity element and a p-type impurity element, and a region containing only a p-type impurity element. The region including only the n-type impurity element and the p-type impurity element is sandwiched between the region including the n-type impurity element and the region including the n-type impurity element and the p-type TFT. An electro-optical device, wherein a wiring connected to the semiconductor device is connected to a region containing only the p-type impurity element. 3. The gate electrode according to claim 1, wherein the gate electrode is made of an element selected from Ta, W, Ti, Mo, Al, and Cu, or an alloy material or a compound material containing the element as a main component. An electro-optical device, wherein the electro-optical device is provided in layers or stacked layers. 4. A first method for forming an amorphous semiconductor layer on an insulator.
A second step of adding a catalytic element that promotes crystallization to the amorphous semiconductor layer; and a second step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer. Step 3, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, providing a conductive film on the gate insulating film, etching the conductive film to form a gate electrode of an n-channel TFT, a fifth step of forming a conductive layer to be a gate electrode later on the p-channel TFT; a sixth step of adding an n-type impurity element to the semiconductor layer using the gate electrode and the conductive layer as a mask; The region to be an n-channel TFT is covered with a resist mask, and the conductive layer is etched to form a p-channel TFT.
After forming the FT gate electrode, the p-channel type TF
And a seventh step of adding a p-type impurity element to the T semiconductor layer. 5. A first method for forming an amorphous semiconductor layer on an insulator.
A second step of adding a catalytic element that promotes crystallization to the amorphous semiconductor layer; A third step of obtaining a semiconductor layer; a fourth step of forming a gate insulating film on the crystalline semiconductor layer; and providing a conductive film on the gate insulating film and etching the conductive film to form an n-channel type. A fifth step of forming a conductive layer serving as a gate electrode of the TFT and a later gate electrode on the p-channel TFT; and a step of adding an n-type impurity element to the semiconductor layer using the gate electrode and the conductive layer as a mask. Step 6, covering the region to be an n-channel TFT with a mask made of resist, etching the conductive layer to form a p-channel TFT
After forming the FT gate electrode, the p-channel type TF
And a seventh step of adding a p-type impurity element to the T semiconductor layer. 6. A first method for forming an amorphous semiconductor layer on an insulator.
A second step of adding a catalytic element that promotes crystallization to the amorphous semiconductor layer; and a second step of heating the amorphous semiconductor layer to which the catalytic element is added to obtain a crystalline semiconductor layer. Step 3, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive film (A) and a conductive film (B) on the gate insulating film.
A sixth step of etching the conductive film (A) and the conductive film (B) to form a gate electrode of a first shape; and a gate of the first shape. A seventh step of adding an n-type impurity element to the semiconductor layer using the electrode as a mask; and etching the gate electrode of the first shape to form a second narrower gate electrode than the gate electrode of the first shape. An eighth step of forming a gate electrode of the second shape, a ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the second shape as a mask, and a gate of the second shape A tenth step of etching the electrode to form a third shape gate electrode, an eleventh step of etching the third shape gate electrode to form a fourth shape gate electrode, Using the gate electrode of the fourth shape as a mask, A twelfth step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT. 7. A first method for forming an amorphous semiconductor layer on an insulator.
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer; A third step of obtaining a crystalline semiconductor layer, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive film (A) and a conductive film (B) on the gate insulating film
A sixth step of etching the conductive film (A) and the conductive film (B) to form a gate electrode of a first shape; and a gate of the first shape. A seventh step of adding an n-type impurity element to the semiconductor layer using the electrode as a mask; and etching the gate electrode of the first shape to form a second narrower gate electrode than the gate electrode of the first shape. An eighth step of forming a gate electrode of the second shape, a ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode of the second shape as a mask, and a gate of the second shape A tenth step of etching the electrode to form a third shape gate electrode, an eleventh step of etching the third shape gate electrode to form a fourth shape gate electrode, Using the gate electrode of the fourth shape as a mask, A twelfth step of adding a p-type impurity element to the semiconductor layer of the p-channel TFT. 8. A first method for forming an amorphous semiconductor layer on an insulator.
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer; and a second step of heating the amorphous semiconductor layer to which the catalyst element is added to obtain a crystalline semiconductor layer. Step 3, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive film (A) and a conductive film (B) on the gate insulating film.
A sixth step of etching the conductive film (A) and the conductive film (B) to form a gate electrode (A) and a gate electrode (C); and A seventh step of adding an n-type impurity element to the semiconductor layer using the gate electrode (A) and the gate electrode (C) formed in the step as masks, and a gate electrode formed in the sixth step An etching process to form a gate electrode (B) and a gate electrode (D); and using the gate electrode (B) and the gate electrode (D) formed in the eighth process as a mask, A ninth step of adding an n-type impurity element to the semiconductor layer; and covering the n-channel TFT with a resist mask.
a tenth step of forming a gate electrode (E) by etching the gate electrode (D) of the p-channel TFT; and forming a p-type TFT on the semiconductor layer of the p-channel TFT using the gate electrode (E) as a mask. Eleventh Addition of Impurity Element
And a method for manufacturing an electro-optical device. 9. A first method for forming an amorphous semiconductor layer on an insulator.
A second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer; and heating the amorphous semiconductor layer to which the catalyst element is added and then irradiating the amorphous semiconductor layer with a laser to form the crystalline semiconductor. A third step of obtaining a layer, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive film (A) and a conductive film (B) on the gate insulating film
A sixth step of etching the conductive film (A) and the conductive film (B) to form a gate electrode (A) and a gate electrode (C); and A seventh step of adding an n-type impurity element to the semiconductor layer using the gate electrode (A) and the gate electrode (C) formed in the step as masks, and a gate electrode formed in the sixth step An etching process to form a gate electrode (B) and a gate electrode (D); and using the gate electrode (B) and the gate electrode (D) formed in the eighth process as a mask, A ninth step of adding an n-type impurity element to the semiconductor layer; and covering the n-channel TFT with a resist mask.
a tenth step of forming a gate electrode (E) by etching the gate electrode (D) of the p-channel TFT; and forming a p-type TFT on the semiconductor layer of the p-channel TFT using the gate electrode (E) as a mask. Eleventh Addition of Impurity Element
And a method for manufacturing an electro-optical device. 10. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer to obtain a crystalline semiconductor layer, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive step on the gate insulating film. Film (A) and conductive film (B)
A fifth step of forming a gate electrode (A), a gate electrode (C), and a gate electrode (F) by etching the conductive film (A) and the conductive film (B). A step of using the gate electrode formed in the sixth step as a mask, a seventh step of adding an n-type impurity element to the semiconductor layer, and etching the gate electrode formed in the sixth step. An eighth step of forming a gate electrode (B), a gate electrode (D), and a gate electrode (G); and using the gate electrode formed in the eighth step as a mask to add n-type impurities to the semiconductor layer. A ninth step of adding an element, and covering the n-channel TFT formed in the drive circuit with a resist mask, etching the gate electrode (D) of the p-channel TFT and the gate electrode (G) of the pixel TFT. Gate A tenth step of forming a pole (D ′) and a gate electrode (H); an eleventh step of etching the gate electrode (D ′) to form a gate electrode (E); ) Is used as a mask to add a p-type impurity element to the semiconductor layer of the p-channel TFT.
And a method for manufacturing an electro-optical device. 11. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer to obtain a crystalline semiconductor layer, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive step on the gate insulating film. Film (A) and conductive film (B)
A fifth step of forming a gate electrode (A), a gate electrode (C), and a gate electrode (F) by etching the conductive film (A) and the conductive film (B). A step of using the gate electrode formed in the sixth step as a mask, a seventh step of adding an n-type impurity element to the semiconductor layer, and etching the gate electrode formed in the sixth step. An eighth step of forming a gate electrode (B), a gate electrode (D), and a gate electrode (G); and using the gate electrode formed in the eighth step as a mask to add n-type impurities to the semiconductor layer. A ninth step of adding an element, and covering the n-channel TFT formed in the drive circuit with a resist mask, etching the gate electrode (D) of the p-channel TFT and the gate electrode (G) of the pixel TFT. Gate A tenth step of forming a pole (D ′) and a gate electrode (H); an eleventh step of etching the gate electrode (D ′) to form a gate electrode (E); ) Is used as a mask to add a p-type impurity element to the semiconductor layer of the p-channel TFT.
A thirteenth step of performing a heat treatment; a fourteenth step of covering the entire surface with an inorganic interlayer insulating film; and a first step of forming an organic interlayer insulating film on the inorganic interlayer insulating film.
A step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film; and a seventeenth step of forming a pixel electrode on the organic interlayer insulating film. And an eighteenth step of forming a connection wiring. 12. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer to obtain a crystalline semiconductor layer, a fourth step of forming a gate insulating film on the crystalline semiconductor layer, and a conductive step on the gate insulating film. Film (A) and conductive film (B)
A fifth step of forming a gate electrode (A), a gate electrode (C), and a gate electrode (F) by etching the conductive film (A) and the conductive film (B). A step of using the gate electrode formed in the sixth step as a mask, a seventh step of adding an n-type impurity element to the semiconductor layer, and etching the gate electrode formed in the sixth step. An eighth step of forming a gate electrode (B), a gate electrode (D), and a gate electrode (G); and using the gate electrode formed in the eighth step as a mask to add n-type impurities to the semiconductor layer. A ninth step of adding an element, and covering the n-channel TFT formed in the drive circuit with a resist mask, etching the gate electrode (D) of the p-channel TFT and the gate electrode (G) of the pixel TFT. Gate A tenth step of forming a pole (D ′) and a gate electrode (H); an eleventh step of etching the gate electrode (D ′) to form a gate electrode (E); ) Is used as a mask to add a p-type impurity element to the semiconductor layer of the p-channel TFT.
A thirteenth step of covering the entire surface with an inorganic interlayer insulating film; a fourteenth step of heat treatment to getter the catalyst element; and a thirteenth step of forming an organic interlayer insulating film on the inorganic interlayer insulating film. 1
A step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film; and a seventeenth step of forming a pixel electrode on the organic interlayer insulating film. And an eighteenth step of forming a connection wiring. 13. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalytic element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer and then irradiating a laser to obtain a crystalline semiconductor layer; a fourth step of forming a gate insulating film on the crystalline semiconductor layer; Conductive film (A) and conductive film (B) on insulating film
A fifth step of forming a gate electrode (A), a gate electrode (C), and a gate electrode (F) by etching the conductive film (A) and the conductive film (B). A step of using the gate electrode formed in the sixth step as a mask, a seventh step of adding an n-type impurity element to the semiconductor layer, and etching the gate electrode formed in the sixth step. An eighth step of forming a gate electrode (B), a gate electrode (D), and a gate electrode (G); and using the gate electrode formed in the eighth step as a mask to add n-type impurities to the semiconductor layer. A ninth step of adding an element, and covering the n-channel TFT formed in the drive circuit with a resist mask, etching the gate electrode (D) of the p-channel TFT and the gate electrode (G) of the pixel TFT. Gate A tenth step of forming a pole (D ′) and a gate electrode (H); an eleventh step of etching the gate electrode (D ′) to form a gate electrode (E); ) Is used as a mask to add a p-type impurity element to the semiconductor layer of the p-channel TFT.
A thirteenth step of performing a heat treatment; a fourteenth step of covering the entire surface with an inorganic interlayer insulating film; and a first step of forming an organic interlayer insulating film on the inorganic interlayer insulating film.
A step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film; and a seventeenth step of forming a pixel electrode on the organic interlayer insulating film. And an eighteenth step of forming a connection wiring. 14. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer and then irradiating a laser to obtain a crystalline semiconductor layer; a fourth step of forming a gate insulating film on the crystalline semiconductor layer; Conductive film (A) and conductive film (B) on insulating film
A fifth step of forming a gate electrode (A), a gate electrode (C), and a gate electrode (F) by etching the conductive film (A) and the conductive film (B). A step of using the gate electrode formed in the sixth step as a mask, a seventh step of adding an n-type impurity element to the semiconductor layer, and etching the gate electrode formed in the sixth step. An eighth step of forming a gate electrode (B), a gate electrode (D), and a gate electrode (G); and using the gate electrode formed in the eighth step as a mask to add n-type impurities to the semiconductor layer. A ninth step of adding an element, and covering the n-channel TFT formed in the drive circuit with a resist mask, etching the gate electrode (D) of the p-channel TFT and the gate electrode (G) of the pixel TFT. Gate A tenth step of forming a pole (D ′) and a gate electrode (H); an eleventh step of etching the gate electrode (D ′) to form a gate electrode (E); ) Is used as a mask to add a p-type impurity element to the semiconductor layer of the p-channel TFT.
A thirteenth step of covering the entire surface with an inorganic interlayer insulating film; a fourteenth step of performing heat treatment to getter the catalyst element; and a thirteenth step of forming an organic interlayer insulating film on the inorganic interlayer insulating film. 1
A step of forming a contact hole reaching the semiconductor layer in the inorganic interlayer insulating film and the organic interlayer insulating film; and a seventeenth step of forming a pixel electrode on the organic interlayer insulating film. And an eighteenth step of forming a connection wiring. 15. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer to obtain a crystalline semiconductor layer; and a fourth step of forming a gate insulating film over the crystalline semiconductor layer. A fifth step of forming a conductive film (A) and a conductive film (B) on the gate insulating film; etching the conductive film (A) and the conductive film (B) to form a gate electrode (A); A sixth step of forming a gate electrode (C) and a gate electrode (F); and a seventh step of adding an n-type impurity element to the semiconductor layer using the gate electrode formed in the sixth step as a mask. An eighth step of etching the gate electrode formed in the sixth step to form a gate electrode (B), a gate electrode (D), and a gate electrode (G); and an eighth step. A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode formed by the mask as a mask, and covering the n-channel TFT formed in the drive circuit with a resist mask, The gate electrode (D) and A tenth step of forming a gate electrode (D ') and a gate electrode (H) by etching the gate electrode (G) of the element TFT; and etching the gate electrode (E) by etching the gate electrode (D'). An eleventh step of forming; a twelfth step of removing the gate insulating film using the gate electrode (B), the gate electrode (E), and the gate electrode (H) as a mask; and the n-channel TFT And a thirteenth step of covering the pixel TFT with a mask made of a resist and adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode (E) as a mask. Method for manufacturing an electro-optical device. 16. A first step of forming an amorphous semiconductor layer on an insulator, a second step of adding a catalyst element for promoting crystallization to the amorphous semiconductor layer, A third step of heating the added amorphous semiconductor layer and then irradiating a laser to obtain a crystalline semiconductor layer; and a fourth step of forming a gate insulating film over the crystalline semiconductor layer. A fifth step of forming a conductive film (A) and a conductive film (B) on the gate insulating film; etching the conductive film (A) and the conductive film (B) to form a gate electrode (A); A sixth step of forming a gate electrode (C) and a gate electrode (F); and a seventh step of adding an n-type impurity element to the semiconductor layer using the gate electrode formed in the sixth step as a mask. An eighth step of etching the gate electrode formed in the sixth step to form a gate electrode (B), a gate electrode (D), and a gate electrode (G); and an eighth step. A ninth step of adding an n-type impurity element to the semiconductor layer using the gate electrode formed by the mask as a mask, and covering the n-channel TFT formed in the drive circuit with a mask made of a resist to form a p-channel TFT. The gate electrode (D) and A tenth step of forming a gate electrode (D ') and a gate electrode (H) by etching the gate electrode (G) of the element TFT; and etching the gate electrode (E) by etching the gate electrode (D'). An eleventh step of forming; a twelfth step of removing the gate insulating film using the gate electrode (B), the gate electrode (E), and the gate electrode (H) as a mask; and the n-channel TFT And a thirteenth step of covering the pixel TFT with a mask made of a resist and adding a p-type impurity element to the semiconductor layer of the p-channel TFT using the gate electrode (E) as a mask. Method for manufacturing an electro-optical device. 17. The conductive film (A) according to claim 8, wherein the gate electrode (B), the gate electrode (E), and the gate electrode (H) are the conductive film (A) and the conductive film (A). A method for manufacturing an electro-optical device, comprising a film (B), wherein the width of the conductive film (A) is formed to be larger than the width of the conductive film (B). 18. A laser for irradiating the semiconductor layer to which the catalytic element is added according to claim 5, claim 7, claim 9, claim 13, claim 14 or claim 16, wherein the laser for irradiating the semiconductor layer to which the catalytic element is added is a pulse transmitting KrF A method for manufacturing an electro-optical device, which is an excimer laser, a XeCl excimer laser, a YAG laser or a YVO ₄ laser.