JP2003303833A - Manufacturing method of semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain a crystalline TFT attaining excellent characteristics at both of an on-region and an off-region at the same time by attaining reliability equal to or more than that of an MOS transistor. <P>SOLUTION: A manufacturing method of a semiconductor device is formed of: a first layer of a gate electrode formed by bringing the gate electrode into contact with a gate insulating film; a second layer of the gate electrode formed inside the first layer of the gate electrode in the first layer of the gate electrode; and a third layer formed by bringing the first layer of the gate electrode into contact with the second layer of the gate electrode. A semiconductor layer has a channel formation region, a first conductive impurity region, and a second conductive impurity region formed between the channel formation region and the first impurity region. Part of the second conductive impurity region is superposed on the first layer of the gate electrode. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a circuit formed of a thin film transistor (hereinafter referred to as TFT) on a substrate having an insulating surface and a method for manufacturing the semiconductor device. For example, the present invention relates to a configuration of an electro-optical device represented by a liquid crystal display device and an electronic device including the electro-optical device. Note that in this specification, a semiconductor device refers to all devices that function by utilizing semiconductor characteristics, and includes in its category the electro-optical device and electronic equipment equipped with the electro-optical device.

[0002]

2. Description of the Related Art Technological development for manufacturing an active matrix type liquid crystal display device by providing TFTs on a glass substrate or a quartz substrate has been actively promoted. Above all, a TFT having a semiconductor film having a crystalline structure as an active layer (hereinafter, referred to as crystalline T
Since FT) has high mobility, it is said that high-definition image display can be realized by integrating functional circuits on the same substrate.

Here, in the present specification, the semiconductor film having a crystal structure means a single crystal semiconductor, a polycrystalline semiconductor,
Including a microcrystalline semiconductor, and further including JP-A-7-130652
JP-A-8-78329, JP-A-10-1
35468, JP-A-10-135469,
Alternatively, it includes the semiconductor disclosed in Japanese Patent Laid-Open No. 10-247735.

To construct an active matrix type liquid crystal display device, an n channel type T of a pixel matrix circuit is used.
FT (hereinafter referred to as pixel TFT) alone is 100 to 20
It is necessary to have 0,000, and if a functional circuit provided in the periphery is further added, more crystalline TFTs are required. The specifications required for liquid crystal display devices are strict, and in order to perform stable image display, it is firstly necessary to ensure the reliability of each crystalline TFT.

Characteristics of a field effect transistor such as a TFT are as follows: a linear region in which the drain current and the drain voltage increase in proportion to each other, a saturation region in which the drain current saturates even if the drain voltage increases, and a drain voltage applied. Ideally, it can be considered separately as a cutoff region in which no current flows. In this specification, the linear region and the saturation region are referred to as a TFT on region, and the cutoff region is referred to as an off region. Further, for convenience, the drain current in the ON region is called an ON current, and the current in the OFF region is called an OFF current.

The pixel TFT has an amplitude of 15 to 2 as a driving condition.
A gate voltage of about 0V is applied. Therefore, it is necessary to satisfy the characteristics of both the ON region and the OFF region. on the other hand,
A peripheral circuit for driving the pixel matrix circuit is a CMO.
It is configured based on the S circuit, and the characteristics of the ON region are mainly emphasized.

However, the crystalline TFT is still inferior in terms of reliability to MOS transistors (transistors manufactured on a single crystal semiconductor substrate) used in LSIs and the like. For example, when a crystalline TFT is continuously driven, a deterioration phenomenon such as a decrease in field effect mobility, an ON current, or an increase in an OFF current may be observed. This is caused by the hot carrier injection phenomenon, and the hot carriers generated by the high electric field near the drain cause the deterioration phenomenon.

In the technical field of LSI, as a method of reducing the off-current of a MOS transistor and mitigating a high electric field near the drain, a low concentration drain (LDD: Lightly Do) is used.
pedDrain) structure is known. In this structure, a low-concentration impurity region is provided outside the channel formation region, and this low-concentration impurity region is called an LDD region.

It is naturally known that an LDD structure is formed even in a crystalline TFT. For example, JP-A-7-20221
According to Japanese Patent Laid-Open No. 0-202, a gate electrode has a two-layer structure having different widths, an upper layer width is formed smaller than a lower layer width, and ion implantation is performed using the gate electrode as a mask.
The LDD region is formed by one-time ion implantation by utilizing the difference in ion penetration depth due to the different thickness of the gate electrode. Then, the structure is such that the gate electrode overlaps directly on the LDD region.

Such a structure has GOLD (Gate-drain
Overlapped LDD) structure, LATID (Large-tilt-angl)
e implanted drain) structure or ITLDD (Inver
seT LDD) structure, etc. Then, the high electric field in the vicinity of the drain can be relaxed, the hot carrier injection phenomenon can be prevented, and the reliability can be improved. For example, "Muts
uko Hatano, Hajime Akimoto and Takeshi Sakai, IEDM97
TECHNICAL DIGEST, p523-526, 1997 ”describes a GOLD structure with sidewalls made of silicon.
It has been confirmed that extremely excellent reliability can be obtained as compared with TFTs having other structures.

However, the structure disclosed in the same paper has a problem that the off current becomes larger than that of the normal LDD structure, and a countermeasure for that is required.
In particular, in the pixel TFT that constitutes the pixel matrix circuit,
If the off-current increases, the power consumption increases and abnormalities appear in the image display.
Cannot be applied as is.

[0012]

The present invention is a technique for solving such a problem, and achieves the reliability equal to or higher than that of a MOS transistor, and at the same time, is excellent in both the ON region and the OFF region. Crystalline TF with excellent characteristics
The purpose is to realize T. Then, an object is to realize a highly reliable semiconductor device having a semiconductor circuit in which a circuit is formed by such a crystalline TFT.

[0013]

FIG. 18 shows the structure of TFT and Vg-obtained at that time, based on the knowledge obtained so far.
3 schematically shows Id (gate voltage-drain current) characteristics. FIG. 18A-1 illustrates a simplest TFT structure in which a semiconductor layer includes a channel formation region, a source region, and a drain region. FIG. 3B-1 shows the characteristics of this TFT, in which the + Vg side is the ON region of the TFT, and −
The Vg side is an off region. The solid line shows the initial characteristic, and the broken line shows the characteristic of deterioration due to the hot carrier injection phenomenon. In this structure, both the on-current and the off-current are high and the deterioration is large, so that it cannot be used as it is, for example, in a pixel TFT of a pixel matrix circuit.

FIG. 18 (A-2) shows the LDD in (A-1).
The structure has a low-concentration impurity region to be a region,
The LDD structure does not overlap with the gate electrode.
FIG. 2B-2 shows the characteristics of this TFT, which can suppress the off current to some extent, but could not prevent the deterioration of the on current. In addition, FIG.
It has a structure in which the D region completely overlaps the gate electrode, and is also called a GOLD structure. In the figure (B-
3) is a characteristic corresponding to this, and although the deterioration can be suppressed to such an extent that there is no problem, the off current is increased on the −Vg side as compared with the structure of (A-2).

Therefore, FIGS. 18 (A-1), (A-2),
In the structure shown in (A-3), the characteristics of the ON region and the characteristics of the OFF region required for the pixel matrix circuit cannot be satisfied at the same time including the problem of reliability. But,
As shown in FIG. 18A-4, when a structure in which the LDD region overlaps with the gate electrode and the non-overlapped region is formed, deterioration of on-state current can be sufficiently suppressed, and It is possible to reduce the off current.

The structure of FIG. 18A-4 is derived from the following consideration. In the structure shown in FIG. 18A-3, when a negative voltage is applied to the gate electrode of the n-channel TFT, that is, in the LDD region formed by overlapping with the gate electrode in the off region. , Holes are induced at the interface with the gate insulating film as the negative voltage increases, and a current path is formed by minority carriers that connect the drain region, the LDD region, and the channel region. At this time, when a positive voltage is applied to the drain region, holes flow toward the source region, which is considered to be the cause of the increase in off current.

In order to cut off such a current path on the way, it can be considered to provide an LDD region in which minority carriers are not accumulated even if a gate voltage is applied.
The present invention relates to a TFT having such a structure and this TFT
It relates to a circuit using.

Therefore, the structure of the present invention has the TF having the semiconductor layer, the gate insulating film formed on the semiconductor layer, and the gate electrode formed on the gate insulating film on the substrate.
In the semiconductor device in which T is formed, the gate electrode is formed on a first layer of the gate electrode formed in contact with the gate insulating film, and on the first layer of the gate electrode. A second layer of the gate electrode formed inside the first layer, and a third layer of the gate electrode formed in contact with the first layer of the gate electrode and the second layer of the gate electrode. And the semiconductor layer has a channel formation region, a first conductivity type first impurity region, and a second conductivity type second region formed between the channel formation region and the first impurity region. And a part of the second impurity region of one conductivity type is overlapped with the first layer of the gate electrode.

According to another aspect of the invention, a first step of forming a semiconductor layer on a substrate having an insulating surface, and a second step of forming a gate insulating film in contact with the semiconductor layer, A third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film, and the conductive layer (B)
Is etched into a predetermined pattern to form a second gate electrode.
A fourth step of forming a layer, a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, a second layer of the conductive layer (A) and the gate electrode A sixth step of forming a conductive layer (C) in contact with the conductive layer (C), and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a third layer of the gate electrode and the gate. The method is characterized by including a seventh step of forming a first layer of an electrode and an eighth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer.

According to another aspect of the invention, a first step of forming a semiconductor layer on a substrate having an insulating surface, and a second step of forming a gate insulating film in contact with the semiconductor layer, A third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film, and the conductive layer (B)
Is etched into a predetermined pattern to form a second gate electrode.
A fourth step of forming a layer, a fifth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer, a second layer of the conductive layer (A) and the gate electrode A sixth step of forming a conductive layer (C) in contact with the conductive layer (C), and etching the conductive layer (C) and the conductive layer (A) into a predetermined pattern to form a third layer of the gate electrode and the gate. A seventh step of forming a first layer of the electrode; an eighth step of adding an impurity element of one conductivity type to a selected region of the semiconductor layer; a first layer of the gate electrode; Third of gate electrode
And a ninth step of removing a part of the layer.

According to another aspect of the invention, there is provided a first step of forming a first semiconductor layer and a second semiconductor layer on a substrate having an insulating surface, and the first semiconductor layer and the second semiconductor layer. A second step of forming a gate insulating film on the semiconductor layer, a third step of sequentially forming a conductive layer (A) and a conductive layer (B) on the gate insulating film, and the conductive layer (B ) Is etched into a predetermined pattern to form a second layer of the gate electrode, and a fifth step of adding an impurity element of one conductivity type to the selected region of the first semiconductor layer is performed. A step of forming a conductive layer (C) in contact with the conductive layer (A) and the second layer of the gate electrode, the conductive layer (C) and the conductive layer (A) Is etched into a predetermined pattern to form a third layer of the gate electrode and a first layer of the gate electrode, An eighth step of adding an impurity element of a conductivity type to selected regions of the first semiconductor layer and the second semiconductor layer, and an impurity of a conductivity type opposite to one conductivity type in the second semiconductor layer And a ninth step of adding the selected region to the selected region.

Such a TFT can be preferably used as an n-channel TFT of a CMOS circuit or a pixel TFT. In the structure of the TFT of the present invention, the first impurity region formed in the semiconductor layer functions as a source region or a drain region, and the second impurity region functions as an LDD region. Therefore, the concentration of the impurity element of one conductivity type is lower in the second impurity region than in the first impurity region.

Further, an impurity region of one conductivity type provided at one end of the semiconductor layer, the gate insulating film, and a wiring formed from the first layer of the gate electrode to the third layer of the gate electrode. A storage capacitor may be formed from the storage capacitor and the storage capacitor may be connected to the source or the drain of the TFT.

Further, the first layer of the gate electrode and the third layer of the gate electrode are composed of silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W),
One or more elements selected from molybdenum (Mo) or a compound containing the element as a component, and the second layer of the gate electrode is selected from aluminum (Al) and copper (Cu). It is characterized in that it is one or more kinds of elements or a compound containing the above elements as a main component.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described with reference to FIG. As the substrate 101 having an insulating surface, a glass substrate, a plastic substrate, a ceramics substrate, or the like can be used. Alternatively, a silicon substrate or a stainless substrate having an insulating film such as a silicon oxide film formed on its surface may be used. It is also possible to use a quartz substrate.

A base film 102 is formed on the surface of the substrate 101 on which the TFT is formed. Base film 102
May be formed by a plasma CVD method or a sputtering method, and may be formed by a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The base film 102 is provided to prevent diffusion of impurities from the substrate 101 to the semiconductor layer. For example, a silicon nitride film having a thickness of 25 to 100 nm
A two-layer structure may be formed in which a silicon oxide film is further formed to a thickness of 50 to 200 nm.

As a semiconductor layer formed in contact with the base film 102, an amorphous semiconductor film formed by a film formation method such as a plasma CVD method, a low pressure CVD method, or a sputtering method is formed by a laser annealing method or a thermal annealing method. Crystallized by phase growth method,
It is desirable to use a crystalline semiconductor. Alternatively, a microcrystalline semiconductor film formed by the above film formation method can be applied. Semiconductor materials applicable here include silicon, germanium, silicon germanium alloys, and silicon carbide, and compound semiconductor materials such as gallium arsenide can also be used.

Alternatively, the semiconductor layer formed on the substrate 301 is an SOI (Silicon On) formed by a single crystal silicon layer.
Insulators) Substrate may be used. Some types of SOI substrates are known depending on their structures and manufacturing methods, but typically, SIMOX (Separation by Implan) is used.
ted Oxygen), ELTRAN (Epitaxial Layer Tra)
nsfer: Canon registered trademark board, Smart-Cut (SOIT
A registered trademark of EC company, etc. can be used. Of course,
It is also possible to use other SOI substrates.

FIG. 1 shows sectional structures of an n-channel TFT and a p-channel TFT. n-channel type TF
The gate electrodes of the T and p-channel TFTs are composed of the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode. First layer of gate electrode 1
13, 116 are formed in contact with the gate insulating film 103. Then, the second layer 11 of the gate electrode formed to have a shorter length in the channel length direction than the first layer of the gate electrode 11
4, 117 are provided to overlap the first layers 113 and 116 of the gate electrode. Furthermore, the third layer of the gate electrode is 11
5 and 118 are the first layers 113 and 116 of the gate electrode.
And is formed on the second layers 114 and 117 of the gate electrode.

The first layers 113 and 116 of the gate electrode are
Silicon (Si), titanium (Ti), tantalum (T
It is formed of a material selected from a), tungsten (W), molybdenum (Mo), or a material containing any of these materials. For example, W-Mo compound and tantalum nitride (Ta
N) or tungsten nitride (WN). The thickness of the first layer of the gate electrode may be 10 to 100 nm, preferably 20 to 50 nm.

For the second layers 114 and 117 of the gate electrode, it is desirable to use a material having a low resistivity and containing aluminum (Al) or copper (Cu) as a component. Second of gate electrode
The thickness of the layer is 50 to 400 nm, preferably 100 to 2
It may be set to 00 nm. The second layer of the gate electrode is formed for the purpose of reducing the electric resistance of the gate electrode,
The length may be determined in consideration of both the length and resistance of the gate wiring or bus line connected to the gate electrode.

The third layers 115 and 118 of the gate electrode are
Similar to the first layer of the gate electrode, silicon (Si), titanium (Ti), tantalum (Ta), tungsten (W),
It is formed of a material selected from molybdenum (Mo) or a material containing these materials as a component. The thickness of the third layer of the gate electrode is 50 to 400 nm, preferably 100 to 200 n.
It should be m.

In any case, the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode may be formed by forming a coating film of the above material by a sputtering method. It is formed into a predetermined shape by etching and dry etching. Here, in order to form the third layer of the gate electrode so as to cover the second layer of the gate electrode, it is of course necessary to control the thickness of the second layer of the gate electrode as described above. It is necessary to set the sputtering conditions appropriately. For example, it is an effective means to make the film formation rate of the formed film relatively slow.

As the structure of the gate electrode as shown in FIG. 1, the second layer of the gate electrode has a clad structure in which it is surrounded by the first layer of the gate electrode and the third layer of the gate electrode to improve heat resistance. Can be increased. As the material of the gate electrode,
It is desirable to use a material having a low resistivity such as Al or Cu, but there are problems that hillocks are generated when heated at 450 ° C. or higher, and that hillocks are diffused into the surrounding insulating film or semiconductor layer. However, such a phenomenon is caused by Si, Ti,
This can be prevented by using a material such as Ta, W, or Mo, or a clad structure surrounded by a material containing these materials.

The semiconductor layer of the n-channel TFT has a channel forming region 104 and first impurity regions 107 and 108.
And second impurity regions 105, 106a, and 106b formed in contact with the channel formation region. An impurity element imparting n-type conductivity is added to both the first impurity region and the second impurity region. At this time, the concentration of the impurity element is 1 × 1 in the first impurity region.
0 ²⁰ to 1 × 10 ²¹ atoms / cm ³ , preferably 2 × 10 ²⁰ to
The concentration of the second impurity region is 5 × 10 ²⁰ atoms / cm ³ , and the concentration of the second impurity region is 1 × 10 ^{16 to} 5 × 10 ¹⁹ atoms / cm ³ , typically 5 ×
It is added at ^{10 17 ~5 × 10 1 8 atoms} / cm 3. First
Impurity regions 107 and 108 function as a source region and a drain region.

On the other hand, the third impurity regions 111, 112a, 112b of the p-channel TFT function as a source region or a drain region. And the third
In the impurity region 112b, the impurity element imparting n-type is contained at the same concentration as that of the first impurity region, but the impurity element imparting p-type is added at a concentration 1.5 to 3 times that of the first impurity region. There is.

The impurity element for the second impurity region is formed by a method of adding an impurity element imparting n-type to be added to the semiconductor layer through the first layer 113 of the gate electrode and the gate insulating film 103. It is a thing.

The second impurity regions 106a and 106b are
As shown in FIGS. 2A and 2B, a second impurity region 106a which overlaps with the gate electrode and a second impurity region 106b which does not overlap with the gate electrode can be divided with the gate insulating film 103 interposed therebetween. That is, the LDD region that overlaps the gate electrode and the LDD that does not overlap.
A region is formed. This region is divided into a first step of adding an impurity element of one conductivity type (formation of a second impurity region) and a second step of adding an impurity element of one conductivity type (first impurity region). Formation), and the photoresist may be used as a mask at this time.

This is a very convenient method when manufacturing circuits with different drive voltages on the same substrate. Figure 2
FIG. 1B shows an example of design values of TFTs used in the logic circuit section, the buffer circuit section, the analog switch section, and the pixel matrix circuit of the liquid crystal display device. At this time,
Considering the driving voltage of each TFT, the second impurity region 106 overlapping the gate electrode as well as the channel length is taken into consideration.
a and the second impurity region 106b which does not overlap with the gate electrode
It is possible to set the length of.

TFT of shift register circuit of drive circuit
In addition, since the TFT of the buffer circuit basically emphasizes the characteristics of the ON region, a so-called GOLD structure may be used, and the second impurity region 106b that does not overlap with the gate electrode is not necessarily provided. However, if it is intentionally provided, it may be set in the range of 0.5 to 3 μm in consideration of the driving voltage.
In any case, considering the breakdown voltage, it is desirable that the value of the second impurity region 106b that does not overlap the gate electrode be increased as the driving voltage increases.

Further, since it is difficult for the analog switch and the TFT provided in the pixel matrix circuit to increase the off current, for example, when the driving voltage is 16 V, the channel length is 3 μm.
As the second impurity region 106a overlapping with the gate electrode is 1.5 μm, and the second impurity region 106b not overlapping with the gate electrode is 1.5 μm. Of course, the present invention is not limited to the design values shown here, and may be determined by the practitioner as appropriate.

Further, as shown in FIG. 17, in the present invention, the first layer 1701 of the gate electrode, the second layer 1702 of the gate electrode, and the third layer 1703 of the gate electrode are arranged in the channel length direction. The length is closely related to the size of the TFT to be manufactured. The length of the second layer 1702 of the gate electrode in the channel length direction substantially corresponds to the channel length L1. At this time, L1 may have a value of 0.1 to 10 μm, typically 0.2 to 5 μm.

Further, the length L of the second impurity region 1705
Although 6 can be arbitrarily set by masking with a photoresist as described above, it is desirable to form 6 to 0.2 μm, typically 0.6 to 3 μm.

The length L4 at which the second impurity region 1705 overlaps with the gate electrode is determined by the first layer 17 of the gate electrode.
It has a close relationship with the length L2 of 01. The length of L4 is
The thickness is preferably 0.1 to 4 μm, typically 0.5 to 3 μm. Further, the length L5 at which the second impurity region 1705 does not overlap the gate electrode may not necessarily be provided as described above, but is usually 0.1 to 3.
μm, typically 0.3 to 2 μm. Here, the lengths of L4 and L5 may be determined based on the driving voltage of the TFT as described above, for example.

Further, in FIG. 1, the channel forming region 10
4 includes 1 × 10 ^{16 to} 5 × 10 ¹⁸ atoms / cm ^{3 in} advance.
Boron may be added at a concentration of. This boron is added to control the threshold voltage, and other elements can be substituted as long as the same effect can be obtained.

As described above, according to the present invention, the gate electrodes are the first layers 113 and 116 of the gate electrodes, the second layers 114 and 117 of the gate electrodes, and the third layer 11 of the gate electrodes.
5, 118, and the second layer 114 and 117 of the gate electrode is the first layer 11 of the gate electrode as shown in FIG.
3 and 116 and the third layer 115, 118 of the gate electrode, which is a clad type structure. At least the n-channel TFT is characterized by the structure in which a part of the second impurity region 106 provided in the semiconductor layer with the gate insulating film 103 interposed therebetween overlaps with such a gate electrode.

In the n-channel TFT, the second impurity region may be provided only on the drain region side (the first impurity region 108 side in FIG. 1) centering on the channel forming region 104. Further, when characteristics of both the ON region and the OFF region are required as in the pixel TFT of the pixel matrix circuit, the source side (the first impurity region 107 side in FIG. 1) is centered on the channel formation region 104. It is desirable to provide both on the drain region side (on the first impurity region 108 side in FIG. 1).

On the other hand, in the p-channel TFT, the channel forming region 109 and the third impurity regions 111, 112a, 1 are formed.
12b is formed. Of course, the structure may be similar to that of the n-channel type TFT of the present invention, but since the p-channel type TFT is originally highly reliable, it is preferable to earn an on-current to balance the characteristics with the n-channel type TFT. When the present invention is applied to a CMOS circuit as shown in FIG. 1, it is important to balance these characteristics. However, the structure of the present invention is applied to a p-channel TFT.
There is no problem even if applied to.

When the n-channel TFT and the p-channel TFT are completed in this way, they are covered with the first interlayer insulating film 119, and the source wirings 120 and 121 and the drain wiring 122.
To provide. In the structure of FIG. 1, after providing these, a silicon nitride film is provided as the passivation film 123. Further, a second interlayer insulating film 124 made of a resin material is provided. The second interlayer insulating film does not need to be limited to a resin material, but when applied to a liquid crystal display device, for example, it is preferable to use a resin material in order to secure the flatness of the surface.

In FIG. 1, a CMOS circuit formed by complementarily combining an n-channel TFT and a p-channel TFT is shown as an example, but an NMO using an n-channel TFT is shown.
The present invention can also be applied to the S circuit and the pixel matrix circuit of the liquid crystal display device.

The structure of the present invention described above will be described in more detail with reference to the following embodiments.

[Embodiment 1] In this embodiment, the structure of the present invention will be described with reference to a method for simultaneously producing a pixel matrix circuit and a CMOS circuit which is a basic form of a driving circuit provided in the periphery thereof.

In FIG. 3A, a non-alkali glass substrate typified by Corning's 1737 glass substrate is used as the substrate 301. Then, a base film 302 is formed by plasma CVD or sputtering on the surface of the substrate 301 on which the TFT is formed. Although not shown, the base film 302 is a silicon nitride film having a thickness of 25 to 100 nm, typically 50 nm, and a silicon oxide film having a thickness of 50 to 300 n.
m, typically 150 nm thick.

In addition, SiH ₄ ,
A silicon oxynitride film made of NH ₃ and N ₂ O
~ 200 nm (preferably 50-100 nm), as well as Si
A silicon oxynitride film made of H ₄ and N ₂ O is applied to 50-
The layers are formed to a thickness of 200 nm (preferably 100 to 150 nm).

Next, an amorphous silicon film having a thickness of 50 nm is formed on the base film 302 by the plasma CVD method. Although depending on the hydrogen content of the amorphous silicon film, it is preferable that the amorphous silicon film is heated at 400 to 550 ° C. for several hours for dehydrogenation treatment, and the hydrogen content is set to 5 atomic% or less before the crystallization step. . Further, the amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, but it is preferable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.

Here, since both the base film and the amorphous silicon film can be formed by the plasma CVD method, even if the base film and the amorphous silicon film are continuously formed in vacuum. good. It is possible to prevent surface contamination and reduce variations in the characteristics of the TFTs to be manufactured by performing a step of not exposing to the air atmosphere after forming the base film.

In the step of crystallizing the amorphous silicon film, a well-known laser annealing method or thermal annealing method may be used. In this embodiment, a pulse oscillation type KrF excimer laser beam is linearly focused and irradiated onto an amorphous silicon film to form a crystalline silicon film.

When the crystallization is performed by the laser annealing method, a pulse oscillation type or continuous emission type excimer laser or an argon laser is used as the light source. Also, YAG
The laser is used as the light source, and its fundamental frequency, second harmonic,
The third harmonic and the fourth harmonic may be used as the light source. When a pulse oscillation type excimer laser is used, laser light is processed into a linear shape and laser annealing is performed. Although the laser annealing conditions are appropriately selected by the practitioner, for example,
The laser pulse oscillation frequency is 30 Hz, and the laser energy density is 100 to 500 mJ / cm ² (typically 300
~ 400 mJ / cm ² ). Then, the linear beam is irradiated over the entire surface of the substrate, and the overlapping rate (overlap rate) of the linear beams at this time is set to 80 to 98%.

Although the crystalline silicon film is formed from the amorphous silicon film as the semiconductor layer in this embodiment, a microcrystalline silicon film may be used or a crystalline silicon film may be directly formed. .

The crystalline silicon film thus formed is patterned to form island-shaped semiconductor layers 303, 304, 305.
To form.

Next, the island-shaped semiconductor layers 303, 304, 3
A gate insulating film 306 containing silicon oxide or silicon nitride as a main component is formed so as to cover 05. The gate insulating film 306 may be formed of a silicon oxynitride film using N ₂ O and SiH ₄ as raw materials in a thickness of 10 to 200 nm, preferably 50 to 150 nm by a plasma CVD method. Here, it is formed to have a thickness of 100 nm.

Then, a gate electrode composed of the first layer of the gate electrode, the second layer of the gate electrode and the third layer of the gate electrode is formed on the gate insulating film 306. First, the conductive layer (A) 307 and the conductive layer (B) 308 are formed. The conductive layer (A) 307 may be formed of a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. The thickness of the conductive layer (A) 307 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, 50 nm
To form a Ti film by the sputtering method.

Gate insulating film 306 and conductive layer (A) 307
It is important to control the thickness of the. This is because in a first step of adding a later impurity, an impurity imparting n-type is added to the semiconductor layers 303 and 305 through the gate insulating film 306 and the conductive layer (A) 307. Actually, the process conditions for the first impurity addition were determined in consideration of the film thicknesses of the gate insulating film 306 and the conductive layer (A) 307 and the concentration of the impurity element to be added. It has been confirmed in advance that an impurity element can be added to the semiconductor layer within the above film thickness range, but if the film thickness fluctuates by 10% or more from the set original value, the concentration of the added impurity will decrease.

The conductive layer (B) is preferably made of a material selected from Al and Cu. This is provided to reduce the electric resistance of the gate electrode, and is 50 to 40
It is formed to a thickness of 0 nm, preferably 100 to 200 nm. When Al is used, pure Al may be used,
0.1-5 atomic elements selected from Ti, Si and Sc
% Al alloy may be used. When copper is used, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 306.

Here, an Al film added with 0.5 atomic% of Sc is formed to a thickness of 200 nm by the sputtering method (FIG. 3A).

Next, a step of removing a part of the conductive layer (B) 308 is performed by forming a resist mask using a known patterning technique. Here, the conductive layer (B) 308 is Sc
Is formed of an Al film to which 0.5 atomic% is added, a wet etching method using a phosphoric acid solution is used.
Then, as shown in FIG. 3B, second layers 309, 310, 311, and 312 of the gate electrode are formed from the conductive layer (B). The length in the channel length direction of the second layer of each gate electrode is 3 μm in the second layers 309 and 310 of the gate electrode forming the CMOS circuit, and the pixel matrix circuit has a multi-gate structure. The length of each of the second layers 311 and 312 of the gate electrode was set to 2 μm.

Although it is possible to perform this step by a dry etching method, in order to remove an unnecessary region of the conductive layer (B) 308 with good selectivity without damaging the conductive layer (A) 307, a wet process is performed. The etching method is preferred.

Further, the storage capacitor is provided on the drain side of the pixel TFT which constitutes the pixel matrix circuit. At this time, the capacitor wiring 313 of the storage capacitor is formed of the same material as the conductive layer (B).

Then, a process for forming a p-channel type TFT
A resist mask 314 is formed in the region to form the first n-type
A step of adding an impurity element to be given is performed. Crystalline semiconductor
As an impurity element that imparts n-type to the body material,
(P), arsenic (As), antimony (Sb), etc.
However, here, using phosphorus, phosphine
(PH₃) Is used for the ion doping method. In this process
Through the gate insulating film 306 and the conductive layer (A) 307
In order to add phosphorus to the semiconductor layer below, the acceleration voltage is
Set a high value of 80 keV. Phosphorus added to the semiconductor layer
Concentration is 1 × 10 ¹⁶~ 5 x 10¹⁹atoms / cm³The range of
It is preferable that it is 1 × 10 here.¹⁸atoms / cm³Tosu
It Then, a region 315 in which phosphorus is added to the semiconductor layer,
316, 317, 318, 319, 320 are formed
(FIG. 3 (B)).

After removing the resist mask 314, the conductive layer (A) 307 and the second layer 30 of the gate electrode are formed.
9, 310, 311, 312 and the conductive layer (C) 3 which is a third layer of the gate electrode in close contact with the storage capacitor wiring 313.
21 is formed. The conductive layer (C) 321 is made of Ti, Ta,
It may be formed of a material selected from W and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. For example, the thickness of the conductive layer (C) 321 needs to be 10 to 100 nm, preferably 20 to 50 nm. Here, a Ta film is formed with a thickness of 50 nm by a sputtering method (FIG. 3C).

Next, a step of removing a part of the conductive layer (C) 321 and the conductive layer (A) 307 is performed by forming a resist mask using a known patterning technique. here,
The dry etching method is used. The conductive layer (C) 321 is Ta, and 100 mT by introducing 80 SCCM of CF ₄ and 20 SCCM of O ₂ as conditions for dry etching.
The high frequency power of 500 W is applied at orr. At this time, the etching rate of Ta is 60 nm / min. The conditions for etching the conductive layer (A) 307 are Si
Introducing 40 SCCM of Cl ₄ , 5 SCCM of Cl ₂ and 180 SCCM of BCl ₃ , 80 mTorr, 1200 W
Is applied by applying high frequency power. At this time, the etching rate of Ti is 34 nm / min.

Although a slight residue may be confirmed after etching, it can be removed by cleaning with a solution such as SPX cleaning liquid or EKC. Further, under the above etching conditions, the etching rate of the underlying gate insulating film 306 is 18 to 38 nm / min, and it should be noted that the etching of the gate insulating film proceeds if the etching time is long.

Then, the first layers 322, 3 of the gate electrodes
23, 324, 325 and the third layer 327 of the gate electrode,
328, 329, 330 are formed. The first layer of the gate electrode and the third layer of the gate electrode are formed to have the same length in the channel length direction, and the first layer of the gate electrode 322,
323 and the third layers 327 and 328 of the gate electrode are 6 μm
To the length of. In addition, the first layer 32 of the gate electrode
4, 325 and the third layer 329, 330 of the gate electrode are 4
It is formed to a length of μm (FIG. 4 (A)).

In this way, the gate electrode composed of the first layer of the gate electrode, the second layer of the gate electrode and the third layer of the gate electrode is formed. In addition, a storage capacitor is provided on the drain side of the pixel TFT that constitutes the pixel matrix circuit. At this time, storage capacitor wirings 326 and 331 are formed from the conductive layer (A) and the conductive layer (C).

Then, as shown in FIG. 4B, resist masks 332, 333, 334, 335, and 336 are formed, and a second step of adding an impurity element imparting n-type conductivity is performed. This is also performed by the ion doping method using phosphine (PH ₃ ). Even in this step, the gate insulating film 30
6 to add phosphorus to the semiconductor layer thereunder,
The acceleration voltage is set as high as 80 keV. Then, the phosphorus added regions 337, 338, 339, 340, 3
41, 342, 343 are formed. The concentration of phosphorus in this region is higher than that in the first step of adding the impurity element imparting n-type conductivity, and is 1 × 10 ¹⁹ to 1 × 10 ^21.
Atoms / cm ³ is preferable, and here 1 × 10 ²⁰ ato
ms / cm ³

In this step, the resist mask 33
The lengths of 2, 333, 334, and 335 in the channel length direction are important in determining the structure of each TFT.
Particularly, in the n-channel TFT, the second impurity region does not overlap with the gate electrode because of the lengths of the first and third layers of the gate electrode and the length of the resist mask. The area can be freely determined within a certain range. In this embodiment, the first layer 322 of the gate electrode
And the length of the third layer 327 is 6 μm, the first of the gate electrode
Since the lengths of the third layers 324 and 325 and the third layers 329 and 330 are 4 μm, the resist mask 332 has a length of 9 μm.
And the resist masks 334 and 335 were formed to have a length of 7 μm. Of course, the respective lengths described here are examples, and it is advisable to determine them in consideration of the driving voltage of the TFT as described above.

Next, a step of covering the regions for forming the n-channel type TFTs with resist masks 344 and 345 and adding a third impurity element imparting p-type to only the regions for forming the p-channel type TFTs. I do. As the impurity element imparting p-type, boron (B), aluminum (A
l) and gallium (Ga) are known, but here, boron is added as the impurity element by an ion doping method using diborane (B ₂ H ₆ ). Also in this case, the acceleration voltage is set to 80 keV, and boron is added at a concentration of 2 × 10 ²⁰ atoms / cm ³ . Then, as shown in FIG. 4C, third impurity regions 346a and
46b, 347a, 347b are formed. Phosphorus added in the previous step is contained in the third impurity regions 346b and 347b, but there is no problem because boron is added at a concentration twice that (FIG. 4C).

When the steps up to FIG.
As shown by, the step of removing the resist masks 344 and 345 and forming the first interlayer insulating film 374 is performed. The first interlayer insulating film 374 has a two-layer structure. First, a silicon nitride film 374a is formed to a thickness of 50 nm. The silicon nitride film is formed by the plasma CVD method, and SiH ₄ is added to 5 SC.
40 SCCM of CM and NH ₃ and 100 SCCM of N ₂ are introduced, and high frequency power of 0.7 Torr and 300 W is applied. Then, subsequently, the silicon oxide film 374b is formed with TEOS.
Introduces 500 SCCM and O ₂ 50 SCCM, 1 Tor
A high frequency power of 200 W is applied to form a film having a thickness of 950 nm. In this manner, the silicon nitride film 374a and the silicon oxide film 374b form a first interlayer insulating film 374 having a total thickness of 1 μm.

The silicon nitride film formed here is necessary for performing the next heat treatment step. In this embodiment, the gate electrode having the clad structure as described above is formed. This structure is formed so that the second layer of the gate electrode formed of Al is surrounded by the first layer of the gate electrode formed of Ti and the third layer of the gate electrode formed of Ta. . Ta has an effect of preventing hillocks of Al and exudation to the surroundings, but has a drawback that it is oxidized immediately when heated at 400 ° C. or higher under normal pressure. As a result, electric resistance increases, but oxidation can be prevented by covering the surface with the silicon nitride film 374a of the first interlayer insulating film.

The heat treatment step must be carried out to activate the impurity element imparting n-type or p-type added at each concentration. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-mentioned excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it is difficult to activate even the shaded region under the gate electrode. Therefore, the activation process is performed here by the thermal annealing method. The condition at this time is 300 to 700 ° C., preferably 350 in a nitrogen atmosphere.
Up to 550 ° C., here 450 ° C., for 2 hours.

Thereafter, the first interlayer insulating film 374 is patterned to form a contact hole reaching the source region and the drain region of each TFT. Then, the source wirings 375, 376, 377 and the drain wiring 37
8 and 379 are formed. Although not shown, this wiring is used as a wiring having a three-layer structure in which a Ti film of 100 nm, an Al film of 300 nm containing Ti, and a Ti film of 150 nm are successively formed by a sputtering method, although not shown.

Then, the source wirings 375, 376, 37
7 and the drain wirings 378 and 379 and the first interlayer insulating film 374, a passivation film 380 is formed.
The passivation film 380 is a silicon nitride film with a thickness of 50 n.
It is formed with a thickness of m. Further, a second interlayer insulating film 381 made of organic resin is formed to a thickness of about 1000 nm.
As the organic resin film, polyimide, acryl, polyimide amide or the like can be used. The advantage of using the organic resin film is that the film formation method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above can also be used. Here, a polyimide of a type that is thermally polymerized after being applied to the substrate is used, and is baked at 300 ° C. to be formed.

Through the above steps, the gate electrode having the clad structure is formed, and the channel forming region 348, the first impurity region 360, and the n-channel TFT of the CMOS circuit are formed.
361, second impurity regions 349a, 349b, 350
a and 350b are formed. Here, in the second impurity region, the regions 349a and 350a overlapping with the gate electrode are 1.
A region (LDD) that does not overlap the gate electrode with a length of 5 μm
Regions 349b and 350b are formed to a length of 1.5 μm, respectively. Then, the first impurity region 360 functions as a source region and the first impurity region 361 functions as a drain region.

Similarly, in the p-channel TFT, a gate electrode having a clad structure is formed, and a channel forming region 362,
Third impurity regions 363a, 363b, 364a, 36
4b is formed. Third impurity regions 363a and 363
b is used as a source region for the third impurity regions 364a, 3
64b becomes a drain region.

Further, the pixel TFT of the pixel matrix circuit
Are channel formation regions 365 and 369, first impurity regions 368 and 372, and second impurity regions 366 and 367.
370 and 371 are formed. The second impurity region has regions 366a, 367a, 37 overlapping the gate electrode.
Areas 366b, 367b that do not overlap with 0a, 371a,
370b and 371b.

Thus, as shown in FIG. 5, an active matrix substrate in which the CMOS circuit and the pixel matrix circuit are formed on the substrate 301 is manufactured. Further, a storage capacitor is simultaneously formed on the drain side of the pixel TFT of the pixel matrix circuit.

[Embodiment 2] Similar to Embodiment 1, this embodiment describes another embodiment in which a CMOS circuit, which is a basic form of a pixel matrix circuit and a driving circuit provided around the pixel matrix circuit, is manufactured at the same time.

First, as in the first embodiment, the steps of FIGS. 3A to 3C and the steps of FIG. 4A are performed.

FIG. 6A shows a state in which the gate electrode is formed from the first layer of the gate electrode, the second layer of the gate electrode, and the third layer of the gate electrode. For the substrate in this state, resist masks 601, 602, 60
3, 604, and 605 are formed, and a step of adding an impurity element imparting n-type is performed. Then, the first impurity region 6
06, 607, 608, 609, 610, 611, 61
2 is formed (FIG. 6 (B)).

The resist mask 601 formed here,
Reference numerals 602 each have a shape in which the LDD region is formed only on the drain region side of the TFT. In this, a region for masking the second impurity region from above the gate insulating film is formed only on one side with the channel forming region as the center.

The formation of such a resist mask is performed by CM
It is particularly effective for the n-channel TFT of the OS circuit. Since the LDD region is formed on only one side, it is possible to substantially reduce the series resistance component of the TFT and increase the on-current.

Both the GOLD structure and the LDD structure described above are provided in order to reduce the high electric field in the vicinity of the drain region, and the effect is obtained if they are formed on the drain side of the TFT. Is enough.

Further, the resist masks 613 and 614 are formed, and the step of adding the impurity element imparting p-type conductivity is performed as in the first embodiment, and the third impurity regions 615a and 61 are formed.
5b and 616 are formed. The third impurity region 615a contains the impurity element imparting n-type which is added in the previous step (FIG. 6C).

Subsequent steps may be performed in the same manner as in Example 1, and the source wirings 375, 376, 377 and drain wirings 378, 379, the passivation film 380, and the second interlayer insulating film 381 made of organic resin are formed. The active matrix substrate shown in FIG. 7 is completed. And CMO
The n-channel TFT of the S circuit has a channel formation region 61.
7, first impurity regions 620 and 621, and second impurity regions 618 and 619 are formed. Here, the second impurity region is a region (GOLD region) 61 overlapping the gate electrode 61.
9a and a region (LDD region) 6 that does not overlap the gate electrode 6
19b are formed respectively. Then, the first impurity region 620 serves as a source region and the first impurity region 621 is used.
Becomes a drain region.

The p-channel TFT has a channel forming region 622 and third impurity regions 624a, 624b, 623.
Is formed. The third impurity region 623 serves as a source region and the third impurity regions 624a and 624b serve as drain regions. The pixel TFT of the pixel matrix circuit includes channel formation regions 625 and 629 and a first impurity region 62.
8, 632 and second impurity regions 626, 627, 63
0, 631 are formed. The second impurity regions are regions 626a, 627a, 630a overlapping the gate electrodes,
Regions 626b, 627b, 630 that do not overlap with 631a
b and 631b.

[Embodiment 3] Similar to Embodiment 1, this embodiment describes another embodiment in which a CMOS circuit, which is a basic form of a pixel matrix circuit and a driving circuit provided around the pixel matrix circuit, is manufactured at the same time.

First, similar to the first embodiment, the steps of FIGS. 3A to 3C are performed.

Then, in FIG. 8A, resist masks 801, 802, 80 are formed by using a known patterning technique.
3, 804 and 805 are formed, and a step of removing a part of the conductive layer (C) 321 and the conductive layer (A) 307 is performed. Here, the dry etching method is performed as in the first embodiment.
Then, the first layers 851, 852, 85 of the gate electrodes
3, 854, 855 and the third layer 856, 8 of the gate electrode
57, 858, 859 and 860 are formed. The first layer of the gate electrode and the third layer of the gate electrode are formed to have the same length in the channel length direction, and the first layers 851 and 852 of the gate electrode and the third layer of the gate electrode of the CMOS circuit are formed. 85
6,857 are formed to have a length of 9 μm, which is longer than the final shape. In addition, the first of the gate electrodes of the pixel matrix circuit
The layers 853 and 854 and the third layers 858 and 8 of the gate electrode
Similarly, 59 is formed to have a length of 7 μm.

Further, the storage capacitor is provided on the drain side of the pixel TFT of the pixel matrix circuit. At this time, wirings 855 and 860 for the storage capacitor are formed from the conductive layer (A) and the conductive layer (C).

Then, as in the first embodiment, the second step of adding the impurity element imparting n-type is performed. In this step, phosphorus is added to the semiconductor layer through a region of the gate insulating film which is not in contact with the gate electrode to form regions 806, 807, 808, 811, 812 to which phosphorus is added at high concentration. After completion of this step, resist masks 801 and 8
02, 803, 804, and 805 are removed (FIG. 8).
(A)).

Next, a photoresist film is formed again, and a patterning process is performed by exposing from the back surface. At this time, as shown in FIG. 8B, the gate electrodes serve as masks, and the resist masks 813, 814, 81 are self-aligned.
5, 816, 817 are formed. The exposure from the back surface is performed using direct light and scattered light. By adjusting the exposure conditions such as light intensity and exposure time, a resist mask is formed inside the gate electrode as shown in FIG. 8B. can do.

Resist masks 813, 814, 815,
Using 816 and 817, the unmasked regions of the third layer of the gate electrode and the first layer of the gate electrode are removed by dry etching. The dry etching conditions are the same as in the first embodiment. After the etching is completed, the resist masks 813, 814, 815, 816, 817 are removed.

Then, as shown in FIG. 8C, the first layer 818, 819, 820, 821 of the gate electrode, the third layer 823, 824, 825, 826 of the gate electrode and the wiring of the storage capacitor. 822 and 827 are formed. By etching, the first layer 85 of the gate electrode of the CMOS circuit is formed.
1 and 852 and the third layer 856 and 857 of the gate electrode are 6
It becomes the length of μm. The first layers 853 and 854 of the gate electrodes and the third layers 858 and 859 of the gate electrodes of the pixel matrix circuit are similarly formed to have a length of 4 μm.

Further, a step of forming resist masks 828 and 829 in a region where an n-channel type TFT is formed and adding a third impurity element imparting p-type conductivity is performed (FIG. 8).
(C)).

The subsequent steps may be performed in the same manner as in Example 1, and the active matrix substrate shown in FIG. 5 can be manufactured.

[Embodiment 4] Similar to Embodiment 1, this embodiment describes another embodiment in which a CMOS circuit, which is a basic form of a pixel matrix circuit and a driving circuit provided around the pixel matrix circuit, is manufactured at the same time.

First, as in the first embodiment, the steps of FIGS. 3A to 3C are performed. Then, as shown in FIG. 9A, a gate electrode is formed.

Next, a step of removing a part of the conductive layer (C) 321 and the conductive layer (A) 307 is performed by forming a resist mask by using a known patterning technique. Here, the dry etching method is used. Conductive layer (C) 32
1 is Ta, and CF is used as a dry etching condition.
100m with ₄ 80 SCCM and O _{2 20} SCCM
The high frequency power of 500 W is applied at Torr. At this time, the etching rate of the Ta film is 60 nm / min. Further, the conditions for etching the conductive layer (A) 307 are as follows: SiCl ₄ = 40 SCCM, Cl ₂ = 5 SCCM, B
Introduced 180 SCCM of Cl ₃ , 80mTorr, 1
It is performed by applying high-frequency power of 200 W. At this time, Ti
The etching rate of the film is 34 nm / min.

Then, the first layers 322, 3 of the gate electrodes
23, 324, 325 and the third layer 327 of the gate electrode,
328, 329, and 330 are formed. The first layer of the gate electrode and the third layer of the gate electrode are formed to have the same length in the channel length direction.
23 and the third layers 327 and 328 of the gate electrode are formed here to a length of 6 μm. In addition, the first layers 324 and 325 of the gate electrode and the third layers 329 and 33 of the gate electrode.
0 is formed with a length of 4 μm.

Under the above etching conditions, the gate insulating film 306 formed of the silicon oxynitride film is also etched. The etching rate is 18 nm / min under the Ta film etching conditions. Normally, this is done carefully so that the gate insulating film is not etched, but by positively utilizing this phenomenon, the region of the gate insulating film that is not in contact with the gate electrode can be thinned. This is a process of etching the gate electrode and can be carried out immediately if the etching time is increased as it is.

However, in order to etch the gate insulating film, it is still necessary to select a gas to be used, and a fluorine-based gas such as CF ₄ or NF ₃ gives better results than a chlorine-based gas. .

Here, the mixed gas of CF ₄ and O ₂ used when etching the Ta film is used. CF ₄ to 8
100 mTo with 0 SCCM and ₂₀ SCCM of O ₂
The high frequency power of 500 W is applied at rr. Then, the gate insulating film 3 formed to have a thickness of 100 nm
As compared with 06, etching for about two and a half minutes is shown in FIG.
As shown in, the region of the gate insulating film which is not in contact with the gate electrode can be thinned to a thickness of 50 nm.

Then, as in the first embodiment, resist masks 332, 333, 334, 335, 336 are formed and the resist mask is formed.
A step of adding an impurity element imparting n-type is performed for the second time. At this time, regions 337, 338, 339, 340, 341, 342 to which the impurity element imparting n-type is added,
Since the gate insulating film 343 has a thickness of 50 nm, the impurity element can be efficiently added to the semiconductor layer.

Since the gate insulating film is thin, the acceleration voltage in the ion doping method is 80 keV to 40 keV.
It is possible to reduce the damage to the gate insulating film and the semiconductor layer (FIG. 9B).

Next, as shown in FIG. 9C, the steps of forming resist masks 344 and 345 and adding an impurity element imparting p-type are also carried out in the same manner. Added regions 346a, 346b, 3
The gate insulating film in contact with 47a and 347b has a thickness of 50n.
Since it is m, the acceleration voltage in the ion doping method can be reduced from 80 keV to 40 keV, and the impurity element can be efficiently added to the semiconductor layer.

Other steps may be in accordance with the first embodiment, and the source wirings 375, 376, 377 and the drain wiring 37.
8, 379, the passivation film 380, and the second interlayer insulating film 381 made of an organic resin are formed to complete the active matrix substrate shown in FIG. CMOS circuit n
The channel type TFT includes a channel formation region 348, first impurity regions 360 and 361, a second impurity region 349,
350 is formed. Here, in the second impurity region, regions 349a and 350a overlapping with the gate electrode and regions (LDD regions) 349b and 350b not overlapping with the gate electrode are formed. Then, the first impurity region 360 functions as a source region and the first impurity region 361 functions as a drain region. Similarly, in the p-channel TFT, a gate electrode having a clad structure is formed, and a channel forming region 36 is formed.
2, third impurity regions 363a, 363b, 364a,
364b is formed. Third impurity regions 363a, 3
63b serves as a source region for the third impurity region 364.
a and 364b become drain regions. Further, the pixel TFTs of the pixel matrix circuit have channel forming regions 365, 3 and 3.
69 and the first impurity regions 368 and 372 and the second impurity regions 366a, 366b, 367a, 367b, and 370.
a, 370b, 371a, 371b are formed. The second impurity region has a region 366 overlapping with the gate electrode.
a, 367a, 370a, 371a and the region 3 which does not overlap
66b, 367b, 370b, 371b.

[Embodiment 5] In this embodiment, the structure of the present invention will be described as a method of simultaneously producing a pixel matrix circuit and a CMOS circuit which is a basic form of a driving circuit provided in the periphery thereof.

In FIG. 11A, a non-alkali glass substrate represented by Corning's 1737 glass substrate is used as the substrate 1101. And the substrate 11
A base film 1102 is formed on the surface where the TFT of No. 01 is formed by a plasma CVD method or a sputtering method. Base film 110
Although not shown in FIG.
nm, typically 50 nm, and a silicon oxide film is formed to a thickness of 50 to 300 nm, typically 150 nm. Alternatively, as the base film 1102, only a silicon nitride film or a silicon oxynitride film may be used.

Next, 50 nm is formed on the base film 1102.
An amorphous silicon film having a thickness of 1 is formed by a plasma CVD method. Although depending on the hydrogen content of the amorphous silicon film, it is preferable that the amorphous silicon film is heated at 400 to 550 ° C. for several hours for dehydrogenation treatment, and the hydrogen content is set to 5 atomic% or less before the crystallization step. . Further, the amorphous silicon film may be formed by another manufacturing method such as a sputtering method or an evaporation method, but it is preferable to sufficiently reduce impurity elements such as oxygen and nitrogen contained in the film.

Here, both the base film and the amorphous silicon film are manufactured by the plasma CVD method, and at this time, even if the base film and the amorphous silicon film are continuously formed in vacuum. good. After the formation of the base film, it is possible to prevent the surface from being contaminated and to reduce the variations in the characteristics of the TFTs to be manufactured, by carrying out the step of not being exposed to the air atmosphere.

Here, the crystalline silicon film used as the semiconductor layer is formed by the thermal crystallization method using a catalytic element. When using a catalytic element, it is desirable to use the techniques disclosed in JP-A-7-130652 and JP-A-8-78329.

An example of applying the technique disclosed in Japanese Patent Application Laid-Open No. 7-130652 to the present invention will be described with reference to FIGS. 19 (A) and 19 (B). A silicon oxide film 1902 is formed on the substrate 1901 and an amorphous silicon film 1903 is formed thereon. A nickel acetate salt solution containing 10 ppm by weight of nickel is applied to the surface of the amorphous silicon film 1903 to form a nickel-containing layer 1904 (FIG. 19A).

Then, after a dehydrogenation step at 500 ° C. for 1 hour, it is carried out at 500 to 650 ° C. for 4 to 12 hours, for example, 550 ° C.
Then, heat treatment is performed for 8 hours to form a crystalline silicon film 1905 (FIG. 19B).

Further, the technique disclosed in Japanese Patent Laid-Open No. 8-78329 enables selective crystallization of an amorphous silicon film by selectively adding a catalytic element. When applying the same technology to the present invention,
This will be described with reference to FIGS.

First, a silicon oxide film 2002 and an amorphous silicon film 2003 are formed on a glass substrate 2001, and a silicon oxide film 2004 is continuously formed. At this time, the thickness of the silicon oxide film 2004 is 150 nm.

Next, the silicon oxide film 2004 is patterned to selectively form the opening portion 2005, and then a nickel acetate salt solution containing 10 ppm by weight of nickel is applied. As a result, the nickel-containing layer 2006 is formed, and the nickel-containing layer 2006 contacts the amorphous silicon film 2003 only at the bottom of the opening portion 2005 (FIG. 2).
0 (A)).

Next, at 500 to 650 ° C. for 4 to 24 hours,
For example, heat treatment is performed at 570 ° C. for 14 hours to form a crystalline silicon film 2007. In this crystallization process, the portion of the amorphous silicon film in contact with nickel is first crystallized, and then the crystallization proceeds in the lateral direction. The crystalline silicon film 2007 thus formed is composed of rod-shaped or needle-shaped crystals aggregated, and each crystal grows in a certain specific direction when viewed macroscopically, so that the crystallinity is uniform. This has the advantage (FIG. 20 (B)).

In addition to nickel (Ni), catalytic elements usable in the above two techniques are iron (Fe), palladium (Pd), tin (Sn), lead (Pb), cobalt (Co), Elements such as platinum (Pt), copper (Cu), and gold (Au) may be used.

By forming a crystalline silicon film using the above technique and patterning it, the semiconductor layers 1103, 1104, 1105 shown in FIG. 11 can be formed.

Further, an example is shown in which a crystalline silicon film is formed using a catalytic element and a gettering step of removing the catalytic element from the crystalline silicon film is performed.

This is a technique of removing the catalytic element used for crystallization of the amorphous silicon film after crystallization by using the gettering action of phosphorus. By using this technique, the concentration of the catalytic element in the crystalline silicon film is set to 1 × 10 ¹⁷ atoms / cm ³
Hereafter, it can be reduced to preferably 1 × 10 ¹⁶ atoms / cm ³ .

FIG. 21A shows a state in which the base film 2102 and the crystalline silicon film 2103 are formed.
Then, a silicon oxide film 2104 for a mask is formed in a thickness of 150 nm on the surface of the crystalline silicon film 2103, an opening is provided by patterning, and an area where the crystalline silicon film is exposed is provided. Then, a step of adding phosphorus is performed to provide a region 2105 in which phosphorus is added to the crystalline silicon film.

In this state, 550 to 80 in a nitrogen atmosphere.
When heat treatment is performed at 0 ° C. for 5 to 24 hours, for example at 600 ° C. for 12 hours, the region 2105 in which phosphorus is added to the crystalline silicon film functions as a gettering site and remains in the crystalline silicon film 2103. The catalytic element can be segregated in the region 2105 where phosphorus is added.

Then, the silicon oxide film 210 for the mask is used.
4 and the region 2105 to which phosphorus is added are removed by etching, so that the concentration of the catalyst element used in the crystallization process is reduced to 1 × 10 ¹⁷ atoms / cm ³ or less. Can be obtained. This crystalline silicon film is used as the semiconductor layers 1103 and 110 of FIG.
4, 1105 can be used.

Next, island-shaped semiconductor layers 1103 and 110
A gate insulating film 1106 containing silicon oxide or silicon nitride as a main component is formed so as to cover 4 and 1105. The gate insulating film 1106 is formed by plasma CVD using N ₂ O and S.
10-200 silicon oxynitride film made from iH ₄
nm, preferably 50 to 150 nm. Here, it is formed to have a thickness of 100 nm.

Then, a conductive layer (A) 1107 which is the first layer of the gate electrode and a conductive layer (B) 1108 which is the second layer of the gate electrode are formed on the surface of the gate insulating film 1106. The conductive layer (A) 1107 is made of Ti, Ta, W, Mo.
Although it may be formed of a material selected from the above, a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. The thickness of the conductive layer (A) 1107 is 10 to 100.
nm, preferably 20-50 nm. Here, a Ti film is formed with a thickness of 50 nm by a sputtering method.

Conductive layer (B) which is the second layer of the gate electrode
It is preferable to use a material selected from Al and Cu for 1108. This is provided to reduce the electric resistance of the gate electrode, and is formed to a thickness of 50 to 400 nm, preferably 100 to 200 nm. When Al is used, pure Al may be used, or Ti, Si, Sc may be used.
Al containing 0.1 to 5 atomic% of element selected from
An alloy may be used. When copper is used, although not shown, it is preferable to provide a silicon nitride film with a thickness of 30 to 100 nm on the surface of the gate insulating film 1106.

Here, an Al film added with 0.5 atomic% of Sc is formed to a thickness of 200 nm by the sputtering method (FIG. 11A).

Next, a step of removing a part of the conductive layer (B) 1108 is performed by forming a resist mask by using a known patterning technique. Although the conductive layer (B) 1108 is formed of an Al film to which Sc is added at 0.5 atomic% here, it can be formed by a wet etching method using a phosphoric acid solution. Then, as shown in FIG. 11B, the second layers 1109, 1110, 1111, 11 of the gate electrode are formed.
12 is formed. The length in the channel length direction of the second layer of each gate electrode is 3 μm in the second layers 1109 and 1110 of the gate electrodes forming the CMOS circuit, and the pixel matrix circuit has a multi-gate structure. Then, the length of each of the second layers 1111 and 1112 of the gate electrode is set to 2 μm.

In addition, a storage capacitor is provided on the drain side of the pixel TFT which constitutes the pixel matrix circuit. At this time, the wiring 1113 of the storage capacitor is formed using the same material as the conductive layer (B).

Then, the first impurity element imparting n-type conductivity
Is added. Here, using phosphorus,
Fin (PH₃) Is used for the ion doping method. this
In the process, the gate insulating film 1106 and the conductive layer (A) 110
7 through the semiconductor layers 1103, 1104, 11 thereunder.
In order to add phosphorus to 05, the accelerating voltage is 80 keV
Set higher. The concentration of phosphorus added to the semiconductor layer is
1 x 10¹⁶~ 5 x 10 ¹⁹atoms / cm³Is preferable to
1x10 here¹⁸atoms / cm³And That
The regions 1114 and 111 in which phosphorus is added to the semiconductor layer
5, 1116, 1117, 1118, 1119, 112
0 and 1121 are formed (FIG. 11B).

Next, a step of covering regions for forming n-channel TFTs with resist masks 1122, 1123 and adding a third impurity element imparting p-type to only regions where p-channel TFTs are formed. I do. Here, boron is added as the impurity element by an ion doping method using diborane (B ₂ H ₆ ). Again, the acceleration voltage is 80
Boron is added at a concentration of 2 × 10 ²⁰ atoms / cm ³ as keV. Then, as shown in FIG. 11C, third impurity regions 1124 and 112 to which boron is added at a high concentration are formed.
5 is formed.

Then, the resist masks 1122 and 112
3 is removed, the conductive layer (A) 1107, the second layers 1109, 1111, 1112 of the gate electrode and the wiring 1113 of the storage capacitor are brought into close contact with the conductive layer (C) to be the third layer of the gate electrode (C). ) 1126 is formed. The conductive layer (C) 1126 may be formed of a material selected from Ti, Ta, W, and Mo, but a compound containing the above material as a component may be used in consideration of electric resistance and heat resistance. For example, the thickness of the conductive layer (C) 1126 is 10 to 100 nm,
It should preferably be 20 to 50 nm. Here, a Mo-W film is formed with a thickness of 50 nm by a sputtering method. (Fig. 12 (A))

Next, a step of removing a part of the conductive layer (C) 1126 and the conductive layer (A) 1107 is performed by forming a resist mask by using a known patterning technique. Here, the dry etching method is used. Conductive layer (C) 11
Reference numeral 26 is a Mo-W film, and as a dry etching condition, 80 SCCM of Cl ₂ is introduced, and high frequency power of 350 W is applied at 10 mTorr. At this time Mo-
The etching rate of the W film is 50 nm / min. Also,
The conditions for etching the conductive layer (A) 1107 are SiC.
l ₄ for 40 SCCM, Cl ₂ for 5 SCCM, BCl ₃ for 1
80 SCCM is introduced, and high frequency power of 80 mTorr and 1200 W is applied. At this time, the etching rate of the Ti film is 34 nm / min.

Although a slight residue may be observed after etching, it can be removed by cleaning with a solution such as SPX cleaning liquid or EKC. In addition, under the above etching conditions, the etching rate of the underlying gate insulating film 1106 is 18 to 38 nm / min, and it should be noted that the etching of the gate insulating film proceeds if the etching time is long.

Then, the first layer 1127 of the gate electrode,
1128, 1129, 1130 and the third layers 1132, 1133, 1134, 1135 of the gate electrodes are formed. The first layer of the gate electrode and the third layer of the gate electrode are formed to have the same length in the channel length direction, and the first layers 1127 and 1128 of the gate electrode and the third layer of the gate electrode 1
Here, 132 and 1133 are formed to have a length of 6 μm. The first layers 1129 and 1130 of the gate electrode and the third layers 1134 and 1135 of the gate electrode are formed to have a length of 4 μm (FIG. 12B).

In addition, a storage capacitor is provided on the drain side of the pixel TFT which constitutes the pixel matrix circuit. At this time, electrodes 1131 and 1136 of the storage capacitor are formed from the conductive layer (A) and the conductive layer (C).

Then, as shown in FIG. 12C, resist masks 1137, 1138, 1139, 1140,
1141 is formed, and a step of adding a second impurity element imparting n-type conductivity is performed. Here, phosphine (PH
₃ ) is used for the ion doping method. Also in this step, the accelerating voltage is set as high as 80 keV in order to add phosphorus to the semiconductor layer thereunder through the gate insulating film 1106. Then, the phosphorus-added regions 1142 and 114
3, 1144, 1145, 1146, 1147, 114
8 is formed. The phosphorus concentration in this region is higher than that in the step of adding the first impurity element imparting n-type conductivity, and is preferably 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ^3. Then, it is set to 1 × 10 ²⁰ atoms / cm ³ .

In this step, the resist mask 113
The length of 7, 1138, 1139, 1140 in the channel length direction is important in determining the structure of each TFT. In particular, in the n-channel TFT, the second impurity region does not overlap with the region overlapping with the gate electrode due to the lengths of the first and third layers of the gate electrode and the length of the resist mask. The area can be freely determined within a certain range. In this embodiment, the first layer 1 of the gate electrode
127, 1128 and the third layer 1132, 1 of the gate electrode
The length of 133 is 6 μm, and the first layer of the gate electrode 1
129, 1130 and the third layer of gate electrodes 1134, 1
Since the length of 135 is 4 μm, the length of the third layer of the first and gate electrodes is 6 μm, so that the resist mask 1137 has a length of 9 μm.
9 and 1140 are formed with a length of 7 μm.

After the steps shown in FIG. 12C are completed, resist masks 1137, 1138, 1139, 114 are formed.
A step of removing the first insulating film 1168 and the first interlayer insulating film 1168 is performed. The first interlayer insulating film 1168 is formed to have a two-layer structure. First, a silicon nitride film is formed to a thickness of 50 nm. The silicon nitride film is formed by a plasma CVD method, SiH ₄ is 5 SCCM, NH ₃ is 40 SCCM, N ₂
Is introduced at 100 SCCM and high frequency power of 0.7 Torr and 300 W is applied. Then, a silicon oxide film is introduced into it with 500 SCCM of TEOS and 50 SCCM of O ₂ and a high-frequency power of 1 Torr and 200 W is applied to obtain 950.
The film is formed to a thickness of nm. Therefore, the first interlayer insulating film 1168 having a total thickness of 1 μm is formed.

The heat treatment step must be carried out to activate the impurity elements imparting n-type or p-type added at the respective concentrations. This step may be performed by a thermal annealing method using an electric heating furnace, a laser annealing method using the above-mentioned excimer laser, or a rapid thermal annealing method (RTA method) using a halogen lamp. However, although the laser annealing method can be activated at a low substrate heating temperature, it is difficult to activate even the semiconductor layer below the gate electrode. Therefore, the activation process is performed here by the thermal annealing method. The heat treatment is performed in a nitrogen atmosphere at 300 to 700 ° C., preferably 350 to 550.
C., here 450.degree. C., for 2 hours.

After that, the first interlayer insulating film 1168 was patterned to form contact holes reaching the source region and the drain region of each TFT. And
Source wirings 1169, 1170 and 1171 and drain wirings 1172 and 1173 are formed. Although not shown, in the present embodiment, this wiring is formed of a Ti film of 100 nm and a T film.
An Al film having a thickness of 300 nm and a Ti film having a thickness of 150 nm are used as a wiring having a three-layer structure formed continuously by a sputtering method.

Then, the source wirings 1169, 1170,
1171, the drain wirings 1172 and 1173, and the first interlayer insulating film 1168 so as to cover the passivation film 117.
4 is formed. The passivation film 1174 is a silicon nitride film and is formed to a thickness of 50 nm. Further, a second interlayer insulating film 1175 made of an organic resin is formed with a thickness of about 1000 nm.
To the thickness of. As the organic resin film, polyimide,
Acrylic, polyimide amide, etc. can be used. The advantage of using the organic resin film is that the film formation method is simple, the relative dielectric constant is low, the parasitic capacitance can be reduced, and the flatness is excellent. Note that organic resin films other than those described above can also be used. here,
After coating on the substrate, use a type of polyimide that thermally polymerizes,
It is formed by firing at 300 ° C.

Through the above steps, the gate electrode having the clad structure is formed, and the channel forming region 1149 and the first impurity region 115 are formed in the n-channel TFT of the CMOS circuit.
2, 1153, second impurity regions 1150a, 1150
b, 1151a, 1151b are formed. Here, the second impurity region is a region (GOLD) that overlaps with the gate electrode.
Area) 1150a and 1151a have a length of 1.5 μm,
Region (LDD region) 1150 not overlapping the gate electrode
b and 1151b are formed to a length of 1.5 μm. Then, the first impurity region 1152 serves as a source region and the first impurity region 1153 serves as a drain region.

In the p-channel TFT, a gate electrode having a clad structure is similarly formed, and the channel forming region 115 is formed.
4, third impurity regions 1155a 1155b, 1156
a, 1156b is formed. Then, the third impurity regions 1155a and 1155b serve as source regions, and the third impurity regions 1156a and 1156b serve as drain regions.

Further, the pixel TFT of the pixel matrix circuit
Are channel formation regions 1157 and 1161, first impurity regions 1160 and 1164, and second impurity regions 115.
8, 1159, 1162, 1163 are formed. Here, the second impurity region is a region 115 overlapping with the gate electrode.
Areas 1158b, 1159b, 1162b, 1163 that do not overlap with 8a, 1159a, 1162a, 1163a.
b are formed.

Thus, as shown in FIG. 13, the substrate 110
An active matrix substrate on which a CMOS circuit and a pixel matrix circuit are formed is manufactured. Further, a storage capacitor portion is simultaneously formed on the drain side of the n-channel TFT of the pixel matrix circuit.

[Embodiment 6] In this embodiment, a process of manufacturing an active matrix type liquid crystal display device from the active matrix substrate manufactured in Embodiment 1 will be described.

For the active matrix substrate in the state of FIG. 5, as shown in FIG. 16A, the second interlayer insulating film 3 is formed.
A light shielding film 1601 and a third interlayer insulating film 1602 are formed on 81. The light shielding film 1601 is an organic resin film containing a pigment,
It is preferable to use a metal film such as Ti or Cr. Further, the third interlayer insulating film 1602 is formed of an organic resin film such as polyimide. Then, a contact hole reaching the drain wiring 379 is formed in the third interlayer insulating film 1602 and the second interlayer insulating film 381, and a pixel electrode 1603 is formed. As the pixel electrode 1603, a transparent conductive film may be used in the case of a transmissive liquid crystal display device, and a metal film may be used in the case of a reflective liquid crystal display device. Here, in order to form a transmissive liquid crystal display device, an indium tin oxide (ITO) film is formed to a thickness of 100 nm by a sputtering method, and the pixel electrode 16 is formed.
Form 03.

The etching treatment of the material of the transparent conductive film is performed with a hydrochloric acid-based solution. However, since a residue is easily generated in the etching of ITO, indium oxide-zinc oxide alloy (In ₂ O ₃ —ZnO) is used to improve etching processability.
May be used. The indium oxide-zinc oxide alloy is characterized by excellent surface smoothness and thermal stability as compared with ITO. Similarly, zinc oxide (ZnO) is also a suitable material, and zinc oxide (ZnO: ZnO added with gallium (Ga) in order to further increase visible light transmittance and conductivity).
Ga) or the like can be used.

Next, as shown in FIG. 16B, an alignment film 1604 is formed on the third interlayer insulating film 1602 and the pixel electrode 160.
3 to form. Polyimide resin is often used for the alignment film of a liquid crystal display element. A transparent conductive film 1606 and an alignment film 1607 are formed on the opposite substrate 1605. After the alignment film is formed, a rubbing process is performed so that liquid crystal molecules are aligned in parallel with a certain pretilt angle.

Through the above steps, the pixel matrix circuit, the active matrix substrate on which the CMOS circuit is formed, and the counter substrate are pasted together by a known cell assembling process via a sealing material, a spacer (both not shown), etc. To match. After that, a liquid crystal material 1608 is injected between both substrates,
Completely seal with a sealant (not shown). Thus, the active matrix liquid crystal display device shown in FIG. 16B is completed.

Next, the structure of the active matrix type liquid crystal display device of this embodiment will be described with reference to FIGS. 14 and 15A and 15B. FIG. 14 is a perspective view of the active matrix substrate of this embodiment. The active matrix substrate includes a pixel matrix circuit 1401 formed on the glass substrate 301, a scanning (gate) line driving circuit 1402,
It is composed of a data (source) line drive circuit 1403. The pixel TFT 1400 of the pixel matrix circuit is an n-channel type T
It is an FT, and the drive circuit provided in the periphery is basically configured by a CMOS circuit. The scan (gate) line driver circuit 1402 and the data (source) line driver circuit 1403 are connected to the pixel matrix circuit 1401 by a gate wiring 1502 and a source wiring 1503, respectively.

FIG. 15A shows a pixel matrix circuit 140.
1 is a top view of FIG. 1, and is a top view of almost one pixel. An n-channel TFT, which is a pixel TFT, is provided in the pixel matrix circuit.
Is provided. The gate electrode 1520 formed continuously with the gate wiring 1502 intersects with the semiconductor layer 1501 thereunder via a gate insulating film (not shown). Although not shown, the semiconductor layer includes a source region,
A drain region and a first impurity region are formed. Further, a storage capacitor 1507 is formed on the drain side of the pixel TFT from a semiconductor layer, a gate insulating film, and an electrode formed of the same material as the gate electrode. Then, a capacitor wiring 1521 connected to the storage capacitor 1507 is provided in parallel with the gate wiring 1502. In addition, FIG.
The sectional structure taken along the line AA ′ shown in (A) corresponds to the sectional view of the CMOS circuit shown in FIG.

On the other hand, in the CMOS circuit shown in FIG. 15B, the gate electrode 151 extending from the gate wiring 1515.
3, 1514 intersect with the underlying semiconductor layers 1510, 1512 via a gate insulating film (not shown), respectively. Although not shown, an n-channel type T
The FT semiconductor layer includes a source region, a drain region, and a first region.
Impurity region is formed. In addition, p-channel type T
A source region and a drain region are formed in the semiconductor layer of the FT. As for the positional relationship, the sectional structure along BB 'corresponds to the sectional view of the pixel matrix circuit shown in FIG.

Although the pixel TFT 1400 has a double gate structure in this embodiment, it may have a single gate structure or a triple gate multi-gate structure. The structure of the active matrix substrate of this embodiment is not limited to the structure of this embodiment. The structure of the present invention is characterized by the structure of the gate electrode, the source region of the semiconductor layer provided via the gate insulating film, the drain region, and the other impurity regions. The practitioner may make the appropriate decision.

The active matrix substrate for manufacturing the active matrix type liquid crystal display device shown in this embodiment is not limited to that shown in the first embodiment, and is based on the steps shown in the second to fifth embodiments. Any active matrix substrate can be applied.

[Embodiment 7] In this embodiment, a method of simplifying the gettering step in the method of manufacturing the active matrix substrate shown in Embodiment 5 will be described. First, Example 5
11A, the semiconductor layer 1103 shown in FIG.
Reference numerals 1104 and 1105 are crystalline silicon films produced by using a catalytic element. At this time, since the catalytic element used in the crystallization step remains in the semiconductor layer, it is desirable to perform the gettering step. In Example 5, after the crystalline silicon film was obtained, phosphorus was added to a part of the crystalline silicon film to getter, but here, the gettering step was not performed. The catalyst element is removed from the TFT channel formation region by the method described below.

Here, FIG. 11 (A) to FIG. 12 (C)
The steps up to the above are carried out as they are. Then, the resist masks 1137, 1138, 1139, 1140, 114.
Remove 1.

At this time, phosphorus is added to the first impurity regions 1152, 1153, 1160, 1164 of the n-channel TFT. In addition, the third of the p-channel TFT
Similarly, phosphorus is added to the impurity regions 1155b and 1156b. According to Example 5, the phosphorus concentration at this time is 1 × 10 ²⁰ to 1 × 10 ²¹ atoms / cm ³ .

In this state, the gate insulating film and the gate electrode are covered with the silicon nitride film 1180 as shown in FIG. The silicon nitride film is formed by the plasma CVD method in the range of 10 to 1
The thickness is 00 nm, here 50 nm. A silicon oxynitride film may be used instead of the silicon nitride film.

In the fifth embodiment, the third layer of the gate electrode is M
It is formed by o-W. In addition, Ti, Ta, Mo, W
You may form by. These materials are relatively easily oxidized by heat treatment under atmospheric pressure or while purging nitrogen gas. In such a situation, oxidation can be prevented by coating the surface with silicon nitride.

In this state, 400 to 80 in a nitrogen atmosphere.
A heat treatment step is performed at 0 ° C. for 1 to 24 hours, for example, 600 ° C. for 12 hours. Through this step, the added impurity element imparting n-type and p-type can be activated. Further, the region to which phosphorus is added becomes a gettering site, and the catalyst element remaining after the crystallization step can be segregated. As a result, the catalytic element can be removed from the channel formation region. As a result, the effect of reducing the off current in the completed TFT can be obtained.

After the step of FIG. 22 is completed, the subsequent steps follow the steps of Example 5 to form a first interlayer insulating film, a source wiring and a drain wiring, a passivation film and a second interlayer insulating film, and then, as shown in FIG. An active matrix substrate can be manufactured by forming a state.

[Embodiment 8] In this embodiment, another example of the circuit configuration of the CMOS circuit shown in FIG. 1 will be described with reference to FIG. Note that the terminal parts a, b, c, d in the inverter circuit diagram of FIG. 23A and the top view of the inverter circuit of FIG. 23B correspond to each other.

A top view of the inverter circuit shown in FIG. 23A is shown in FIG. The cross-sectional structure taken along the line AA ′ of FIG. 23B is shown in FIG.
409 and 2409 ′, source wiring 2411 of n-channel TFT, source wiring 2414 of p-channel TFT,
It is composed of a common drain wiring 2413. Here, the gate electrodes 2409 and 2409 ′ are the first layers 2408 and 2408 ′ of the gate electrodes, the second layers 2409 and 2409 ′ of the gate electrodes, and the third layers 241 of the gate electrodes.
0 and 2410 'are integrated.

N-channel TFT of this inverter circuit
A second impurity region 2402 is provided in. Specifically, a second impurity region 2402a that overlaps with the gate electrode 2409 and a second impurity region (LDD region) 2402b that does not overlap are formed. Such a structure may be provided only on the drain side. Moreover, such an impurity region is not provided in the p-channel TFT.

[Embodiment 9] Various liquid crystals other than nematic liquid crystal can be used in the above-described liquid crystal display device of the present invention. For example, 1998, SID, "Characteristics an
d Driving Scheme of Polymer-Stabilized Monostable F
LCD Exhibiting Fast Response Time and High Contrast
Ratio with Gray-Scale Capability "by H. Furue et
al., 1997, SID DIGEST, 841, "A Full-Color Thresh
oldless Antiferroelectric LCDExhibiting Wide Viewi
ng Angle with Fast Response Time "by T. Yoshida et
al., 1996, J. Mater. Chem. 6 (4), 671-673, "Thres
holdless antiferroelectricity in liquid crystals a
nd its application to displays "by S. Inui et al.
Alternatively, the liquid crystal disclosed in US Pat. No. 5,594,569 can be used.

Ferroelectric liquid crystal (FLC) showing isotropic phase-cholesteric phase-chiral smectic C phase transition series
FIG. 24 shows the electro-optical characteristics of a monostable FLC in which a cholesteric phase-chiral smectic C phase transition is applied while a DC voltage is applied, and the cone edge is almost aligned with the rubbing direction. The display mode using the ferroelectric liquid crystal as shown in FIG. 24 is called “Half-V-shaped switching mode”. The vertical axis of the graph shown in FIG. 24 is the transmittance (arbitrary unit), and the horizontal axis is the applied voltage. "Hal
For "f-V switching mode", see Terada et al.
Half-V shaped switching mode FLCD ", 46th
Proceedings of the 12th Joint Lecture Meeting on Applied Physics, 1999 1999
Moon, p. 1316, and Yoshihara et al., "Time-division full-color LCD with ferroelectric liquid crystal," Liquid Crystal, Volume 3, No. 19,
Details on page 0.

As shown in FIG. 24, it can be seen that use of such a ferroelectric mixed liquid crystal enables low voltage driving and gradation display. The liquid crystal display device of the present invention,
A ferroelectric liquid crystal exhibiting such electro-optical characteristics can also be used.

A liquid crystal exhibiting an antiferroelectric phase in a certain temperature range is called an antiferroelectric liquid crystal (AFLC). Among mixed liquid crystals having antiferroelectric liquid crystals, there is a so-called thresholdless antiferroelectric mixed liquid crystal that exhibits electro-optical response characteristics in which the transmittance continuously changes with respect to an electric field. This thresholdless antiferroelectric mixed liquid crystal has a so-called V-shaped electro-optical response characteristic, and its driving voltage is about ± 2.5 V.
Some (about 1 μm to 2 μm in cell thickness) have been found.

Generally, the thresholdless antiferroelectric mixed liquid crystal has a large spontaneous polarization and the liquid crystal itself has a high dielectric constant. Therefore, when the thresholdless antiferroelectric mixed liquid crystal is used in a liquid crystal display device, a pixel requires a relatively large storage capacitance. Therefore, it is preferable to use a thresholdless antiferroelectric mixed liquid crystal having a small spontaneous polarization.

By using such a thresholdless antiferroelectric mixed liquid crystal in the liquid crystal display device of the present invention, low voltage driving is realized, and low power consumption is realized.

[Embodiment 10] The active matrix substrate, the liquid crystal display device and the organic EL display device manufactured by implementing the present invention can be used for various electro-optical devices. Then, the present invention can be applied to all electronic devices in which such an electro-optical device is incorporated as a display unit. Examples of the electronic device include a mobile phone, a video camera, a personal digital assistant, a goggle type display, a recording medium player, a mobile book, a personal computer, a digital camera, and a projector. Examples of these are shown in FIGS. 25 and 26.

FIG. 25A shows a mobile phone, which is a main body 90.
01, voice output unit 9002, voice input unit 9003, display device 9004, operation switch 9005, antenna 900
It is composed of 6. The present invention has a voice output unit 900.
2, and can be applied to a display device 9004 including a voice input portion 9003 and an active matrix substrate.

FIG. 25B shows a video camera, which includes a main body 9101, a display device 9102, a voice input portion 9103, operation switches 9104, a battery 9105, and an image receiving portion 91.
It is composed of 06. The present invention can be applied to the display device 9102 and other signal control circuits.

FIG. 25C shows a portable information terminal which is composed of a main body 9201, an image input portion 9202, an image receiving portion 9203, operation switches 9204, and a display device 9205. The present invention can be applied to the display device 9205 and other signal control circuits.

FIG. 25D shows a goggle type display, which includes a main body 9301, a display device 9302, an arm portion 93.
It is composed of 03. The present invention can be applied to the display device 9302. Although not shown, it can also be used for other signal control circuits.

FIG. 25 (E) shows a player using a recording medium (hereinafter referred to as a recording medium) in which a program is recorded, which includes a main body 9401, a display device 9402, and a speaker section 9.
403, a recording medium 9404, and an operation switch 9405. The recording medium is a DVD (Digital Versati
le Disc) or compact disc (CD),
It is possible to play music programs, display images, display information via a video game (or video game) or the Internet. The present invention can be preferably used for the display device 9402 and other signal control circuits.

FIG. 25F shows a portable book, which is a main body 95.
01, display devices 9502 and 9503, storage medium 950
4, the operation switch 9505 and the antenna 9506, and displays the data stored in the mini disk (MD) or DVD or the data received by the antenna. The display devices 9502 and 9503 are direct-view display devices, and the present invention can be applied to this.

FIG. 25G shows a personal computer, which is composed of a main body 9601 provided with a microprocessor and a memory, an image input portion 9602, a display device 9603, and a keyboard 9604. The present invention is a display device 96
03 and other signal processing circuits can be formed.

FIG. 26H shows a digital camera which is composed of a main body 9701, a display device 9702, an eyepiece section 9703, operation switches 9704, and an image receiving section (not shown). The present invention can be applied to the display device 9702 and other signal control circuits.

FIG. 26A shows a front type projector, which comprises a light source optical system, a display device 2601, and a screen 2602. The present invention can be applied to a display device and other signal control circuits. FIG. 26B shows a rear type projector including a main body 2701, a light source optical system and a display device 2702, a mirror 2703, and a screen 2704. The present invention can be applied to a display device and other signal control circuits.

26C, the light source optical system and the display device 26 shown in FIGS. 26A and 26B.
An example of the structure of 01 and 2702 is shown. The light source optical system and display devices 2601 and 2702 include a light source optical system 2801, mirrors 2802, 2804 to 2806, a dichroic mirror 2803, a beam splitter 2807, a liquid crystal display device 2808, a retardation plate 2809, and a projection optical system 2810.
Composed of. The projection optical system 2810 is composed of a plurality of optical lenses. In FIG. 26C, a liquid crystal display device 2808
Although an example of a three-plate type using three is shown, the invention is not limited to such a system, and a single-plate type optical system may be used. 26C, an optical lens, a film having a polarizing function, a film for adjusting the phase, an IR film, or the like may be provided in the optical path indicated by an arrow in FIG. Further, FIG. 26D shows the light source optical system 2 in FIG.
It is the figure which showed an example of the structure of 801. In this embodiment,
The light source optical system 2801 includes a reflector 2811 and a light source 28.
12, lens arrays 2813 and 2814, a polarization conversion element 2815, and a condenser lens 2816. Incidentally, FIG.
The light source optical system shown in FIG. 6D is an example and is not limited to the illustrated configuration.

Although not shown here, the present invention can also be applied to a navigation system, an image sensor reading circuit, and the like.
As described above, the applicable range of the present invention is extremely wide, and the present invention can be applied to electronic devices in all fields. Also,
The electronic device of the present example can be realized by using the embodiment and the configuration including any combination of the examples 1 to 9 and the example 11.

[Embodiment 11] In this embodiment, an example of manufacturing an EL (electroluminescence) display device using the present invention will be described.

FIG. 27A is a top view of an EL display device using the present invention. In FIG. 27A, 4010
Is a substrate, 4011 is a pixel portion, 4012 is a source side driver circuit, and 4013 is a gate side driver circuit. Each driver circuit is connected to an FPC 4017 through wirings 4014 to 4016.
And connected to an external device.

At this time, at least the pixel portion, preferably the drive circuit and the pixel portion are surrounded so as to cover the cover material 600.
0, sealing material (also called housing material) 7000,
A sealing material (second sealing material) 7001 is provided.

FIG. 27B shows a cross-sectional structure of the EL display device of this embodiment, which includes a substrate 4010 and a base film 4021.
A driver circuit TFT (however, here, a CMOS circuit in which an n-channel TFT and a p-channel TFT are combined is shown) 4022 and a pixel portion TFT 40.
23 (However, in this case, the TF that controls the current to the EL element
Only T is shown. ) Has been formed.

The invention of the present application is to provide a TFT 4022 for a driving circuit,
It can be used for the TF4023 for the pixel portion.

A TFT 402 for a drive circuit using the present invention
2. When the pixel part TFT 4023 is completed, the pixel part T is formed on the interlayer insulating film (planarizing film) 4026 made of a resin material.
A pixel electrode 4027 made of a transparent conductive film that is electrically connected to the drain of the FT 4023 is formed. Pixel electrode 4027
When is a transparent conductive film, the pixel part TFT is p
It is preferable to use a channel type TFT. As the transparent conductive film, a compound of indium oxide and tin oxide (IT
(Called O) or a compound of indium oxide and zinc oxide can be used. Then, the pixel electrode 4027
Then, an insulating film 4028 is formed, and the pixel electrode 40
An opening is formed on 27.

Next, an EL layer 4029 is formed. The EL layer 4029 is a known EL material (hole injection layer, hole transport layer,
A light emitting layer, an electron transporting layer or an electron injecting layer) may be freely combined to form a laminated structure or a single layer structure. A publicly known technique may be used to determine the structure. Also, E
The L material includes a low molecular weight material and a high molecular weight (polymer) material. The vapor deposition method is used when a low molecular weight material is used, but the spin coating method is used when a high molecular weight material is used.
A simple method such as a printing method or an inkjet method can be used.

In this embodiment, the EL layer is formed by a vapor deposition method using a shadow mask. Color display can be performed by forming light emitting layers (red light emitting layer, green light emitting layer, and blue light emitting layer) capable of emitting light with different wavelengths for each pixel using a shadow mask. In addition, a color conversion layer (CC
There is a method in which M) and a color filter are combined, and a method in which a white light emitting layer and a color filter are combined, but any method may be used. Of course, an EL display device that emits monochromatic light can also be used.

After forming the EL layer 4029, the cathode 4030 is formed thereon. Cathode 4030 and EL layer 4029
It is desirable that the water and oxygen existing at the interface of are removed as much as possible. Therefore, in vacuum, the EL layer 4029 and the cathode 40
It is necessary to continuously devise 30 or to form the EL layer 4029 in an inert atmosphere and form the cathode 4030 without exposing to the atmosphere. In the present embodiment, the above-described film formation is possible by using a multi-chamber type (cluster tool type) film forming apparatus.

In this embodiment, as the cathode 4030,
A laminated structure of a LiF (lithium fluoride) film and an Al (aluminum) film is used. Specifically, a 1-nm-thick LiF (lithium fluoride) film is formed over the EL layer 4029 by an evaporation method, and a 300-nm-thick aluminum film is formed thereover. Of course, a MgAg electrode which is a known cathode material may be used. The cathode 4030 is connected to the wiring 4016 in the area indicated by 4031. The wiring 4016 is a power supply line for applying a predetermined voltage to the cathode 4030, and the FPC 401 is provided through the conductive paste material 4032.
Connected to 7.

Cathode 40 in the region shown at 4031
In order to electrically connect 30 and the wiring 4016, it is necessary to form a contact hole in the interlayer insulating film 4026 and the insulating film 4028. These are when the interlayer insulating film 4026 is etched (when the pixel electrode contact holes are formed).
It may be formed when the insulating film 4028 and the insulating film 4028 are etched (when the opening is formed before the EL layer is formed). In addition, the insulating film 40
When etching 28, the interlayer insulating film 4026 may be collectively etched. In this case, the interlayer insulating film 40
If 26 and the insulating film 4028 are made of the same resin material, the contact hole can have a good shape.

[0207] The passivation film 6003 and the filler 600 are formed so as to cover the surface of the EL element thus formed.
4, cover material 6000 is formed.

Further, a sealing material is provided inside the cover material 7000 and the substrate 4010 so as to surround the EL element portion, and a sealing material (second sealing material) 7001 is formed outside the sealing material 7000.

At this time, the filling material 6004 also functions as an adhesive for bonding the cover material 6000.
As the filler 6004, PVC (polyvinyl chloride), epoxy resin, silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.

A spacer may be included in the filler 6004. At this time, the spacer may be made of a granular material such as BaO so that the spacer itself has a hygroscopic property.

When the spacer is provided, the passivation film 6003 can relieve the spacer pressure.
In addition to the passivation film, a resin film that relieves the spacer pressure may be provided.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless plate, an FRP (Fiber) is used.
rglass-Reinforced Plastic
s) board, PVF (polyvinyl fluoride) film,
A mylar film, a polyester film or an acrylic film can be used. Note that the filler 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which an aluminum foil having a thickness of several tens of μm is sandwiched between PVF films or Mylar films.

However, the cover material 6000 needs to have translucency depending on the light emitting direction (light emitting direction) from the EL element.

The wiring 4016 is made of the sealing material 700.
0 and the gap between the sealing material 7001 and the substrate 4010, and is electrically connected to the FPC 4017. Note that although the wiring 4016 is described here, another wiring 401
Similarly, 4, 4015 also pass under the sealing material 7000 and the sealing material 7001 and are electrically connected to the FPC 4017.

[Embodiment 12] In this embodiment, an example in which an EL display device of a mode different from that of Embodiment 11 is manufactured by using the present invention will be described with reference to FIGS. 28A and 28B. The same numbers as those in FIGS. 27A and 27B indicate the same portions, and thus the description thereof will be omitted.

FIG. 28A is a top view of the EL display device of this embodiment, and FIG. 28B is a sectional view taken along the line AA ′ in FIG. 28A.

According to the eleventh embodiment, the passivation film 6003 is formed so as to cover the surface of the EL element.

Further, the filler 6 is provided so as to cover the EL element.
004 is provided. This filling material 6004 is a cover material 60.
It also functions as an adhesive for bonding 00. As the filler 6004, PVC (polyvinyl chloride),
Epoxy resin, silicone resin, PVB (polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. It is preferable to provide a desiccant inside the filler 6004 because the moisture absorption effect can be maintained.

A spacer may be included in the filler 6004. At this time, the spacer may be made of a granular material such as BaO so that the spacer itself has a hygroscopic property.

When the spacer is provided, the passivation film 6003 can relieve the spacer pressure.
In addition to the passivation film, a resin film that relieves the spacer pressure may be provided.

Further, as the cover material 6000, a glass plate, an aluminum plate, a stainless plate, an FRP (Fiber) is used.
rglass-Reinforced Plastic
s) board, PVF (polyvinyl fluoride) film,
A mylar film, a polyester film or an acrylic film can be used. Note that the filler 600
When PVB or EVA is used as 4, it is preferable to use a sheet having a structure in which an aluminum foil having a thickness of several tens of μm is sandwiched between PVF films or Mylar films.

However, the cover material 6000 needs to have a light-transmitting property depending on the light emitting direction (light emitting direction) from the EL element.

Next, the cover material 6 is formed by using the filler 6004.
After bonding 000, the side surface (exposed surface) of the filler 6004
The frame member 6001 is attached so as to cover the. Frame material 6001 is a sealing material (functions as an adhesive)
Bonded by 6002. At this time, it is preferable to use a photocurable resin as the sealing material 6002, but a thermosetting resin may be used if the heat resistance of the EL layer allows. Note that the sealing material 6002 is preferably a material which does not allow moisture and oxygen to pass therethrough as much as possible. Further, a desiccant may be added inside the sealing material 6002.

The wiring 4016 is made of the sealing material 600.
2 is electrically connected to the FPC 4017 through a gap between the substrate 2 and the substrate 4010. Note that although the wiring 4016 is described here, the other wirings 4014 and 4015 also pass under the sealing material 6002 and are electrically connected to the FPC 4017 in a similar manner.

[Embodiment 13] In this embodiment, a detailed sectional structure of a pixel portion of an EL display device is shown in FIG. 29, and a top surface structure thereof is shown in FIG.
A circuit diagram is shown in FIG. 29 and 3
0 (A) and FIG. 30 (B) use the same code, so they may be referred to each other.

In FIG. 29, the switching TFT 3002 provided on the substrate 3001 is formed by using the n-channel TFT of the present invention (see Examples 1 to 8). Although a double gate structure is used in this embodiment, there is no significant difference in structure and manufacturing process, and a description thereof will be omitted. However, the double gate structure has an advantage in that two TFTs are substantially connected in series and the off-current value can be reduced. Although a double gate structure is used in this embodiment, a single gate structure may be used, a triple gate structure or a multi-gate structure having more gates may be used. Alternatively, the p-channel TFT of the present invention may be used for the formation.

The current control TFT 3003 is formed by using the n-channel type TFT of the present invention. At this time, the drain wiring 30 of the switching TFT 3002
Reference numeral 35 is electrically connected to the gate electrode 3037 of the current controlling TFT by the wiring 3036. Also, 303
The wiring indicated by 8 is a gate wiring that electrically connects the gate electrodes 3039a and 3039b of the switching TFT 3002.

At this time, it is very important that the current controlling TFT 3003 has the structure of the present invention. Since the current control TFT is an element for controlling the amount of current flowing through the EL element, a large amount of current flows, and there is a high risk of deterioration due to heat or deterioration due to hot carriers. Therefore, the structure of the present invention in which the GOLD region (second impurity region) is provided on the drain side of the current control TFT so as to overlap the gate electrode via the gate insulating film is extremely effective.

In the present embodiment, the current controlling TFT 30 is used.
03 is shown as a single gate structure, a plurality of T
A multi-gate structure in which FTs are connected in series may be used.
Furthermore, a structure may be adopted in which a plurality of TFTs are connected in parallel and the channel formation region is substantially divided into a plurality of portions so that heat radiation can be performed with high efficiency. Such a structure is effective as a measure against deterioration due to heat.

Further, as shown in FIG. 30A, the wiring to be the gate electrode 3037 of the current control TFT 3003 is in the region 3004, and the current control TFT 3003 is provided.
Of the drain wiring 3040 and the drain wiring 3040 of FIG. At this time, a capacitor is formed in the area indicated by 3004. This capacitor 3004 is used for the current control TFT 30.
03 functions as a capacitor for holding the voltage applied to the gate. Note that the drain wiring 3040 is connected to the current supply line (power supply line) 3006, and a constant voltage is always applied.

The first passivation film 3 is formed on the switching TFT 3002 and the current control TFT 3003.
041 is provided, and a flattening film 3042 made of a resin insulating film is formed thereon. TF using the flattening film 3042
It is very important to flatten the step due to T. Since the EL layer formed later is very thin, the presence of the step may cause defective light emission. Therefore, E
It is desirable to flatten the L layer before forming the pixel electrode so that the L layer can be formed as flat as possible.

Reference numeral 3043 denotes a pixel electrode (cathode of EL element) made of a conductive film having high reflectivity, which is a current control TF.
It is electrically connected to the drain of T3003. In this case, an n-channel TF is used as the current control TFT.
It is preferable to use T. As the pixel electrode 3043, it is preferable to use a low resistance conductive film such as an aluminum alloy film, a copper alloy film, or a silver alloy film, or a laminated film thereof. Of course, a laminated structure with another conductive film may be used.

Further, the light emitting layer 45 is formed in the groove (corresponding to a pixel) formed by the banks 44a and 44b formed of an insulating film (preferably resin). Although only one pixel is shown here, R (red), G (green),
A light emitting layer corresponding to each color of B (blue) may be separately formed.
A π-conjugated polymer material is used as the organic EL material for the light emitting layer. Typical polymer materials include polyparaphenylene vinylene (PPV) materials, polyvinylcarbazole (PVK) materials, polyfluorene materials, and the like.

There are various types of PPV organic EL materials. For example, “H. Shenk, H. Becker, O. Ge
lsen, E.Kluge, W.Kreuder, and H.Spreitzer, “Polymers
forLight Emitting Diodes ”, Euro Display, Proceeding
s, 1999, p.33-37 "and Japanese Patent Application Laid-Open No. 10-92576.

As specific light emitting layers, cyanopolyphenylene vinylene is used for the red light emitting layer, polyphenylene vinylene is used for the green light emitting layer, and polyphenylene vinylene or polyalkylphenylene is used for the blue light emitting layer. Good. Film thickness is 30-150n
It may be set to m (preferably 40 to 100 nm).

However, the above example is an example of an organic EL material that can be used as a light emitting layer, and it is not necessary to limit to this. An EL layer (a layer for emitting light and moving carriers therefor) may be formed by freely combining the light emitting layer, the charge transport layer, or the charge injection layer.

For example, although the polymer material is used for the light emitting layer in this embodiment, a low molecular organic EL material may be used. Further, it is also possible to use an inorganic material such as silicon carbide for the charge transport layer and the charge injection layer. Known materials can be used as these organic EL materials and inorganic materials.

In this embodiment, PED is formed on the light emitting layer 3045.
EL having a laminated structure provided with a hole injection layer 3046 made of OT (polythiophene) or PAni (polyaniline)
There are layers. Then, an anode 47 made of a transparent conductive film is provided on the hole injection layer 3046. In the case of this embodiment, since the light generated in the light emitting layer 3045 is emitted toward the upper surface side (upward of the TFT), the anode must be transparent. As the transparent conductive film, a compound of indium oxide and tin oxide or a compound of indium oxide and zinc oxide can be used, but it is possible because it is formed after forming a light-emitting layer or a hole injection layer having low heat resistance. Those capable of forming a film at a temperature as low as possible are preferable.

When the anode 3047 is formed, the EL element 3005 is completed. The EL element 30 referred to here
Reference numeral 05 denotes a pixel electrode (cathode) 3043, a light emitting layer 3045,
This refers to a capacitor formed of the hole injection layer 3046 and the anode 3047. As shown in FIG. 30A, the pixel electrode 30
Since 43 is almost the same as the pixel area, the entire pixel is EL
Functions as an element. Therefore, the utilization efficiency of light emission is very high, and a bright image can be displayed.

By the way, in this embodiment, a second passivation film 3048 is further provided on the anode 3047. As the second passivation film 3048, a silicon nitride film or a silicon nitride oxide film is preferable. This purpose is to shut off the EL element from the outside, and has both the meaning of preventing deterioration of the organic EL material due to oxidation and the meaning of suppressing degassing from the organic EL material. This improves the reliability of the EL display device.

As described above, the EL display panel of the present invention has the pixel portion composed of the pixels having the structure as shown in FIG. 29, the switching TFT having a sufficiently low off-current value, and the current control strong against hot carrier injection. And TFT. Therefore, an EL display panel having high reliability and capable of displaying a good image can be obtained.

The constitution of this embodiment can be implemented by freely combining it with the constitutions of Embodiments 1-8. In addition, as the display unit of the electronic device of the tenth embodiment,
It is effective to use the L display device.

[Embodiment 14] In this embodiment, a structure obtained by inverting the structure of the EL element 3005 in the pixel portion shown in Embodiment 13 will be described. FIG. 31 is used for the description. The difference from the structure of FIG. 29 is only the EL element portion and the current control TFT, and therefore the other description will be omitted.

In FIG. 31, the current control TFT 310 is used.
3 is formed using the p-channel TFT of the present invention. Refer to Examples 1 to 8 for the manufacturing process.

In this embodiment, the pixel electrode (anode) 3050 is used.
Is used as a transparent conductive film. Specifically, a conductive film made of a compound of indium oxide and zinc oxide is used. Needless to say, a conductive film made of a compound of indium oxide and tin oxide may be used.

Then, a bank 3051a made of an insulating film,
After forming 3051b, the light emitting layer 52 made of polyvinylcarbazole is formed by solution coating. An electron injection layer 3053 made of potassium acetylacetonate (denoted as acacK) and a cathode 3054 made of an aluminum alloy are formed thereon. In this case, the cathode 305
4 also functions as a passivation film. Thus E
The L element 3101 is formed.

In the case of this embodiment, the light generated in the light emitting layer 3052 is radiated toward the substrate on which the TFT is formed as shown by the arrow.

The constitution of this embodiment can be combined with any constitution of Embodiments 1 to 8 in any desired manner.
Moreover, it is effective to use the EL display panel of the present embodiment as the display unit of the electronic device of the tenth embodiment.

[Embodiment 15] In this embodiment, FIG.
32A to 32C show examples of the case where the pixel has a structure different from that of the circuit diagram shown in FIG. In this embodiment, 3201 is a source wiring of the switching TFT 3202, 3203 is a gate wiring of the switching TFT 3202, 3204 is a current control TFT, 3205 is a capacitor, 3206 and 3208 are current supply lines, and 320.
7 is an EL element.

FIG. 32A shows an example in which the current supply line 3206 is shared between two pixels. That is, the feature is that the two pixels are formed so as to be line-symmetric with respect to the current supply line 3206. In this case, since the number of power supply lines can be reduced, the pixel portion can be made even finer.

Further, FIG. 32B shows the current supply line 320.
8 is an example in which 8 is provided in parallel with the gate wiring 3203. Note that in FIG. 32B, the current supply line 3208 and the gate wiring 3203 are provided so as not to overlap with each other; however, if the wirings are formed in different layers,
Alternatively, the insulating films may be provided so as to overlap with each other. In this case, since the power supply line 3208 and the gate wiring 3203 can share the exclusive area, the pixel portion can have higher definition.

32C, the current supply line 3208 is connected to the gate wiring 3203 in the same manner as the structure of FIG.
It is characterized in that it is provided in parallel with a 3230b and that two pixels are formed so as to be line-symmetrical with respect to the current supply line 3208. It is also effective to provide the current supply line 3208 so as to overlap with either one of the gate wirings 3203a and 3230b. In this case, since the number of power supply lines can be reduced, the pixel portion can be made even finer.

The constitution of this embodiment can be combined with any constitution of Embodiments 1 to 8 in any desired manner.
Moreover, it is effective to use the EL display device having the pixel structure of the present embodiment as the display unit of the electronic device of the tenth embodiment.

Example 16 FIG. 30 shown in Example 13
In (A) and (B), the capacitor 3004 is provided to hold the voltage applied to the gate of the current control TFT 3003, but the capacitor 3004 can be omitted. In the case of Example 13, TF for current control
Since the n-channel TFT of the present invention as shown in Examples 1 to 8 is used as T3003, it has a GOLD region (second impurity region) provided so as to overlap with the gate electrode through the gate insulating film. is doing. A parasitic capacitance, which is generally called a gate capacitance, is formed in this overlapping region. In this embodiment, this parasitic capacitance is used as the capacitor 3
It is characterized in that it is positively used instead of 004.

Since the capacitance of the parasitic capacitance changes depending on the area where the gate electrode and the GOLD region overlap, the GOL included in the overlap region is formed.
It depends on the length of the D area.

Further, FIG. 32A shown in the fifteenth embodiment,
Similarly, in the structures of (B) and (C), the capacitor 3
It is possible to omit 205.

The constitution of this embodiment can be implemented by freely combining with the constitution of Embodiments 1-8.
Further, it is effective to use the EL display device having the pixel structure of this embodiment as the display unit of the electronic device of the tenth embodiment.

[0258]

By implementing the present invention, it is possible to obtain a stable operation even when the gate voltage of 15 to 20 V is applied to the n-channel TFT of the pixel matrix circuit to drive it. As a result, a CMO made of crystalline TFT
The reliability of the semiconductor device including the S circuit, more specifically, the pixel matrix circuit of the liquid crystal display device and the drive circuit provided around the pixel matrix circuit, and the liquid crystal display device which can be used for a long time can be obtained. .

Further, according to the present invention, an n-channel TF
In the second impurity region formed between the T channel formation region and the drain region, the length of the region (LDD region) where the second impurity region does not overlap with the region (GOLD region) overlapping with the gate electrode is defined as It is possible to make them separately easily. Specifically, depending on the driving voltage of the TFT, the second
It is also possible to determine the lengths of the region (LDD region) where the impurity region of (1) overlaps the gate electrode (LDD region) and the region where the impurity region does not overlap (LDD region). It is possible to manufacture TFTs corresponding to respective driving voltages in the same process.

Further, such a feature of the present invention is extremely suitable for the active matrix type liquid crystal display device in which the driving voltage and the required TFT characteristics are different between the pixel matrix circuit and the driver circuit.

[Brief description of drawings]

FIG. 1 is a cross-sectional view of a TFT of this embodiment.

FIG. 2 is a diagram illustrating a positional relationship between a gate electrode and a second impurity region.

3A to 3C are cross-sectional views illustrating a manufacturing process of a TFT.

FIG. 4 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 5 is a cross-sectional view showing a manufacturing process of a TFT.

6A to 6C are cross-sectional views illustrating a manufacturing process of a TFT.

7A to 7C are cross-sectional views illustrating a manufacturing process of a TFT.

FIG. 8 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 9 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 10 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 11 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 12 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 13 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 14 is a perspective view of an active matrix substrate.

FIG. 15 is a top view of an active matrix circuit and a CMOS circuit.

16A to 16C are cross-sectional views illustrating a manufacturing process of a liquid crystal display device.

FIG. 17 is a diagram showing a structure of a gate electrode.

FIG. 18 is a diagram illustrating a structure and electrical characteristics of a TFT.

FIG. 19 is a diagram showing a process of manufacturing a crystalline silicon film.

FIG. 20 is a diagram showing a process of manufacturing a crystalline silicon film.

FIG. 21 is a diagram showing a process of manufacturing a crystalline silicon film.

FIG. 22 is a cross-sectional view showing a manufacturing process of a TFT.

FIG. 23 is an inverter circuit diagram, a top view, and a cross-sectional structure diagram.

FIG. 24 is a diagram showing a light transmittance characteristic of a ferroelectric mixed liquid crystal.

FIG. 25 illustrates an example of a semiconductor device.

FIG. 26 is a diagram illustrating a configuration of a projector.

27A and 27B are a top view and a cross-sectional view of an active matrix EL display device.

28A and 28B are a top view and a cross-sectional view of an active matrix EL display device.

FIG. 29 is a cross-sectional view of a pixel portion of an active matrix EL display device.

30A and 30B are a top view and a circuit diagram of a pixel portion of an active matrix EL display device.

FIG. 31 is a cross-sectional view of a pixel portion of an active matrix EL display device.

FIG. 32 is a circuit diagram of a pixel portion of an active matrix EL display device.

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H05B 33/14 H01L 29/78 627G 617L 627F 617K F term (reference) 2H092 JA25 JA28 JA36 JA40 JB56 JB64 JB66 JB69 KA04 KB25 MA29 NA22 3K007 AB11 BA06 DB03 FA01 5F052 AA02 AA03 AA17 BA02 BA07 BB01 BB07 DA01 DA02 DA03 DA05 DB02 DB03 DB04 DB07 EA12 EA15 EA16 FA01 FA06 JA04 5F110 AA06 AA14 AA16 BB02 BB04 CC02 DD01 DD02 DD03 DD05 DD12 DD13 DD14 DD15 DD17 EE01 EE02 EE03 EE04 EE06 EE08 EE15 EE22 EE28 EE44 FF02 FF03 FF04 FF30 GG01 GG02 GG03 GG04 GG12 GG13 GG25 GG28 GG32. QQ09 QQ11 QQ28

Claims (13)

[Claims] 1. A crystalline silicon film is formed using a catalytic element on a substrate having an insulating surface, a gate insulating film is formed in contact with the crystalline silicon film, and a gate insulating film is formed on the gate insulating film. A first conductive layer and a second conductive layer are sequentially formed, a part of the second conductive layer is etched to form an island-shaped second conductive layer, and one conductivity type impurity element is added to the island-shaped first conductive layer. The second conductive layer is used as a mask to add to the crystalline silicon film, the third conductive layer is formed in contact with the first conductive layer and the second layer of the gate electrode, and the third conductive layer and the third conductive layer are formed. Part of the first conductive layer is etched to form an island-shaped third conductive layer and an island-shaped first conductive layer, and the one conductivity type impurity element is added to a selected region of the crystalline silicon film. A method for manufacturing a semiconductor device, characterized in that heat treatment is performed after addition to the semiconductor device. 2. A first crystalline silicon film and a second crystalline silicon film are respectively formed on a substrate having an insulating surface by using a catalytic element, and the first crystalline silicon film and the second crystalline silicon film are formed. Forming a gate insulating film on the crystalline silicon film, sequentially forming a first conductive layer and a second conductive layer on the gate insulating film, and etching a part of the second conductive layer to form islands. A second conductive layer is formed, an impurity element of one conductivity type is added to a selected region of the first crystalline silicon film, and the first conductive layer and the second conductive layer are in contact with each other, Forming a third conductive layer, etching a part of the third conductive layer and the first conductive layer to form an island-shaped third conductive layer and an island-shaped first conductive layer, respectively. -Type impurity element is added to a part of the selected region of the first crystalline silicon film, An impurity element having a conductivity type opposite to the conductivity type is added to the second
A method for manufacturing a semiconductor device, comprising: performing heat treatment after adding the crystalline silicon film to a selected region of the crystalline silicon film. 3. A first crystalline silicon film and a second crystalline silicon film are formed on a substrate having an insulating surface by using a catalytic element, and the first crystalline silicon film and the second crystalline silicon film are formed. Forming a gate insulating film on the crystalline silicon film, sequentially forming a first conductive layer and a second conductive layer on the gate insulating film, and etching a part of the second conductive layer to form islands. A second conductive layer in the form of a stripe, an impurity element of one conductivity type is added to a selected region of the first crystalline silicon film, and the first conductive layer and the second conductive layer are in contact with each other, Forming a third conductive layer, etching a part of the third conductive layer and the first conductive layer to form an island-shaped third conductive layer and an island-shaped first conductive layer, respectively. A second type impurity element and a part of the selected region of the first crystalline silicon film and the second crystalline silicon film. An impurity element having a conductivity type opposite to the one conductivity type is added to a selected region of the crystalline silicon film,
A method for manufacturing a semiconductor device, which comprises performing heat treatment after adding to a region including a selected region of the crystalline silicon film of. 4. A first crystalline silicon film and a second crystalline silicon film are respectively formed on a substrate having an insulating surface by using a catalytic element, and the first crystalline silicon film and the second crystalline silicon film are formed. Forming a gate insulating film on the crystalline silicon film, sequentially forming a first conductive layer and a second conductive layer on the gate insulating film, and etching a part of the second conductive layer to form islands. A second conductive layer is formed, an impurity element of one conductivity type is added to a selected region of the first crystalline silicon film, and an impurity element of a conductivity type opposite to the one conductivity type is added. Addition to a selected region of the second crystalline silicon film, contacting the first conductive layer and the second layer of the gate electrode to form a third conductive layer, the third conductive layer and the third conductive layer Part of the first conductive layer is etched to form an island-shaped third conductive layer and an island-shaped first conductive layer, respectively. And adding the one conductivity type impurity element to a part of the selected region of the first crystalline silicon film, and then performing heat treatment. 5. A first crystalline silicon film and a second crystalline silicon film are respectively formed on a substrate having an insulating surface by using a catalytic element, and the first crystalline silicon film and the second crystalline silicon film are formed. Forming a gate insulating film on the crystalline silicon film, sequentially forming a first conductive layer and a second conductive layer on the gate insulating film, and etching a part of the second conductive layer to form islands. A second conductive layer is formed, an impurity element of one conductivity type is added to a selected region of the first crystalline silicon film, and an impurity element of a conductivity type opposite to the one conductivity type is added. Addition to a selected region of the second crystalline silicon film, contacting the first conductive layer and the second layer of the gate electrode to form a third conductive layer, the third conductive layer and the third conductive layer Part of the first conductive layer is etched to form an island-shaped third conductive layer and an island-shaped first conductive layer, respectively. The impurity element of one conductivity type is formed in a part of the selected region of the first crystalline silicon film and in a part of the selected region of the second crystalline silicon film. A method for manufacturing a semiconductor device, characterized in that heat treatment is performed after addition to the semiconductor device. 6. The method for manufacturing a semiconductor device according to claim 1, wherein an interlayer insulating film is formed before the heat treatment. 7. The method for manufacturing a semiconductor device according to claim 6, wherein the interlayer insulating film is formed using a silicon nitride film or a silicon oxynitride film. 8. The heat treatment according to claim 1, wherein the heat treatment is 400 to 800 in a nitrogen atmosphere.
A method for manufacturing a semiconductor device, which is performed at a temperature of 1 to 24 hours. 9. The gate electrode of the semiconductor device according to claim 1, wherein the gate electrode of the semiconductor device is the island-shaped first electrode.
A method of manufacturing a semiconductor device, comprising a conductive layer or the island-shaped third conductive layer. 10. The island-shaped first conductive layer and the island-shaped third conductive layer according to claim 1, wherein the island-shaped third conductive layer is selected from silicon, titanium, tantalum, tungsten, and molybdenum. 1. A method for manufacturing a semiconductor device, which is characterized in that it is formed of one or more kinds of the selected elements or a compound containing the elements. 11. The island-shaped second conductive layer according to claim 1, wherein the island-shaped second conductive layer contains one or more elements selected from aluminum and copper, or contains the element as a main component. Forming a semiconductor device. 12. The method for manufacturing a semiconductor device according to claim 1, wherein the semiconductor device is a display device using an organic electroluminescent material. 13. The semiconductor device according to claim 1, wherein the semiconductor device is a personal computer, a video camera, a portable information terminal, a digital camera,
A method for manufacturing a semiconductor device, which is one selected from a digital video disc player, a goggle type display, and a projector.