JP2002134553A - Connecting structure of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the degradation of electrical characteristics due to a coupling capacitance between adjacent connecting bumps without modification of a semiconductor device size. SOLUTION: In order to solve the above problem, in the bump connecting structure of this invention in which the electrode pitch and the electrode size of the semiconductor device are different from the electrode pitch and the electrode size of a printed circuit board (PCB), and the electrode pitch and the electrode size of the semiconductor device are smaller than the electrode pitch and the electrode size of the PCB, if a centerline between adjacent electrodes on the semiconductor device is overlapped with a centerline between adjacent electrodes on the PCB, each electrode on the PCB is defined as a power supply electrode and a ground electrode, and if a centerline of an electrode on the PCB is overlapped with a centerline of a signal electrode on the semiconductor device, the electrode on the PCB is defined as a signal electrode, and each electrode is connected between the semiconductor device and the PCB through a bump which is arranged in each center of the power supply electrode, the ground electrode, and the signal electrode respectively on the semiconductor device.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connection structure between electrodes by bumps between a semiconductor integrated circuit and a wiring board on which the semiconductor integrated circuit is mounted.

[0002]

2. Description of the Related Art In recent years, semiconductor devices have been reduced in size and density, and the electrode pitch has also been reduced. When the signal electrode pitch becomes narrow, the coupling capacitance between the bumps arranged on the electrode increases, and crosstalk cannot be ignored. FIGS. 10 and 11 show a conventional bump connection structure disclosed in Japanese Patent Laid-Open Publication No.
104260 and a connection structure described in JP-A-3-198358. As a countermeasure, in FIG. 10, a ground electrode is arranged around the signal electrode of the semiconductor integrated circuit, and the signal bump 5 is surrounded by the ground bump 6, thereby reducing noise due to crosstalk between the signal electrodes. I have. In FIG. 11, a power supply bump is provided around a signal bump, and a signal lead is surrounded by a ground lead to reduce crosstalk.

[0003]

In the conventional bump connection structure described above, the signal bumps and the ground bumps or the power supply bumps shown in FIGS. 10 and 11 are formed by interposing air or a mold resin between the bumps. 12, an equivalent circuit 1206- of the coupling capacitance between the bumps shown in FIG.
1, 1206-2. Due to this coupling capacitance, a signal in a high frequency range to be transmitted between the semiconductor integrated circuit and the wiring board on which the semiconductor integrated circuit is mounted flows into the bump for ground, causing a loss in the signal. In addition, when a signal leaks into the ground bump, the ground level in the semiconductor integrated circuit fluctuates, and the circuit operation becomes unstable.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor integrated circuit in which deterioration of signal characteristics in a high frequency region due to the coupling capacitance of adjacent bumps is reduced, and a connection structure between electrodes by bumps between a semiconductor integrated circuit and a wiring board on which the same is mounted. It is to provide.

[0005]

According to the present invention, there is provided a connection structure for a semiconductor device, wherein an electrode of a semiconductor integrated circuit is connected to an electrode of a wiring board on which the electrode is mounted by bumps. A plurality of electrodes arranged at equal intervals on a semiconductor integrated circuit, and an electrode arrangement in which a plurality of electrodes having an electrode interval wider than the electrodes on the semiconductor integrated circuit are arranged on the wiring substrate, The electrode on the semiconductor integrated circuit and the electrode on the wiring board are arranged at a position such that a straight line perpendicular to the electrode surface on the integrated circuit and located at the center of the electrode passes through the center of the electrode on the wiring board. The electrode is a signal electrode, and a straight line perpendicular to the electrode surface on the semiconductor integrated circuit and passing through the center between two adjacent electrodes passes through the center between two adjacent electrodes on the wiring board. In position The two electrodes on the semiconductor integrated circuit and the two electrodes on the wiring substrate corresponding to these two electrodes are arranged as power supply electrodes and the other as a ground electrode, A bump is disposed at the center of each of the signal electrode, the power supply electrode, and the ground electrode, and is characterized in that the signal electrode, the power supply electrode, and the ground electrode on the wiring board are connected. Also,
A plurality of power supply electrodes are continuously arranged in an electrode layout in which the electrode pitch and the electrode size on the semiconductor integrated circuit are equal to the electrode pitch and the electrode size on the wiring substrate, and on the semiconductor integrated circuit and the wiring substrate, respectively. A plurality of ground electrodes are continuously arranged, the signal electrodes on the semiconductor integrated circuit and the wiring substrate are arranged with a power supply electrode or a ground electrode interposed therebetween, and the signal electrodes are connected by bumps; The portion where the power electrode and the ground electrode of the integrated circuit are adjacent connects the power electrode and the ground electrode on the semiconductor integrated circuit and the wiring substrate with bumps, respectively. For the power electrode and the ground electrode adjacent to the signal electrode, It is characterized by no connection. Also, in the layout of the electrodes in which the electrode pitch and the electrode size on the semiconductor integrated circuit are equal to the electrode pitch and the electrode size of the wiring board,
When two or more electrodes on a semiconductor integrated circuit are connected to form an input terminal for the same signal or two or more electrodes are connected to an output terminal for the same signal, only one of the two or more connected electrodes is used. It is characterized in that it is connected to the electrode of the wiring board by a bump. 4. The connection structure for a semiconductor device according to claim 1, wherein the bump is an elliptical metal bump formed by crushing a metal ball, and the bump is connected by the elliptical metal bump. In addition, the bumps are formed as conductive pillars formed of metal or conductive resin in a cylindrical or prismatic shape, and are connected by the conductive pillars. Further, the present invention is characterized in that the bump is a ball bump formed by a solder ball having a copper ball as a core, and the bump is connected by the ball bump.

[0006]

Next, the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a first embodiment of the present invention. This is a case where the electrode pitch and the electrode size of the semiconductor integrated circuit 101 are different from the electrode pitch and the electrode size of the wiring substrate 102, and a straight line 115 perpendicular to the electrode surface passing through the center 113 of the electrode of the semiconductor circuit 101.
However, the electrodes on the semiconductor integrated circuit 102 passing through the center 114 of the electrodes on the wiring board 102 and the electrodes on the wiring board are signal electrodes 103 and 107-3, and these electrodes are connected by bumps.

In addition to the connection of the signal electrodes described above, a straight line 116 perpendicular to the electrode surface passing through the midpoint 111 between two adjacent electrodes on the semiconductor integrated circuit 102 is formed on the wiring board 1.
When passing through the midpoint 112 between two adjacent electrodes on the semiconductor integrated circuit 02, the two electrodes on the semiconductor integrated circuit 101 are used as a ground electrode 105-1 and a power supply electrode, respectively.
1. An electrode on the wiring board, which makes a pair with each of the two electrodes 105-1 and 104-1, is a ground electrode 107-
1, two power supply electrodes 107-2, two ground electrodes 105-1, on the semiconductor integrated circuit 101 and on the wiring substrate 102;
107-1 are connected by bumps, and similarly, the two power supply electrodes 104-1 and 107-2 are connected by bumps.

By employing the above-described bump connection method, the bump 110-1 connecting the power supply electrode and the bump 109-1 connecting the ground electrode are close to each other, and the coupling capacitance is increased, thereby reducing the effect of the bypass capacitor. None, power supply noise can be reduced. Also, the bump 103 connecting the signal electrode and the bump 1 connecting the ground electrode and the power electrode are connected.
The electrical characteristics of the bumps connecting the signal electrodes can be improved by widening the interval between 09-1 and 110-2 and reducing the coupling capacitance.

FIG. 2 shows a second embodiment of the present invention. This is a case where the electrode pitch and the electrode size of the semiconductor integrated circuit 201 are different from the electrode pitch and the electrode size of the wiring substrate 202. What differs from the embodiment of FIG. 1 is the electrode pitch and the electrode size on the wiring substrate side. When a straight line 216 perpendicular to the electrode surface passing through a midpoint 209 between two adjacent electrodes on the semiconductor integrated circuit 201 passes through a midpoint 210 between two adjacent electrodes on the wiring board 202, the semiconductor The two electrodes on the integrated circuit 201 are connected to the ground electrode 2 respectively.
04-1 and a power supply electrode 203-1.
The electrodes on the wiring board, which make a pair with each of 04-1 and 203-1, are a ground electrode 206-1 and a power supply electrode 206-2.
Then, two ground electrodes on the semiconductor integrated circuit and the wiring substrate are connected by a bump 208-1, and similarly, two power electrodes are connected by a bump 207-1. By adopting the bump connection method as described above, the bump 208-1 connecting the ground electrode and the bump 207-1 connecting the power supply electrode are close to each other to increase the coupling capacitance, thereby achieving the effect of the bypass capacitor and reducing the power supply noise. Can be reduced.

FIG. 3 shows a third embodiment of the present invention. This is a case where the electrode pitch and the electrode size of the semiconductor integrated circuit 301 are different from the electrode pitch and the electrode size of the wiring substrate 302. The difference from the first and second is the electrode pitch and the electrode size on the wiring substrate side. A straight line 316 perpendicular to the electrode surface passing through the midpoint 310 between two adjacent electrodes on the semiconductor integrated circuit 301 is formed on the adjacent two electrodes on the wiring board 302.
When passing through the midpoint 311 between the two electrodes, the two electrodes on the semiconductor integrated circuit 301 are connected to the ground electrode 307, respectively.
-2, a power supply electrode 308-1, and the two electrodes 307
-2 and 308-1 are paired with a ground electrode 309-1 and a power supply electrode 309-2, respectively, on the wiring board, and two ground electrodes 307-2 and 309- on the semiconductor integrated circuit and the wiring board. 1 are connected by a bump 304, and similarly, two power supply electrodes 308-1 and 309-2 are connected by a bump 305. In addition, the signal electrodes 303-1 and 303- arranged continuously as the same signal input terminal or the same signal output terminal on the semiconductor integrated circuit 301.
2, the electrode 3 farthest from the nearest bump 305
03-2 is used as a signal electrode and connected to a signal electrode 309-3 on the wiring board 302 by a bump 306.

By adopting the above-described bump connection method, the bump 304 connecting the ground electrode and the bump 305 connecting the power electrode are close to each other, and the coupling capacitance is increased.
The effect of the bypass capacitor is achieved, and the power supply noise can be reduced. Further, the distance between the bump 306 connecting the signal electrode and the bump 305 connecting the power supply electrode is widened, and the electrical characteristics of the bump connecting the signal electrode can be improved by reducing the coupling capacitance.

FIG. 4 shows a fourth embodiment of the present invention. This is when the electrode pitch and the electrode size of the semiconductor integrated circuit 401 are equal to the electrode pitch and the electrode size of the wiring substrate 402, and the power supply electrode 409-1 and the ground electrode 408- Reference numeral 2 denotes a power supply electrode 410-2 and a ground electrode 411- on the wiring board 402.
1 via a power bump 406 and a ground bump 405. The power supply electrode 40 adjacent to the signal electrode 404
9-3 and the ground electrode 408-3 are not connected.

By adopting the above-described bump connection method, the coupling capacitance between the bump 406 connecting the power supply electrode and the bump 405 connecting the ground electrode is increased, and the effect of the bypass capacitor can be achieved, thereby reducing the power supply noise. . In addition, by reducing the coupling capacitance between the bump 407 connecting the signal electrode and the bump 406 connecting the power supply electrode or the bump 405 connecting the ground electrode, the electrical characteristics of the joint can be improved.

FIG. 5 shows a fifth embodiment of the present invention. This is the case where the electrode pitch and the electrode size on the semiconductor integrated circuit 501 are equal to the electrode pitch and the electrode size on the wiring substrate 502, and the electrodes on the semiconductor integrated circuit 501 are the same signal input terminals or the same. Either of the adjacent electrodes 504-1 and 504-2, which are signal electrodes serving as signal output terminals, is arbitrary, and in FIG.
2, a bump 505 is arranged on
03-2. Regarding the connection of the signal electrodes 503-3 and 503-4, which are the input terminal or the output terminal of the same signal, the signal electrodes 503-4 and 504-4 farther from the bump 505 are connected by the bump 506. Similarly, bump 5
The electrodes 504-6 and 503-6, which are farther from the reference numeral 06, are connected by bumps 507. By using the bump connection method as described above, the bumps 505 and 50 connecting the respective signal electrodes are formed.
6,507 are widened, the coupling capacity is reduced, and the electrical characteristics can be improved.

FIG. 6 shows the second embodiment of the present invention in which the electrode pitch and the electrode size on the semiconductor integrated circuit and the electrode pitch and the electrode size of the wiring board are the same as those of the embodiment of FIG. 1, and the connection portion bumps are replaced with conductive pillars. 6 is an embodiment of FIG. The conductive pillar is formed by plating a metal, a conductive resin, or an insulator to have conductivity, and has a columnar shape or a prismatic shape. By adopting the connection method using the conductive pillar as described above, the conductive pillar 610-1 for connecting the power electrode and the conductive pillar 609-1 for connecting the ground electrode are close to each other, as in the first embodiment. A conductive pillar 608 for connecting a signal electrode, and a ground electrode 605.
-2 and conductive pillar 61 for connecting power supply electrode 604-1
Since the interval between 0-2 and 609-1 is widened and the coupling capacitance is reduced, the electrical characteristics of the conductive pillar connecting the signal electrodes can be improved.

FIGS. 7 and 8 show seventh and eighth embodiments, respectively, in which the shape of the conductive pillar in the embodiment of FIG. 6 is modified. FIG. 7 shows a case where the cross section of the pillar 710-1 is smaller than the electrode surface, and the electrode 705 on the semiconductor integrated circuit 701 is formed.
-1 and the electrode 707-1 on the wiring board 702 are connected. FIG. 8 shows a structure in which a pillar longer than the distance between the electrode on the semiconductor integrated circuit 801 and the electrode on the wiring board 802 is bent to connect the electrode on the semiconductor integrated circuit to the electrode on the wiring board. By adopting the connection method using the conductive pillars, for the same reason as in the first embodiment, the noise of the power supply can be further reduced, and the electrical characteristics of the conductive pillars connecting the signal electrodes can be improved.

FIG. 9 shows a semiconductor integrated circuit in which the electrode pitch and the electrode size and the electrode pitch and the electrode size of the wiring board are the same as those of the first embodiment, and the connection portion bumps are replaced by ball bumps. The ball bump is a copper ball 917
This is performed by forming a solder ball 910-1 between the electrode 905-1 on the semiconductor circuit and the electrode 907-1 on the wiring board, with the core as the core. By adopting the connection method using ball bumps as described above, similarly to the first embodiment, the ball bumps 909-1 for connecting the power supply electrodes and the copper balls 910-1 for connecting the ground electrodes are close to each other and bypassed. The effect of the capacitor is achieved, and the noise of the power supply can be reduced. Further, for the ball bump 908 connecting the signal electrode,
Ball bump 910 connecting ground electrode 905-2
-Bump 90 connecting -2 and power electrode 904-1
By increasing the interval of 9-1 and reducing the coupling capacitance, the electrical characteristics of the ball bumps connecting the signal electrodes can be improved.

[0018]

As described above, the first effect of the present invention is that the electrical characteristics of the bump joint are improved. The reason is that the coupling capacitance between the signal electrode and the adjacent bump is reduced. A second effect is that noise between the power supply and the ground is reduced. The reason for this is that the coupling capacitance can be increased by arranging the power supply bumps and the ground bumps with a small distance, and they serve as a bypass capacitor. In the connection structure of the present invention, the bump interval between the power electrode and the ground electrode is reduced, and the bump interval between the signal electrodes is increased. Therefore the power supply
Since the coupling capacitance between the bumps of the ground electrode increases and plays the role of a bypass capacitor, power supply noise can be reduced. Further, there is an effect that the coupling capacitance between the bumps of the signal electrode is reduced, noise due to crosstalk is reduced, and electrical characteristics can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a connection structure using bumps according to a first embodiment of the present invention.

FIG. 2 is a sectional view of a connection structure using bumps according to a second embodiment of the present invention.

FIG. 3 is a sectional view showing a connection structure using bumps according to a third embodiment of the present invention.

FIG. 4 is a sectional view showing a connection structure using bumps according to a fourth embodiment of the present invention.

FIG. 5 is a sectional view showing a connection structure using bumps according to a fifth embodiment of the present invention.

FIG. 6 is a sectional view showing a connection structure using bumps according to a sixth embodiment of the present invention.

FIG. 7 is a sectional view showing a connection structure using bumps according to a seventh embodiment of the present invention.

FIG. 8 is a sectional view showing a connection structure using bumps according to an eighth embodiment of the present invention.

FIG. 9 is a sectional view of a connection structure using bumps according to a ninth embodiment of the present invention.

FIG. 10 is a cross-sectional view showing a coupling capacitance between bumps in a conventional connection structure using bumps.

FIG. 11 is a plan view showing a conventional connection structure using bumps.

FIG. 12 is a cross-sectional view showing a coupling capacitance between bumps in a conventional connection structure using bumps.

[Explanation of symbols]

101, 201, 301, 401, 501, 601, 7
01,801,901,1201 Semiconductor integrated circuit 102,202,302,402,502,602,7
02, 802, 902, 1202 Wiring board 103, 107-3, 303-1, 303-2, 309
-3,403,404,504-1 to 6,503-1
6,603,607-3,903,907-3,120
4-2, 1203-2 Signal electrode 104-1, 104-2, 107-2, 107-5, 2
03-1, 203-2, 206-2, 206-4, 30
8-1, 308-2, 309-2, 409-1 to 3, 4
11-1 to 3, 604-1, 604-2, 607-2,
707-5, 704-1, 704-2, 707-2, 7
07-5, 804-1, 804-2, 807-2, 80
7-5, 904-1, 904-2, 907-2, 907
−5, 1203-3, 1204-3 Power supply electrodes 105-1, 105-2, 107-1, 107-4, 2
04-1, 204-2, 206-1, 206-3, 30
7-1, 307-2, 309-1, 408-1 to 3, 4
10-1 to 3, 605-1 to 2, 607-1, 607-
4,705-1 to 2,707-1,707-4,805
-1 to 2,807-1,807-4,905-1 to 2,
907-1, 907-4, 1203-1, 1204-1
Ground electrodes 107-1 to 5, 206-1 to 4,309-1 to 3,6
06-1-3, 706-1-3 806-1-3, 90
6-1-3 electrodes 110-1, 109-1, 108, 110-2, 109
−2, 208-1, 207-1, 208-2, 207−
2,304,305,306,405,406,40
7,505,506,507,1205-1,1205
−2, 1204-3 Bump 111, 112, 209, 210, 310, 311, 6
11,612,711,712,811,812,91
1,912 The center between two adjacent electrodes 113,114,613,614,713,714,8
13,814,913,914 Electrode center 115,116,615,616,715,716,8
15,816,915,916 Straight line 610-1,609-1,608,610-2,609 perpendicular to electrode surface
−2, 710-1, 709-1, 708, 710-2,
709-2, 810-1, 809-1, 808, 810
−2, 809-2 conductive pillars 910-1, 909-1, 908, 910-2, 909
-2 Ball bump 1206-1, 1206-2 Equivalent circuit of coupling capacitance between bumps 917 Copper ball

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Yuki Fujimura 5-7-1, Shiba, Minato-ku, Tokyo F-term in NEC Corporation 5F044 KK01 LL01 LL04 LL13

Claims (6)

[Claims] The present invention relates to a structure in which an electrode of a semiconductor integrated circuit and an electrode of a wiring board on which the electrode is mounted are connected to each other by bumps, and a plurality of electrodes are arranged at equal intervals on the semiconductor integrated circuit.
On the wiring substrate, there is provided an electrode arrangement in which a plurality of electrodes having a larger electrode interval than the electrodes on the semiconductor integrated circuit are arranged, and the electrode arrangement is perpendicular to the electrode surface on the semiconductor integrated circuit and located at the center of the electrode. An electrode on the semiconductor integrated circuit and an electrode on the wiring substrate arranged at a position where a straight line passing through the center of the electrode on the wiring substrate are signal electrodes, and The above-mentioned semiconductor integrated circuit, wherein the vertical straight line passing through the center between two adjacent electrodes is located at a position where the straight line passes through the center between two adjacent electrodes on the wiring board, and is disposed at an opposed position. One of the two electrodes and the corresponding two electrodes on the wiring board are a power supply electrode, and the other is a ground electrode, and the signal electrode, the power supply electrode, and the ground electrode on the semiconductor integrated circuit, respectively. Connection structure of bump arranged in the center, a semiconductor device which is characterized by structure for connecting the signal electrode on the wiring board, the power supply electrode and a ground electrode. 2. An electrode pitch and an electrode size on a semiconductor integrated circuit are equal to an electrode pitch and an electrode size on a wiring board.
And, regarding the electrode connection structure, a plurality of power supply electrodes or ground electrodes, in which electrodes on a semiconductor integrated circuit and electrodes on a wiring board are arranged facing each other, are arranged in series, and a signal electrode serves as a power supply electrode or a ground electrode. In the interposed area, the signal electrodes are connected to each other by bumps, and a portion where the power electrode and the ground electrode of the semiconductor integrated circuit are adjacent to each other is a power electrode and a ground electrode on the semiconductor integrated circuit and the wiring substrate, respectively. 2. The connection structure for a semiconductor device according to claim 1, wherein the power supply electrodes and the ground electrodes are not connected to each other by bumps. 3. An electrode layout in which the electrode pitch and the electrode size on the semiconductor integrated circuit are equal to the electrode pitch and the electrode size on the wiring substrate, and two or more electrodes on the semiconductor integrated circuit are connected to each other to input the same signal or 2. The device according to claim 1, wherein when two or more electrodes are connected to serve as an output terminal of the same signal, only one of the two or more connected electrodes is connected to an electrode of the wiring board by a bump. Connection structure of semiconductor device. 4. The connection structure for a semiconductor device according to claim 1, wherein the bump is an elliptical metal bump crushed by a metal ball, and the bump is connected by the elliptical metal bump. 5. The semiconductor device according to claim 1, wherein said bumps are formed of conductive pillars formed of metal or conductive resin in a columnar or prismatic shape, and are connected by said conductive pillars. Connection structure. 6. The connection structure for a semiconductor device according to claim 1, wherein the bump is a ball bump formed by a solder ball having a copper ball as a core, and the bump is connected by the ball bump.