JPH1174407A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH1174407A JPH1174407A JP9234272A JP23427297A JPH1174407A JP H1174407 A JPH1174407 A JP H1174407A JP 9234272 A JP9234272 A JP 9234272A JP 23427297 A JP23427297 A JP 23427297A JP H1174407 A JPH1174407 A JP H1174407A
- Authority
- JP
- Japan
- Prior art keywords
- electrode terminals
- electrode terminal
- semiconductor device
- solder
- solder balls
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0213—Electrical arrangements not otherwise provided for
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Wire Bonding (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体装置に関
し、特にＢＧＡ（Ball Grid Array）、ＣＳＰ（Chip Sc
ale Package）等、外部電極端子に半田ボールを使用し
た多ピンの面実装パッケージにおける電極配置に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly, to a BGA (Ball Grid Array) and a CSP (Chip Sc
The present invention relates to an electrode arrangement in a multi-pin surface mount package using solder balls for external electrode terminals, such as an ale package.
【０００２】[0002]
【従来の技術】メモリＩＣやＡＳＩＣ等の分野では、高
速化、多ピン化及び小型化の要求から、従来のＱＦＰ等
のような外部電極端子にピンを使用したパッケージでは
対応できなくなっていた。このため、外部電極端子に半
田ボールを使用したＢＧＡ、ＣＳＰ等のような薄く小形
で外部電極端子数の多いパッケージが開発され、このよ
うなパッケージでは、多端子化及び小型化を行うため
に、外部電極端子をなす半田ボールのピッチは１ｍｍ以
下となるように形成されていた。2. Description of the Related Art In the fields of memory ICs and ASICs, demands for higher speed, more pins, and smaller size have made it impossible to respond to a package using pins for external electrode terminals such as a conventional QFP. For this reason, thin and small packages with a large number of external electrode terminals, such as BGAs and CSPs using solder balls for the external electrode terminals, have been developed. In such packages, in order to increase the number of terminals and reduce the size, The pitch of the solder balls forming the external electrode terminals was 1 mm or less.
【０００３】図７は、従来の半導体装置における実装面
の例を示した平面図である。図７において、半導体装置
１００は、パッケージ１０１における実装面１０２上に
それぞれの外部電極端子をなす各半田ボールがそれぞれ
形成されている。実装面１０２上に形成された各半田ボ
ールは、電源電極端子をなす半田ボール１０３ａ、アー
ス電極端子をなす半田ボール１０３ｂ、並びに電源電極
端子及びアース電極端子以外の外部電極端子である信号
電極端子をなす半田ボール１０３ｃからなる。FIG. 7 is a plan view showing an example of a mounting surface in a conventional semiconductor device. In FIG. 7, in a semiconductor device 100, solder balls forming external electrode terminals are formed on a mounting surface 102 of a package 101, respectively. Each solder ball formed on the mounting surface 102 has a solder ball 103a serving as a power electrode terminal, a solder ball 103b serving as an earth electrode terminal, and signal electrode terminals which are external electrode terminals other than the power electrode terminal and the earth electrode terminal. The solder ball 103c is formed.
【０００４】[0004]
【発明が解決しようとする課題】ここで、半田ボール間
のピッチが１ｍｍ以下になると、実装の際に半田ショー
トや、固定異物又は可動異物による電極端子間のショー
トが発生しやすくなる。しかし、ＢＧＡやＣＳＰ等の面
実装パッケージにおいては、このようなショートを、Ｑ
ＦＰ等のピンを使用したパッケージのように目視やプロ
ービングで発見することは不可能である。このため、Ｂ
ＧＡやＣＳＰ等の面実装パッケージにおける電極端子間
のショート等の接続不良を検出する方法として、バウン
ダリスキャンがあった。Here, if the pitch between the solder balls is 1 mm or less, a solder short or a short between the electrode terminals due to a fixed foreign matter or a movable foreign matter easily occurs during mounting. However, in a surface mount package such as BGA or CSP, such a short circuit is caused by Q
It is impossible to find it by visual inspection or probing like a package using pins such as FP. Therefore, B
As a method for detecting a connection failure such as a short circuit between electrode terminals in a surface mount package such as a GA or a CSP, there is a boundary scan.
【０００５】上記バウンダリスキャンは、電源電極端子
及びアース電極端子以外の外部電極端子である信号電極
端子が絡んだショート、すなわち、信号電極端子間、信
号電極端子と電源電極端子との間、及び信号電極端子と
アース電極端子との間で生じたショートを電気的に検出
することができる。しかし、図７で示したように、半田
ボール１０３ａ及び１０３ｂを隣接させて形成した場
合、半田ボールのピッチが１ｍｍ以下になると、電源電
極端子とアース電極端子との間で半田くず等の異物によ
ってショートする可能性が大きくなる。これに対して、
電源電極端子とアース電極端子との間で生じたショート
は、バウンダリスキャンでは検出することができないと
いう問題があった。[0005] The above boundary scan is a short circuit in which a signal electrode terminal which is an external electrode terminal other than the power supply electrode terminal and the ground electrode terminal is entangled, that is, between signal electrode terminals, between a signal electrode terminal and a power supply electrode terminal, and between signal electrode terminals. A short circuit between the electrode terminal and the ground electrode terminal can be electrically detected. However, as shown in FIG. 7, when the solder balls 103a and 103b are formed adjacent to each other, if the pitch of the solder balls becomes 1 mm or less, foreign matter such as scraps of solder between the power supply electrode terminal and the ground electrode terminal. The possibility of short circuit increases. On the contrary,
There is a problem that a short circuit generated between the power supply electrode terminal and the ground electrode terminal cannot be detected by the boundary scan.
【０００６】本発明は、上記のような問題を解決するた
めになされたものであり、ＢＧＡやＣＳＰ等の面実装パ
ッケージで形成され、電源電極端子及びアース電極端子
の間でのショートを防止することができる半導体装置を
得ることを目的とする。SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and is formed of a surface mount package such as a BGA or a CSP to prevent a short circuit between a power supply electrode terminal and a ground electrode terminal. It is an object to obtain a semiconductor device which can be used.
【０００７】なお、本発明と目的が異なるが、電源リー
ドと接地リードとの間に２本の信号リードを配置するこ
とによって、電源電位及び接地電位の変動を抑えてトラ
ンジスタの誤動作を防止した、外部電極端子にリードを
使用する半導体装置が、特開平６−１５１６８８号公報
で開示されている。Although the purpose is different from that of the present invention, by arranging two signal leads between a power supply lead and a ground lead, fluctuations of a power supply potential and a ground potential are suppressed to prevent a malfunction of a transistor. A semiconductor device using leads for external electrode terminals is disclosed in Japanese Patent Application Laid-Open No. Hei 6-151688.
【０００８】[0008]
【課題を解決するための手段】この発明に係る半導体装
置は、各外部電極端子に半田ボールをそれぞれ使用した
面実装パッケージで形成される半導体装置において、極
性の異なる電源電極端子を隣接させないように、各外部
電極端子を配置するものである。A semiconductor device according to the present invention is a semiconductor device formed by a surface mount package using solder balls for each external electrode terminal so that power supply electrode terminals having different polarities are not adjacent to each other. , And each of the external electrode terminals.
【０００９】また、この発明に係る半導体装置は、請求
項１において、上記面実装パッケージにおける外部電極
端子の半田ボールピッチは、１ｍｍ以下であるものであ
る。Further, in the semiconductor device according to the present invention, the solder ball pitch of the external electrode terminal in the surface mount package is 1 mm or less.
【００１０】また、この発明に係る半導体装置は、請求
項１又は請求項２のいずれかにおいて、極性の異なる電
源電極端子間に、電源電極端子とは異なる少なくとも１
つの信号電極端子を設けるように、上記各外部電極端子
を配置するものである。Further, according to the present invention, in the semiconductor device according to any one of the first and second aspects, at least one of the power supply electrode terminals having different polarities is different from the power supply electrode terminal.
Each of the external electrode terminals is arranged such that one signal electrode terminal is provided.
【００１１】[0011]
【発明の実施の形態】次に、図面に示す実施の形態に基
づいて、本発明を詳細に説明する。 実施の形態１．図１は、本発明の実施の形態１における
半導体装置の例を示した斜視図であり、図２は、図１で
示した半導体装置の側面図である。図１及び図２におい
て、半導体装置１は、パッケージ２における実装面上に
それぞれの外部電極端子をなす各半田ボール３がそれぞ
れ形成されており、ＢＧＡ又はＣＳＰ等で形成されてい
る。該各半田ボール３は、１ｍｍ以下のピッチでそれぞ
れ形成されており、例えば１.５ｃｍ角の実装面を有す
るパッケージ２において、該実装面上には１５０個以上
の半田ボール３が形成されている。なお、本実施の形態
１においては、分かりやすいように半田ボール３の数を
少なく示している。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described in detail based on an embodiment shown in the drawings. Embodiment 1 FIG. FIG. 1 is a perspective view showing an example of the semiconductor device according to the first embodiment of the present invention, and FIG. 2 is a side view of the semiconductor device shown in FIG. 1 and 2, the semiconductor device 1 has solder balls 3 forming respective external electrode terminals formed on a mounting surface of a package 2 and is formed of BGA or CSP. The solder balls 3 are formed at a pitch of 1 mm or less. For example, in a package 2 having a mounting surface of 1.5 cm square, 150 or more solder balls 3 are formed on the mounting surface. . In the first embodiment, the number of solder balls 3 is shown small for easy understanding.
【００１２】図３は、図１及び図２で示した半導体装置
１を実装基板上に実装した状態を示す側面図である。図
３において、実装基板５上に形成された配線パターン
（図示せず）における所定の位置に配置された各半田ボ
ール３は、加熱されて熱溶融することによって実装基板
５上にそれぞれ接続される。図４は、半導体装置１にお
ける実装面の例を示した平面図である。図４において、
パッケージ２の実装面６上に形成された各半田ボール３
は、電源電極端子をなす半田ボール３ａ、アース電極端
子をなす半田ボール３ｂ、並びに電源電極端子及びアー
ス電極端子以外の外部電極端子である信号電極端子をな
す半田ボール３ｃで構成されている。FIG. 3 is a side view showing a state where the semiconductor device 1 shown in FIGS. 1 and 2 is mounted on a mounting board. In FIG. 3, each solder ball 3 arranged at a predetermined position in a wiring pattern (not shown) formed on the mounting board 5 is connected to the mounting board 5 by being heated and melted. . FIG. 4 is a plan view illustrating an example of a mounting surface in the semiconductor device 1. In FIG.
Each solder ball 3 formed on the mounting surface 6 of the package 2
Are composed of a solder ball 3a serving as a power electrode terminal, a solder ball 3b serving as an earth electrode terminal, and a solder ball 3c serving as a signal electrode terminal which is an external electrode terminal other than the power electrode terminal and the earth electrode terminal.
【００１３】半田ボール３ａと３ｂとの間には、少なく
とも１つの半田ボール３ｃが設けられており、半田ボー
ル３ａと３ｂが隣接しないように半田ボール３ａ〜３ｃ
がそれぞれ配置されて形成されている。このようにする
ことによって、外部電極端子間のショートを引き起こす
半田くず等の異物は、大きさが１ｍｍ以下であることか
ら、半田くず等の異物によって外部電極端子間がショー
トしたとしても、ほとんどすべて電源電極端子と信号電
極端子との間、又はアース電極端子と信号電極端子との
間で生じるショートであり、電源電極端子とアース電極
端子との間でショートが発生し難い。このため、これら
の電極端子間のショートは、バウンダリスキャンで検出
することができる。At least one solder ball 3c is provided between the solder balls 3a and 3b, and the solder balls 3a to 3c are arranged so that the solder balls 3a and 3b are not adjacent to each other.
Are arranged and formed. By doing so, foreign matter such as solder debris that causes a short circuit between the external electrode terminals is 1 mm or less in size. This is a short circuit between the power electrode terminal and the signal electrode terminal or between the ground electrode terminal and the signal electrode terminal, and a short circuit between the power electrode terminal and the ground electrode terminal hardly occurs. Therefore, a short circuit between these electrode terminals can be detected by boundary scan.
【００１４】なお、外部電極端子間のショートを引き起
こす半田くず等の異物は、通常大きさが１ｍｍ以下であ
ることから、半田ボール３ａと３ｂとの間の間隔を電極
端子間のショートが発生し難くなるぐらいまで広げるよ
うにしてもよい。図５及び図６は、このようにした場合
の半導体装置１の実装面の例を示した平面図である。図
５では、半田ボール３ａと半田ボール３ｂとの間は、一
定の半田ボールピッチに対して少なくとも１つ以上半田
ボール３を設けないようにしており、このようにするこ
とによって、電源電極端子とアース電極端子との間でシ
ョートが発生し難くすることができる。また図６では、
半田ボール３ａと半田ボール３ｂとの間のみ半田ボール
ピッチを大きくしており、このようにすることによっ
て、電源電極端子とアース電極端子との間でショートが
発生し難くすることができる。Since foreign matters such as solder debris that cause a short circuit between the external electrode terminals are usually 1 mm or less in size, the distance between the solder balls 3a and 3b causes a short circuit between the electrode terminals. You may make it spread until it becomes difficult. 5 and 6 are plan views showing examples of the mounting surface of the semiconductor device 1 in such a case. In FIG. 5, between the solder balls 3a and 3b, at least one or more solder balls 3 are not provided for a fixed solder ball pitch. It is possible to prevent a short circuit from occurring with the ground electrode terminal. In FIG. 6,
The pitch of the solder balls is increased only between the solder balls 3a and the solder balls 3b. By doing so, a short circuit between the power supply electrode terminal and the ground electrode terminal can be suppressed.
【００１５】このように、本発明の実施の形態１におけ
る半導体装置は、パッケージ２の実装面６上に形成する
半田ボール３において、電源電極端子をなす半田ボール
３ａとアース電極端子をなす半田ボール３ｂとの間に、
少なくとも１つの信号電極端子をなす半田ボール３ｃを
配置して設けるようにした、このことから、実装基板に
実装した後、バウンダリスキャンで検出することができ
なかった電源電極端子とアース電極端子とのショートを
発生し難くすることができ、バウンダリスキャンによる
各電極端子間で生じたショート検出率を大幅に向上さ
せ、半導体装置の実装時の信頼性を大幅に向上させるこ
とができる。As described above, in the semiconductor device according to the first embodiment of the present invention, the solder ball 3 formed on the mounting surface 6 of the package 2 has the solder ball 3 a forming the power supply electrode terminal and the solder ball forming the ground electrode terminal. 3b
At least one solder electrode 3c serving as a signal electrode terminal is arranged and provided. For this reason, after mounting on the mounting board, the power supply electrode terminal and the ground electrode terminal which cannot be detected by the boundary scan are connected. Short circuits can be made less likely to occur, the rate of detection of short circuits between electrode terminals due to boundary scan can be greatly improved, and the reliability of the semiconductor device during mounting can be greatly improved.
【００１６】[0016]
【発明の効果】請求項１に係る半導体装置は、極性の異
なる電源電極端子を隣接させないように、各外部電極端
子を配置したことから、実装基板に実装した後、バウン
ダリスキャンで検出することができなかった電源電極端
子とアース電極端子とのショートを発生し難くすること
ができ、バウンダリスキャンによる各電極端子間で生じ
たショート検出率を大幅に向上させ、半導体装置の実装
時の信頼性を大幅に向上させることができる。According to the semiconductor device of the present invention, since the external electrode terminals are arranged so that the power supply electrode terminals having different polarities are not adjacent to each other, the semiconductor device can be detected by the boundary scan after being mounted on the mounting substrate. Short circuit between the power supply electrode terminal and the ground electrode terminal, which could not be done, can be made difficult to occur, the detection rate of short circuit between each electrode terminal by boundary scan can be greatly improved, and the reliability at the time of mounting the semiconductor device It can be greatly improved.
【００１７】請求項２に係る半導体装置は、請求項１に
おいて、具体的には、上記面実装パッケージにおける外
部電極端子の半田ボールピッチは、１ｍｍ以下である。
このことから、外部電極端子間のショートを引き起こす
半田くず等の異物は、大きさが１ｍｍ以下であり、半田
くず等の異物によって外部電極端子間がショートしたと
しても、電源電極端子とアース電極端子との間でショー
トが発生せず、電源電極端子と信号電極端子との間、又
はアース電極端子と信号電極端子との間で生じるショー
トである。このため、これらの電極端子間のショート
は、バウンダリスキャンで検出することができ、半導体
装置の実装時の信頼性を大幅に向上させることができ
る。According to a second aspect of the present invention, specifically, in the first aspect, the solder ball pitch of the external electrode terminals in the surface mount package is 1 mm or less.
For this reason, the size of the foreign matter such as solder waste that causes a short between the external electrode terminals is 1 mm or less. Even if the foreign electrode terminal is short-circuited by the foreign material such as the solder waste, the power supply electrode terminal and the ground electrode terminal may be short-circuited. Does not occur between the power supply electrode terminal and the signal electrode terminal, or between the ground electrode terminal and the signal electrode terminal. Therefore, a short circuit between these electrode terminals can be detected by the boundary scan, and the reliability at the time of mounting the semiconductor device can be greatly improved.
【００１８】請求項３に係る半導体装置は、請求項１又
は請求項２において、具体的には、極性の異なる電源電
極端子間に、電源電極端子とは異なる少なくとも１つの
信号電極端子を設けるように、上記各外部電極端子を配
置した。このことから、電源電極端子とアース電極端子
との間でショートが発生し難く、半田くず等の異物によ
って生じる外部電極端子間のショートは、ほとんどすべ
て電源電極端子と信号電極端子との間、又はアース電極
端子と信号電極端子との間で生じるショートである。こ
のため、これらの電極端子間のショートは、バウンダリ
スキャンで検出することができ、半導体装置の実装時の
信頼性を大幅に向上させることができる。According to a third aspect of the present invention, in the semiconductor device according to the first or second aspect, at least one signal electrode terminal different from the power supply electrode terminal is provided between power supply electrode terminals having different polarities. Each of the above-mentioned external electrode terminals was disposed at the same time. For this reason, a short circuit between the power electrode terminal and the ground electrode terminal is unlikely to occur, and a short circuit between the external electrode terminals caused by foreign matter such as solder waste is almost entirely between the power electrode terminal and the signal electrode terminal, or This is a short circuit between the ground electrode terminal and the signal electrode terminal. Therefore, a short circuit between these electrode terminals can be detected by the boundary scan, and the reliability at the time of mounting the semiconductor device can be greatly improved.
【図１】 本発明の実施の形態１における半導体装置の
例を示した斜視図である。FIG. 1 is a perspective view showing an example of a semiconductor device according to a first embodiment of the present invention.
【図２】 図１で示した半導体装置の側面図である。FIG. 2 is a side view of the semiconductor device shown in FIG.
【図３】 図１及び図２で示した半導体装置１を実装基
板上に実装した状態を示す側面図である。FIG. 3 is a side view showing a state where the semiconductor device 1 shown in FIGS. 1 and 2 is mounted on a mounting board.
【図４】 図１及び図２で示した半導体装置１における
実装面の例を示した平面図である。FIG. 4 is a plan view showing an example of a mounting surface in the semiconductor device 1 shown in FIGS. 1 and 2;
【図５】 図１及び図２で示した半導体装置１の実装面
の他の例を示した平面図である。FIG. 5 is a plan view showing another example of the mounting surface of the semiconductor device 1 shown in FIGS. 1 and 2.
【図６】 図１及び図２で示した半導体装置１の実装面
の他の例を示した平面図である。FIG. 6 is a plan view showing another example of the mounting surface of the semiconductor device 1 shown in FIGS. 1 and 2.
【図７】 従来の半導体装置における実装面の例を示し
た平面図である。FIG. 7 is a plan view showing an example of a mounting surface in a conventional semiconductor device.
１ 半導体装置、 ２ パッケージ、 ３ 半田ボー
ル、 ３ａ 電源電極端子をなす半田ボール、 ３ｂ
アース電極端子をなす半田ボール、 ３ｃ 信号電極端
子をなす半田ボール、 ６ 実装面Reference Signs List 1 semiconductor device, 2 package, 3 solder ball, 3a solder ball forming power electrode terminal, 3b
Solder ball forming a ground electrode terminal, 3c Solder ball forming a signal electrode terminal, 6 Mounting surface
Claims (3)
使用した面実装パッケージで形成される半導体装置にお
いて、 極性の異なる電源電極端子を隣接させないように、上記
各外部電極端子を配置することを特徴とする半導体装
置。In a semiconductor device formed by a surface mounting package using solder balls for each external electrode terminal, the external electrode terminals are arranged so that power supply electrode terminals having different polarities are not adjacent to each other. Semiconductor device.
端子の半田ボールピッチは、１ｍｍ以下であることを特
徴とする請求項１に記載の半導体装置。2. The semiconductor device according to claim 1, wherein the solder ball pitch of the external electrode terminals in the surface mount package is 1 mm or less.
極端子とは異なる少なくとも１つの信号電極端子を設け
るように、上記各外部電極端子を配置することを特徴と
する請求項１又は請求項２のいずれかに記載の半導体装
置。3. The external electrode terminals are arranged so that at least one signal electrode terminal different from the power electrode terminals is provided between power electrode terminals having different polarities. 3. The semiconductor device according to any one of 2.
Priority Applications (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9234272A JPH1174407A (en) | 1997-08-29 | 1997-08-29 | Semiconductor device |
| US09/018,342 US6225702B1 (en) | 1997-08-29 | 1998-02-04 | Ball grid array to prevent shorting between a power supply and ground terminal |
| TW087101884A TW424316B (en) | 1997-08-29 | 1998-02-10 | Semiconductor device |
| DE19809509A DE19809509A1 (en) | 1997-08-29 | 1998-03-05 | Semiconductor component with ball grid array (BGA) |
| KR1019980007231A KR100294771B1 (en) | 1997-08-29 | 1998-03-05 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9234272A JPH1174407A (en) | 1997-08-29 | 1997-08-29 | Semiconductor device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2006122442A Division JP2006203261A (en) | 2006-04-26 | 2006-04-26 | Semiconductor apparatus |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH1174407A true JPH1174407A (en) | 1999-03-16 |
Family
ID=16968377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9234272A Pending JPH1174407A (en) | 1997-08-29 | 1997-08-29 | Semiconductor device |
Country Status (5)
| Country | Link |
|---|---|
| US (1) | US6225702B1 (en) |
| JP (1) | JPH1174407A (en) |
| KR (1) | KR100294771B1 (en) |
| DE (1) | DE19809509A1 (en) |
| TW (1) | TW424316B (en) |
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| JP2002134553A (en) * | 2000-10-30 | 2002-05-10 | Nec Corp | Connecting structure of semiconductor device |
| US6608379B2 (en) * | 2001-11-02 | 2003-08-19 | Institute Of Microelectronics, Et Al. | Enhanced chip scale package for flip chips |
| US7763960B2 (en) | 2006-09-11 | 2010-07-27 | Panasonic Corporation | Semiconductor device, method for manufacturing semiconductor device, and electric equipment system |
| JP2016039348A (en) * | 2014-08-11 | 2016-03-22 | 富士通株式会社 | Semiconductor circuit device and method for testing semiconductor circuit device |
| JP2016109439A (en) * | 2014-12-02 | 2016-06-20 | 富士通株式会社 | Semiconductor device and method for testing semiconductor device |
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| JP3343730B2 (en) * | 1999-08-27 | 2002-11-11 | 埼玉日本電気株式会社 | Mounting method of mounting board and electric component |
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-
1997
- 1997-08-29 JP JP9234272A patent/JPH1174407A/en active Pending
-
1998
- 1998-02-04 US US09/018,342 patent/US6225702B1/en not_active Expired - Fee Related
- 1998-02-10 TW TW087101884A patent/TW424316B/en not_active IP Right Cessation
- 1998-03-05 DE DE19809509A patent/DE19809509A1/en not_active Ceased
- 1998-03-05 KR KR1019980007231A patent/KR100294771B1/en not_active IP Right Cessation
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20000053847A (en) * | 2000-04-26 | 2000-09-05 | 김영선 | Advanced Area Array CSP : Triple A CSP |
| JP2002134553A (en) * | 2000-10-30 | 2002-05-10 | Nec Corp | Connecting structure of semiconductor device |
| JP2011135112A (en) * | 2000-10-30 | 2011-07-07 | Nec Corp | Connection structure of semiconductor device |
| US6608379B2 (en) * | 2001-11-02 | 2003-08-19 | Institute Of Microelectronics, Et Al. | Enhanced chip scale package for flip chips |
| US7763960B2 (en) | 2006-09-11 | 2010-07-27 | Panasonic Corporation | Semiconductor device, method for manufacturing semiconductor device, and electric equipment system |
| JP2016039348A (en) * | 2014-08-11 | 2016-03-22 | 富士通株式会社 | Semiconductor circuit device and method for testing semiconductor circuit device |
| JP2016109439A (en) * | 2014-12-02 | 2016-06-20 | 富士通株式会社 | Semiconductor device and method for testing semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| TW424316B (en) | 2001-03-01 |
| KR19990023082A (en) | 1999-03-25 |
| DE19809509A1 (en) | 1999-03-11 |
| US6225702B1 (en) | 2001-05-01 |
| KR100294771B1 (en) | 2001-07-12 |
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